ARMRegisterInfo.h revision 194612 
1285SN/A//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
2462SN/A//
3285SN/A//                     The LLVM Compiler Infrastructure
4285SN/A//
5285SN/A// This file is distributed under the University of Illinois Open Source
6285SN/A// License. See LICENSE.TXT for details.
7285SN/A//
8285SN/A//===----------------------------------------------------------------------===//
9285SN/A//
10285SN/A// This file contains the ARM implementation of the TargetRegisterInfo class.
11285SN/A//
12285SN/A//===----------------------------------------------------------------------===//
13285SN/A
14285SN/A#ifndef ARMREGISTERINFO_H
15285SN/A#define ARMREGISTERINFO_H
16285SN/A
17285SN/A#include "llvm/Target/TargetRegisterInfo.h"
18285SN/A#include "ARMGenRegisterInfo.h.inc"
19285SN/A
20285SN/Anamespace llvm {
21285SN/A  class ARMSubtarget;
22285SN/A  class TargetInstrInfo;
23285SN/A  class Type;
24285SN/A
25285SN/A/// Register allocation hints.
26285SN/Anamespace ARMRI {
27285SN/A  enum {
28285SN/A    RegPairOdd  = 1,
29285SN/A    RegPairEven = 2
30285SN/A  };
31285SN/A}
32285SN/A
33285SN/Astruct ARMRegisterInfo : public ARMGenRegisterInfo {
34285SN/A  const TargetInstrInfo &TII;
35285SN/A  const ARMSubtarget &STI;
36285SN/A
37285SN/Apublic:
38285SN/A  ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
39285SN/A
40285SN/A  /// emitLoadConstPool - Emits a load from constpool to materialize the
41285SN/A  /// specified immediate.
42285SN/A  void emitLoadConstPool(MachineBasicBlock &MBB,
43285SN/A                         MachineBasicBlock::iterator &MBBI,
44285SN/A                         unsigned DestReg, int Val,
45285SN/A                         unsigned Pred, unsigned PredReg,
46285SN/A                         const TargetInstrInfo *TII, bool isThumb,
47285SN/A                         DebugLoc dl) const;
48285SN/A
49285SN/A  /// getRegisterNumbering - Given the enum value for some register, e.g.
50285SN/A  /// ARM::LR, return the number that it corresponds to (e.g. 14).
51285SN/A  static unsigned getRegisterNumbering(unsigned RegEnum);
52285SN/A
53285SN/A  /// Same as previous getRegisterNumbering except it returns true in isSPVFP
54285SN/A  /// if the register is a single precision VFP register.
55285SN/A  static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
56285SN/A
57285SN/A  /// Code Generation virtual methods...
58285SN/A  const TargetRegisterClass *
59285SN/A    getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
60285SN/A  const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
61285SN/A
62285SN/A  const TargetRegisterClass* const*
63285SN/A  getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
64285SN/A
65285SN/A  BitVector getReservedRegs(const MachineFunction &MF) const;
66285SN/A
67285SN/A  bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
68
69  const TargetRegisterClass *getPointerRegClass() const;
70
71  std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
72  getAllocationOrder(const TargetRegisterClass *RC,
73                     unsigned HintType, unsigned HintReg,
74                     const MachineFunction &MF) const;
75
76  unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
77                               const MachineFunction &MF) const;
78
79  void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
80                          MachineFunction &MF) const;
81
82  bool requiresRegisterScavenging(const MachineFunction &MF) const;
83
84  bool hasFP(const MachineFunction &MF) const;
85
86  bool hasReservedCallFrame(MachineFunction &MF) const;
87
88  void eliminateCallFramePseudoInstr(MachineFunction &MF,
89                                     MachineBasicBlock &MBB,
90                                     MachineBasicBlock::iterator I) const;
91
92  void eliminateFrameIndex(MachineBasicBlock::iterator II,
93                           int SPAdj, RegScavenger *RS = NULL) const;
94
95  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
96                                            RegScavenger *RS = NULL) const;
97
98  void emitPrologue(MachineFunction &MF) const;
99  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
100
101  // Debug information queries.
102  unsigned getRARegister() const;
103  unsigned getFrameRegister(MachineFunction &MF) const;
104
105  // Exception handling queries.
106  unsigned getEHExceptionRegister() const;
107  unsigned getEHHandlerRegister() const;
108
109  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
110
111  bool isLowRegister(unsigned Reg) const;
112
113private:
114  /// FramePtr - ARM physical register used as frame ptr.
115  unsigned FramePtr;
116
117  unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
118
119  unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
120
121};
122
123} // end namespace llvm
124
125#endif
126