ARMRegisterInfo.cpp revision 194612 
166458Sdfr//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
2139790Simp//
366458Sdfr//                     The LLVM Compiler Infrastructure
466458Sdfr//
566458Sdfr// This file is distributed under the University of Illinois Open Source
666458Sdfr// License. See LICENSE.TXT for details.
766458Sdfr//
866458Sdfr//===----------------------------------------------------------------------===//
966458Sdfr//
1066458Sdfr// This file contains the ARM implementation of the TargetRegisterInfo class.
1166458Sdfr//
1266458Sdfr//===----------------------------------------------------------------------===//
1366458Sdfr
1466458Sdfr#include "ARM.h"
1566458Sdfr#include "ARMAddressingModes.h"
1666458Sdfr#include "ARMInstrInfo.h"
1766458Sdfr#include "ARMMachineFunctionInfo.h"
1866458Sdfr#include "ARMRegisterInfo.h"
1966458Sdfr#include "ARMSubtarget.h"
2066458Sdfr#include "llvm/Constants.h"
2166458Sdfr#include "llvm/DerivedTypes.h"
2266458Sdfr#include "llvm/CodeGen/MachineConstantPool.h"
2366458Sdfr#include "llvm/CodeGen/MachineFrameInfo.h"
2466458Sdfr#include "llvm/CodeGen/MachineFunction.h"
2566458Sdfr#include "llvm/CodeGen/MachineInstrBuilder.h"
2666458Sdfr#include "llvm/CodeGen/MachineLocation.h"
2766458Sdfr#include "llvm/CodeGen/MachineRegisterInfo.h"
2866458Sdfr#include "llvm/CodeGen/RegisterScavenging.h"
2983301Sdfr#include "llvm/Target/TargetFrameInfo.h"
30138145Smarcel#include "llvm/Target/TargetMachine.h"
31138145Smarcel#include "llvm/Target/TargetOptions.h"
32138145Smarcel#include "llvm/ADT/BitVector.h"
33220313Smarcel#include "llvm/ADT/SmallVector.h"
34220313Smarcel#include "llvm/ADT/STLExtras.h"
35220313Smarcel#include "llvm/Support/CommandLine.h"
36220313Smarcel#include <algorithm>
37220313Smarcelusing namespace llvm;
38219691Smarcel
39138145Smarcelstatic cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
40138145Smarcel                               cl::Hidden,
41138145Smarcel                               cl::desc("Enable register scavenging on Thumb"));
42138145Smarcel
43138145Smarcelunsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
44138145Smarcel  using namespace ARM;
45138145Smarcel  switch (RegEnum) {
46138145Smarcel  case R0:  case S0:  case D0:  return 0;
47219691Smarcel  case R1:  case S1:  case D1:  return 1;
48138145Smarcel  case R2:  case S2:  case D2:  return 2;
49138145Smarcel  case R3:  case S3:  case D3:  return 3;
50138145Smarcel  case R4:  case S4:  case D4:  return 4;
51138145Smarcel  case R5:  case S5:  case D5:  return 5;
52138145Smarcel  case R6:  case S6:  case D6:  return 6;
5366458Sdfr  case R7:  case S7:  case D7:  return 7;
5466458Sdfr  case R8:  case S8:  case D8:  return 8;
55219841Smarcel  case R9:  case S9:  case D9:  return 9;
56  case R10: case S10: case D10: return 10;
57  case R11: case S11: case D11: return 11;
58  case R12: case S12: case D12: return 12;
59  case SP:  case S13: case D13: return 13;
60  case LR:  case S14: case D14: return 14;
61  case PC:  case S15: case D15: return 15;
62  case S16: return 16;
63  case S17: return 17;
64  case S18: return 18;
65  case S19: return 19;
66  case S20: return 20;
67  case S21: return 21;
68  case S22: return 22;
69  case S23: return 23;
70  case S24: return 24;
71  case S25: return 25;
72  case S26: return 26;
73  case S27: return 27;
74  case S28: return 28;
75  case S29: return 29;
76  case S30: return 30;
77  case S31: return 31;
78  default:
79    assert(0 && "Unknown ARM register!");
80    abort();
81  }
82}
83
84unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum,
85                                               bool &isSPVFP) {
86  isSPVFP = false;
87
88  using namespace ARM;
89  switch (RegEnum) {
90  default:
91    assert(0 && "Unknown ARM register!");
92    abort();
93  case R0:  case D0:  return 0;
94  case R1:  case D1:  return 1;
95  case R2:  case D2:  return 2;
96  case R3:  case D3:  return 3;
97  case R4:  case D4:  return 4;
98  case R5:  case D5:  return 5;
99  case R6:  case D6:  return 6;
100  case R7:  case D7:  return 7;
101  case R8:  case D8:  return 8;
102  case R9:  case D9:  return 9;
103  case R10: case D10: return 10;
104  case R11: case D11: return 11;
105  case R12: case D12: return 12;
106  case SP:  case D13: return 13;
107  case LR:  case D14: return 14;
108  case PC:  case D15: return 15;
109
110  case S0: case S1: case S2: case S3:
111  case S4: case S5: case S6: case S7:
112  case S8: case S9: case S10: case S11:
113  case S12: case S13: case S14: case S15:
114  case S16: case S17: case S18: case S19:
115  case S20: case S21: case S22: case S23:
116  case S24: case S25: case S26: case S27:
117  case S28: case S29: case S30: case S31:  {
118    isSPVFP = true;
119    switch (RegEnum) {
120    default: return 0; // Avoid compile time warning.
121    case S0: return 0;
122    case S1: return 1;
123    case S2: return 2;
124    case S3: return 3;
125    case S4: return 4;
126    case S5: return 5;
127    case S6: return 6;
128    case S7: return 7;
129    case S8: return 8;
130    case S9: return 9;
131    case S10: return 10;
132    case S11: return 11;
133    case S12: return 12;
134    case S13: return 13;
135    case S14: return 14;
136    case S15: return 15;
137    case S16: return 16;
138    case S17: return 17;
139    case S18: return 18;
140    case S19: return 19;
141    case S20: return 20;
142    case S21: return 21;
143    case S22: return 22;
144    case S23: return 23;
145    case S24: return 24;
146    case S25: return 25;
147    case S26: return 26;
148    case S27: return 27;
149    case S28: return 28;
150    case S29: return 29;
151    case S30: return 30;
152    case S31: return 31;
153    }
154  }
155  }
156}
157
158ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
159                                 const ARMSubtarget &sti)
160  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
161    TII(tii), STI(sti),
162    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
163}
164
165static inline
166const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
167  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
168}
169
170static inline
171const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
172  return MIB.addReg(0);
173}
174
175/// emitLoadConstPool - Emits a load from constpool to materialize the
176/// specified immediate.
177void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
178                                        MachineBasicBlock::iterator &MBBI,
179                                        unsigned DestReg, int Val,
180                                        unsigned Pred, unsigned PredReg,
181                                        const TargetInstrInfo *TII,
182                                        bool isThumb,
183                                        DebugLoc dl) const {
184  MachineFunction &MF = *MBB.getParent();
185  MachineConstantPool *ConstantPool = MF.getConstantPool();
186  Constant *C = ConstantInt::get(Type::Int32Ty, Val);
187  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
188  if (isThumb)
189    BuildMI(MBB, MBBI, dl,
190            TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
191  else
192    BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
193      .addConstantPoolIndex(Idx)
194      .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
195}
196
197/// isLowRegister - Returns true if the register is low register r0-r7.
198///
199bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
200  using namespace ARM;
201  switch (Reg) {
202  case R0:  case R1:  case R2:  case R3:
203  case R4:  case R5:  case R6:  case R7:
204    return true;
205  default:
206    return false;
207  }
208}
209
210const TargetRegisterClass*
211ARMRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
212  if (STI.isThumb()) {
213    if (isLowRegister(Reg))
214      return ARM::tGPRRegisterClass;
215    switch (Reg) {
216    default:
217      break;
218    case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
219    case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
220      return ARM::GPRRegisterClass;
221    }
222  }
223  return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
224}
225
226const unsigned*
227ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
228  static const unsigned CalleeSavedRegs[] = {
229    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
230    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
231
232    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
233    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
234    0
235  };
236
237  static const unsigned DarwinCalleeSavedRegs[] = {
238    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
239    ARM::R11, ARM::R10, ARM::R9, ARM::R8,
240
241    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
242    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
243    0
244  };
245  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
246}
247
248const TargetRegisterClass* const *
249ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
250  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
251    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
252    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
253    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
254
255    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
256    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
257    0
258  };
259  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
260    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
261    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
262    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
263
264    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
265    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
266    0
267  };
268  return STI.isThumb() ? ThumbCalleeSavedRegClasses : CalleeSavedRegClasses;
269}
270
271BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
272  // FIXME: avoid re-calculating this everytime.
273  BitVector Reserved(getNumRegs());
274  Reserved.set(ARM::SP);
275  Reserved.set(ARM::PC);
276  if (STI.isTargetDarwin() || hasFP(MF))
277    Reserved.set(FramePtr);
278  // Some targets reserve R9.
279  if (STI.isR9Reserved())
280    Reserved.set(ARM::R9);
281  return Reserved;
282}
283
284bool
285ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
286  switch (Reg) {
287  default: break;
288  case ARM::SP:
289  case ARM::PC:
290    return true;
291  case ARM::R7:
292  case ARM::R11:
293    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
294      return true;
295    break;
296  case ARM::R9:
297    return STI.isR9Reserved();
298  }
299
300  return false;
301}
302
303const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
304  return &ARM::GPRRegClass;
305}
306
307/// getAllocationOrder - Returns the register allocation order for a specified
308/// register class in the form of a pair of TargetRegisterClass iterators.
309std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
310ARMRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
311                                    unsigned HintType, unsigned HintReg,
312                                    const MachineFunction &MF) const {
313  // Alternative register allocation orders when favoring even / odd registers
314  // of register pairs.
315
316  // No FP, R9 is available.
317  static const unsigned GPREven1[] = {
318    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
319    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
320    ARM::R9, ARM::R11
321  };
322  static const unsigned GPROdd1[] = {
323    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
324    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
325    ARM::R8, ARM::R10
326  };
327
328  // FP is R7, R9 is available.
329  static const unsigned GPREven2[] = {
330    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
331    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
332    ARM::R9, ARM::R11
333  };
334  static const unsigned GPROdd2[] = {
335    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
336    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
337    ARM::R8, ARM::R10
338  };
339
340  // FP is R11, R9 is available.
341  static const unsigned GPREven3[] = {
342    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
343    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
344    ARM::R9
345  };
346  static const unsigned GPROdd3[] = {
347    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
348    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
349    ARM::R8
350  };
351
352  // No FP, R9 is not available.
353  static const unsigned GPREven4[] = {
354    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
355    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
356    ARM::R11
357  };
358  static const unsigned GPROdd4[] = {
359    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
360    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
361    ARM::R10
362  };
363
364  // FP is R7, R9 is not available.
365  static const unsigned GPREven5[] = {
366    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
367    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
368    ARM::R11
369  };
370  static const unsigned GPROdd5[] = {
371    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
372    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
373    ARM::R10
374  };
375
376  // FP is R11, R9 is not available.
377  static const unsigned GPREven6[] = {
378    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
379    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
380  };
381  static const unsigned GPROdd6[] = {
382    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
383    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
384  };
385
386
387  if (HintType == ARMRI::RegPairEven) {
388    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
389      // It's no longer possible to fulfill this hint. Return the default
390      // allocation order.
391      return std::make_pair(RC->allocation_order_begin(MF),
392                            RC->allocation_order_end(MF));
393
394    if (!STI.isTargetDarwin() && !hasFP(MF)) {
395      if (!STI.isR9Reserved())
396        return std::make_pair(GPREven1,
397                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
398      else
399        return std::make_pair(GPREven4,
400                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
401    } else if (FramePtr == ARM::R7) {
402      if (!STI.isR9Reserved())
403        return std::make_pair(GPREven2,
404                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
405      else
406        return std::make_pair(GPREven5,
407                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
408    } else { // FramePtr == ARM::R11
409      if (!STI.isR9Reserved())
410        return std::make_pair(GPREven3,
411                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
412      else
413        return std::make_pair(GPREven6,
414                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
415    }
416  } else if (HintType == ARMRI::RegPairOdd) {
417    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
418      // It's no longer possible to fulfill this hint. Return the default
419      // allocation order.
420      return std::make_pair(RC->allocation_order_begin(MF),
421                            RC->allocation_order_end(MF));
422
423    if (!STI.isTargetDarwin() && !hasFP(MF)) {
424      if (!STI.isR9Reserved())
425        return std::make_pair(GPROdd1,
426                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
427      else
428        return std::make_pair(GPROdd4,
429                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
430    } else if (FramePtr == ARM::R7) {
431      if (!STI.isR9Reserved())
432        return std::make_pair(GPROdd2,
433                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
434      else
435        return std::make_pair(GPROdd5,
436                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
437    } else { // FramePtr == ARM::R11
438      if (!STI.isR9Reserved())
439        return std::make_pair(GPROdd3,
440                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
441      else
442        return std::make_pair(GPROdd6,
443                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
444    }
445  }
446  return std::make_pair(RC->allocation_order_begin(MF),
447                        RC->allocation_order_end(MF));
448}
449
450/// ResolveRegAllocHint - Resolves the specified register allocation hint
451/// to a physical register. Returns the physical register if it is successful.
452unsigned
453ARMRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
454                                     const MachineFunction &MF) const {
455  if (Reg == 0 || !isPhysicalRegister(Reg))
456    return 0;
457  if (Type == 0)
458    return Reg;
459  else if (Type == (unsigned)ARMRI::RegPairOdd)
460    // Odd register.
461    return getRegisterPairOdd(Reg, MF);
462  else if (Type == (unsigned)ARMRI::RegPairEven)
463    // Even register.
464    return getRegisterPairEven(Reg, MF);
465  return 0;
466}
467
468void
469ARMRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
470                                    MachineFunction &MF) const {
471  MachineRegisterInfo *MRI = &MF.getRegInfo();
472  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
473  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
474       Hint.first == (unsigned)ARMRI::RegPairEven) &&
475      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
476    // If 'Reg' is one of the even / odd register pair and it's now changed
477    // (e.g. coalesced) into a different register. The other register of the
478    // pair allocation hint must be updated to reflect the relationship
479    // change.
480    unsigned OtherReg = Hint.second;
481    Hint = MRI->getRegAllocationHint(OtherReg);
482    if (Hint.second == Reg)
483      // Make sure the pair has not already divorced.
484      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
485  }
486}
487
488bool
489ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
490  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
491  return ThumbRegScavenging || !AFI->isThumbFunction();
492}
493
494/// hasFP - Return true if the specified function should have a dedicated frame
495/// pointer register.  This is true if the function has variable sized allocas
496/// or if frame pointer elimination is disabled.
497///
498bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
499  const MachineFrameInfo *MFI = MF.getFrameInfo();
500  return NoFramePointerElim || MFI->hasVarSizedObjects();
501}
502
503// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
504// not required, we reserve argument space for call sites in the function
505// immediately on entry to the current function. This eliminates the need for
506// add/sub sp brackets around call sites. Returns true if the call frame is
507// included as part of the stack frame.
508bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
509  const MachineFrameInfo *FFI = MF.getFrameInfo();
510  unsigned CFSize = FFI->getMaxCallFrameSize();
511  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
512  // It's not always a good idea to include the call frame as part of the
513  // stack frame. ARM (especially Thumb) has small immediate offset to
514  // address the stack frame. So a large call frame can cause poor codegen
515  // and may even makes it impossible to scavenge a register.
516  if (AFI->isThumbFunction()) {
517    if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
518      return false;
519  } else {
520    if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
521      return false;
522  }
523  return !MF.getFrameInfo()->hasVarSizedObjects();
524}
525
526/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
527/// a destreg = basereg + immediate in ARM code.
528static
529void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
530                             MachineBasicBlock::iterator &MBBI,
531                             unsigned DestReg, unsigned BaseReg, int NumBytes,
532                             ARMCC::CondCodes Pred, unsigned PredReg,
533                             const TargetInstrInfo &TII,
534                             DebugLoc dl) {
535  bool isSub = NumBytes < 0;
536  if (isSub) NumBytes = -NumBytes;
537
538  while (NumBytes) {
539    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
540    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
541    assert(ThisVal && "Didn't extract field correctly");
542
543    // We will handle these bits from offset, clear them.
544    NumBytes &= ~ThisVal;
545
546    // Get the properly encoded SOImmVal field.
547    int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
548    assert(SOImmVal != -1 && "Bit extraction didn't work?");
549
550    // Build the new ADD / SUB.
551    BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
552      .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
553      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
554    BaseReg = DestReg;
555  }
556}
557
558/// calcNumMI - Returns the number of instructions required to materialize
559/// the specific add / sub r, c instruction.
560static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
561                          unsigned NumBits, unsigned Scale) {
562  unsigned NumMIs = 0;
563  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
564
565  if (Opc == ARM::tADDrSPi) {
566    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
567    Bytes -= ThisVal;
568    NumMIs++;
569    NumBits = 8;
570    Scale = 1;  // Followed by a number of tADDi8.
571    Chunk = ((1 << NumBits) - 1) * Scale;
572  }
573
574  NumMIs += Bytes / Chunk;
575  if ((Bytes % Chunk) != 0)
576    NumMIs++;
577  if (ExtraOpc)
578    NumMIs++;
579  return NumMIs;
580}
581
582/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
583/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
584/// in a register using mov / mvn sequences or load the immediate from a
585/// constpool entry.
586static
587void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
588                              MachineBasicBlock::iterator &MBBI,
589                              unsigned DestReg, unsigned BaseReg,
590                              int NumBytes, bool CanChangeCC,
591                              const TargetInstrInfo &TII,
592                              const ARMRegisterInfo& MRI,
593                              DebugLoc dl) {
594    bool isHigh = !MRI.isLowRegister(DestReg) ||
595                  (BaseReg != 0 && !MRI.isLowRegister(BaseReg));
596    bool isSub = false;
597    // Subtract doesn't have high register version. Load the negative value
598    // if either base or dest register is a high register. Also, if do not
599    // issue sub as part of the sequence if condition register is to be
600    // preserved.
601    if (NumBytes < 0 && !isHigh && CanChangeCC) {
602      isSub = true;
603      NumBytes = -NumBytes;
604    }
605    unsigned LdReg = DestReg;
606    if (DestReg == ARM::SP) {
607      assert(BaseReg == ARM::SP && "Unexpected!");
608      LdReg = ARM::R3;
609      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
610        .addReg(ARM::R3, RegState::Kill);
611    }
612
613    if (NumBytes <= 255 && NumBytes >= 0)
614      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
615    else if (NumBytes < 0 && NumBytes >= -255) {
616      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
617      BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
618        .addReg(LdReg, RegState::Kill);
619    } else
620      MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII,
621                            true, dl);
622
623    // Emit add / sub.
624    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
625    const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
626                                            TII.get(Opc), DestReg);
627    if (DestReg == ARM::SP || isSub)
628      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
629    else
630      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
631    if (DestReg == ARM::SP)
632      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
633        .addReg(ARM::R12, RegState::Kill);
634}
635
636/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
637/// a destreg = basereg + immediate in Thumb code.
638static
639void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
640                               MachineBasicBlock::iterator &MBBI,
641                               unsigned DestReg, unsigned BaseReg,
642                               int NumBytes, const TargetInstrInfo &TII,
643                               const ARMRegisterInfo& MRI,
644                               DebugLoc dl) {
645  bool isSub = NumBytes < 0;
646  unsigned Bytes = (unsigned)NumBytes;
647  if (isSub) Bytes = -NumBytes;
648  bool isMul4 = (Bytes & 3) == 0;
649  bool isTwoAddr = false;
650  bool DstNotEqBase = false;
651  unsigned NumBits = 1;
652  unsigned Scale = 1;
653  int Opc = 0;
654  int ExtraOpc = 0;
655
656  if (DestReg == BaseReg && BaseReg == ARM::SP) {
657    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
658    NumBits = 7;
659    Scale = 4;
660    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
661    isTwoAddr = true;
662  } else if (!isSub && BaseReg == ARM::SP) {
663    // r1 = add sp, 403
664    // =>
665    // r1 = add sp, 100 * 4
666    // r1 = add r1, 3
667    if (!isMul4) {
668      Bytes &= ~3;
669      ExtraOpc = ARM::tADDi3;
670    }
671    NumBits = 8;
672    Scale = 4;
673    Opc = ARM::tADDrSPi;
674  } else {
675    // sp = sub sp, c
676    // r1 = sub sp, c
677    // r8 = sub sp, c
678    if (DestReg != BaseReg)
679      DstNotEqBase = true;
680    NumBits = 8;
681    Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
682    isTwoAddr = true;
683  }
684
685  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
686  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
687  if (NumMIs > Threshold) {
688    // This will expand into too many instructions. Load the immediate from a
689    // constpool entry.
690    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
691                             MRI, dl);
692    return;
693  }
694
695  if (DstNotEqBase) {
696    if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
697      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
698      unsigned Chunk = (1 << 3) - 1;
699      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
700      Bytes -= ThisVal;
701      BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
702        .addReg(BaseReg, RegState::Kill).addImm(ThisVal);
703    } else {
704      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
705        .addReg(BaseReg, RegState::Kill);
706    }
707    BaseReg = DestReg;
708  }
709
710  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
711  while (Bytes) {
712    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
713    Bytes -= ThisVal;
714    ThisVal /= Scale;
715    // Build the new tADD / tSUB.
716    if (isTwoAddr)
717      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
718        .addReg(DestReg).addImm(ThisVal);
719    else {
720      bool isKill = BaseReg != ARM::SP;
721      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
722        .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
723      BaseReg = DestReg;
724
725      if (Opc == ARM::tADDrSPi) {
726        // r4 = add sp, imm
727        // r4 = add r4, imm
728        // ...
729        NumBits = 8;
730        Scale = 1;
731        Chunk = ((1 << NumBits) - 1) * Scale;
732        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
733        isTwoAddr = true;
734      }
735    }
736  }
737
738  if (ExtraOpc)
739    BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
740      .addReg(DestReg, RegState::Kill)
741      .addImm(((unsigned)NumBytes) & 3);
742}
743
744static
745void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
746                  int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
747                  bool isThumb, const TargetInstrInfo &TII,
748                  const ARMRegisterInfo& MRI,
749                  DebugLoc dl) {
750  if (isThumb)
751    emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
752                              MRI, dl);
753  else
754    emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
755                            Pred, PredReg, TII, dl);
756}
757
758void ARMRegisterInfo::
759eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
760                              MachineBasicBlock::iterator I) const {
761  if (!hasReservedCallFrame(MF)) {
762    // If we have alloca, convert as follows:
763    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
764    // ADJCALLSTACKUP   -> add, sp, sp, amount
765    MachineInstr *Old = I;
766    DebugLoc dl = Old->getDebugLoc();
767    unsigned Amount = Old->getOperand(0).getImm();
768    if (Amount != 0) {
769      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
770      // We need to keep the stack aligned properly.  To do this, we round the
771      // amount of space needed for the outgoing arguments up to the next
772      // alignment boundary.
773      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
774      Amount = (Amount+Align-1)/Align*Align;
775
776      // Replace the pseudo instruction with a new instruction...
777      unsigned Opc = Old->getOpcode();
778      bool isThumb = AFI->isThumbFunction();
779      ARMCC::CondCodes Pred = isThumb
780        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
781      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
782        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
783        unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
784        emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl);
785      } else {
786        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
787        unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
788        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
789        emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl);
790      }
791    }
792  }
793  MBB.erase(I);
794}
795
796/// emitThumbConstant - Emit a series of instructions to materialize a
797/// constant.
798static void emitThumbConstant(MachineBasicBlock &MBB,
799                              MachineBasicBlock::iterator &MBBI,
800                              unsigned DestReg, int Imm,
801                              const TargetInstrInfo &TII,
802                              const ARMRegisterInfo& MRI,
803                              DebugLoc dl) {
804  bool isSub = Imm < 0;
805  if (isSub) Imm = -Imm;
806
807  int Chunk = (1 << 8) - 1;
808  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
809  Imm -= ThisVal;
810  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
811  if (Imm > 0)
812    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
813  if (isSub)
814    BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
815      .addReg(DestReg, RegState::Kill);
816}
817
818/// findScratchRegister - Find a 'free' ARM register. If register scavenger
819/// is not being used, R12 is available. Otherwise, try for a call-clobbered
820/// register first and then a spilled callee-saved register if that fails.
821static
822unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
823                             ARMFunctionInfo *AFI) {
824  unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
825  assert (!AFI->isThumbFunction());
826  if (Reg == 0)
827    // Try a already spilled CS register.
828    Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
829
830  return Reg;
831}
832
833void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
834                                          int SPAdj, RegScavenger *RS) const{
835  unsigned i = 0;
836  MachineInstr &MI = *II;
837  MachineBasicBlock &MBB = *MI.getParent();
838  MachineFunction &MF = *MBB.getParent();
839  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
840  bool isThumb = AFI->isThumbFunction();
841  DebugLoc dl = MI.getDebugLoc();
842
843  while (!MI.getOperand(i).isFI()) {
844    ++i;
845    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
846  }
847
848  unsigned FrameReg = ARM::SP;
849  int FrameIndex = MI.getOperand(i).getIndex();
850  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
851               MF.getFrameInfo()->getStackSize() + SPAdj;
852
853  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
854    Offset -= AFI->getGPRCalleeSavedArea1Offset();
855  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
856    Offset -= AFI->getGPRCalleeSavedArea2Offset();
857  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
858    Offset -= AFI->getDPRCalleeSavedAreaOffset();
859  else if (hasFP(MF)) {
860    assert(SPAdj == 0 && "Unexpected");
861    // There is alloca()'s in this function, must reference off the frame
862    // pointer instead.
863    FrameReg = getFrameRegister(MF);
864    Offset -= AFI->getFramePtrSpillOffset();
865  }
866
867  unsigned Opcode = MI.getOpcode();
868  const TargetInstrDesc &Desc = MI.getDesc();
869  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
870  bool isSub = false;
871
872  // Memory operands in inline assembly always use AddrMode2.
873  if (Opcode == ARM::INLINEASM)
874    AddrMode = ARMII::AddrMode2;
875
876  if (Opcode == ARM::ADDri) {
877    Offset += MI.getOperand(i+1).getImm();
878    if (Offset == 0) {
879      // Turn it into a move.
880      MI.setDesc(TII.get(ARM::MOVr));
881      MI.getOperand(i).ChangeToRegister(FrameReg, false);
882      MI.RemoveOperand(i+1);
883      return;
884    } else if (Offset < 0) {
885      Offset = -Offset;
886      isSub = true;
887      MI.setDesc(TII.get(ARM::SUBri));
888    }
889
890    // Common case: small offset, fits into instruction.
891    int ImmedOffset = ARM_AM::getSOImmVal(Offset);
892    if (ImmedOffset != -1) {
893      // Replace the FrameIndex with sp / fp
894      MI.getOperand(i).ChangeToRegister(FrameReg, false);
895      MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
896      return;
897    }
898
899    // Otherwise, we fallback to common code below to form the imm offset with
900    // a sequence of ADDri instructions.  First though, pull as much of the imm
901    // into this ADDri as possible.
902    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
903    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
904
905    // We will handle these bits from offset, clear them.
906    Offset &= ~ThisImmVal;
907
908    // Get the properly encoded SOImmVal field.
909    int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
910    assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
911    MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
912  } else if (Opcode == ARM::tADDrSPi) {
913    Offset += MI.getOperand(i+1).getImm();
914
915    // Can't use tADDrSPi if it's based off the frame pointer.
916    unsigned NumBits = 0;
917    unsigned Scale = 1;
918    if (FrameReg != ARM::SP) {
919      Opcode = ARM::tADDi3;
920      MI.setDesc(TII.get(ARM::tADDi3));
921      NumBits = 3;
922    } else {
923      NumBits = 8;
924      Scale = 4;
925      assert((Offset & 3) == 0 &&
926             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
927    }
928
929    if (Offset == 0) {
930      // Turn it into a move.
931      MI.setDesc(TII.get(ARM::tMOVhir2lor));
932      MI.getOperand(i).ChangeToRegister(FrameReg, false);
933      MI.RemoveOperand(i+1);
934      return;
935    }
936
937    // Common case: small offset, fits into instruction.
938    unsigned Mask = (1 << NumBits) - 1;
939    if (((Offset / Scale) & ~Mask) == 0) {
940      // Replace the FrameIndex with sp / fp
941      MI.getOperand(i).ChangeToRegister(FrameReg, false);
942      MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
943      return;
944    }
945
946    unsigned DestReg = MI.getOperand(0).getReg();
947    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
948    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
949    // MI would expand into a large number of instructions. Don't try to
950    // simplify the immediate.
951    if (NumMIs > 2) {
952      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
953                                *this, dl);
954      MBB.erase(II);
955      return;
956    }
957
958    if (Offset > 0) {
959      // Translate r0 = add sp, imm to
960      // r0 = add sp, 255*4
961      // r0 = add r0, (imm - 255*4)
962      MI.getOperand(i).ChangeToRegister(FrameReg, false);
963      MI.getOperand(i+1).ChangeToImmediate(Mask);
964      Offset = (Offset - Mask * Scale);
965      MachineBasicBlock::iterator NII = next(II);
966      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
967                                *this, dl);
968    } else {
969      // Translate r0 = add sp, -imm to
970      // r0 = -imm (this is then translated into a series of instructons)
971      // r0 = add r0, sp
972      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
973      MI.setDesc(TII.get(ARM::tADDhirr));
974      MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
975      MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
976    }
977    return;
978  } else {
979    unsigned ImmIdx = 0;
980    int InstrOffs = 0;
981    unsigned NumBits = 0;
982    unsigned Scale = 1;
983    switch (AddrMode) {
984    case ARMII::AddrMode2: {
985      ImmIdx = i+2;
986      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
987      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
988        InstrOffs *= -1;
989      NumBits = 12;
990      break;
991    }
992    case ARMII::AddrMode3: {
993      ImmIdx = i+2;
994      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
995      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
996        InstrOffs *= -1;
997      NumBits = 8;
998      break;
999    }
1000    case ARMII::AddrMode5: {
1001      ImmIdx = i+1;
1002      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1003      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1004        InstrOffs *= -1;
1005      NumBits = 8;
1006      Scale = 4;
1007      break;
1008    }
1009    case ARMII::AddrModeTs: {
1010      ImmIdx = i+1;
1011      InstrOffs = MI.getOperand(ImmIdx).getImm();
1012      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
1013      Scale = 4;
1014      break;
1015    }
1016    default:
1017      assert(0 && "Unsupported addressing mode!");
1018      abort();
1019      break;
1020    }
1021
1022    Offset += InstrOffs * Scale;
1023    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1024    if (Offset < 0 && !isThumb) {
1025      Offset = -Offset;
1026      isSub = true;
1027    }
1028
1029    // Common case: small offset, fits into instruction.
1030    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1031    int ImmedOffset = Offset / Scale;
1032    unsigned Mask = (1 << NumBits) - 1;
1033    if ((unsigned)Offset <= Mask * Scale) {
1034      // Replace the FrameIndex with sp
1035      MI.getOperand(i).ChangeToRegister(FrameReg, false);
1036      if (isSub)
1037        ImmedOffset |= 1 << NumBits;
1038      ImmOp.ChangeToImmediate(ImmedOffset);
1039      return;
1040    }
1041
1042    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
1043    if (AddrMode == ARMII::AddrModeTs) {
1044      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
1045      // a different base register.
1046      NumBits = 5;
1047      Mask = (1 << NumBits) - 1;
1048    }
1049    // If this is a thumb spill / restore, we will be using a constpool load to
1050    // materialize the offset.
1051    if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
1052      ImmOp.ChangeToImmediate(0);
1053    else {
1054      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1055      ImmedOffset = ImmedOffset & Mask;
1056      if (isSub)
1057        ImmedOffset |= 1 << NumBits;
1058      ImmOp.ChangeToImmediate(ImmedOffset);
1059      Offset &= ~(Mask*Scale);
1060    }
1061  }
1062
1063  // If we get here, the immediate doesn't fit into the instruction.  We folded
1064  // as much as possible above, handle the rest, providing a register that is
1065  // SP+LargeImm.
1066  assert(Offset && "This code isn't needed if offset already handled!");
1067
1068  if (isThumb) {
1069    if (Desc.mayLoad()) {
1070      // Use the destination register to materialize sp + offset.
1071      unsigned TmpReg = MI.getOperand(0).getReg();
1072      bool UseRR = false;
1073      if (Opcode == ARM::tRestore) {
1074        if (FrameReg == ARM::SP)
1075          emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
1076                                   Offset, false, TII, *this, dl);
1077        else {
1078          emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
1079                            true, dl);
1080          UseRR = true;
1081        }
1082      } else
1083        emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
1084                                  *this, dl);
1085      MI.setDesc(TII.get(ARM::tLDR));
1086      MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1087      if (UseRR)
1088        // Use [reg, reg] addrmode.
1089        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
1090      else  // tLDR has an extra register operand.
1091        MI.addOperand(MachineOperand::CreateReg(0, false));
1092    } else if (Desc.mayStore()) {
1093      // FIXME! This is horrific!!! We need register scavenging.
1094      // Our temporary workaround has marked r3 unavailable. Of course, r3 is
1095      // also a ABI register so it's possible that is is the register that is
1096      // being storing here. If that's the case, we do the following:
1097      // r12 = r2
1098      // Use r2 to materialize sp + offset
1099      // str r3, r2
1100      // r2 = r12
1101      unsigned ValReg = MI.getOperand(0).getReg();
1102      unsigned TmpReg = ARM::R3;
1103      bool UseRR = false;
1104      if (ValReg == ARM::R3) {
1105        BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
1106          .addReg(ARM::R2, RegState::Kill);
1107        TmpReg = ARM::R2;
1108      }
1109      if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1110        BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
1111          .addReg(ARM::R3, RegState::Kill);
1112      if (Opcode == ARM::tSpill) {
1113        if (FrameReg == ARM::SP)
1114          emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
1115                                   Offset, false, TII, *this, dl);
1116        else {
1117          emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
1118                            true, dl);
1119          UseRR = true;
1120        }
1121      } else
1122        emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
1123                                  *this, dl);
1124      MI.setDesc(TII.get(ARM::tSTR));
1125      MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1126      if (UseRR)  // Use [reg, reg] addrmode.
1127        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
1128      else // tSTR has an extra register operand.
1129        MI.addOperand(MachineOperand::CreateReg(0, false));
1130
1131      MachineBasicBlock::iterator NII = next(II);
1132      if (ValReg == ARM::R3)
1133        BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
1134          .addReg(ARM::R12, RegState::Kill);
1135      if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1136        BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
1137          .addReg(ARM::R12, RegState::Kill);
1138    } else
1139      assert(false && "Unexpected opcode!");
1140  } else {
1141    // Insert a set of r12 with the full address: r12 = sp + offset
1142    // If the offset we have is too large to fit into the instruction, we need
1143    // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
1144    // out of 'Offset'.
1145    unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1146    if (ScratchReg == 0)
1147      // No register is "free". Scavenge a register.
1148      ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1149    int PIdx = MI.findFirstPredOperandIdx();
1150    ARMCC::CondCodes Pred = (PIdx == -1)
1151      ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1152    unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1153    emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1154                            isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
1155    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1156  }
1157}
1158
1159static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1160  const MachineFrameInfo *FFI = MF.getFrameInfo();
1161  int Offset = 0;
1162  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1163    int FixedOff = -FFI->getObjectOffset(i);
1164    if (FixedOff > Offset) Offset = FixedOff;
1165  }
1166  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1167    if (FFI->isDeadObjectIndex(i))
1168      continue;
1169    Offset += FFI->getObjectSize(i);
1170    unsigned Align = FFI->getObjectAlignment(i);
1171    // Adjust to alignment boundary
1172    Offset = (Offset+Align-1)/Align*Align;
1173  }
1174  return (unsigned)Offset;
1175}
1176
1177void
1178ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1179                                                      RegScavenger *RS) const {
1180  // This tells PEI to spill the FP as if it is any other callee-save register
1181  // to take advantage the eliminateFrameIndex machinery. This also ensures it
1182  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1183  // to combine multiple loads / stores.
1184  bool CanEliminateFrame = true;
1185  bool CS1Spilled = false;
1186  bool LRSpilled = false;
1187  unsigned NumGPRSpills = 0;
1188  SmallVector<unsigned, 4> UnspilledCS1GPRs;
1189  SmallVector<unsigned, 4> UnspilledCS2GPRs;
1190  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1191
1192  // Don't spill FP if the frame can be eliminated. This is determined
1193  // by scanning the callee-save registers to see if any is used.
1194  const unsigned *CSRegs = getCalleeSavedRegs();
1195  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1196  for (unsigned i = 0; CSRegs[i]; ++i) {
1197    unsigned Reg = CSRegs[i];
1198    bool Spilled = false;
1199    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
1200      AFI->setCSRegisterIsSpilled(Reg);
1201      Spilled = true;
1202      CanEliminateFrame = false;
1203    } else {
1204      // Check alias registers too.
1205      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1206        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
1207          Spilled = true;
1208          CanEliminateFrame = false;
1209        }
1210      }
1211    }
1212
1213    if (CSRegClasses[i] == &ARM::GPRRegClass) {
1214      if (Spilled) {
1215        NumGPRSpills++;
1216
1217        if (!STI.isTargetDarwin()) {
1218          if (Reg == ARM::LR)
1219            LRSpilled = true;
1220          CS1Spilled = true;
1221          continue;
1222        }
1223
1224        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1225        switch (Reg) {
1226        case ARM::LR:
1227          LRSpilled = true;
1228          // Fallthrough
1229        case ARM::R4:
1230        case ARM::R5:
1231        case ARM::R6:
1232        case ARM::R7:
1233          CS1Spilled = true;
1234          break;
1235        default:
1236          break;
1237        }
1238      } else {
1239        if (!STI.isTargetDarwin()) {
1240          UnspilledCS1GPRs.push_back(Reg);
1241          continue;
1242        }
1243
1244        switch (Reg) {
1245        case ARM::R4:
1246        case ARM::R5:
1247        case ARM::R6:
1248        case ARM::R7:
1249        case ARM::LR:
1250          UnspilledCS1GPRs.push_back(Reg);
1251          break;
1252        default:
1253          UnspilledCS2GPRs.push_back(Reg);
1254          break;
1255        }
1256      }
1257    }
1258  }
1259
1260  bool ForceLRSpill = false;
1261  if (!LRSpilled && AFI->isThumbFunction()) {
1262    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
1263    // Force LR to be spilled if the Thumb function size is > 2048. This enables
1264    // use of BL to implement far jump. If it turns out that it's not needed
1265    // then the branch fix up path will undo it.
1266    if (FnSize >= (1 << 11)) {
1267      CanEliminateFrame = false;
1268      ForceLRSpill = true;
1269    }
1270  }
1271
1272  bool ExtraCSSpill = false;
1273  if (!CanEliminateFrame || hasFP(MF)) {
1274    AFI->setHasStackFrame(true);
1275
1276    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1277    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1278    if (!LRSpilled && CS1Spilled) {
1279      MF.getRegInfo().setPhysRegUsed(ARM::LR);
1280      AFI->setCSRegisterIsSpilled(ARM::LR);
1281      NumGPRSpills++;
1282      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1283                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1284      ForceLRSpill = false;
1285      ExtraCSSpill = true;
1286    }
1287
1288    // Darwin ABI requires FP to point to the stack slot that contains the
1289    // previous FP.
1290    if (STI.isTargetDarwin() || hasFP(MF)) {
1291      MF.getRegInfo().setPhysRegUsed(FramePtr);
1292      NumGPRSpills++;
1293    }
1294
1295    // If stack and double are 8-byte aligned and we are spilling an odd number
1296    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1297    // the integer and double callee save areas.
1298    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1299    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1300      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1301        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1302          unsigned Reg = UnspilledCS1GPRs[i];
1303          // Don't spiil high register if the function is thumb
1304          if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1305            MF.getRegInfo().setPhysRegUsed(Reg);
1306            AFI->setCSRegisterIsSpilled(Reg);
1307            if (!isReservedReg(MF, Reg))
1308              ExtraCSSpill = true;
1309            break;
1310          }
1311        }
1312      } else if (!UnspilledCS2GPRs.empty() &&
1313                 !AFI->isThumbFunction()) {
1314        unsigned Reg = UnspilledCS2GPRs.front();
1315        MF.getRegInfo().setPhysRegUsed(Reg);
1316        AFI->setCSRegisterIsSpilled(Reg);
1317        if (!isReservedReg(MF, Reg))
1318          ExtraCSSpill = true;
1319      }
1320    }
1321
1322    // Estimate if we might need to scavenge a register at some point in order
1323    // to materialize a stack offset. If so, either spill one additiona
1324    // callee-saved register or reserve a special spill slot to facilitate
1325    // register scavenging.
1326    if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1327      MachineFrameInfo  *MFI = MF.getFrameInfo();
1328      unsigned Size = estimateStackSize(MF, MFI);
1329      unsigned Limit = (1 << 12) - 1;
1330      for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1331        for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1332          for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1333            if (I->getOperand(i).isFI()) {
1334              unsigned Opcode = I->getOpcode();
1335              const TargetInstrDesc &Desc = TII.get(Opcode);
1336              unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1337              if (AddrMode == ARMII::AddrMode3) {
1338                Limit = (1 << 8) - 1;
1339                goto DoneEstimating;
1340              } else if (AddrMode == ARMII::AddrMode5) {
1341                unsigned ThisLimit = ((1 << 8) - 1) * 4;
1342                if (ThisLimit < Limit)
1343                  Limit = ThisLimit;
1344              }
1345            }
1346        }
1347    DoneEstimating:
1348      if (Size >= Limit) {
1349        // If any non-reserved CS register isn't spilled, just spill one or two
1350        // extra. That should take care of it!
1351        unsigned NumExtras = TargetAlign / 4;
1352        SmallVector<unsigned, 2> Extras;
1353        while (NumExtras && !UnspilledCS1GPRs.empty()) {
1354          unsigned Reg = UnspilledCS1GPRs.back();
1355          UnspilledCS1GPRs.pop_back();
1356          if (!isReservedReg(MF, Reg)) {
1357            Extras.push_back(Reg);
1358            NumExtras--;
1359          }
1360        }
1361        while (NumExtras && !UnspilledCS2GPRs.empty()) {
1362          unsigned Reg = UnspilledCS2GPRs.back();
1363          UnspilledCS2GPRs.pop_back();
1364          if (!isReservedReg(MF, Reg)) {
1365            Extras.push_back(Reg);
1366            NumExtras--;
1367          }
1368        }
1369        if (Extras.size() && NumExtras == 0) {
1370          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1371            MF.getRegInfo().setPhysRegUsed(Extras[i]);
1372            AFI->setCSRegisterIsSpilled(Extras[i]);
1373          }
1374        } else {
1375          // Reserve a slot closest to SP or frame pointer.
1376          const TargetRegisterClass *RC = &ARM::GPRRegClass;
1377          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1378                                                           RC->getAlignment()));
1379        }
1380      }
1381    }
1382  }
1383
1384  if (ForceLRSpill) {
1385    MF.getRegInfo().setPhysRegUsed(ARM::LR);
1386    AFI->setCSRegisterIsSpilled(ARM::LR);
1387    AFI->setLRIsSpilledForFarJump(true);
1388  }
1389}
1390
1391/// Move iterator pass the next bunch of callee save load / store ops for
1392/// the particular spill area (1: integer area 1, 2: integer area 2,
1393/// 3: fp area, 0: don't care).
1394static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1395                                   MachineBasicBlock::iterator &MBBI,
1396                                   int Opc, unsigned Area,
1397                                   const ARMSubtarget &STI) {
1398  while (MBBI != MBB.end() &&
1399         MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1400    if (Area != 0) {
1401      bool Done = false;
1402      unsigned Category = 0;
1403      switch (MBBI->getOperand(0).getReg()) {
1404      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1405      case ARM::LR:
1406        Category = 1;
1407        break;
1408      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1409        Category = STI.isTargetDarwin() ? 2 : 1;
1410        break;
1411      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1412      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1413        Category = 3;
1414        break;
1415      default:
1416        Done = true;
1417        break;
1418      }
1419      if (Done || Category != Area)
1420        break;
1421    }
1422
1423    ++MBBI;
1424  }
1425}
1426
1427void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1428  MachineBasicBlock &MBB = MF.front();
1429  MachineBasicBlock::iterator MBBI = MBB.begin();
1430  MachineFrameInfo  *MFI = MF.getFrameInfo();
1431  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1432  bool isThumb = AFI->isThumbFunction();
1433  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1434  unsigned NumBytes = MFI->getStackSize();
1435  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1436  DebugLoc dl = (MBBI != MBB.end() ?
1437                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1438
1439  if (isThumb) {
1440    // Check if R3 is live in. It might have to be used as a scratch register.
1441    for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1442         E = MF.getRegInfo().livein_end(); I != E; ++I) {
1443      if (I->first == ARM::R3) {
1444        AFI->setR3IsLiveIn(true);
1445        break;
1446      }
1447    }
1448
1449    // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1450    NumBytes = (NumBytes + 3) & ~3;
1451    MFI->setStackSize(NumBytes);
1452  }
1453
1454  // Determine the sizes of each callee-save spill areas and record which frame
1455  // belongs to which callee-save spill areas.
1456  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1457  int FramePtrSpillFI = 0;
1458
1459  if (VARegSaveSize)
1460    emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
1461                 *this, dl);
1462
1463  if (!AFI->hasStackFrame()) {
1464    if (NumBytes != 0)
1465      emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1466    return;
1467  }
1468
1469  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1470    unsigned Reg = CSI[i].getReg();
1471    int FI = CSI[i].getFrameIdx();
1472    switch (Reg) {
1473    case ARM::R4:
1474    case ARM::R5:
1475    case ARM::R6:
1476    case ARM::R7:
1477    case ARM::LR:
1478      if (Reg == FramePtr)
1479        FramePtrSpillFI = FI;
1480      AFI->addGPRCalleeSavedArea1Frame(FI);
1481      GPRCS1Size += 4;
1482      break;
1483    case ARM::R8:
1484    case ARM::R9:
1485    case ARM::R10:
1486    case ARM::R11:
1487      if (Reg == FramePtr)
1488        FramePtrSpillFI = FI;
1489      if (STI.isTargetDarwin()) {
1490        AFI->addGPRCalleeSavedArea2Frame(FI);
1491        GPRCS2Size += 4;
1492      } else {
1493        AFI->addGPRCalleeSavedArea1Frame(FI);
1494        GPRCS1Size += 4;
1495      }
1496      break;
1497    default:
1498      AFI->addDPRCalleeSavedAreaFrame(FI);
1499      DPRCSSize += 8;
1500    }
1501  }
1502
1503  if (!isThumb) {
1504    // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1505    emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl);
1506    movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1507  } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
1508    ++MBBI;
1509    if (MBBI != MBB.end())
1510      dl = MBBI->getDebugLoc();
1511  }
1512
1513  // Darwin ABI requires FP to point to the stack slot that contains the
1514  // previous FP.
1515  if (STI.isTargetDarwin() || hasFP(MF)) {
1516    MachineInstrBuilder MIB =
1517      BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),
1518              FramePtr)
1519      .addFrameIndex(FramePtrSpillFI).addImm(0);
1520    if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
1521  }
1522
1523  if (!isThumb) {
1524    // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1525    emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl);
1526
1527    // Build the new SUBri to adjust SP for FP callee-save spill area.
1528    movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1529    emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl);
1530  }
1531
1532  // Determine starting offsets of spill areas.
1533  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1534  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1535  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1536  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1537  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1538  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1539  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1540
1541  NumBytes = DPRCSOffset;
1542  if (NumBytes) {
1543    // Insert it after all the callee-save spills.
1544    if (!isThumb)
1545      movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1546    emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1547  }
1548
1549  if(STI.isTargetELF() && hasFP(MF)) {
1550    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1551                             AFI->getFramePtrSpillOffset());
1552  }
1553
1554  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1555  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1556  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1557}
1558
1559static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1560  for (unsigned i = 0; CSRegs[i]; ++i)
1561    if (Reg == CSRegs[i])
1562      return true;
1563  return false;
1564}
1565
1566static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1567  return ((MI->getOpcode() == ARM::FLDD ||
1568           MI->getOpcode() == ARM::LDR  ||
1569           MI->getOpcode() == ARM::tRestore) &&
1570          MI->getOperand(1).isFI() &&
1571          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1572}
1573
1574void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1575                                   MachineBasicBlock &MBB) const {
1576  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1577  assert((MBBI->getOpcode() == ARM::BX_RET ||
1578          MBBI->getOpcode() == ARM::tBX_RET ||
1579          MBBI->getOpcode() == ARM::tPOP_RET) &&
1580         "Can only insert epilog into returning blocks");
1581  DebugLoc dl = MBBI->getDebugLoc();
1582  MachineFrameInfo *MFI = MF.getFrameInfo();
1583  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1584  bool isThumb = AFI->isThumbFunction();
1585  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1586  int NumBytes = (int)MFI->getStackSize();
1587
1588  if (!AFI->hasStackFrame()) {
1589    if (NumBytes != 0)
1590      emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1591  } else {
1592    // Unwind MBBI to point to first LDR / FLDD.
1593    const unsigned *CSRegs = getCalleeSavedRegs();
1594    if (MBBI != MBB.begin()) {
1595      do
1596        --MBBI;
1597      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1598      if (!isCSRestore(MBBI, CSRegs))
1599        ++MBBI;
1600    }
1601
1602    // Move SP to start of FP callee save spill area.
1603    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1604                 AFI->getGPRCalleeSavedArea2Size() +
1605                 AFI->getDPRCalleeSavedAreaSize());
1606    if (isThumb) {
1607      if (hasFP(MF)) {
1608        NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1609        // Reset SP based on frame pointer only if the stack frame extends beyond
1610        // frame pointer stack slot or target is ELF and the function has FP.
1611        if (NumBytes)
1612          emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
1613                                    TII, *this, dl);
1614        else
1615          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
1616            .addReg(FramePtr);
1617      } else {
1618        if (MBBI->getOpcode() == ARM::tBX_RET &&
1619            &MBB.front() != MBBI &&
1620            prior(MBBI)->getOpcode() == ARM::tPOP) {
1621          MachineBasicBlock::iterator PMBBI = prior(MBBI);
1622          emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
1623                       *this, dl);
1624        } else
1625          emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
1626                       *this, dl);
1627      }
1628    } else {
1629      // Darwin ABI requires FP to point to the stack slot that contains the
1630      // previous FP.
1631      if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1632        NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1633        // Reset SP based on frame pointer only if the stack frame extends beyond
1634        // frame pointer stack slot or target is ELF and the function has FP.
1635        if (AFI->getGPRCalleeSavedArea2Size() ||
1636            AFI->getDPRCalleeSavedAreaSize()  ||
1637            AFI->getDPRCalleeSavedAreaOffset()||
1638            hasFP(MF)) {
1639          if (NumBytes)
1640            BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1641              .addImm(NumBytes)
1642              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1643          else
1644            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1645              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1646        }
1647      } else if (NumBytes) {
1648        emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl);
1649      }
1650
1651      // Move SP to start of integer callee save spill area 2.
1652      movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1653      emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1654                   false, TII, *this, dl);
1655
1656      // Move SP to start of integer callee save spill area 1.
1657      movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1658      emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1659                   false, TII, *this, dl);
1660
1661      // Move SP to SP upon entry to the function.
1662      movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1663      emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1664                   false, TII, *this, dl);
1665    }
1666  }
1667
1668  if (VARegSaveSize) {
1669    if (isThumb)
1670      // Epilogue for vararg functions: pop LR to R3 and branch off it.
1671      // FIXME: Verify this is still ok when R3 is no longer being reserved.
1672      BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
1673
1674    emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
1675                 *this, dl);
1676
1677    if (isThumb) {
1678      BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1679      MBB.erase(MBBI);
1680    }
1681  }
1682}
1683
1684unsigned ARMRegisterInfo::getRARegister() const {
1685  return ARM::LR;
1686}
1687
1688unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1689  if (STI.isTargetDarwin() || hasFP(MF))
1690    return FramePtr;
1691  return ARM::SP;
1692}
1693
1694unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1695  assert(0 && "What is the exception register");
1696  return 0;
1697}
1698
1699unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1700  assert(0 && "What is the exception handler register");
1701  return 0;
1702}
1703
1704int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1705  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1706}
1707
1708unsigned ARMRegisterInfo::getRegisterPairEven(unsigned Reg,
1709                                              const MachineFunction &MF) const {
1710  switch (Reg) {
1711  default: break;
1712  // Return 0 if either register of the pair is a special register.
1713  // So no R12, etc.
1714  case ARM::R1:
1715    return ARM::R0;
1716  case ARM::R3:
1717    // FIXME!
1718    return STI.isThumb() ? 0 : ARM::R2;
1719  case ARM::R5:
1720    return ARM::R4;
1721  case ARM::R7:
1722    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
1723  case ARM::R9:
1724    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1725  case ARM::R11:
1726    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1727
1728  case ARM::S1:
1729    return ARM::S0;
1730  case ARM::S3:
1731    return ARM::S2;
1732  case ARM::S5:
1733    return ARM::S4;
1734  case ARM::S7:
1735    return ARM::S6;
1736  case ARM::S9:
1737    return ARM::S8;
1738  case ARM::S11:
1739    return ARM::S10;
1740  case ARM::S13:
1741    return ARM::S12;
1742  case ARM::S15:
1743    return ARM::S14;
1744  case ARM::S17:
1745    return ARM::S16;
1746  case ARM::S19:
1747    return ARM::S18;
1748  case ARM::S21:
1749    return ARM::S20;
1750  case ARM::S23:
1751    return ARM::S22;
1752  case ARM::S25:
1753    return ARM::S24;
1754  case ARM::S27:
1755    return ARM::S26;
1756  case ARM::S29:
1757    return ARM::S28;
1758  case ARM::S31:
1759    return ARM::S30;
1760
1761  case ARM::D1:
1762    return ARM::D0;
1763  case ARM::D3:
1764    return ARM::D2;
1765  case ARM::D5:
1766    return ARM::D4;
1767  case ARM::D7:
1768    return ARM::D6;
1769  case ARM::D9:
1770    return ARM::D8;
1771  case ARM::D11:
1772    return ARM::D10;
1773  case ARM::D13:
1774    return ARM::D12;
1775  case ARM::D15:
1776    return ARM::D14;
1777  }
1778
1779  return 0;
1780}
1781
1782unsigned ARMRegisterInfo::getRegisterPairOdd(unsigned Reg,
1783                                             const MachineFunction &MF) const {
1784  switch (Reg) {
1785  default: break;
1786  // Return 0 if either register of the pair is a special register.
1787  // So no R12, etc.
1788  case ARM::R0:
1789    return ARM::R1;
1790  case ARM::R2:
1791    // FIXME!
1792    return STI.isThumb() ? 0 : ARM::R3;
1793  case ARM::R4:
1794    return ARM::R5;
1795  case ARM::R6:
1796    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
1797  case ARM::R8:
1798    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1799  case ARM::R10:
1800    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1801
1802  case ARM::S0:
1803    return ARM::S1;
1804  case ARM::S2:
1805    return ARM::S3;
1806  case ARM::S4:
1807    return ARM::S5;
1808  case ARM::S6:
1809    return ARM::S7;
1810  case ARM::S8:
1811    return ARM::S9;
1812  case ARM::S10:
1813    return ARM::S11;
1814  case ARM::S12:
1815    return ARM::S13;
1816  case ARM::S14:
1817    return ARM::S15;
1818  case ARM::S16:
1819    return ARM::S17;
1820  case ARM::S18:
1821    return ARM::S19;
1822  case ARM::S20:
1823    return ARM::S21;
1824  case ARM::S22:
1825    return ARM::S23;
1826  case ARM::S24:
1827    return ARM::S25;
1828  case ARM::S26:
1829    return ARM::S27;
1830  case ARM::S28:
1831    return ARM::S29;
1832  case ARM::S30:
1833    return ARM::S31;
1834
1835  case ARM::D0:
1836    return ARM::D1;
1837  case ARM::D2:
1838    return ARM::D3;
1839  case ARM::D4:
1840    return ARM::D5;
1841  case ARM::D6:
1842    return ARM::D7;
1843  case ARM::D8:
1844    return ARM::D9;
1845  case ARM::D10:
1846    return ARM::D11;
1847  case ARM::D12:
1848    return ARM::D13;
1849  case ARM::D14:
1850    return ARM::D15;
1851  }
1852
1853  return 0;
1854}
1855
1856#include "ARMGenRegisterInfo.inc"
1857