ARMInstrThumb.td revision 218893 
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Thumb specific DAG Nodes.
16//
17
18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
20                       SDNPVariadic]>;
21
22def imm_neg_XFORM : SDNodeXForm<imm, [{
23  return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24}]>;
25def imm_comp_XFORM : SDNodeXForm<imm, [{
26  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
27}]>;
28
29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30def imm0_7 : PatLeaf<(i32 imm), [{
31  return (uint32_t)N->getZExtValue() < 8;
32}]>;
33def imm0_7_neg : PatLeaf<(i32 imm), [{
34  return (uint32_t)-N->getZExtValue() < 8;
35}], imm_neg_XFORM>;
36
37def imm0_255 : PatLeaf<(i32 imm), [{
38  return (uint32_t)N->getZExtValue() < 256;
39}]>;
40def imm0_255_comp : PatLeaf<(i32 imm), [{
41  return ~((uint32_t)N->getZExtValue()) < 256;
42}]>;
43
44def imm8_255 : PatLeaf<(i32 imm), [{
45  return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
46}]>;
47def imm8_255_neg : PatLeaf<(i32 imm), [{
48  unsigned Val = -N->getZExtValue();
49  return Val >= 8 && Val < 256;
50}], imm_neg_XFORM>;
51
52// Break imm's up into two pieces: an immediate + a left shift. This uses
53// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54// to get the val/shift pieces.
55def thumb_immshifted : PatLeaf<(imm), [{
56  return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
57}]>;
58
59def thumb_immshifted_val : SDNodeXForm<imm, [{
60  unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61  return CurDAG->getTargetConstant(V, MVT::i32);
62}]>;
63
64def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65  unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66  return CurDAG->getTargetConstant(V, MVT::i32);
67}]>;
68
69// ADR instruction labels.
70def t_adrlabel : Operand<i32> {
71  let EncoderMethod = "getThumbAdrLabelOpValue";
72}
73
74// Scaled 4 immediate.
75def t_imm_s4 : Operand<i32> {
76  let PrintMethod = "printThumbS4ImmOperand";
77}
78
79// Define Thumb specific addressing modes.
80
81def t_brtarget : Operand<OtherVT> {
82  let EncoderMethod = "getThumbBRTargetOpValue";
83}
84
85def t_bcctarget : Operand<i32> {
86  let EncoderMethod = "getThumbBCCTargetOpValue";
87}
88
89def t_cbtarget : Operand<i32> {
90  let EncoderMethod = "getThumbCBTargetOpValue";
91}
92
93def t_bltarget : Operand<i32> {
94  let EncoderMethod = "getThumbBLTargetOpValue";
95}
96
97def t_blxtarget : Operand<i32> {
98  let EncoderMethod = "getThumbBLXTargetOpValue";
99}
100
101def MemModeRegThumbAsmOperand : AsmOperandClass {
102  let Name = "MemModeRegThumb";
103  let SuperClasses = [];
104}
105
106def MemModeImmThumbAsmOperand : AsmOperandClass {
107  let Name = "MemModeImmThumb";
108  let SuperClasses = [];
109}
110
111// t_addrmode_rr := reg + reg
112//
113def t_addrmode_rr : Operand<i32>,
114                    ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116  let PrintMethod = "printThumbAddrModeRROperand";
117  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
118}
119
120// t_addrmode_rrs := reg + reg
121//
122def t_addrmode_rrs1 : Operand<i32>,
123                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125  let PrintMethod = "printThumbAddrModeRROperand";
126  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127  let ParserMatchClass = MemModeRegThumbAsmOperand;
128}
129def t_addrmode_rrs2 : Operand<i32>,
130                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132  let PrintMethod = "printThumbAddrModeRROperand";
133  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134  let ParserMatchClass = MemModeRegThumbAsmOperand;
135}
136def t_addrmode_rrs4 : Operand<i32>,
137                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139  let PrintMethod = "printThumbAddrModeRROperand";
140  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141  let ParserMatchClass = MemModeRegThumbAsmOperand;
142}
143
144// t_addrmode_is4 := reg + imm5 * 4
145//
146def t_addrmode_is4 : Operand<i32>,
147                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148  let EncoderMethod = "getAddrModeISOpValue";
149  let PrintMethod = "printThumbAddrModeImm5S4Operand";
150  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151  let ParserMatchClass = MemModeImmThumbAsmOperand;
152}
153
154// t_addrmode_is2 := reg + imm5 * 2
155//
156def t_addrmode_is2 : Operand<i32>,
157                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158  let EncoderMethod = "getAddrModeISOpValue";
159  let PrintMethod = "printThumbAddrModeImm5S2Operand";
160  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161  let ParserMatchClass = MemModeImmThumbAsmOperand;
162}
163
164// t_addrmode_is1 := reg + imm5
165//
166def t_addrmode_is1 : Operand<i32>,
167                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168  let EncoderMethod = "getAddrModeISOpValue";
169  let PrintMethod = "printThumbAddrModeImm5S1Operand";
170  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171  let ParserMatchClass = MemModeImmThumbAsmOperand;
172}
173
174// t_addrmode_sp := sp + imm8 * 4
175//
176def t_addrmode_sp : Operand<i32>,
177                    ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178  let EncoderMethod = "getAddrModeThumbSPOpValue";
179  let PrintMethod = "printThumbAddrModeSPOperand";
180  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181  let ParserMatchClass = MemModeImmThumbAsmOperand;
182}
183
184// t_addrmode_pc := <label> => pc + imm8 * 4
185//
186def t_addrmode_pc : Operand<i32> {
187  let EncoderMethod = "getAddrModePCOpValue";
188  let ParserMatchClass = MemModeImmThumbAsmOperand;
189}
190
191//===----------------------------------------------------------------------===//
192//  Miscellaneous Instructions.
193//
194
195// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196// from removing one half of the matched pairs. That breaks PEI, which assumes
197// these will always be in pairs, and asserts if it finds otherwise. Better way?
198let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199def tADJCALLSTACKUP :
200  PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201             [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202            Requires<[IsThumb, IsThumb1Only]>;
203
204def tADJCALLSTACKDOWN :
205  PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206             [(ARMcallseq_start imm:$amt)]>,
207            Requires<[IsThumb, IsThumb1Only]>;
208}
209
210// T1Disassembly - A simple class to make encoding some disassembly patterns
211// easier and less verbose.
212class T1Disassembly<bits<2> op1, bits<8> op2>
213  : T1Encoding<0b101111> {
214  let Inst{9-8} = op1;
215  let Inst{7-0} = op2;
216}
217
218def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219                [/* For disassembly only; pattern left blank */]>,
220           T1Disassembly<0b11, 0x00>; // A8.6.110
221
222def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223                  [/* For disassembly only; pattern left blank */]>,
224           T1Disassembly<0b11, 0x10>; // A8.6.410
225
226def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227                [/* For disassembly only; pattern left blank */]>,
228           T1Disassembly<0b11, 0x20>; // A8.6.408
229
230def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231                [/* For disassembly only; pattern left blank */]>,
232           T1Disassembly<0b11, 0x30>; // A8.6.409
233
234def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235                [/* For disassembly only; pattern left blank */]>,
236           T1Disassembly<0b11, 0x40>; // A8.6.157
237
238// The i32imm operand $val can be used by a debugger to store more information
239// about the breakpoint.
240def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241                [/* For disassembly only; pattern left blank */]>,
242           T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
243  // A8.6.22
244  bits<8> val;
245  let Inst{7-0} = val;
246}
247
248def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
249                    [/* For disassembly only; pattern left blank */]>,
250                T1Encoding<0b101101> {
251  // A8.6.156
252  let Inst{9-5} = 0b10010;
253  let Inst{4}   = 1;
254  let Inst{3}   = 1;            // Big-Endian
255  let Inst{2-0} = 0b000;
256}
257
258def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
259                    [/* For disassembly only; pattern left blank */]>,
260                T1Encoding<0b101101> {
261  // A8.6.156
262  let Inst{9-5} = 0b10010;
263  let Inst{4}   = 1;
264  let Inst{3}   = 0;            // Little-Endian
265  let Inst{2-0} = 0b000;
266}
267
268// Change Processor State is a system instruction -- for disassembly only.
269def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
270                NoItinerary, "cps$imod $iflags",
271                [/* For disassembly only; pattern left blank */]>,
272           T1Misc<0b0110011> {
273  // A8.6.38 & B6.1.1
274  bit imod;
275  bits<3> iflags;
276
277  let Inst{4}   = imod;
278  let Inst{3}   = 0;
279  let Inst{2-0} = iflags;
280}
281
282// For both thumb1 and thumb2.
283let isNotDuplicable = 1, isCodeGenOnly = 1 in
284def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
285                  [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
286              T1Special<{0,0,?,?}> {
287  // A8.6.6
288  bits<3> dst;
289  let Inst{6-3} = 0b1111; // Rm = pc
290  let Inst{2-0} = dst;
291}
292
293// PC relative add (ADR).
294def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
295                   "add\t$dst, pc, $rhs", []>,
296               T1Encoding<{1,0,1,0,0,?}> {
297  // A6.2 & A8.6.10
298  bits<3> dst;
299  bits<8> rhs;
300  let Inst{10-8} = dst;
301  let Inst{7-0}  = rhs;
302}
303
304// ADD <Rd>, sp, #<imm8>
305// This is rematerializable, which is particularly useful for taking the
306// address of locals.
307let isReMaterializable = 1 in
308def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
309                   "add\t$dst, $sp, $rhs", []>,
310               T1Encoding<{1,0,1,0,1,?}> {
311  // A6.2 & A8.6.8
312  bits<3> dst;
313  bits<8> rhs;
314  let Inst{10-8} = dst;
315  let Inst{7-0}  = rhs;
316}
317
318// ADD sp, sp, #<imm7>
319def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320                  "add\t$dst, $rhs", []>,
321              T1Misc<{0,0,0,0,0,?,?}> {
322  // A6.2.5 & A8.6.8
323  bits<7> rhs;
324  let Inst{6-0} = rhs;
325}
326
327// SUB sp, sp, #<imm7>
328// FIXME: The encoding and the ASM string don't match up.
329def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
330                  "sub\t$dst, $rhs", []>,
331              T1Misc<{0,0,0,0,1,?,?}> {
332  // A6.2.5 & A8.6.214
333  bits<7> rhs;
334  let Inst{6-0} = rhs;
335}
336
337// ADD <Rm>, sp
338def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
339                  "add\t$dst, $rhs", []>,
340              T1Special<{0,0,?,?}> {
341  // A8.6.9 Encoding T1
342  bits<4> dst;
343  let Inst{7}   = dst{3};
344  let Inst{6-3} = 0b1101;
345  let Inst{2-0} = dst{2-0};
346}
347
348// ADD sp, <Rm>
349def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350                  "add\t$dst, $rhs", []>,
351              T1Special<{0,0,?,?}> {
352  // A8.6.9 Encoding T2
353  bits<4> dst;
354  let Inst{7} = 1;
355  let Inst{6-3} = dst;
356  let Inst{2-0} = 0b101;
357}
358
359//===----------------------------------------------------------------------===//
360//  Control Flow Instructions.
361//
362
363let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
364  def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
365                   [(ARMretflag)]>,
366                T1Special<{1,1,0,?}> {
367    // A6.2.3 & A8.6.25
368    let Inst{6-3} = 0b1110; // Rm = lr
369    let Inst{2-0} = 0b000;
370  }
371
372  // Alternative return instruction used by vararg functions.
373  def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
374                          IIC_Br, "bx\t$Rm",
375                          []>,
376                       T1Special<{1,1,0,?}> {
377    // A6.2.3 & A8.6.25
378    bits<4> Rm;
379    let Inst{6-3} = Rm;
380    let Inst{2-0} = 0b000;
381  }
382}
383
384// Indirect branches
385let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
386  def tBRIND : TI<(outs), (ins GPR:$Rm),
387                  IIC_Br,
388                  "mov\tpc, $Rm",
389                  [(brind GPR:$Rm)]>,
390               T1Special<{1,0,?,?}> {
391    // A8.6.97
392    bits<4> Rm;
393    let Inst{7}   = 1;          // <Rd> = Inst{7:2-0} = pc
394    let Inst{6-3} = Rm;
395    let Inst{2-0} = 0b111;
396  }
397}
398
399// FIXME: remove when we have a way to marking a MI with these properties.
400let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
401    hasExtraDefRegAllocReq = 1 in
402def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
403                   IIC_iPop_Br,
404                   "pop${p}\t$regs", []>,
405               T1Misc<{1,1,0,?,?,?,?}> {
406  // A8.6.121
407  bits<16> regs;
408  let Inst{8}   = regs{15};     // registers = P:'0000000':register_list
409  let Inst{7-0} = regs{7-0};
410}
411
412// All calls clobber the non-callee saved registers. SP is marked as a use to
413// prevent stack-pointer assignments that appear immediately before calls from
414// potentially appearing dead.
415let isCall = 1,
416  // On non-Darwin platforms R9 is callee-saved.
417  Defs = [R0,  R1,  R2,  R3,  R12, LR,
418          D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
419          D16, D17, D18, D19, D20, D21, D22, D23,
420          D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
421  Uses = [SP] in {
422  // Also used for Thumb2
423  def tBL  : TIx2<0b11110, 0b11, 1,
424                  (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
425                  "bl\t$func",
426                  [(ARMtcall tglobaladdr:$func)]>,
427             Requires<[IsThumb, IsNotDarwin]> {
428    bits<21> func;
429    let Inst{25-16} = func{20-11};
430    let Inst{13} = 1;
431    let Inst{11} = 1;
432    let Inst{10-0} = func{10-0};
433  }
434
435  // ARMv5T and above, also used for Thumb2
436  def tBLXi : TIx2<0b11110, 0b11, 0,
437                   (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
438                   "blx\t$func",
439                   [(ARMcall tglobaladdr:$func)]>,
440              Requires<[IsThumb, HasV5T, IsNotDarwin]> {
441    bits<21> func;
442    let Inst{25-16} = func{20-11};
443    let Inst{13} = 1;
444    let Inst{11} = 1;
445    let Inst{10-1} = func{10-1};
446    let Inst{0} = 0; // func{0} is assumed zero
447  }
448
449  // Also used for Thumb2
450  def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
451                  "blx\t$func",
452                  [(ARMtcall GPR:$func)]>,
453              Requires<[IsThumb, HasV5T, IsNotDarwin]>,
454              T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
455
456  // ARMv4T
457  // FIXME: Should be a pseudo.
458  let isCodeGenOnly = 1 in
459  def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
460                  (outs), (ins tGPR:$func, variable_ops), IIC_Br,
461                  "mov\tlr, pc\n\tbx\t$func",
462                  [(ARMcall_nolink tGPR:$func)]>,
463            Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
464}
465
466let isCall = 1,
467  // On Darwin R9 is call-clobbered.
468  // R7 is marked as a use to prevent frame-pointer assignments from being
469  // moved above / below calls.
470  Defs = [R0,  R1,  R2,  R3,  R9,  R12, LR,
471          D0,  D1,  D2,  D3,  D4,  D5,  D6,  D7,
472          D16, D17, D18, D19, D20, D21, D22, D23,
473          D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
474  Uses = [R7, SP] in {
475  // Also used for Thumb2
476  def tBLr9 : TIx2<0b11110, 0b11, 1,
477                   (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
478                   IIC_Br, "bl${p}\t$func",
479                   [(ARMtcall tglobaladdr:$func)]>,
480              Requires<[IsThumb, IsDarwin]> {
481    bits<21> func;
482    let Inst{25-16} = func{20-11};
483    let Inst{13} = 1;
484    let Inst{11} = 1;
485    let Inst{10-0} = func{10-0};
486  }
487
488  // ARMv5T and above, also used for Thumb2
489  def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
490                      (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
491                      IIC_Br, "blx${p}\t$func",
492                      [(ARMcall tglobaladdr:$func)]>,
493                 Requires<[IsThumb, HasV5T, IsDarwin]> {
494    bits<21> func;
495    let Inst{25-16} = func{20-11};
496    let Inst{13} = 1;
497    let Inst{11} = 1;
498    let Inst{10-1} = func{10-1};
499    let Inst{0} = 0; // func{0} is assumed zero
500  }
501
502  // Also used for Thumb2
503  def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
504                    "blx${p}\t$func",
505                    [(ARMtcall GPR:$func)]>,
506                 Requires<[IsThumb, HasV5T, IsDarwin]>,
507                 T1Special<{1,1,1,?}> {
508    // A6.2.3 & A8.6.24
509    bits<4> func;
510    let Inst{6-3} = func;
511    let Inst{2-0} = 0b000;
512  }
513
514  // ARMv4T
515  let isCodeGenOnly = 1 in
516  // FIXME: Should be a pseudo.
517  def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
518                   (outs), (ins tGPR:$func, variable_ops), IIC_Br,
519                   "mov\tlr, pc\n\tbx\t$func",
520                   [(ARMcall_nolink tGPR:$func)]>,
521              Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
522}
523
524let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
525  let isPredicable = 1 in
526  def tB   : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
527                 "b\t$target", [(br bb:$target)]>,
528             T1Encoding<{1,1,1,0,0,?}> {
529    bits<11> target;
530    let Inst{10-0} = target;
531  }
532
533  // Far jump
534  // Just a pseudo for a tBL instruction. Needed to let regalloc know about
535  // the clobber of LR.
536  let Defs = [LR] in
537  def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
538                          Size4Bytes, IIC_Br, []>;
539
540  def tBR_JTr : tPseudoInst<(outs),
541                      (ins tGPR:$target, i32imm:$jt, i32imm:$id),
542                      SizeSpecial, IIC_Br,
543                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
544    list<Predicate> Predicates = [IsThumb, IsThumb1Only];
545  }
546}
547
548// FIXME: should be able to write a pattern for ARMBrcond, but can't use
549// a two-value operand where a dag node expects two operands. :(
550let isBranch = 1, isTerminator = 1 in
551  def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
552                 "b${p}\t$target",
553                 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
554             T1Encoding<{1,1,0,1,?,?}> {
555  bits<4> p;
556  bits<8> target;
557  let Inst{11-8} = p;
558  let Inst{7-0} = target;
559}
560
561// Compare and branch on zero / non-zero
562let isBranch = 1, isTerminator = 1 in {
563  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
564                  "cbz\t$Rn, $target", []>,
565              T1Misc<{0,0,?,1,?,?,?}> {
566    // A8.6.27
567    bits<6> target;
568    bits<3> Rn;
569    let Inst{9}   = target{5};
570    let Inst{7-3} = target{4-0};
571    let Inst{2-0} = Rn;
572  }
573
574  def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
575                  "cbnz\t$cmp, $target", []>,
576              T1Misc<{1,0,?,1,?,?,?}> {
577    // A8.6.27
578    bits<6> target;
579    bits<3> Rn;
580    let Inst{9}   = target{5};
581    let Inst{7-3} = target{4-0};
582    let Inst{2-0} = Rn;
583  }
584}
585
586// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
587// A8.6.16 B: Encoding T1
588// If Inst{11-8} == 0b1111 then SEE SVC
589let isCall = 1, Uses = [SP] in
590def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
591                "svc", "\t$imm", []>, Encoding16 {
592  bits<8> imm;
593  let Inst{15-12} = 0b1101;
594  let Inst{11-8}  = 0b1111;
595  let Inst{7-0}   = imm;
596}
597
598// The assembler uses 0xDEFE for a trap instruction.
599let isBarrier = 1, isTerminator = 1 in
600def tTRAP : TI<(outs), (ins), IIC_Br, 
601               "trap", [(trap)]>, Encoding16 {
602  let Inst = 0xdefe;
603}
604
605//===----------------------------------------------------------------------===//
606//  Load Store Instructions.
607//
608
609// Loads: reg/reg and reg/imm5
610let canFoldAsLoad = 1, isReMaterializable = 1 in
611multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
612                              Operand AddrMode_r, Operand AddrMode_i,
613                              AddrMode am, InstrItinClass itin_r,
614                              InstrItinClass itin_i, string asm,
615                              PatFrag opnode> {
616  def r : // reg/reg
617    T1pILdStEncode<reg_opc,
618                   (outs tGPR:$Rt), (ins AddrMode_r:$addr),
619                   am, itin_r, asm, "\t$Rt, $addr",
620                   [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
621  def i : // reg/imm5
622    T1pILdStEncodeImm<imm_opc, 1 /* Load */,
623                      (outs tGPR:$Rt), (ins AddrMode_i:$addr),
624                      am, itin_i, asm, "\t$Rt, $addr",
625                      [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
626}
627// Stores: reg/reg and reg/imm5
628multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
629                              Operand AddrMode_r, Operand AddrMode_i,
630                              AddrMode am, InstrItinClass itin_r,
631                              InstrItinClass itin_i, string asm,
632                              PatFrag opnode> {
633  def r : // reg/reg
634    T1pILdStEncode<reg_opc,
635                   (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
636                   am, itin_r, asm, "\t$Rt, $addr",
637                   [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
638  def i : // reg/imm5
639    T1pILdStEncodeImm<imm_opc, 0 /* Store */,
640                      (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
641                      am, itin_i, asm, "\t$Rt, $addr",
642                      [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
643}
644
645// A8.6.57 & A8.6.60
646defm tLDR  : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
647                                t_addrmode_is4, AddrModeT1_4,
648                                IIC_iLoad_r, IIC_iLoad_i, "ldr",
649                                UnOpFrag<(load node:$Src)>>;
650
651// A8.6.64 & A8.6.61
652defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
653                                t_addrmode_is1, AddrModeT1_1,
654                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
655                                UnOpFrag<(zextloadi8 node:$Src)>>;
656
657// A8.6.76 & A8.6.73
658defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
659                                t_addrmode_is2, AddrModeT1_2,
660                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
661                                UnOpFrag<(zextloadi16 node:$Src)>>;
662
663let AddedComplexity = 10 in
664def tLDRSB :                    // A8.6.80
665  T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
666                 AddrModeT1_1, IIC_iLoad_bh_r,
667                 "ldrsb", "\t$dst, $addr",
668                 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
669
670let AddedComplexity = 10 in
671def tLDRSH :                    // A8.6.84
672  T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
673                 AddrModeT1_2, IIC_iLoad_bh_r,
674                 "ldrsh", "\t$dst, $addr",
675                 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
676
677let canFoldAsLoad = 1 in
678def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
679                    "ldr", "\t$Rt, $addr",
680                    [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
681              T1LdStSP<{1,?,?}> {
682  bits<3> Rt;
683  bits<8> addr;
684  let Inst{10-8} = Rt;
685  let Inst{7-0} = addr;
686}
687
688// Special instruction for restore. It cannot clobber condition register
689// when it's expanded by eliminateCallFramePseudoInstr().
690let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
691// FIXME: Pseudo for tLDRspi
692def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
693                     "ldr", "\t$dst, $addr", []>,
694               T1LdStSP<{1,?,?}> {
695  bits<3> Rt;
696  bits<8> addr;
697  let Inst{10-8} = Rt;
698  let Inst{7-0} = addr;
699}
700
701// Load tconstpool
702// FIXME: Use ldr.n to work around a Darwin assembler bug.
703let canFoldAsLoad = 1, isReMaterializable = 1 in
704def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
705                  "ldr", ".n\t$Rt, $addr",
706                  [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
707              T1Encoding<{0,1,0,0,1,?}> {
708  // A6.2 & A8.6.59
709  bits<3> Rt;
710  bits<8> addr;
711  let Inst{10-8} = Rt;
712  let Inst{7-0}  = addr;
713}
714
715// A8.6.194 & A8.6.192
716defm tSTR  : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
717                                t_addrmode_is4, AddrModeT1_4,
718                                IIC_iStore_r, IIC_iStore_i, "str",
719                                BinOpFrag<(store node:$LHS, node:$RHS)>>;
720
721// A8.6.197 & A8.6.195
722defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
723                                t_addrmode_is1, AddrModeT1_1,
724                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
725                                BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
726
727// A8.6.207 & A8.6.205
728defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
729                                t_addrmode_is2, AddrModeT1_2,
730                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
731                                BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
732
733
734def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
735                    "str", "\t$Rt, $addr",
736                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
737              T1LdStSP<{0,?,?}> {
738  bits<3> Rt;
739  bits<8> addr;
740  let Inst{10-8} = Rt;
741  let Inst{7-0} = addr;
742}
743
744let mayStore = 1, neverHasSideEffects = 1 in
745// Special instruction for spill. It cannot clobber condition register when it's
746// expanded by eliminateCallFramePseudoInstr().
747// FIXME: Pseudo for tSTRspi
748def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
749                  "str", "\t$src, $addr", []>,
750             T1LdStSP<{0,?,?}> {
751  bits<3> Rt;
752  bits<8> addr;
753  let Inst{10-8} = Rt;
754  let Inst{7-0} = addr;
755}
756
757//===----------------------------------------------------------------------===//
758//  Load / store multiple Instructions.
759//
760
761multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
762                           InstrItinClass itin_upd, bits<6> T1Enc,
763                           bit L_bit> {
764  def IA :
765    T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
766        itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
767       T1Encoding<T1Enc> {
768    bits<3> Rn;
769    bits<8> regs;
770    let Inst{10-8} = Rn;
771    let Inst{7-0}  = regs;
772  }
773  def IA_UPD :
774    T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
775         itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
776        T1Encoding<T1Enc> {
777    bits<3> Rn;
778    bits<8> regs;
779    let Inst{10-8} = Rn;
780    let Inst{7-0}  = regs;
781  }
782}
783
784// These require base address to be written back or one of the loaded regs.
785let neverHasSideEffects = 1 in {
786
787let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
788defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
789                            {1,1,0,0,1,?}, 1>;
790
791let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
792defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
793                            {1,1,0,0,0,?}, 0>;
794 
795} // neverHasSideEffects
796
797let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
798def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
799               IIC_iPop,
800               "pop${p}\t$regs", []>,
801           T1Misc<{1,1,0,?,?,?,?}> {
802  bits<16> regs;
803  let Inst{8}   = regs{15};
804  let Inst{7-0} = regs{7-0};
805}
806
807let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
808def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
809                IIC_iStore_m,
810                "push${p}\t$regs", []>,
811            T1Misc<{0,1,0,?,?,?,?}> {
812  bits<16> regs;
813  let Inst{8}   = regs{14};
814  let Inst{7-0} = regs{7-0};
815}
816
817//===----------------------------------------------------------------------===//
818//  Arithmetic Instructions.
819//
820
821// Helper classes for encoding T1pI patterns:
822class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
823                   string opc, string asm, list<dag> pattern>
824    : T1pI<oops, iops, itin, opc, asm, pattern>,
825      T1DataProcessing<opA> {
826  bits<3> Rm;
827  bits<3> Rn;
828  let Inst{5-3} = Rm;
829  let Inst{2-0} = Rn;
830}
831class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
832                     string opc, string asm, list<dag> pattern>
833    : T1pI<oops, iops, itin, opc, asm, pattern>,
834      T1Misc<opA> {
835  bits<3> Rm;
836  bits<3> Rd;
837  let Inst{5-3} = Rm;
838  let Inst{2-0} = Rd;
839}
840
841// Helper classes for encoding T1sI patterns:
842class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
843                   string opc, string asm, list<dag> pattern>
844    : T1sI<oops, iops, itin, opc, asm, pattern>,
845      T1DataProcessing<opA> {
846  bits<3> Rd;
847  bits<3> Rn;
848  let Inst{5-3} = Rn;
849  let Inst{2-0} = Rd;
850}
851class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
852                    string opc, string asm, list<dag> pattern>
853    : T1sI<oops, iops, itin, opc, asm, pattern>,
854      T1General<opA> {
855  bits<3> Rm;
856  bits<3> Rn;
857  bits<3> Rd;
858  let Inst{8-6} = Rm;
859  let Inst{5-3} = Rn;
860  let Inst{2-0} = Rd;
861}
862class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
863                       string opc, string asm, list<dag> pattern>
864    : T1sI<oops, iops, itin, opc, asm, pattern>,
865      T1General<opA> {
866  bits<3> Rd;
867  bits<3> Rm;
868  let Inst{5-3} = Rm;
869  let Inst{2-0} = Rd;
870}
871
872// Helper classes for encoding T1sIt patterns:
873class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
874                    string opc, string asm, list<dag> pattern>
875    : T1sIt<oops, iops, itin, opc, asm, pattern>,
876      T1DataProcessing<opA> {
877  bits<3> Rdn;
878  bits<3> Rm;
879  let Inst{5-3} = Rm;
880  let Inst{2-0} = Rdn;
881}
882class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
883                        string opc, string asm, list<dag> pattern>
884    : T1sIt<oops, iops, itin, opc, asm, pattern>,
885      T1General<opA> {
886  bits<3> Rdn;
887  bits<8> imm8;
888  let Inst{10-8} = Rdn;
889  let Inst{7-0}  = imm8;
890}
891
892// Add with carry register
893let isCommutable = 1, Uses = [CPSR] in
894def tADC :                      // A8.6.2
895  T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
896                "adc", "\t$Rdn, $Rm",
897                [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
898
899// Add immediate
900def tADDi3 :                    // A8.6.4 T1
901  T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
902                   "add", "\t$Rd, $Rm, $imm3",
903                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
904  bits<3> imm3;
905  let Inst{8-6} = imm3;
906}
907
908def tADDi8 :                    // A8.6.4 T2
909  T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
910                    IIC_iALUi,
911                    "add", "\t$Rdn, $imm8",
912                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
913
914// Add register
915let isCommutable = 1 in
916def tADDrr :                    // A8.6.6 T1
917  T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
918                IIC_iALUr,
919                "add", "\t$Rd, $Rn, $Rm",
920                [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
921
922let neverHasSideEffects = 1 in
923def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
924                     "add", "\t$Rdn, $Rm", []>,
925               T1Special<{0,0,?,?}> {
926  // A8.6.6 T2
927  bits<4> Rdn;
928  bits<4> Rm;
929  let Inst{7}   = Rdn{3};
930  let Inst{6-3} = Rm;
931  let Inst{2-0} = Rdn{2-0};
932}
933
934// AND register
935let isCommutable = 1 in
936def tAND :                      // A8.6.12
937  T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
938                IIC_iBITr,
939                "and", "\t$Rdn, $Rm",
940                [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
941
942// ASR immediate
943def tASRri :                    // A8.6.14
944  T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
945                   IIC_iMOVsi,
946                   "asr", "\t$Rd, $Rm, $imm5",
947                   [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
948  bits<5> imm5;
949  let Inst{10-6} = imm5;
950}
951
952// ASR register
953def tASRrr :                    // A8.6.15
954  T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
955                IIC_iMOVsr,
956                "asr", "\t$Rdn, $Rm",
957                [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
958
959// BIC register
960def tBIC :                      // A8.6.20
961  T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
962                IIC_iBITr,
963                "bic", "\t$Rdn, $Rm",
964                [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
965
966// CMN register
967let isCompare = 1, Defs = [CPSR] in {
968//FIXME: Disable CMN, as CCodes are backwards from compare expectations
969//       Compare-to-zero still works out, just not the relationals
970//def tCMN :                     // A8.6.33
971//  T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
972//               IIC_iCMPr,
973//               "cmn", "\t$lhs, $rhs",
974//               [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
975
976def tCMNz :                     // A8.6.33
977  T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
978               IIC_iCMPr,
979               "cmn", "\t$Rn, $Rm",
980               [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
981
982} // isCompare = 1, Defs = [CPSR]
983
984// CMP immediate
985let isCompare = 1, Defs = [CPSR] in {
986def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
987                  "cmp", "\t$Rn, $imm8",
988                  [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
989             T1General<{1,0,1,?,?}> {
990  // A8.6.35
991  bits<3> Rn;
992  bits<8> imm8;
993  let Inst{10-8} = Rn;
994  let Inst{7-0}  = imm8;
995}
996
997// CMP register
998def tCMPr :                     // A8.6.36 T1
999  T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1000               IIC_iCMPr,
1001               "cmp", "\t$Rn, $Rm",
1002               [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
1003
1004def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1005                   "cmp", "\t$Rn, $Rm", []>,
1006              T1Special<{0,1,?,?}> {
1007  // A8.6.36 T2
1008  bits<4> Rm;
1009  bits<4> Rn;
1010  let Inst{7}   = Rn{3};
1011  let Inst{6-3} = Rm;
1012  let Inst{2-0} = Rn{2-0};
1013}
1014} // isCompare = 1, Defs = [CPSR]
1015
1016
1017// XOR register
1018let isCommutable = 1 in
1019def tEOR :                      // A8.6.45
1020  T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1021                IIC_iBITr,
1022                "eor", "\t$Rdn, $Rm",
1023                [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1024
1025// LSL immediate
1026def tLSLri :                    // A8.6.88
1027  T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1028                   IIC_iMOVsi,
1029                   "lsl", "\t$Rd, $Rm, $imm5",
1030                   [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1031  bits<5> imm5;
1032  let Inst{10-6} = imm5;
1033}
1034
1035// LSL register
1036def tLSLrr :                    // A8.6.89
1037  T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1038                IIC_iMOVsr,
1039                "lsl", "\t$Rdn, $Rm",
1040                [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1041
1042// LSR immediate
1043def tLSRri :                    // A8.6.90
1044  T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1045                   IIC_iMOVsi,
1046                   "lsr", "\t$Rd, $Rm, $imm5",
1047                   [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1048  bits<5> imm5;
1049  let Inst{10-6} = imm5;
1050}
1051
1052// LSR register
1053def tLSRrr :                    // A8.6.91
1054  T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1055                IIC_iMOVsr,
1056                "lsr", "\t$Rdn, $Rm",
1057                [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1058
1059// Move register
1060let isMoveImm = 1 in
1061def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1062                  "mov", "\t$Rd, $imm8",
1063                  [(set tGPR:$Rd, imm0_255:$imm8)]>,
1064             T1General<{1,0,0,?,?}> {
1065  // A8.6.96
1066  bits<3> Rd;
1067  bits<8> imm8;
1068  let Inst{10-8} = Rd;
1069  let Inst{7-0}  = imm8;
1070}
1071
1072// TODO: A7-73: MOV(2) - mov setting flag.
1073
1074let neverHasSideEffects = 1 in {
1075// FIXME: Make this predicable.
1076def tMOVr       : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1077                      "mov\t$Rd, $Rm", []>,
1078                  T1Special<0b1000> {
1079  // A8.6.97
1080  bits<4> Rd;
1081  bits<4> Rm;
1082  // Bits {7-6} are encoded by the T1Special value.
1083  let Inst{5-3} = Rm{2-0};
1084  let Inst{2-0} = Rd{2-0};
1085}
1086let Defs = [CPSR] in
1087def tMOVSr      : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1088                      "movs\t$Rd, $Rm", []>, Encoding16 {
1089  // A8.6.97
1090  bits<3> Rd;
1091  bits<3> Rm;
1092  let Inst{15-6} = 0b0000000000;
1093  let Inst{5-3}  = Rm;
1094  let Inst{2-0}  = Rd;
1095}
1096
1097// FIXME: Make these predicable.
1098def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1099                       "mov\t$Rd, $Rm", []>,
1100                   T1Special<{1,0,0,?}> {
1101  // A8.6.97
1102  bits<4> Rd;
1103  bits<4> Rm;
1104  // Bit {7} is encoded by the T1Special value.
1105  let Inst{6-3} = Rm;
1106  let Inst{2-0} = Rd{2-0};
1107}
1108def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1109                       "mov\t$Rd, $Rm", []>,
1110                   T1Special<{1,0,?,0}> {
1111  // A8.6.97
1112  bits<4> Rd;
1113  bits<4> Rm;
1114  // Bit {6} is encoded by the T1Special value.
1115  let Inst{7}   = Rd{3};
1116  let Inst{5-3} = Rm{2-0};
1117  let Inst{2-0} = Rd{2-0};
1118}
1119def tMOVgpr2gpr  : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1120                       "mov\t$Rd, $Rm", []>,
1121                   T1Special<{1,0,?,?}> {
1122  // A8.6.97
1123  bits<4> Rd;
1124  bits<4> Rm;
1125  let Inst{7}   = Rd{3};
1126  let Inst{6-3} = Rm;
1127  let Inst{2-0} = Rd{2-0};
1128}
1129} // neverHasSideEffects
1130
1131// Multiply register
1132let isCommutable = 1 in
1133def tMUL :                      // A8.6.105 T1
1134  T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1135                IIC_iMUL32,
1136                "mul", "\t$Rdn, $Rm, $Rdn",
1137                [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1138
1139// Move inverse register
1140def tMVN :                      // A8.6.107
1141  T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1142               "mvn", "\t$Rd, $Rn",
1143               [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1144
1145// Bitwise or register
1146let isCommutable = 1 in
1147def tORR :                      // A8.6.114
1148  T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1149                IIC_iBITr,
1150                "orr", "\t$Rdn, $Rm",
1151                [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1152
1153// Swaps
1154def tREV :                      // A8.6.134
1155  T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1156                 IIC_iUNAr,
1157                 "rev", "\t$Rd, $Rm",
1158                 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1159                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1160
1161def tREV16 :                    // A8.6.135
1162  T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1163                 IIC_iUNAr,
1164                 "rev16", "\t$Rd, $Rm",
1165             [(set tGPR:$Rd,
1166                   (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1167                       (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1168                           (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1169                               (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1170                Requires<[IsThumb, IsThumb1Only, HasV6]>;
1171
1172def tREVSH :                    // A8.6.136
1173  T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1174                 IIC_iUNAr,
1175                 "revsh", "\t$Rd, $Rm",
1176                 [(set tGPR:$Rd,
1177                       (sext_inreg
1178                         (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1179                             (shl tGPR:$Rm, (i32 8))), i16))]>,
1180                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1181
1182// Rotate right register
1183def tROR :                      // A8.6.139
1184  T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1185                IIC_iMOVsr,
1186                "ror", "\t$Rdn, $Rm",
1187                [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1188
1189// Negate register
1190def tRSB :                      // A8.6.141
1191  T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1192               IIC_iALUi,
1193               "rsb", "\t$Rd, $Rn, #0",
1194               [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1195
1196// Subtract with carry register
1197let Uses = [CPSR] in
1198def tSBC :                      // A8.6.151
1199  T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1200                IIC_iALUr,
1201                "sbc", "\t$Rdn, $Rm",
1202                [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1203
1204// Subtract immediate
1205def tSUBi3 :                    // A8.6.210 T1
1206  T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1207                   IIC_iALUi,
1208                   "sub", "\t$Rd, $Rm, $imm3",
1209                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1210  bits<3> imm3;
1211  let Inst{8-6} = imm3;
1212}
1213
1214def tSUBi8 :                    // A8.6.210 T2
1215  T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1216                    IIC_iALUi,
1217                    "sub", "\t$Rdn, $imm8",
1218                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1219
1220// Subtract register
1221def tSUBrr :                    // A8.6.212
1222  T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1223                IIC_iALUr,
1224                "sub", "\t$Rd, $Rn, $Rm",
1225                [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1226
1227// TODO: A7-96: STMIA - store multiple.
1228
1229// Sign-extend byte
1230def tSXTB :                     // A8.6.222
1231  T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1232                 IIC_iUNAr,
1233                 "sxtb", "\t$Rd, $Rm",
1234                 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1235                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1236
1237// Sign-extend short
1238def tSXTH :                     // A8.6.224
1239  T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1240                 IIC_iUNAr,
1241                 "sxth", "\t$Rd, $Rm",
1242                 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1243                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1244
1245// Test
1246let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1247def tTST :                      // A8.6.230
1248  T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1249               "tst", "\t$Rn, $Rm",
1250               [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1251
1252// Zero-extend byte
1253def tUXTB :                     // A8.6.262
1254  T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1255                 IIC_iUNAr,
1256                 "uxtb", "\t$Rd, $Rm",
1257                 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1258                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1259
1260// Zero-extend short
1261def tUXTH :                     // A8.6.264
1262  T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1263                 IIC_iUNAr,
1264                 "uxth", "\t$Rd, $Rm",
1265                 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1266                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1267
1268// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1269// Expanded after instruction selection into a branch sequence.
1270let usesCustomInserter = 1 in  // Expanded after instruction selection.
1271  def tMOVCCr_pseudo :
1272  PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1273              NoItinerary,
1274             [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1275
1276
1277// 16-bit movcc in IT blocks for Thumb2.
1278let neverHasSideEffects = 1 in {
1279def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1280                    "mov", "\t$Rdn, $Rm", []>,
1281              T1Special<{1,0,?,?}> {
1282  bits<4> Rdn;
1283  bits<4> Rm;
1284  let Inst{7}   = Rdn{3};
1285  let Inst{6-3} = Rm;
1286  let Inst{2-0} = Rdn{2-0};
1287}
1288
1289let isMoveImm = 1 in
1290def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1291                    "mov", "\t$Rdn, $Rm", []>,
1292              T1General<{1,0,0,?,?}> {
1293  bits<3> Rdn;
1294  bits<8> Rm;
1295  let Inst{10-8} = Rdn;
1296  let Inst{7-0}  = Rm;
1297}
1298
1299} // neverHasSideEffects
1300
1301// tLEApcrel - Load a pc-relative address into a register without offending the
1302// assembler.
1303
1304def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1305               IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1306               T1Encoding<{1,0,1,0,0,?}> {
1307  bits<3> Rd;
1308  bits<8> addr;
1309  let Inst{10-8} = Rd;
1310  let Inst{7-0} = addr;
1311}
1312
1313let neverHasSideEffects = 1, isReMaterializable = 1 in
1314def tLEApcrel   : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1315                              Size2Bytes, IIC_iALUi, []>;
1316
1317def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1318                              (ins i32imm:$label, nohash_imm:$id, pred:$p),
1319                              Size2Bytes, IIC_iALUi, []>;
1320
1321//===----------------------------------------------------------------------===//
1322// Move between coprocessor and ARM core register -- for disassembly only
1323//
1324
1325class tMovRCopro<string opc, bit direction>
1326  : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1327                       GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1328          !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1329          [/* For disassembly only; pattern left blank */]> {
1330  let Inst{27-24} = 0b1110;
1331  let Inst{20} = direction;
1332  let Inst{4} = 1;
1333
1334  bits<4> Rt;
1335  bits<4> cop;
1336  bits<3> opc1;
1337  bits<3> opc2;
1338  bits<4> CRm;
1339  bits<4> CRn;
1340
1341  let Inst{15-12} = Rt;
1342  let Inst{11-8}  = cop;
1343  let Inst{23-21} = opc1;
1344  let Inst{7-5}   = opc2;
1345  let Inst{3-0}   = CRm;
1346  let Inst{19-16} = CRn;
1347}
1348
1349def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
1350def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
1351
1352class tMovRRCopro<string opc, bit direction>
1353  : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1354          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
1355          [/* For disassembly only; pattern left blank */]> {
1356  let Inst{27-24} = 0b1100;
1357  let Inst{23-21} = 0b010;
1358  let Inst{20} = direction;
1359
1360  bits<4> Rt;
1361  bits<4> Rt2;
1362  bits<4> cop;
1363  bits<4> opc1;
1364  bits<4> CRm;
1365
1366  let Inst{15-12} = Rt;
1367  let Inst{19-16} = Rt2;
1368  let Inst{11-8}  = cop;
1369  let Inst{7-4}   = opc1;
1370  let Inst{3-0}   = CRm;
1371}
1372
1373def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
1374def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1375
1376//===----------------------------------------------------------------------===//
1377// Other Coprocessor Instructions.  For disassembly only.
1378//
1379def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1380                 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1381                 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1382                 [/* For disassembly only; pattern left blank */]> {
1383  let Inst{27-24} = 0b1110;
1384
1385  bits<4> opc1;
1386  bits<4> CRn;
1387  bits<4> CRd;
1388  bits<4> cop;
1389  bits<3> opc2;
1390  bits<4> CRm;
1391
1392  let Inst{3-0}   = CRm;
1393  let Inst{4}     = 0;
1394  let Inst{7-5}   = opc2;
1395  let Inst{11-8}  = cop;
1396  let Inst{15-12} = CRd;
1397  let Inst{19-16} = CRn;
1398  let Inst{23-20} = opc1;
1399}
1400
1401//===----------------------------------------------------------------------===//
1402// TLS Instructions
1403//
1404
1405// __aeabi_read_tp preserves the registers r1-r3.
1406let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1407def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1408                   "bl\t__aeabi_read_tp",
1409                   [(set R0, ARMthread_pointer)]> {
1410  // Encoding is 0xf7fffffe.
1411  let Inst = 0xf7fffffe;
1412}
1413
1414//===----------------------------------------------------------------------===//
1415// SJLJ Exception handling intrinsics
1416// 
1417
1418// eh_sjlj_setjmp() is an instruction sequence to store the return address and
1419// save #0 in R0 for the non-longjmp case.  Since by its nature we may be coming
1420// from some other function to get here, and we're using the stack frame for the
1421// containing function to save/restore registers, we can't keep anything live in
1422// regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1423// tromped upon when we get here from a longjmp(). We force everthing out of
1424// registers except for our own input by listing the relevant registers in
1425// Defs. By doing so, we also cause the prologue/epilogue code to actively
1426// preserve all of the callee-saved resgisters, which is exactly what we want.
1427// $val is a scratch register for our use.
1428let Defs = [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12 ],
1429    hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1430def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1431                                  AddrModeNone, SizeSpecial, NoItinerary, "","",
1432                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1433
1434// FIXME: Non-Darwin version(s)
1435let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1436    Defs = [ R7, LR, SP ] in
1437def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1438                              AddrModeNone, SizeSpecial, IndexModeNone,
1439                              Pseudo, NoItinerary, "", "",
1440                              [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1441                             Requires<[IsThumb, IsDarwin]>;
1442
1443//===----------------------------------------------------------------------===//
1444// Non-Instruction Patterns
1445//
1446
1447// Comparisons
1448def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1449            (tCMPi8  tGPR:$Rn, imm0_255:$imm8)>;
1450def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1451            (tCMPr   tGPR:$Rn, tGPR:$Rm)>;
1452
1453// Add with carry
1454def : T1Pat<(addc   tGPR:$lhs, imm0_7:$rhs),
1455            (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1456def : T1Pat<(addc   tGPR:$lhs, imm8_255:$rhs),
1457            (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1458def : T1Pat<(addc   tGPR:$lhs, tGPR:$rhs),
1459            (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1460
1461// Subtract with carry
1462def : T1Pat<(addc   tGPR:$lhs, imm0_7_neg:$rhs),
1463            (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1464def : T1Pat<(addc   tGPR:$lhs, imm8_255_neg:$rhs),
1465            (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1466def : T1Pat<(subc   tGPR:$lhs, tGPR:$rhs),
1467            (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1468
1469// ConstantPool, GlobalAddress
1470def : T1Pat<(ARMWrapper  tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1471def : T1Pat<(ARMWrapper  tconstpool  :$dst), (tLEApcrel tconstpool  :$dst)>;
1472
1473// JumpTable
1474def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1475            (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1476
1477// Direct calls
1478def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1479      Requires<[IsThumb, IsNotDarwin]>;
1480def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1481      Requires<[IsThumb, IsDarwin]>;
1482
1483def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1484      Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1485def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1486      Requires<[IsThumb, HasV5T, IsDarwin]>;
1487
1488// Indirect calls to ARM routines
1489def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1490      Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1491def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1492      Requires<[IsThumb, HasV5T, IsDarwin]>;
1493
1494// zextload i1 -> zextload i8
1495def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1496            (tLDRBr t_addrmode_rrs1:$addr)>;
1497def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1498            (tLDRBi t_addrmode_is1:$addr)>;
1499
1500// extload -> zextload
1501def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1502def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
1503def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1504def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
1505def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1506def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
1507
1508// If it's impossible to use [r,r] address mode for sextload, select to
1509// ldr{b|h} + sxt{b|h} instead.
1510def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1511            (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1512      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1513def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1514            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1515      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1516def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1517            (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1518      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1519def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1520            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1521      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1522
1523def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1524            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1525def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1526            (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1527def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1528            (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1529def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1530            (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1531
1532// Large immediate handling.
1533
1534// Two piece imms.
1535def : T1Pat<(i32 thumb_immshifted:$src),
1536            (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1537                    (thumb_immshifted_shamt imm:$src))>;
1538
1539def : T1Pat<(i32 imm0_255_comp:$src),
1540            (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1541
1542// Pseudo instruction that combines ldr from constpool and add pc. This should
1543// be expanded into two instructions late to allow if-conversion and
1544// scheduling.
1545let isReMaterializable = 1 in
1546def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1547                             NoItinerary,
1548               [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1549                                           imm:$cp))]>,
1550               Requires<[IsThumb, IsThumb1Only]>;
1551