ARMInstrThumb.td revision 199481
1//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 20 21def imm_neg_XFORM : SDNodeXForm<imm, [{ 22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 23}]>; 24def imm_comp_XFORM : SDNodeXForm<imm, [{ 25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 26}]>; 27 28 29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7]. 30def imm0_7 : PatLeaf<(i32 imm), [{ 31 return (uint32_t)N->getZExtValue() < 8; 32}]>; 33def imm0_7_neg : PatLeaf<(i32 imm), [{ 34 return (uint32_t)-N->getZExtValue() < 8; 35}], imm_neg_XFORM>; 36 37def imm0_255 : PatLeaf<(i32 imm), [{ 38 return (uint32_t)N->getZExtValue() < 256; 39}]>; 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : PatLeaf<(i32 imm), [{ 45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. 53// This uses thumb_immshifted to match and thumb_immshifted_val and 54// thumb_immshifted_shamt to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, MVT::i32); 67}]>; 68 69// Define Thumb specific addressing modes. 70 71// t_addrmode_rr := reg + reg 72// 73def t_addrmode_rr : Operand<i32>, 74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 75 let PrintMethod = "printThumbAddrModeRROperand"; 76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 77} 78 79// t_addrmode_s4 := reg + reg 80// reg + imm5 * 4 81// 82def t_addrmode_s4 : Operand<i32>, 83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> { 84 let PrintMethod = "printThumbAddrModeS4Operand"; 85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 86} 87 88// t_addrmode_s2 := reg + reg 89// reg + imm5 * 2 90// 91def t_addrmode_s2 : Operand<i32>, 92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> { 93 let PrintMethod = "printThumbAddrModeS2Operand"; 94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 95} 96 97// t_addrmode_s1 := reg + reg 98// reg + imm5 99// 100def t_addrmode_s1 : Operand<i32>, 101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> { 102 let PrintMethod = "printThumbAddrModeS1Operand"; 103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 104} 105 106// t_addrmode_sp := sp + imm8 * 4 107// 108def t_addrmode_sp : Operand<i32>, 109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 110 let PrintMethod = "printThumbAddrModeSPOperand"; 111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 112} 113 114//===----------------------------------------------------------------------===// 115// Miscellaneous Instructions. 116// 117 118let Defs = [SP], Uses = [SP] in { 119def tADJCALLSTACKUP : 120PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 121 "@ tADJCALLSTACKUP $amt1", 122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>; 123 124def tADJCALLSTACKDOWN : 125PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 126 "@ tADJCALLSTACKDOWN $amt", 127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>; 128} 129 130// For both thumb1 and thumb2. 131let isNotDuplicable = 1 in 132def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, 133 "\n$cp:\n\tadd\t$dst, pc", 134 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; 135 136// PC relative add. 137def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi, 138 "add\t$dst, pc, $rhs * 4", []>; 139 140// ADD rd, sp, #imm8 141def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi, 142 "add\t$dst, $sp, $rhs * 4", []>; 143 144// ADD sp, sp, #imm7 145def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi, 146 "add\t$dst, $rhs * 4", []>; 147 148// SUB sp, sp, #imm7 149def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi, 150 "sub\t$dst, $rhs * 4", []>; 151 152// ADD rm, sp 153def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 154 "add\t$dst, $rhs", []>; 155 156// ADD sp, rm 157def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 158 "add\t$dst, $rhs", []>; 159 160// Pseudo instruction that will expand into a tSUBspi + a copy. 161let usesCustomInserter = 1 in { // Expanded after instruction selection. 162def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 163 NoItinerary, "@ sub\t$dst, $rhs * 4", []>; 164 165def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 166 NoItinerary, "@ add\t$dst, $rhs", []>; 167 168let Defs = [CPSR] in 169def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), 170 NoItinerary, "@ and\t$dst, $rhs", []>; 171} // usesCustomInserter 172 173//===----------------------------------------------------------------------===// 174// Control Flow Instructions. 175// 176 177let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 178 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>; 179 // Alternative return instruction used by vararg functions. 180 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>; 181} 182 183// Indirect branches 184let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 185 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst", 186 [(brind GPR:$dst)]>; 187} 188 189// FIXME: remove when we have a way to marking a MI with these properties. 190let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 191 hasExtraDefRegAllocReq = 1 in 192def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 193 "pop${p}\t$wb", []>; 194 195let isCall = 1, 196 Defs = [R0, R1, R2, R3, R12, LR, 197 D0, D1, D2, D3, D4, D5, D6, D7, 198 D16, D17, D18, D19, D20, D21, D22, D23, 199 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 200 // Also used for Thumb2 201 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br, 202 "bl\t${func:call}", 203 [(ARMtcall tglobaladdr:$func)]>, 204 Requires<[IsThumb, IsNotDarwin]>; 205 206 // ARMv5T and above, also used for Thumb2 207 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br, 208 "blx\t${func:call}", 209 [(ARMcall tglobaladdr:$func)]>, 210 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 211 212 // Also used for Thumb2 213 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 214 "blx\t$func", 215 [(ARMtcall GPR:$func)]>, 216 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 217 218 // ARMv4T 219 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br, 220 "mov\tlr, pc\n\tbx\t$func", 221 [(ARMcall_nolink tGPR:$func)]>, 222 Requires<[IsThumb1Only, IsNotDarwin]>; 223} 224 225// On Darwin R9 is call-clobbered. 226let isCall = 1, 227 Defs = [R0, R1, R2, R3, R9, R12, LR, 228 D0, D1, D2, D3, D4, D5, D6, D7, 229 D16, D17, D18, D19, D20, D21, D22, D23, 230 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 231 // Also used for Thumb2 232 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br, 233 "bl\t${func:call}", 234 [(ARMtcall tglobaladdr:$func)]>, 235 Requires<[IsThumb, IsDarwin]>; 236 237 // ARMv5T and above, also used for Thumb2 238 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br, 239 "blx\t${func:call}", 240 [(ARMcall tglobaladdr:$func)]>, 241 Requires<[IsThumb, HasV5T, IsDarwin]>; 242 243 // Also used for Thumb2 244 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 245 "blx\t$func", 246 [(ARMtcall GPR:$func)]>, 247 Requires<[IsThumb, HasV5T, IsDarwin]>; 248 249 // ARMv4T 250 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br, 251 "mov\tlr, pc\n\tbx\t$func", 252 [(ARMcall_nolink tGPR:$func)]>, 253 Requires<[IsThumb1Only, IsDarwin]>; 254} 255 256let isBranch = 1, isTerminator = 1 in { 257 let isBarrier = 1 in { 258 let isPredicable = 1 in 259 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br, 260 "b\t$target", [(br bb:$target)]>; 261 262 // Far jump 263 let Defs = [LR] in 264 def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br, 265 "bl\t$target\t@ far jump",[]>; 266 267 def tBR_JTr : T1JTI<(outs), 268 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id), 269 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt", 270 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>; 271 } 272} 273 274// FIXME: should be able to write a pattern for ARMBrcond, but can't use 275// a two-value operand where a dag node expects two operands. :( 276let isBranch = 1, isTerminator = 1 in 277 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br, 278 "b$cc\t$target", 279 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 280 281// Compare and branch on zero / non-zero 282let isBranch = 1, isTerminator = 1 in { 283 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 284 "cbz\t$cmp, $target", []>; 285 286 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 287 "cbnz\t$cmp, $target", []>; 288} 289 290//===----------------------------------------------------------------------===// 291// Load Store Instructions. 292// 293 294let canFoldAsLoad = 1 in 295def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 296 "ldr", "\t$dst, $addr", 297 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>; 298 299def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr, 300 "ldrb", "\t$dst, $addr", 301 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>; 302 303def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr, 304 "ldrh", "\t$dst, $addr", 305 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>; 306 307let AddedComplexity = 10 in 308def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 309 "ldrsb", "\t$dst, $addr", 310 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; 311 312let AddedComplexity = 10 in 313def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 314 "ldrsh", "\t$dst, $addr", 315 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; 316 317let canFoldAsLoad = 1 in 318def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 319 "ldr", "\t$dst, $addr", 320 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>; 321 322// Special instruction for restore. It cannot clobber condition register 323// when it's expanded by eliminateCallFramePseudoInstr(). 324let canFoldAsLoad = 1, mayLoad = 1 in 325def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 326 "ldr", "\t$dst, $addr", []>; 327 328// Load tconstpool 329// FIXME: Use ldr.n to work around a Darwin assembler bug. 330let canFoldAsLoad = 1 in 331def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 332 "ldr", ".n\t$dst, $addr", 333 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; 334 335// Special LDR for loads from non-pc-relative constpools. 336let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in 337def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 338 "ldr", "\t$dst, $addr", []>; 339 340def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer, 341 "str", "\t$src, $addr", 342 [(store tGPR:$src, t_addrmode_s4:$addr)]>; 343 344def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer, 345 "strb", "\t$src, $addr", 346 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>; 347 348def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer, 349 "strh", "\t$src, $addr", 350 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>; 351 352def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 353 "str", "\t$src, $addr", 354 [(store tGPR:$src, t_addrmode_sp:$addr)]>; 355 356let mayStore = 1 in { 357// Special instruction for spill. It cannot clobber condition register 358// when it's expanded by eliminateCallFramePseudoInstr(). 359def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 360 "str", "\t$src, $addr", []>; 361} 362 363//===----------------------------------------------------------------------===// 364// Load / store multiple Instructions. 365// 366 367// These requires base address to be written back or one of the loaded regs. 368let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 369def tLDM : T1I<(outs), 370 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 371 IIC_iLoadm, 372 "ldm${addr:submode}${p}\t$addr, $wb", []>; 373 374let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 375def tSTM : T1I<(outs), 376 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 377 IIC_iStorem, 378 "stm${addr:submode}${p}\t$addr, $wb", []>; 379 380let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 381def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 382 "pop${p}\t$wb", []>; 383 384let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 385def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 386 "push${p}\t$wb", []>; 387 388//===----------------------------------------------------------------------===// 389// Arithmetic Instructions. 390// 391 392// Add with carry register 393let isCommutable = 1, Uses = [CPSR] in 394def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 395 "adc", "\t$dst, $rhs", 396 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>; 397 398// Add immediate 399def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 400 "add", "\t$dst, $lhs, $rhs", 401 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>; 402 403def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 404 "add", "\t$dst, $rhs", 405 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>; 406 407// Add register 408let isCommutable = 1 in 409def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 410 "add", "\t$dst, $lhs, $rhs", 411 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>; 412 413let neverHasSideEffects = 1 in 414def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 415 "add", "\t$dst, $rhs", []>; 416 417// And register 418let isCommutable = 1 in 419def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 420 "and", "\t$dst, $rhs", 421 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>; 422 423// ASR immediate 424def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 425 "asr", "\t$dst, $lhs, $rhs", 426 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>; 427 428// ASR register 429def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 430 "asr", "\t$dst, $rhs", 431 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>; 432 433// BIC register 434def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 435 "bic", "\t$dst, $rhs", 436 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>; 437 438// CMN register 439let Defs = [CPSR] in { 440def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 441 "cmn", "\t$lhs, $rhs", 442 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 443def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 444 "cmn", "\t$lhs, $rhs", 445 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>; 446} 447 448// CMP immediate 449let Defs = [CPSR] in { 450def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 451 "cmp", "\t$lhs, $rhs", 452 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>; 453def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 454 "cmp", "\t$lhs, $rhs", 455 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>; 456 457} 458 459// CMP register 460let Defs = [CPSR] in { 461def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 462 "cmp", "\t$lhs, $rhs", 463 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>; 464def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 465 "cmp", "\t$lhs, $rhs", 466 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>; 467 468def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 469 "cmp", "\t$lhs, $rhs", []>; 470def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 471 "cmp", "\t$lhs, $rhs", []>; 472} 473 474 475// XOR register 476let isCommutable = 1 in 477def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 478 "eor", "\t$dst, $rhs", 479 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>; 480 481// LSL immediate 482def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 483 "lsl", "\t$dst, $lhs, $rhs", 484 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>; 485 486// LSL register 487def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 488 "lsl", "\t$dst, $rhs", 489 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>; 490 491// LSR immediate 492def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 493 "lsr", "\t$dst, $lhs, $rhs", 494 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>; 495 496// LSR register 497def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 498 "lsr", "\t$dst, $rhs", 499 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>; 500 501// move register 502def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi, 503 "mov", "\t$dst, $src", 504 [(set tGPR:$dst, imm0_255:$src)]>; 505 506// TODO: A7-73: MOV(2) - mov setting flag. 507 508 509let neverHasSideEffects = 1 in { 510// FIXME: Make this predicable. 511def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 512 "mov\t$dst, $src", []>; 513let Defs = [CPSR] in 514def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 515 "movs\t$dst, $src", []>; 516 517// FIXME: Make these predicable. 518def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr, 519 "mov\t$dst, $src", []>; 520def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr, 521 "mov\t$dst, $src", []>; 522def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 523 "mov\t$dst, $src", []>; 524} // neverHasSideEffects 525 526// multiply register 527let isCommutable = 1 in 528def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32, 529 "mul", "\t$dst, $rhs", 530 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>; 531 532// move inverse register 533def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 534 "mvn", "\t$dst, $src", 535 [(set tGPR:$dst, (not tGPR:$src))]>; 536 537// bitwise or register 538let isCommutable = 1 in 539def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 540 "orr", "\t$dst, $rhs", 541 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>; 542 543// swaps 544def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 545 "rev", "\t$dst, $src", 546 [(set tGPR:$dst, (bswap tGPR:$src))]>, 547 Requires<[IsThumb1Only, HasV6]>; 548 549def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 550 "rev16", "\t$dst, $src", 551 [(set tGPR:$dst, 552 (or (and (srl tGPR:$src, (i32 8)), 0xFF), 553 (or (and (shl tGPR:$src, (i32 8)), 0xFF00), 554 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000), 555 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, 556 Requires<[IsThumb1Only, HasV6]>; 557 558def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 559 "revsh", "\t$dst, $src", 560 [(set tGPR:$dst, 561 (sext_inreg 562 (or (srl (and tGPR:$src, 0xFF00), (i32 8)), 563 (shl tGPR:$src, (i32 8))), i16))]>, 564 Requires<[IsThumb1Only, HasV6]>; 565 566// rotate right register 567def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 568 "ror", "\t$dst, $rhs", 569 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>; 570 571// negate register 572def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi, 573 "rsb", "\t$dst, $src, #0", 574 [(set tGPR:$dst, (ineg tGPR:$src))]>; 575 576// Subtract with carry register 577let Uses = [CPSR] in 578def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 579 "sbc", "\t$dst, $rhs", 580 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>; 581 582// Subtract immediate 583def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 584 "sub", "\t$dst, $lhs, $rhs", 585 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>; 586 587def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 588 "sub", "\t$dst, $rhs", 589 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>; 590 591// subtract register 592def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 593 "sub", "\t$dst, $lhs, $rhs", 594 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>; 595 596// TODO: A7-96: STMIA - store multiple. 597 598// sign-extend byte 599def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 600 "sxtb", "\t$dst, $src", 601 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, 602 Requires<[IsThumb1Only, HasV6]>; 603 604// sign-extend short 605def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 606 "sxth", "\t$dst, $src", 607 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, 608 Requires<[IsThumb1Only, HasV6]>; 609 610// test 611let isCommutable = 1, Defs = [CPSR] in 612def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 613 "tst", "\t$lhs, $rhs", 614 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>; 615 616// zero-extend byte 617def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 618 "uxtb", "\t$dst, $src", 619 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, 620 Requires<[IsThumb1Only, HasV6]>; 621 622// zero-extend short 623def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 624 "uxth", "\t$dst, $src", 625 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, 626 Requires<[IsThumb1Only, HasV6]>; 627 628 629// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation. 630// Expanded after instruction selection into a branch sequence. 631let usesCustomInserter = 1 in // Expanded after instruction selection. 632 def tMOVCCr_pseudo : 633 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 634 NoItinerary, "@ tMOVCCr $cc", 635 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 636 637 638// 16-bit movcc in IT blocks for Thumb2. 639def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr, 640 "mov", "\t$dst, $rhs", []>; 641 642def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi, 643 "mov", "\t$dst, $rhs", []>; 644 645// tLEApcrel - Load a pc-relative address into a register without offending the 646// assembler. 647def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 648 "adr$p\t$dst, #$label", []>; 649 650def tLEApcrelJT : T1I<(outs tGPR:$dst), 651 (ins i32imm:$label, nohash_imm:$id, pred:$p), 652 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>; 653 654//===----------------------------------------------------------------------===// 655// TLS Instructions 656// 657 658// __aeabi_read_tp preserves the registers r1-r3. 659let isCall = 1, 660 Defs = [R0, LR] in { 661 def tTPsoft : TIx2<(outs), (ins), IIC_Br, 662 "bl\t__aeabi_read_tp", 663 [(set R0, ARMthread_pointer)]>; 664} 665 666//===----------------------------------------------------------------------===// 667// Non-Instruction Patterns 668// 669 670// Add with carry 671def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 672 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 673def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 674 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 675def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 676 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 677 678// Subtract with carry 679def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 680 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 681def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 682 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 683def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 684 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 685 686// ConstantPool, GlobalAddress 687def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 688def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 689 690// JumpTable 691def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 692 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 693 694// Direct calls 695def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 696 Requires<[IsThumb, IsNotDarwin]>; 697def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 698 Requires<[IsThumb, IsDarwin]>; 699 700def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 701 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 702def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 703 Requires<[IsThumb, HasV5T, IsDarwin]>; 704 705// Indirect calls to ARM routines 706def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 707 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 708def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 709 Requires<[IsThumb, HasV5T, IsDarwin]>; 710 711// zextload i1 -> zextload i8 712def : T1Pat<(zextloadi1 t_addrmode_s1:$addr), 713 (tLDRB t_addrmode_s1:$addr)>; 714 715// extload -> zextload 716def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 717def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 718def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>; 719 720// If it's impossible to use [r,r] address mode for sextload, select to 721// ldr{b|h} + sxt{b|h} instead. 722def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 723 (tSXTB (tLDRB t_addrmode_s1:$addr))>, 724 Requires<[IsThumb1Only, HasV6]>; 725def : T1Pat<(sextloadi16 t_addrmode_s2:$addr), 726 (tSXTH (tLDRH t_addrmode_s2:$addr))>, 727 Requires<[IsThumb1Only, HasV6]>; 728 729def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 730 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>; 731def : T1Pat<(sextloadi16 t_addrmode_s1:$addr), 732 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>; 733 734// Large immediate handling. 735 736// Two piece imms. 737def : T1Pat<(i32 thumb_immshifted:$src), 738 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 739 (thumb_immshifted_shamt imm:$src))>; 740 741def : T1Pat<(i32 imm0_255_comp:$src), 742 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 743 744// Pseudo instruction that combines ldr from constpool and add pc. This should 745// be expanded into two instructions late to allow if-conversion and 746// scheduling. 747let isReMaterializable = 1 in 748def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 749 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 750 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 751 imm:$cp))]>, 752 Requires<[IsThumb1Only]>; 753