ARMInstrThumb.td revision 224145
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_neg_XFORM : SDNodeXForm<imm, [{ 23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 24}]>; 25def imm_comp_XFORM : SDNodeXForm<imm, [{ 26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 27}]>; 28 29def imm0_7_neg : PatLeaf<(i32 imm), [{ 30 return (uint32_t)-N->getZExtValue() < 8; 31}], imm_neg_XFORM>; 32 33def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; } 34def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 35 let ParserMatchClass = imm0_255_asmoperand; 36} 37def imm0_255_comp : PatLeaf<(i32 imm), [{ 38 return ~((uint32_t)N->getZExtValue()) < 256; 39}]>; 40 41def imm8_255 : ImmLeaf<i32, [{ 42 return Imm >= 8 && Imm < 256; 43}]>; 44def imm8_255_neg : PatLeaf<(i32 imm), [{ 45 unsigned Val = -N->getZExtValue(); 46 return Val >= 8 && Val < 256; 47}], imm_neg_XFORM>; 48 49// Break imm's up into two pieces: an immediate + a left shift. This uses 50// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 51// to get the val/shift pieces. 52def thumb_immshifted : PatLeaf<(imm), [{ 53 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 54}]>; 55 56def thumb_immshifted_val : SDNodeXForm<imm, [{ 57 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 58 return CurDAG->getTargetConstant(V, MVT::i32); 59}]>; 60 61def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 62 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 63 return CurDAG->getTargetConstant(V, MVT::i32); 64}]>; 65 66// ADR instruction labels. 67def t_adrlabel : Operand<i32> { 68 let EncoderMethod = "getThumbAdrLabelOpValue"; 69} 70 71// Scaled 4 immediate. 72def t_imm_s4 : Operand<i32> { 73 let PrintMethod = "printThumbS4ImmOperand"; 74 let OperandType = "OPERAND_IMMEDIATE"; 75} 76 77// Define Thumb specific addressing modes. 78 79let OperandType = "OPERAND_PCREL" in { 80def t_brtarget : Operand<OtherVT> { 81 let EncoderMethod = "getThumbBRTargetOpValue"; 82} 83 84def t_bcctarget : Operand<i32> { 85 let EncoderMethod = "getThumbBCCTargetOpValue"; 86} 87 88def t_cbtarget : Operand<i32> { 89 let EncoderMethod = "getThumbCBTargetOpValue"; 90} 91 92def t_bltarget : Operand<i32> { 93 let EncoderMethod = "getThumbBLTargetOpValue"; 94} 95 96def t_blxtarget : Operand<i32> { 97 let EncoderMethod = "getThumbBLXTargetOpValue"; 98} 99} 100 101def MemModeRegThumbAsmOperand : AsmOperandClass { 102 let Name = "MemModeRegThumb"; 103 let SuperClasses = []; 104} 105 106def MemModeImmThumbAsmOperand : AsmOperandClass { 107 let Name = "MemModeImmThumb"; 108 let SuperClasses = []; 109} 110 111// t_addrmode_rr := reg + reg 112// 113def t_addrmode_rr : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 115 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 116 let PrintMethod = "printThumbAddrModeRROperand"; 117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 118} 119 120// t_addrmode_rrs := reg + reg 121// 122def t_addrmode_rrs1 : Operand<i32>, 123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 124 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 125 let PrintMethod = "printThumbAddrModeRROperand"; 126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 127 let ParserMatchClass = MemModeRegThumbAsmOperand; 128} 129def t_addrmode_rrs2 : Operand<i32>, 130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 131 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 132 let PrintMethod = "printThumbAddrModeRROperand"; 133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 134 let ParserMatchClass = MemModeRegThumbAsmOperand; 135} 136def t_addrmode_rrs4 : Operand<i32>, 137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 138 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 139 let PrintMethod = "printThumbAddrModeRROperand"; 140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 141 let ParserMatchClass = MemModeRegThumbAsmOperand; 142} 143 144// t_addrmode_is4 := reg + imm5 * 4 145// 146def t_addrmode_is4 : Operand<i32>, 147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 148 let EncoderMethod = "getAddrModeISOpValue"; 149 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 151 let ParserMatchClass = MemModeImmThumbAsmOperand; 152} 153 154// t_addrmode_is2 := reg + imm5 * 2 155// 156def t_addrmode_is2 : Operand<i32>, 157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 158 let EncoderMethod = "getAddrModeISOpValue"; 159 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 161 let ParserMatchClass = MemModeImmThumbAsmOperand; 162} 163 164// t_addrmode_is1 := reg + imm5 165// 166def t_addrmode_is1 : Operand<i32>, 167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 168 let EncoderMethod = "getAddrModeISOpValue"; 169 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 171 let ParserMatchClass = MemModeImmThumbAsmOperand; 172} 173 174// t_addrmode_sp := sp + imm8 * 4 175// 176def t_addrmode_sp : Operand<i32>, 177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 178 let EncoderMethod = "getAddrModeThumbSPOpValue"; 179 let PrintMethod = "printThumbAddrModeSPOperand"; 180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 181 let ParserMatchClass = MemModeImmThumbAsmOperand; 182} 183 184// t_addrmode_pc := <label> => pc + imm8 * 4 185// 186def t_addrmode_pc : Operand<i32> { 187 let EncoderMethod = "getAddrModePCOpValue"; 188 let ParserMatchClass = MemModeImmThumbAsmOperand; 189} 190 191//===----------------------------------------------------------------------===// 192// Miscellaneous Instructions. 193// 194 195// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 196// from removing one half of the matched pairs. That breaks PEI, which assumes 197// these will always be in pairs, and asserts if it finds otherwise. Better way? 198let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 199def tADJCALLSTACKUP : 200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 202 Requires<[IsThumb, IsThumb1Only]>; 203 204def tADJCALLSTACKDOWN : 205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 206 [(ARMcallseq_start imm:$amt)]>, 207 Requires<[IsThumb, IsThumb1Only]>; 208} 209 210// T1Disassembly - A simple class to make encoding some disassembly patterns 211// easier and less verbose. 212class T1Disassembly<bits<2> op1, bits<8> op2> 213 : T1Encoding<0b101111> { 214 let Inst{9-8} = op1; 215 let Inst{7-0} = op2; 216} 217 218def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", 219 [/* For disassembly only; pattern left blank */]>, 220 T1Disassembly<0b11, 0x00>; // A8.6.110 221 222def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", 223 [/* For disassembly only; pattern left blank */]>, 224 T1Disassembly<0b11, 0x10>; // A8.6.410 225 226def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", 227 [/* For disassembly only; pattern left blank */]>, 228 T1Disassembly<0b11, 0x20>; // A8.6.408 229 230def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", 231 [/* For disassembly only; pattern left blank */]>, 232 T1Disassembly<0b11, 0x30>; // A8.6.409 233 234def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", 235 [/* For disassembly only; pattern left blank */]>, 236 T1Disassembly<0b11, 0x40>; // A8.6.157 237 238// The i32imm operand $val can be used by a debugger to store more information 239// about the breakpoint. 240def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val", 241 [/* For disassembly only; pattern left blank */]>, 242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> { 243 // A8.6.22 244 bits<8> val; 245 let Inst{7-0} = val; 246} 247 248def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe", 249 [/* For disassembly only; pattern left blank */]>, 250 T1Encoding<0b101101> { 251 // A8.6.156 252 let Inst{9-5} = 0b10010; 253 let Inst{4} = 1; 254 let Inst{3} = 1; // Big-Endian 255 let Inst{2-0} = 0b000; 256} 257 258def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle", 259 [/* For disassembly only; pattern left blank */]>, 260 T1Encoding<0b101101> { 261 // A8.6.156 262 let Inst{9-5} = 0b10010; 263 let Inst{4} = 1; 264 let Inst{3} = 0; // Little-Endian 265 let Inst{2-0} = 0b000; 266} 267 268// Change Processor State is a system instruction -- for disassembly only. 269def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 270 NoItinerary, "cps$imod $iflags", 271 [/* For disassembly only; pattern left blank */]>, 272 T1Misc<0b0110011> { 273 // A8.6.38 & B6.1.1 274 bit imod; 275 bits<3> iflags; 276 277 let Inst{4} = imod; 278 let Inst{3} = 0; 279 let Inst{2-0} = iflags; 280} 281 282// For both thumb1 and thumb2. 283let isNotDuplicable = 1, isCodeGenOnly = 1 in 284def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 285 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 286 T1Special<{0,0,?,?}> { 287 // A8.6.6 288 bits<3> dst; 289 let Inst{6-3} = 0b1111; // Rm = pc 290 let Inst{2-0} = dst; 291} 292 293// PC relative add (ADR). 294def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, 295 "add\t$dst, pc, $rhs", []>, 296 T1Encoding<{1,0,1,0,0,?}> { 297 // A6.2 & A8.6.10 298 bits<3> dst; 299 bits<8> rhs; 300 let Inst{10-8} = dst; 301 let Inst{7-0} = rhs; 302} 303 304// ADD <Rd>, sp, #<imm8> 305// This is rematerializable, which is particularly useful for taking the 306// address of locals. 307let isReMaterializable = 1 in 308def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, 309 "add\t$dst, $sp, $rhs", []>, 310 T1Encoding<{1,0,1,0,1,?}> { 311 // A6.2 & A8.6.8 312 bits<3> dst; 313 bits<8> rhs; 314 let Inst{10-8} = dst; 315 let Inst{7-0} = rhs; 316} 317 318// ADD sp, sp, #<imm7> 319def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 320 "add\t$dst, $rhs", []>, 321 T1Misc<{0,0,0,0,0,?,?}> { 322 // A6.2.5 & A8.6.8 323 bits<7> rhs; 324 let Inst{6-0} = rhs; 325} 326 327// SUB sp, sp, #<imm7> 328// FIXME: The encoding and the ASM string don't match up. 329def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 330 "sub\t$dst, $rhs", []>, 331 T1Misc<{0,0,0,0,1,?,?}> { 332 // A6.2.5 & A8.6.214 333 bits<7> rhs; 334 let Inst{6-0} = rhs; 335} 336 337// ADD <Rm>, sp 338def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 339 "add\t$dst, $rhs", []>, 340 T1Special<{0,0,?,?}> { 341 // A8.6.9 Encoding T1 342 bits<4> dst; 343 let Inst{7} = dst{3}; 344 let Inst{6-3} = 0b1101; 345 let Inst{2-0} = dst{2-0}; 346} 347 348// ADD sp, <Rm> 349def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 350 "add\t$dst, $rhs", []>, 351 T1Special<{0,0,?,?}> { 352 // A8.6.9 Encoding T2 353 bits<4> dst; 354 let Inst{7} = 1; 355 let Inst{6-3} = dst; 356 let Inst{2-0} = 0b101; 357} 358 359//===----------------------------------------------------------------------===// 360// Control Flow Instructions. 361// 362 363// Indirect branches 364let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 365 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 366 T1Special<{1,1,0,?}> { 367 // A6.2.3 & A8.6.25 368 bits<4> Rm; 369 let Inst{6-3} = Rm; 370 let Inst{2-0} = 0b000; 371 } 372} 373 374let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 375 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 376 [(ARMretflag)], (tBX LR, pred:$p)>; 377 378 // Alternative return instruction used by vararg functions. 379 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 380 2, IIC_Br, [], 381 (tBX GPR:$Rm, pred:$p)>; 382} 383 384// All calls clobber the non-callee saved registers. SP is marked as a use to 385// prevent stack-pointer assignments that appear immediately before calls from 386// potentially appearing dead. 387let isCall = 1, 388 // On non-Darwin platforms R9 is callee-saved. 389 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], 390 Uses = [SP] in { 391 // Also used for Thumb2 392 def tBL : TIx2<0b11110, 0b11, 1, 393 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br, 394 "bl\t$func", 395 [(ARMtcall tglobaladdr:$func)]>, 396 Requires<[IsThumb, IsNotDarwin]> { 397 bits<21> func; 398 let Inst{25-16} = func{20-11}; 399 let Inst{13} = 1; 400 let Inst{11} = 1; 401 let Inst{10-0} = func{10-0}; 402 } 403 404 // ARMv5T and above, also used for Thumb2 405 def tBLXi : TIx2<0b11110, 0b11, 0, 406 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br, 407 "blx\t$func", 408 [(ARMcall tglobaladdr:$func)]>, 409 Requires<[IsThumb, HasV5T, IsNotDarwin]> { 410 bits<21> func; 411 let Inst{25-16} = func{20-11}; 412 let Inst{13} = 1; 413 let Inst{11} = 1; 414 let Inst{10-1} = func{10-1}; 415 let Inst{0} = 0; // func{0} is assumed zero 416 } 417 418 // Also used for Thumb2 419 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 420 "blx\t$func", 421 [(ARMtcall GPR:$func)]>, 422 Requires<[IsThumb, HasV5T, IsNotDarwin]>, 423 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; 424 bits<4> func; 425 let Inst{6-3} = func; 426 let Inst{2-0} = 0b000; 427 } 428 429 // ARMv4T 430 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 431 4, IIC_Br, 432 [(ARMcall_nolink tGPR:$func)]>, 433 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; 434} 435 436let isCall = 1, 437 // On Darwin R9 is call-clobbered. 438 // R7 is marked as a use to prevent frame-pointer assignments from being 439 // moved above / below calls. 440 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], 441 Uses = [R7, SP] in { 442 // Also used for Thumb2 443 def tBLr9 : TIx2<0b11110, 0b11, 1, 444 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), 445 IIC_Br, "bl${p}\t$func", 446 [(ARMtcall tglobaladdr:$func)]>, 447 Requires<[IsThumb, IsDarwin]> { 448 bits<21> func; 449 let Inst{25-16} = func{20-11}; 450 let Inst{13} = 1; 451 let Inst{11} = 1; 452 let Inst{10-0} = func{10-0}; 453 } 454 455 // ARMv5T and above, also used for Thumb2 456 def tBLXi_r9 : TIx2<0b11110, 0b11, 0, 457 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), 458 IIC_Br, "blx${p}\t$func", 459 [(ARMcall tglobaladdr:$func)]>, 460 Requires<[IsThumb, HasV5T, IsDarwin]> { 461 bits<21> func; 462 let Inst{25-16} = func{20-11}; 463 let Inst{13} = 1; 464 let Inst{11} = 1; 465 let Inst{10-1} = func{10-1}; 466 let Inst{0} = 0; // func{0} is assumed zero 467 } 468 469 // Also used for Thumb2 470 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, 471 "blx${p}\t$func", 472 [(ARMtcall GPR:$func)]>, 473 Requires<[IsThumb, HasV5T, IsDarwin]>, 474 T1Special<{1,1,1,?}> { 475 // A6.2.3 & A8.6.24 476 bits<4> func; 477 let Inst{6-3} = func; 478 let Inst{2-0} = 0b000; 479 } 480 481 // ARMv4T 482 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), 483 4, IIC_Br, 484 [(ARMcall_nolink tGPR:$func)]>, 485 Requires<[IsThumb, IsThumb1Only, IsDarwin]>; 486} 487 488let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 489 let isPredicable = 1 in 490 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br, 491 "b\t$target", [(br bb:$target)]>, 492 T1Encoding<{1,1,1,0,0,?}> { 493 bits<11> target; 494 let Inst{10-0} = target; 495 } 496 497 // Far jump 498 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 499 // the clobber of LR. 500 let Defs = [LR] in 501 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target), 502 4, IIC_Br, [], (tBL t_bltarget:$target)>; 503 504 def tBR_JTr : tPseudoInst<(outs), 505 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 506 0, IIC_Br, 507 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { 508 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 509 } 510} 511 512// FIXME: should be able to write a pattern for ARMBrcond, but can't use 513// a two-value operand where a dag node expects two operands. :( 514let isBranch = 1, isTerminator = 1 in 515 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 516 "b${p}\t$target", 517 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 518 T1BranchCond<{1,1,0,1}> { 519 bits<4> p; 520 bits<8> target; 521 let Inst{11-8} = p; 522 let Inst{7-0} = target; 523} 524 525// Compare and branch on zero / non-zero 526let isBranch = 1, isTerminator = 1 in { 527 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 528 "cbz\t$Rn, $target", []>, 529 T1Misc<{0,0,?,1,?,?,?}> { 530 // A8.6.27 531 bits<6> target; 532 bits<3> Rn; 533 let Inst{9} = target{5}; 534 let Inst{7-3} = target{4-0}; 535 let Inst{2-0} = Rn; 536 } 537 538 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br, 539 "cbnz\t$cmp, $target", []>, 540 T1Misc<{1,0,?,1,?,?,?}> { 541 // A8.6.27 542 bits<6> target; 543 bits<3> Rn; 544 let Inst{9} = target{5}; 545 let Inst{7-3} = target{4-0}; 546 let Inst{2-0} = Rn; 547 } 548} 549 550// Tail calls 551let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 552 // Darwin versions. 553 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], 554 Uses = [SP] in { 555 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls 556 // on Darwin), so it's in ARMInstrThumb2.td. 557 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 558 4, IIC_Br, [], 559 (tBX GPR:$dst, (ops 14, zero_reg))>, 560 Requires<[IsThumb, IsDarwin]>; 561 } 562 // Non-Darwin versions (the difference is R9). 563 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], 564 Uses = [SP] in { 565 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops), 566 4, IIC_Br, [], 567 (tB t_brtarget:$dst)>, 568 Requires<[IsThumb, IsNotDarwin]>; 569 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 570 4, IIC_Br, [], 571 (tBX GPR:$dst, (ops 14, zero_reg))>, 572 Requires<[IsThumb, IsNotDarwin]>; 573 } 574} 575 576 577// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only 578// A8.6.16 B: Encoding T1 579// If Inst{11-8} == 0b1111 then SEE SVC 580let isCall = 1, Uses = [SP] in 581def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br, 582 "svc", "\t$imm", []>, Encoding16 { 583 bits<8> imm; 584 let Inst{15-12} = 0b1101; 585 let Inst{11-8} = 0b1111; 586 let Inst{7-0} = imm; 587} 588 589// The assembler uses 0xDEFE for a trap instruction. 590let isBarrier = 1, isTerminator = 1 in 591def tTRAP : TI<(outs), (ins), IIC_Br, 592 "trap", [(trap)]>, Encoding16 { 593 let Inst = 0xdefe; 594} 595 596//===----------------------------------------------------------------------===// 597// Load Store Instructions. 598// 599 600// Loads: reg/reg and reg/imm5 601let canFoldAsLoad = 1, isReMaterializable = 1 in 602multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 603 Operand AddrMode_r, Operand AddrMode_i, 604 AddrMode am, InstrItinClass itin_r, 605 InstrItinClass itin_i, string asm, 606 PatFrag opnode> { 607 def r : // reg/reg 608 T1pILdStEncode<reg_opc, 609 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 610 am, itin_r, asm, "\t$Rt, $addr", 611 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 612 def i : // reg/imm5 613 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 614 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 615 am, itin_i, asm, "\t$Rt, $addr", 616 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 617} 618// Stores: reg/reg and reg/imm5 619multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 620 Operand AddrMode_r, Operand AddrMode_i, 621 AddrMode am, InstrItinClass itin_r, 622 InstrItinClass itin_i, string asm, 623 PatFrag opnode> { 624 def r : // reg/reg 625 T1pILdStEncode<reg_opc, 626 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 627 am, itin_r, asm, "\t$Rt, $addr", 628 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 629 def i : // reg/imm5 630 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 631 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 632 am, itin_i, asm, "\t$Rt, $addr", 633 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 634} 635 636// A8.6.57 & A8.6.60 637defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 638 t_addrmode_is4, AddrModeT1_4, 639 IIC_iLoad_r, IIC_iLoad_i, "ldr", 640 UnOpFrag<(load node:$Src)>>; 641 642// A8.6.64 & A8.6.61 643defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 644 t_addrmode_is1, AddrModeT1_1, 645 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 646 UnOpFrag<(zextloadi8 node:$Src)>>; 647 648// A8.6.76 & A8.6.73 649defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 650 t_addrmode_is2, AddrModeT1_2, 651 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 652 UnOpFrag<(zextloadi16 node:$Src)>>; 653 654let AddedComplexity = 10 in 655def tLDRSB : // A8.6.80 656 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr), 657 AddrModeT1_1, IIC_iLoad_bh_r, 658 "ldrsb", "\t$dst, $addr", 659 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; 660 661let AddedComplexity = 10 in 662def tLDRSH : // A8.6.84 663 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr), 664 AddrModeT1_2, IIC_iLoad_bh_r, 665 "ldrsh", "\t$dst, $addr", 666 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; 667 668let canFoldAsLoad = 1 in 669def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 670 "ldr", "\t$Rt, $addr", 671 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 672 T1LdStSP<{1,?,?}> { 673 bits<3> Rt; 674 bits<8> addr; 675 let Inst{10-8} = Rt; 676 let Inst{7-0} = addr; 677} 678 679// Load tconstpool 680// FIXME: Use ldr.n to work around a Darwin assembler bug. 681let canFoldAsLoad = 1, isReMaterializable = 1 in 682def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 683 "ldr", ".n\t$Rt, $addr", 684 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 685 T1Encoding<{0,1,0,0,1,?}> { 686 // A6.2 & A8.6.59 687 bits<3> Rt; 688 bits<8> addr; 689 let Inst{10-8} = Rt; 690 let Inst{7-0} = addr; 691} 692 693// FIXME: Remove this entry when the above ldr.n workaround is fixed. 694// For disassembly use only. 695def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 696 "ldr", "\t$Rt, $addr", 697 [/* disassembly only */]>, 698 T1Encoding<{0,1,0,0,1,?}> { 699 // A6.2 & A8.6.59 700 bits<3> Rt; 701 bits<8> addr; 702 let Inst{10-8} = Rt; 703 let Inst{7-0} = addr; 704} 705 706// A8.6.194 & A8.6.192 707defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 708 t_addrmode_is4, AddrModeT1_4, 709 IIC_iStore_r, IIC_iStore_i, "str", 710 BinOpFrag<(store node:$LHS, node:$RHS)>>; 711 712// A8.6.197 & A8.6.195 713defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 714 t_addrmode_is1, AddrModeT1_1, 715 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 716 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 717 718// A8.6.207 & A8.6.205 719defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 720 t_addrmode_is2, AddrModeT1_2, 721 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 722 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 723 724 725def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 726 "str", "\t$Rt, $addr", 727 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 728 T1LdStSP<{0,?,?}> { 729 bits<3> Rt; 730 bits<8> addr; 731 let Inst{10-8} = Rt; 732 let Inst{7-0} = addr; 733} 734 735//===----------------------------------------------------------------------===// 736// Load / store multiple Instructions. 737// 738 739multiclass thumb_ldst_mult<string asm, InstrItinClass itin, 740 InstrItinClass itin_upd, bits<6> T1Enc, 741 bit L_bit> { 742 def IA : 743 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 744 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>, 745 T1Encoding<T1Enc> { 746 bits<3> Rn; 747 bits<8> regs; 748 let Inst{10-8} = Rn; 749 let Inst{7-0} = regs; 750 } 751 def IA_UPD : 752 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 753 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>, 754 T1Encoding<T1Enc> { 755 bits<3> Rn; 756 bits<8> regs; 757 let Inst{10-8} = Rn; 758 let Inst{7-0} = regs; 759 } 760} 761 762// These require base address to be written back or one of the loaded regs. 763let neverHasSideEffects = 1 in { 764 765let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 766defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 767 {1,1,0,0,1,?}, 1>; 768 769let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 770defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 771 {1,1,0,0,0,?}, 0>; 772 773} // neverHasSideEffects 774 775let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 776def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 777 IIC_iPop, 778 "pop${p}\t$regs", []>, 779 T1Misc<{1,1,0,?,?,?,?}> { 780 bits<16> regs; 781 let Inst{8} = regs{15}; 782 let Inst{7-0} = regs{7-0}; 783} 784 785let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 786def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 787 IIC_iStore_m, 788 "push${p}\t$regs", []>, 789 T1Misc<{0,1,0,?,?,?,?}> { 790 bits<16> regs; 791 let Inst{8} = regs{14}; 792 let Inst{7-0} = regs{7-0}; 793} 794 795//===----------------------------------------------------------------------===// 796// Arithmetic Instructions. 797// 798 799// Helper classes for encoding T1pI patterns: 800class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 801 string opc, string asm, list<dag> pattern> 802 : T1pI<oops, iops, itin, opc, asm, pattern>, 803 T1DataProcessing<opA> { 804 bits<3> Rm; 805 bits<3> Rn; 806 let Inst{5-3} = Rm; 807 let Inst{2-0} = Rn; 808} 809class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 810 string opc, string asm, list<dag> pattern> 811 : T1pI<oops, iops, itin, opc, asm, pattern>, 812 T1Misc<opA> { 813 bits<3> Rm; 814 bits<3> Rd; 815 let Inst{5-3} = Rm; 816 let Inst{2-0} = Rd; 817} 818 819// Helper classes for encoding T1sI patterns: 820class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 821 string opc, string asm, list<dag> pattern> 822 : T1sI<oops, iops, itin, opc, asm, pattern>, 823 T1DataProcessing<opA> { 824 bits<3> Rd; 825 bits<3> Rn; 826 let Inst{5-3} = Rn; 827 let Inst{2-0} = Rd; 828} 829class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 830 string opc, string asm, list<dag> pattern> 831 : T1sI<oops, iops, itin, opc, asm, pattern>, 832 T1General<opA> { 833 bits<3> Rm; 834 bits<3> Rn; 835 bits<3> Rd; 836 let Inst{8-6} = Rm; 837 let Inst{5-3} = Rn; 838 let Inst{2-0} = Rd; 839} 840class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 841 string opc, string asm, list<dag> pattern> 842 : T1sI<oops, iops, itin, opc, asm, pattern>, 843 T1General<opA> { 844 bits<3> Rd; 845 bits<3> Rm; 846 let Inst{5-3} = Rm; 847 let Inst{2-0} = Rd; 848} 849 850// Helper classes for encoding T1sIt patterns: 851class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 852 string opc, string asm, list<dag> pattern> 853 : T1sIt<oops, iops, itin, opc, asm, pattern>, 854 T1DataProcessing<opA> { 855 bits<3> Rdn; 856 bits<3> Rm; 857 let Inst{5-3} = Rm; 858 let Inst{2-0} = Rdn; 859} 860class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 861 string opc, string asm, list<dag> pattern> 862 : T1sIt<oops, iops, itin, opc, asm, pattern>, 863 T1General<opA> { 864 bits<3> Rdn; 865 bits<8> imm8; 866 let Inst{10-8} = Rdn; 867 let Inst{7-0} = imm8; 868} 869 870// Add with carry register 871let isCommutable = 1, Uses = [CPSR] in 872def tADC : // A8.6.2 873 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 874 "adc", "\t$Rdn, $Rm", 875 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>; 876 877// Add immediate 878def tADDi3 : // A8.6.4 T1 879 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), 880 IIC_iALUi, 881 "add", "\t$Rd, $Rm, $imm3", 882 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 883 bits<3> imm3; 884 let Inst{8-6} = imm3; 885} 886 887def tADDi8 : // A8.6.4 T2 888 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), 889 IIC_iALUi, 890 "add", "\t$Rdn, $imm8", 891 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 892 893// Add register 894let isCommutable = 1 in 895def tADDrr : // A8.6.6 T1 896 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 897 IIC_iALUr, 898 "add", "\t$Rd, $Rn, $Rm", 899 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>; 900 901let neverHasSideEffects = 1 in 902def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 903 "add", "\t$Rdn, $Rm", []>, 904 T1Special<{0,0,?,?}> { 905 // A8.6.6 T2 906 bits<4> Rdn; 907 bits<4> Rm; 908 let Inst{7} = Rdn{3}; 909 let Inst{6-3} = Rm; 910 let Inst{2-0} = Rdn{2-0}; 911} 912 913// AND register 914let isCommutable = 1 in 915def tAND : // A8.6.12 916 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 917 IIC_iBITr, 918 "and", "\t$Rdn, $Rm", 919 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>; 920 921// ASR immediate 922def tASRri : // A8.6.14 923 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 924 IIC_iMOVsi, 925 "asr", "\t$Rd, $Rm, $imm5", 926 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> { 927 bits<5> imm5; 928 let Inst{10-6} = imm5; 929} 930 931// ASR register 932def tASRrr : // A8.6.15 933 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 934 IIC_iMOVsr, 935 "asr", "\t$Rdn, $Rm", 936 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>; 937 938// BIC register 939def tBIC : // A8.6.20 940 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 941 IIC_iBITr, 942 "bic", "\t$Rdn, $Rm", 943 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>; 944 945// CMN register 946let isCompare = 1, Defs = [CPSR] in { 947//FIXME: Disable CMN, as CCodes are backwards from compare expectations 948// Compare-to-zero still works out, just not the relationals 949//def tCMN : // A8.6.33 950// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 951// IIC_iCMPr, 952// "cmn", "\t$lhs, $rhs", 953// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 954 955def tCMNz : // A8.6.33 956 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 957 IIC_iCMPr, 958 "cmn", "\t$Rn, $Rm", 959 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>; 960 961} // isCompare = 1, Defs = [CPSR] 962 963// CMP immediate 964let isCompare = 1, Defs = [CPSR] in { 965def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi, 966 "cmp", "\t$Rn, $imm8", 967 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 968 T1General<{1,0,1,?,?}> { 969 // A8.6.35 970 bits<3> Rn; 971 bits<8> imm8; 972 let Inst{10-8} = Rn; 973 let Inst{7-0} = imm8; 974} 975 976// CMP register 977def tCMPr : // A8.6.36 T1 978 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 979 IIC_iCMPr, 980 "cmp", "\t$Rn, $Rm", 981 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>; 982 983def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 984 "cmp", "\t$Rn, $Rm", []>, 985 T1Special<{0,1,?,?}> { 986 // A8.6.36 T2 987 bits<4> Rm; 988 bits<4> Rn; 989 let Inst{7} = Rn{3}; 990 let Inst{6-3} = Rm; 991 let Inst{2-0} = Rn{2-0}; 992} 993} // isCompare = 1, Defs = [CPSR] 994 995 996// XOR register 997let isCommutable = 1 in 998def tEOR : // A8.6.45 999 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1000 IIC_iBITr, 1001 "eor", "\t$Rdn, $Rm", 1002 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>; 1003 1004// LSL immediate 1005def tLSLri : // A8.6.88 1006 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 1007 IIC_iMOVsi, 1008 "lsl", "\t$Rd, $Rm, $imm5", 1009 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> { 1010 bits<5> imm5; 1011 let Inst{10-6} = imm5; 1012} 1013 1014// LSL register 1015def tLSLrr : // A8.6.89 1016 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1017 IIC_iMOVsr, 1018 "lsl", "\t$Rdn, $Rm", 1019 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>; 1020 1021// LSR immediate 1022def tLSRri : // A8.6.90 1023 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 1024 IIC_iMOVsi, 1025 "lsr", "\t$Rd, $Rm, $imm5", 1026 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> { 1027 bits<5> imm5; 1028 let Inst{10-6} = imm5; 1029} 1030 1031// LSR register 1032def tLSRrr : // A8.6.91 1033 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1034 IIC_iMOVsr, 1035 "lsr", "\t$Rdn, $Rm", 1036 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>; 1037 1038// Move register 1039let isMoveImm = 1 in 1040def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1041 "mov", "\t$Rd, $imm8", 1042 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1043 T1General<{1,0,0,?,?}> { 1044 // A8.6.96 1045 bits<3> Rd; 1046 bits<8> imm8; 1047 let Inst{10-8} = Rd; 1048 let Inst{7-0} = imm8; 1049} 1050 1051// A7-73: MOV(2) - mov setting flag. 1052 1053let neverHasSideEffects = 1 in { 1054def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1055 2, IIC_iMOVr, 1056 "mov", "\t$Rd, $Rm", "", []>, 1057 T1Special<{1,0,?,?}> { 1058 // A8.6.97 1059 bits<4> Rd; 1060 bits<4> Rm; 1061 let Inst{7} = Rd{3}; 1062 let Inst{6-3} = Rm; 1063 let Inst{2-0} = Rd{2-0}; 1064} 1065let Defs = [CPSR] in 1066def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1067 "movs\t$Rd, $Rm", []>, Encoding16 { 1068 // A8.6.97 1069 bits<3> Rd; 1070 bits<3> Rm; 1071 let Inst{15-6} = 0b0000000000; 1072 let Inst{5-3} = Rm; 1073 let Inst{2-0} = Rd; 1074} 1075} // neverHasSideEffects 1076 1077// Multiply register 1078let isCommutable = 1 in 1079def tMUL : // A8.6.105 T1 1080 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1081 IIC_iMUL32, 1082 "mul", "\t$Rdn, $Rm, $Rdn", 1083 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>; 1084 1085// Move inverse register 1086def tMVN : // A8.6.107 1087 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1088 "mvn", "\t$Rd, $Rn", 1089 [(set tGPR:$Rd, (not tGPR:$Rn))]>; 1090 1091// Bitwise or register 1092let isCommutable = 1 in 1093def tORR : // A8.6.114 1094 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1095 IIC_iBITr, 1096 "orr", "\t$Rdn, $Rm", 1097 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>; 1098 1099// Swaps 1100def tREV : // A8.6.134 1101 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1102 IIC_iUNAr, 1103 "rev", "\t$Rd, $Rm", 1104 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1105 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1106 1107def tREV16 : // A8.6.135 1108 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1109 IIC_iUNAr, 1110 "rev16", "\t$Rd, $Rm", 1111 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1112 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1113 1114def tREVSH : // A8.6.136 1115 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1116 IIC_iUNAr, 1117 "revsh", "\t$Rd, $Rm", 1118 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1119 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1120 1121// Rotate right register 1122def tROR : // A8.6.139 1123 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1124 IIC_iMOVsr, 1125 "ror", "\t$Rdn, $Rm", 1126 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>; 1127 1128// Negate register 1129def tRSB : // A8.6.141 1130 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1131 IIC_iALUi, 1132 "rsb", "\t$Rd, $Rn, #0", 1133 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; 1134 1135// Subtract with carry register 1136let Uses = [CPSR] in 1137def tSBC : // A8.6.151 1138 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1139 IIC_iALUr, 1140 "sbc", "\t$Rdn, $Rm", 1141 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>; 1142 1143// Subtract immediate 1144def tSUBi3 : // A8.6.210 T1 1145 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), 1146 IIC_iALUi, 1147 "sub", "\t$Rd, $Rm, $imm3", 1148 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1149 bits<3> imm3; 1150 let Inst{8-6} = imm3; 1151} 1152 1153def tSUBi8 : // A8.6.210 T2 1154 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), 1155 IIC_iALUi, 1156 "sub", "\t$Rdn, $imm8", 1157 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>; 1158 1159// Subtract register 1160def tSUBrr : // A8.6.212 1161 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1162 IIC_iALUr, 1163 "sub", "\t$Rd, $Rn, $Rm", 1164 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; 1165 1166// TODO: A7-96: STMIA - store multiple. 1167 1168// Sign-extend byte 1169def tSXTB : // A8.6.222 1170 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1171 IIC_iUNAr, 1172 "sxtb", "\t$Rd, $Rm", 1173 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1174 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1175 1176// Sign-extend short 1177def tSXTH : // A8.6.224 1178 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1179 IIC_iUNAr, 1180 "sxth", "\t$Rd, $Rm", 1181 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1182 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1183 1184// Test 1185let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1186def tTST : // A8.6.230 1187 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1188 "tst", "\t$Rn, $Rm", 1189 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>; 1190 1191// Zero-extend byte 1192def tUXTB : // A8.6.262 1193 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1194 IIC_iUNAr, 1195 "uxtb", "\t$Rd, $Rm", 1196 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1197 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1198 1199// Zero-extend short 1200def tUXTH : // A8.6.264 1201 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1202 IIC_iUNAr, 1203 "uxth", "\t$Rd, $Rm", 1204 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1205 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1206 1207// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1208// Expanded after instruction selection into a branch sequence. 1209let usesCustomInserter = 1 in // Expanded after instruction selection. 1210 def tMOVCCr_pseudo : 1211 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1212 NoItinerary, 1213 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1214 1215// tLEApcrel - Load a pc-relative address into a register without offending the 1216// assembler. 1217 1218def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1219 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>, 1220 T1Encoding<{1,0,1,0,0,?}> { 1221 bits<3> Rd; 1222 bits<8> addr; 1223 let Inst{10-8} = Rd; 1224 let Inst{7-0} = addr; 1225} 1226 1227let neverHasSideEffects = 1, isReMaterializable = 1 in 1228def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1229 2, IIC_iALUi, []>; 1230 1231def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1232 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1233 2, IIC_iALUi, []>; 1234 1235//===----------------------------------------------------------------------===// 1236// TLS Instructions 1237// 1238 1239// __aeabi_read_tp preserves the registers r1-r3. 1240// This is a pseudo inst so that we can get the encoding right, 1241// complete with fixup for the aeabi_read_tp function. 1242let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1243def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1244 [(set R0, ARMthread_pointer)]>; 1245 1246//===----------------------------------------------------------------------===// 1247// SJLJ Exception handling intrinsics 1248// 1249 1250// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1251// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1252// from some other function to get here, and we're using the stack frame for the 1253// containing function to save/restore registers, we can't keep anything live in 1254// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1255// tromped upon when we get here from a longjmp(). We force everything out of 1256// registers except for our own input by listing the relevant registers in 1257// Defs. By doing so, we also cause the prologue/epilogue code to actively 1258// preserve all of the callee-saved resgisters, which is exactly what we want. 1259// $val is a scratch register for our use. 1260let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1261 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in 1262def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1263 AddrModeNone, 0, NoItinerary, "","", 1264 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1265 1266// FIXME: Non-Darwin version(s) 1267let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1268 Defs = [ R7, LR, SP ] in 1269def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1270 AddrModeNone, 0, IndexModeNone, 1271 Pseudo, NoItinerary, "", "", 1272 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1273 Requires<[IsThumb, IsDarwin]>; 1274 1275//===----------------------------------------------------------------------===// 1276// Non-Instruction Patterns 1277// 1278 1279// Comparisons 1280def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1281 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1282def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1283 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1284 1285// Add with carry 1286def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1287 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1288def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1289 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1290def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1291 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1292 1293// Subtract with carry 1294def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1295 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1296def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1297 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1298def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1299 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1300 1301// ConstantPool, GlobalAddress 1302def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1303def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1304 1305// JumpTable 1306def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1307 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1308 1309// Direct calls 1310def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1311 Requires<[IsThumb, IsNotDarwin]>; 1312def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 1313 Requires<[IsThumb, IsDarwin]>; 1314 1315def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1316 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 1317def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 1318 Requires<[IsThumb, HasV5T, IsDarwin]>; 1319 1320// Indirect calls to ARM routines 1321def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1322 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 1323def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 1324 Requires<[IsThumb, HasV5T, IsDarwin]>; 1325 1326// zextload i1 -> zextload i8 1327def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1328 (tLDRBr t_addrmode_rrs1:$addr)>; 1329def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1330 (tLDRBi t_addrmode_is1:$addr)>; 1331 1332// extload -> zextload 1333def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1334def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1335def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1336def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1337def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1338def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1339 1340// If it's impossible to use [r,r] address mode for sextload, select to 1341// ldr{b|h} + sxt{b|h} instead. 1342def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1343 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1344 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1345def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1346 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1347 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1348def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1349 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1350 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1351def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1352 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1353 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1354 1355def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1356 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1357def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1358 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1359def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1360 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1361def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1362 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1363 1364// Large immediate handling. 1365 1366// Two piece imms. 1367def : T1Pat<(i32 thumb_immshifted:$src), 1368 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1369 (thumb_immshifted_shamt imm:$src))>; 1370 1371def : T1Pat<(i32 imm0_255_comp:$src), 1372 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1373 1374// Pseudo instruction that combines ldr from constpool and add pc. This should 1375// be expanded into two instructions late to allow if-conversion and 1376// scheduling. 1377let isReMaterializable = 1 in 1378def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1379 NoItinerary, 1380 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1381 imm:$cp))]>, 1382 Requires<[IsThumb, IsThumb1Only]>; 1383 1384// Pseudo-instruction for merged POP and return. 1385// FIXME: remove when we have a way to marking a MI with these properties. 1386let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1387 hasExtraDefRegAllocReq = 1 in 1388def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1389 2, IIC_iPop_Br, [], 1390 (tPOP pred:$p, reglist:$regs)>; 1391 1392// Indirect branch using "mov pc, $Rm" 1393let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1394 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1395 2, IIC_Br, [(brind GPR:$Rm)], 1396 (tMOVr PC, GPR:$Rm, pred:$p)>; 1397} 1398