ARMCodeEmitter.cpp revision 221345
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstPoolInstruction(const MachineInstr &MI); 92 void emitMOVi32immInstruction(const MachineInstr &MI); 93 void emitMOVi2piecesInstruction(const MachineInstr &MI); 94 void emitLEApcrelJTInstruction(const MachineInstr &MI); 95 void emitPseudoMoveInstruction(const MachineInstr &MI); 96 void addPCLabel(unsigned LabelID); 97 void emitPseudoInstruction(const MachineInstr &MI); 98 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 99 const TargetInstrDesc &TID, 100 const MachineOperand &MO, 101 unsigned OpIdx); 102 103 unsigned getMachineSoImmOpValue(unsigned SoImm); 104 unsigned getAddrModeSBit(const MachineInstr &MI, 105 const TargetInstrDesc &TID) const; 106 107 void emitDataProcessingInstruction(const MachineInstr &MI, 108 unsigned ImplicitRd = 0, 109 unsigned ImplicitRn = 0); 110 111 void emitLoadStoreInstruction(const MachineInstr &MI, 112 unsigned ImplicitRd = 0, 113 unsigned ImplicitRn = 0); 114 115 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 116 unsigned ImplicitRn = 0); 117 118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 119 120 void emitMulFrmInstruction(const MachineInstr &MI); 121 122 void emitExtendInstruction(const MachineInstr &MI); 123 124 void emitMiscArithInstruction(const MachineInstr &MI); 125 126 void emitSaturateInstruction(const MachineInstr &MI); 127 128 void emitBranchInstruction(const MachineInstr &MI); 129 130 void emitInlineJumpTable(unsigned JTIndex); 131 132 void emitMiscBranchInstruction(const MachineInstr &MI); 133 134 void emitVFPArithInstruction(const MachineInstr &MI); 135 136 void emitVFPConversionInstruction(const MachineInstr &MI); 137 138 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 141 142 void emitNEONLaneInstruction(const MachineInstr &MI); 143 void emitNEONDupInstruction(const MachineInstr &MI); 144 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 145 void emitNEON2RegInstruction(const MachineInstr &MI); 146 void emitNEON3RegInstruction(const MachineInstr &MI); 147 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 149 /// operand requires relocation, record the relocation and return zero. 150 unsigned getMachineOpValue(const MachineInstr &MI, 151 const MachineOperand &MO) const; 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 154 } 155 156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 157 // TableGen'erated getBinaryCodeForInstr() function to encode any 158 // operand values, instead querying getMachineOpValue() directly for 159 // each operand it needs to encode. Thus, any of the new encoder 160 // helper functions can simply return 0 as the values the return 161 // are already handled elsewhere. They are placeholders to allow this 162 // encoder to continue to function until the MC encoder is sufficiently 163 // far along that this one can be eliminated entirely. 164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 165 const { return 0; } 166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 167 const { return 0; } 168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 169 const { return 0; } 170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 171 const { return 0; } 172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 173 const { return 0; } 174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 175 const { return 0; } 176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 177 const { return 0; } 178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 179 const { return 0; } 180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 181 const { return 0; } 182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 189 unsigned Op) const { return 0; } 190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) 199 const { return 0; } 200 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 205 const { return 0; } 206 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 207 const { return 0; } 208 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 209 const { return 0; } 210 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 211 const { return 0; } 212 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 213 const { return 0; } 214 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 215 const { return 0; } 216 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) 217 const { return 0; } 218 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) 219 const { return 0; } 220 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 221 const { return 0; } 222 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 223 const { return 0; } 224 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 225 const { return 0; } 226 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 227 const { return 0; } 228 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 229 unsigned Op) const { return 0; } 230 unsigned getMsbOpValue(const MachineInstr &MI, 231 unsigned Op) const { return 0; } 232 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 233 const {return 0; } 234 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 235 const { return 0; } 236 237 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 238 const { 239 // {17-13} = reg 240 // {12} = (U)nsigned (add == '1', sub == '0') 241 // {11-0} = imm12 242 const MachineOperand &MO = MI.getOperand(Op); 243 const MachineOperand &MO1 = MI.getOperand(Op + 1); 244 if (!MO.isReg()) { 245 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 246 return 0; 247 } 248 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 249 int32_t Imm12 = MO1.getImm(); 250 uint32_t Binary; 251 Binary = Imm12 & 0xfff; 252 if (Imm12 >= 0) 253 Binary |= (1 << 12); 254 Binary |= (Reg << 13); 255 return Binary; 256 } 257 258 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const { 259 return 0; 260 } 261 262 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 263 const { return 0;} 264 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 265 const { return 0;} 266 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 267 const { return 0;} 268 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 269 const { return 0; } 270 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 271 const { return 0; } 272 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op) 273 const { return 0; } 274 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 275 const { return 0; } 276 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 277 const { return 0; } 278 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 279 // {17-13} = reg 280 // {12} = (U)nsigned (add == '1', sub == '0') 281 // {11-0} = imm12 282 const MachineOperand &MO = MI.getOperand(Op); 283 const MachineOperand &MO1 = MI.getOperand(Op + 1); 284 if (!MO.isReg()) { 285 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 286 return 0; 287 } 288 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 289 int32_t Imm12 = MO1.getImm(); 290 291 // Special value for #-0 292 if (Imm12 == INT32_MIN) 293 Imm12 = 0; 294 295 // Immediate is always encoded as positive. The 'U' bit controls add vs 296 // sub. 297 bool isAdd = true; 298 if (Imm12 < 0) { 299 Imm12 = -Imm12; 300 isAdd = false; 301 } 302 303 uint32_t Binary = Imm12 & 0xfff; 304 if (isAdd) 305 Binary |= (1 << 12); 306 Binary |= (Reg << 13); 307 return Binary; 308 } 309 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 310 const { return 0; } 311 312 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 313 const { return 0; } 314 315 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 316 const { return 0; } 317 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 318 const { return 0; } 319 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 320 const { return 0; } 321 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 322 const { return 0; } 323 324 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 325 /// machine operand requires relocation, record the relocation and return 326 /// zero. 327 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 328 unsigned Reloc); 329 330 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 331 /// 332 unsigned getShiftOp(unsigned Imm) const ; 333 334 /// Routines that handle operands which add machine relocations which are 335 /// fixed up by the relocation stage. 336 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 337 bool MayNeedFarStub, bool Indirect, 338 intptr_t ACPV = 0) const; 339 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 340 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 341 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 342 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 343 intptr_t JTBase = 0) const; 344 }; 345} 346 347char ARMCodeEmitter::ID = 0; 348 349/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 350/// code to the specified MCE object. 351FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 352 JITCodeEmitter &JCE) { 353 return new ARMCodeEmitter(TM, JCE); 354} 355 356bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 357 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 358 MF.getTarget().getRelocationModel() != Reloc::Static) && 359 "JIT relocation model must be set to static or default!"); 360 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 361 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 362 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 363 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 364 MCPEs = &MF.getConstantPool()->getConstants(); 365 MJTEs = 0; 366 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 367 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 368 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 369 JTI->Initialize(MF, IsPIC); 370 MMI = &getAnalysis<MachineModuleInfo>(); 371 MCE.setModuleInfo(MMI); 372 373 do { 374 DEBUG(errs() << "JITTing function '" 375 << MF.getFunction()->getName() << "'\n"); 376 MCE.startFunction(MF); 377 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 378 MBB != E; ++MBB) { 379 MCE.StartMachineBasicBlock(MBB); 380 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 381 I != E; ++I) 382 emitInstruction(*I); 383 } 384 } while (MCE.finishFunction(MF)); 385 386 return false; 387} 388 389/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 390/// 391unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 392 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 393 default: llvm_unreachable("Unknown shift opc!"); 394 case ARM_AM::asr: return 2; 395 case ARM_AM::lsl: return 0; 396 case ARM_AM::lsr: return 1; 397 case ARM_AM::ror: 398 case ARM_AM::rrx: return 3; 399 } 400 return 0; 401} 402 403/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 404/// machine operand requires relocation, record the relocation and return zero. 405unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 406 const MachineOperand &MO, 407 unsigned Reloc) { 408 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 409 && "Relocation to this function should be for movt or movw"); 410 411 if (MO.isImm()) 412 return static_cast<unsigned>(MO.getImm()); 413 else if (MO.isGlobal()) 414 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 415 else if (MO.isSymbol()) 416 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 417 else if (MO.isMBB()) 418 emitMachineBasicBlock(MO.getMBB(), Reloc); 419 else { 420#ifndef NDEBUG 421 errs() << MO; 422#endif 423 llvm_unreachable("Unsupported operand type for movw/movt"); 424 } 425 return 0; 426} 427 428/// getMachineOpValue - Return binary encoding of operand. If the machine 429/// operand requires relocation, record the relocation and return zero. 430unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 431 const MachineOperand &MO) const { 432 if (MO.isReg()) 433 return getARMRegisterNumbering(MO.getReg()); 434 else if (MO.isImm()) 435 return static_cast<unsigned>(MO.getImm()); 436 else if (MO.isGlobal()) 437 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 438 else if (MO.isSymbol()) 439 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 440 else if (MO.isCPI()) { 441 const TargetInstrDesc &TID = MI.getDesc(); 442 // For VFP load, the immediate offset is multiplied by 4. 443 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 444 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 445 emitConstPoolAddress(MO.getIndex(), Reloc); 446 } else if (MO.isJTI()) 447 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 448 else if (MO.isMBB()) 449 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 450 else 451 llvm_unreachable("Unable to encode MachineOperand!"); 452 return 0; 453} 454 455/// emitGlobalAddress - Emit the specified address to the code stream. 456/// 457void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 458 bool MayNeedFarStub, bool Indirect, 459 intptr_t ACPV) const { 460 MachineRelocation MR = Indirect 461 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 462 const_cast<GlobalValue *>(GV), 463 ACPV, MayNeedFarStub) 464 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 465 const_cast<GlobalValue *>(GV), ACPV, 466 MayNeedFarStub); 467 MCE.addRelocation(MR); 468} 469 470/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 471/// be emitted to the current location in the function, and allow it to be PC 472/// relative. 473void ARMCodeEmitter:: 474emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 475 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 476 Reloc, ES)); 477} 478 479/// emitConstPoolAddress - Arrange for the address of an constant pool 480/// to be emitted to the current location in the function, and allow it to be PC 481/// relative. 482void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 483 // Tell JIT emitter we'll resolve the address. 484 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 485 Reloc, CPI, 0, true)); 486} 487 488/// emitJumpTableAddress - Arrange for the address of a jump table to 489/// be emitted to the current location in the function, and allow it to be PC 490/// relative. 491void ARMCodeEmitter:: 492emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 493 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 494 Reloc, JTIndex, 0, true)); 495} 496 497/// emitMachineBasicBlock - Emit the specified address basic block. 498void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 499 unsigned Reloc, 500 intptr_t JTBase) const { 501 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 502 Reloc, BB, JTBase)); 503} 504 505void ARMCodeEmitter::emitWordLE(unsigned Binary) { 506 DEBUG(errs() << " 0x"; 507 errs().write_hex(Binary) << "\n"); 508 MCE.emitWordLE(Binary); 509} 510 511void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 512 DEBUG(errs() << " 0x"; 513 errs().write_hex(Binary) << "\n"); 514 MCE.emitDWordLE(Binary); 515} 516 517void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 518 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 519 520 MCE.processDebugLoc(MI.getDebugLoc(), true); 521 522 ++NumEmitted; // Keep track of the # of mi's emitted 523 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 524 default: { 525 llvm_unreachable("Unhandled instruction encoding format!"); 526 break; 527 } 528 case ARMII::MiscFrm: 529 if (MI.getOpcode() == ARM::LEApcrelJT) { 530 // Materialize jumptable address. 531 emitLEApcrelJTInstruction(MI); 532 break; 533 } 534 llvm_unreachable("Unhandled instruction encoding!"); 535 break; 536 case ARMII::Pseudo: 537 emitPseudoInstruction(MI); 538 break; 539 case ARMII::DPFrm: 540 case ARMII::DPSoRegFrm: 541 emitDataProcessingInstruction(MI); 542 break; 543 case ARMII::LdFrm: 544 case ARMII::StFrm: 545 emitLoadStoreInstruction(MI); 546 break; 547 case ARMII::LdMiscFrm: 548 case ARMII::StMiscFrm: 549 emitMiscLoadStoreInstruction(MI); 550 break; 551 case ARMII::LdStMulFrm: 552 emitLoadStoreMultipleInstruction(MI); 553 break; 554 case ARMII::MulFrm: 555 emitMulFrmInstruction(MI); 556 break; 557 case ARMII::ExtFrm: 558 emitExtendInstruction(MI); 559 break; 560 case ARMII::ArithMiscFrm: 561 emitMiscArithInstruction(MI); 562 break; 563 case ARMII::SatFrm: 564 emitSaturateInstruction(MI); 565 break; 566 case ARMII::BrFrm: 567 emitBranchInstruction(MI); 568 break; 569 case ARMII::BrMiscFrm: 570 emitMiscBranchInstruction(MI); 571 break; 572 // VFP instructions. 573 case ARMII::VFPUnaryFrm: 574 case ARMII::VFPBinaryFrm: 575 emitVFPArithInstruction(MI); 576 break; 577 case ARMII::VFPConv1Frm: 578 case ARMII::VFPConv2Frm: 579 case ARMII::VFPConv3Frm: 580 case ARMII::VFPConv4Frm: 581 case ARMII::VFPConv5Frm: 582 emitVFPConversionInstruction(MI); 583 break; 584 case ARMII::VFPLdStFrm: 585 emitVFPLoadStoreInstruction(MI); 586 break; 587 case ARMII::VFPLdStMulFrm: 588 emitVFPLoadStoreMultipleInstruction(MI); 589 break; 590 591 // NEON instructions. 592 case ARMII::NGetLnFrm: 593 case ARMII::NSetLnFrm: 594 emitNEONLaneInstruction(MI); 595 break; 596 case ARMII::NDupFrm: 597 emitNEONDupInstruction(MI); 598 break; 599 case ARMII::N1RegModImmFrm: 600 emitNEON1RegModImmInstruction(MI); 601 break; 602 case ARMII::N2RegFrm: 603 emitNEON2RegInstruction(MI); 604 break; 605 case ARMII::N3RegFrm: 606 emitNEON3RegInstruction(MI); 607 break; 608 } 609 MCE.processDebugLoc(MI.getDebugLoc(), false); 610} 611 612void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 613 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 614 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 615 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 616 617 // Remember the CONSTPOOL_ENTRY address for later relocation. 618 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 619 620 // Emit constpool island entry. In most cases, the actual values will be 621 // resolved and relocated after code emission. 622 if (MCPE.isMachineConstantPoolEntry()) { 623 ARMConstantPoolValue *ACPV = 624 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 625 626 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 627 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 628 629 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 630 const GlobalValue *GV = ACPV->getGV(); 631 if (GV) { 632 Reloc::Model RelocM = TM.getRelocationModel(); 633 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 634 isa<Function>(GV), 635 Subtarget->GVIsIndirectSymbol(GV, RelocM), 636 (intptr_t)ACPV); 637 } else { 638 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 639 } 640 emitWordLE(0); 641 } else { 642 const Constant *CV = MCPE.Val.ConstVal; 643 644 DEBUG({ 645 errs() << " ** Constant pool #" << CPI << " @ " 646 << (void*)MCE.getCurrentPCValue() << " "; 647 if (const Function *F = dyn_cast<Function>(CV)) 648 errs() << F->getName(); 649 else 650 errs() << *CV; 651 errs() << '\n'; 652 }); 653 654 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 655 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 656 emitWordLE(0); 657 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 658 uint32_t Val = uint32_t(*CI->getValue().getRawData()); 659 emitWordLE(Val); 660 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 661 if (CFP->getType()->isFloatTy()) 662 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 663 else if (CFP->getType()->isDoubleTy()) 664 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 665 else { 666 llvm_unreachable("Unable to handle this constantpool entry!"); 667 } 668 } else { 669 llvm_unreachable("Unable to handle this constantpool entry!"); 670 } 671 } 672} 673 674void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 675 const MachineOperand &MO0 = MI.getOperand(0); 676 const MachineOperand &MO1 = MI.getOperand(1); 677 678 // Emit the 'movw' instruction. 679 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 680 681 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 682 683 // Set the conditional execution predicate. 684 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 685 686 // Encode Rd. 687 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 688 689 // Encode imm16 as imm4:imm12 690 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 691 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 692 emitWordLE(Binary); 693 694 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 695 // Emit the 'movt' instruction. 696 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 697 698 // Set the conditional execution predicate. 699 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 700 701 // Encode Rd. 702 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 703 704 // Encode imm16 as imm4:imm1, same as movw above. 705 Binary |= Hi16 & 0xFFF; 706 Binary |= ((Hi16 >> 12) & 0xF) << 16; 707 emitWordLE(Binary); 708} 709 710void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 711 const MachineOperand &MO0 = MI.getOperand(0); 712 const MachineOperand &MO1 = MI.getOperand(1); 713 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 714 "Not a valid so_imm value!"); 715 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 716 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 717 718 // Emit the 'mov' instruction. 719 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 720 721 // Set the conditional execution predicate. 722 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 723 724 // Encode Rd. 725 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 726 727 // Encode so_imm. 728 // Set bit I(25) to identify this is the immediate form of <shifter_op> 729 Binary |= 1 << ARMII::I_BitShift; 730 Binary |= getMachineSoImmOpValue(V1); 731 emitWordLE(Binary); 732 733 // Now the 'orr' instruction. 734 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 735 736 // Set the conditional execution predicate. 737 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 738 739 // Encode Rd. 740 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 741 742 // Encode Rn. 743 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 744 745 // Encode so_imm. 746 // Set bit I(25) to identify this is the immediate form of <shifter_op> 747 Binary |= 1 << ARMII::I_BitShift; 748 Binary |= getMachineSoImmOpValue(V2); 749 emitWordLE(Binary); 750} 751 752void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 753 // It's basically add r, pc, (LJTI - $+8) 754 755 const TargetInstrDesc &TID = MI.getDesc(); 756 757 // Emit the 'add' instruction. 758 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 759 760 // Set the conditional execution predicate 761 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 762 763 // Encode S bit if MI modifies CPSR. 764 Binary |= getAddrModeSBit(MI, TID); 765 766 // Encode Rd. 767 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 768 769 // Encode Rn which is PC. 770 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 771 772 // Encode the displacement. 773 Binary |= 1 << ARMII::I_BitShift; 774 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 775 776 emitWordLE(Binary); 777} 778 779void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 780 unsigned Opcode = MI.getDesc().Opcode; 781 782 // Part of binary is determined by TableGn. 783 unsigned Binary = getBinaryCodeForInstr(MI); 784 785 // Set the conditional execution predicate 786 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 787 788 // Encode S bit if MI modifies CPSR. 789 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 790 Binary |= 1 << ARMII::S_BitShift; 791 792 // Encode register def if there is one. 793 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 794 795 // Encode the shift operation. 796 switch (Opcode) { 797 default: break; 798 case ARM::RRX: 799 // rrx 800 Binary |= 0x6 << 4; 801 break; 802 case ARM::MOVsrl_flag: 803 // lsr #1 804 Binary |= (0x2 << 4) | (1 << 7); 805 break; 806 case ARM::MOVsra_flag: 807 // asr #1 808 Binary |= (0x4 << 4) | (1 << 7); 809 break; 810 } 811 812 // Encode register Rm. 813 Binary |= getMachineOpValue(MI, 1); 814 815 emitWordLE(Binary); 816} 817 818void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 819 DEBUG(errs() << " ** LPC" << LabelID << " @ " 820 << (void*)MCE.getCurrentPCValue() << '\n'); 821 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 822} 823 824void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 825 unsigned Opcode = MI.getDesc().Opcode; 826 switch (Opcode) { 827 default: 828 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 829 case ARM::BX_CALL: 830 case ARM::BMOVPCRX_CALL: 831 case ARM::BXr9_CALL: 832 case ARM::BMOVPCRXr9_CALL: { 833 // First emit mov lr, pc 834 unsigned Binary = 0x01a0e00f; 835 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 836 emitWordLE(Binary); 837 838 // and then emit the branch. 839 emitMiscBranchInstruction(MI); 840 break; 841 } 842 case TargetOpcode::INLINEASM: { 843 // We allow inline assembler nodes with empty bodies - they can 844 // implicitly define registers, which is ok for JIT. 845 if (MI.getOperand(0).getSymbolName()[0]) { 846 report_fatal_error("JIT does not support inline asm!"); 847 } 848 break; 849 } 850 case TargetOpcode::PROLOG_LABEL: 851 case TargetOpcode::EH_LABEL: 852 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 853 break; 854 case TargetOpcode::IMPLICIT_DEF: 855 case TargetOpcode::KILL: 856 // Do nothing. 857 break; 858 case ARM::CONSTPOOL_ENTRY: 859 emitConstPoolInstruction(MI); 860 break; 861 case ARM::PICADD: { 862 // Remember of the address of the PC label for relocation later. 863 addPCLabel(MI.getOperand(2).getImm()); 864 // PICADD is just an add instruction that implicitly read pc. 865 emitDataProcessingInstruction(MI, 0, ARM::PC); 866 break; 867 } 868 case ARM::PICLDR: 869 case ARM::PICLDRB: 870 case ARM::PICSTR: 871 case ARM::PICSTRB: { 872 // Remember of the address of the PC label for relocation later. 873 addPCLabel(MI.getOperand(2).getImm()); 874 // These are just load / store instructions that implicitly read pc. 875 emitLoadStoreInstruction(MI, 0, ARM::PC); 876 break; 877 } 878 case ARM::PICLDRH: 879 case ARM::PICLDRSH: 880 case ARM::PICLDRSB: 881 case ARM::PICSTRH: { 882 // Remember of the address of the PC label for relocation later. 883 addPCLabel(MI.getOperand(2).getImm()); 884 // These are just load / store instructions that implicitly read pc. 885 emitMiscLoadStoreInstruction(MI, ARM::PC); 886 break; 887 } 888 889 case ARM::MOVi32imm: 890 // Two instructions to materialize a constant. 891 if (Subtarget->hasV6T2Ops()) 892 emitMOVi32immInstruction(MI); 893 else 894 emitMOVi2piecesInstruction(MI); 895 break; 896 897 case ARM::LEApcrelJT: 898 // Materialize jumptable address. 899 emitLEApcrelJTInstruction(MI); 900 break; 901 case ARM::RRX: 902 case ARM::MOVsrl_flag: 903 case ARM::MOVsra_flag: 904 emitPseudoMoveInstruction(MI); 905 break; 906 } 907} 908 909unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 910 const TargetInstrDesc &TID, 911 const MachineOperand &MO, 912 unsigned OpIdx) { 913 unsigned Binary = getMachineOpValue(MI, MO); 914 915 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 916 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 917 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 918 919 // Encode the shift opcode. 920 unsigned SBits = 0; 921 unsigned Rs = MO1.getReg(); 922 if (Rs) { 923 // Set shift operand (bit[7:4]). 924 // LSL - 0001 925 // LSR - 0011 926 // ASR - 0101 927 // ROR - 0111 928 // RRX - 0110 and bit[11:8] clear. 929 switch (SOpc) { 930 default: llvm_unreachable("Unknown shift opc!"); 931 case ARM_AM::lsl: SBits = 0x1; break; 932 case ARM_AM::lsr: SBits = 0x3; break; 933 case ARM_AM::asr: SBits = 0x5; break; 934 case ARM_AM::ror: SBits = 0x7; break; 935 case ARM_AM::rrx: SBits = 0x6; break; 936 } 937 } else { 938 // Set shift operand (bit[6:4]). 939 // LSL - 000 940 // LSR - 010 941 // ASR - 100 942 // ROR - 110 943 switch (SOpc) { 944 default: llvm_unreachable("Unknown shift opc!"); 945 case ARM_AM::lsl: SBits = 0x0; break; 946 case ARM_AM::lsr: SBits = 0x2; break; 947 case ARM_AM::asr: SBits = 0x4; break; 948 case ARM_AM::ror: SBits = 0x6; break; 949 } 950 } 951 Binary |= SBits << 4; 952 if (SOpc == ARM_AM::rrx) 953 return Binary; 954 955 // Encode the shift operation Rs or shift_imm (except rrx). 956 if (Rs) { 957 // Encode Rs bit[11:8]. 958 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 959 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 960 } 961 962 // Encode shift_imm bit[11:7]. 963 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 964} 965 966unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 967 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 968 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 969 970 // Encode rotate_imm. 971 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 972 << ARMII::SoRotImmShift; 973 974 // Encode immed_8. 975 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 976 return Binary; 977} 978 979unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 980 const TargetInstrDesc &TID) const { 981 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i >= e; --i){ 982 const MachineOperand &MO = MI.getOperand(i-1); 983 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 984 return 1 << ARMII::S_BitShift; 985 } 986 return 0; 987} 988 989void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 990 unsigned ImplicitRd, 991 unsigned ImplicitRn) { 992 const TargetInstrDesc &TID = MI.getDesc(); 993 994 // Part of binary is determined by TableGn. 995 unsigned Binary = getBinaryCodeForInstr(MI); 996 997 // Set the conditional execution predicate 998 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 999 1000 // Encode S bit if MI modifies CPSR. 1001 Binary |= getAddrModeSBit(MI, TID); 1002 1003 // Encode register def if there is one. 1004 unsigned NumDefs = TID.getNumDefs(); 1005 unsigned OpIdx = 0; 1006 if (NumDefs) 1007 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1008 else if (ImplicitRd) 1009 // Special handling for implicit use (e.g. PC). 1010 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1011 1012 if (TID.Opcode == ARM::MOVi16) { 1013 // Get immediate from MI. 1014 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1015 ARM::reloc_arm_movw); 1016 // Encode imm which is the same as in emitMOVi32immInstruction(). 1017 Binary |= Lo16 & 0xFFF; 1018 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1019 emitWordLE(Binary); 1020 return; 1021 } else if(TID.Opcode == ARM::MOVTi16) { 1022 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1023 ARM::reloc_arm_movt) >> 16); 1024 Binary |= Hi16 & 0xFFF; 1025 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1026 emitWordLE(Binary); 1027 return; 1028 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { 1029 uint32_t v = ~MI.getOperand(2).getImm(); 1030 int32_t lsb = CountTrailingZeros_32(v); 1031 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 1032 // Instr{20-16} = msb, Instr{11-7} = lsb 1033 Binary |= (msb & 0x1F) << 16; 1034 Binary |= (lsb & 0x1F) << 7; 1035 emitWordLE(Binary); 1036 return; 1037 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { 1038 // Encode Rn in Instr{0-3} 1039 Binary |= getMachineOpValue(MI, OpIdx++); 1040 1041 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1042 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1043 1044 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1045 Binary |= (widthm1 & 0x1F) << 16; 1046 Binary |= (lsb & 0x1F) << 7; 1047 emitWordLE(Binary); 1048 return; 1049 } 1050 1051 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1052 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1053 ++OpIdx; 1054 1055 // Encode first non-shifter register operand if there is one. 1056 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 1057 if (!isUnary) { 1058 if (ImplicitRn) 1059 // Special handling for implicit use (e.g. PC). 1060 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1061 else { 1062 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1063 ++OpIdx; 1064 } 1065 } 1066 1067 // Encode shifter operand. 1068 const MachineOperand &MO = MI.getOperand(OpIdx); 1069 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1070 // Encode SoReg. 1071 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 1072 return; 1073 } 1074 1075 if (MO.isReg()) { 1076 // Encode register Rm. 1077 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1078 return; 1079 } 1080 1081 // Encode so_imm. 1082 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1083 1084 emitWordLE(Binary); 1085} 1086 1087void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1088 unsigned ImplicitRd, 1089 unsigned ImplicitRn) { 1090 const TargetInstrDesc &TID = MI.getDesc(); 1091 unsigned Form = TID.TSFlags & ARMII::FormMask; 1092 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1093 1094 // Part of binary is determined by TableGn. 1095 unsigned Binary = getBinaryCodeForInstr(MI); 1096 1097 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1098 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1099 MI.getOpcode() == ARM::STRi12) { 1100 emitWordLE(Binary); 1101 return; 1102 } 1103 1104 // Set the conditional execution predicate 1105 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1106 1107 unsigned OpIdx = 0; 1108 1109 // Operand 0 of a pre- and post-indexed store is the address base 1110 // writeback. Skip it. 1111 bool Skipped = false; 1112 if (IsPrePost && Form == ARMII::StFrm) { 1113 ++OpIdx; 1114 Skipped = true; 1115 } 1116 1117 // Set first operand 1118 if (ImplicitRd) 1119 // Special handling for implicit use (e.g. PC). 1120 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1121 else 1122 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1123 1124 // Set second operand 1125 if (ImplicitRn) 1126 // Special handling for implicit use (e.g. PC). 1127 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1128 else 1129 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1130 1131 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1132 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1133 ++OpIdx; 1134 1135 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1136 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1137 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1138 1139 // Set bit U(23) according to sign of immed value (positive or negative). 1140 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1141 ARMII::U_BitShift); 1142 if (!MO2.getReg()) { // is immediate 1143 if (ARM_AM::getAM2Offset(AM2Opc)) 1144 // Set the value of offset_12 field 1145 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1146 emitWordLE(Binary); 1147 return; 1148 } 1149 1150 // Set bit I(25), because this is not in immediate encoding. 1151 Binary |= 1 << ARMII::I_BitShift; 1152 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1153 // Set bit[3:0] to the corresponding Rm register 1154 Binary |= getARMRegisterNumbering(MO2.getReg()); 1155 1156 // If this instr is in scaled register offset/index instruction, set 1157 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1158 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1159 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1160 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1161 } 1162 1163 emitWordLE(Binary); 1164} 1165 1166void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1167 unsigned ImplicitRn) { 1168 const TargetInstrDesc &TID = MI.getDesc(); 1169 unsigned Form = TID.TSFlags & ARMII::FormMask; 1170 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1171 1172 // Part of binary is determined by TableGn. 1173 unsigned Binary = getBinaryCodeForInstr(MI); 1174 1175 // Set the conditional execution predicate 1176 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1177 1178 unsigned OpIdx = 0; 1179 1180 // Operand 0 of a pre- and post-indexed store is the address base 1181 // writeback. Skip it. 1182 bool Skipped = false; 1183 if (IsPrePost && Form == ARMII::StMiscFrm) { 1184 ++OpIdx; 1185 Skipped = true; 1186 } 1187 1188 // Set first operand 1189 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1190 1191 // Skip LDRD and STRD's second operand. 1192 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 1193 ++OpIdx; 1194 1195 // Set second operand 1196 if (ImplicitRn) 1197 // Special handling for implicit use (e.g. PC). 1198 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1199 else 1200 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1201 1202 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1203 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1204 ++OpIdx; 1205 1206 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1207 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1208 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1209 1210 // Set bit U(23) according to sign of immed value (positive or negative) 1211 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1212 ARMII::U_BitShift); 1213 1214 // If this instr is in register offset/index encoding, set bit[3:0] 1215 // to the corresponding Rm register. 1216 if (MO2.getReg()) { 1217 Binary |= getARMRegisterNumbering(MO2.getReg()); 1218 emitWordLE(Binary); 1219 return; 1220 } 1221 1222 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1223 Binary |= 1 << ARMII::AM3_I_BitShift; 1224 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1225 // Set operands 1226 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1227 Binary |= (ImmOffs & 0xF); // immedL 1228 } 1229 1230 emitWordLE(Binary); 1231} 1232 1233static unsigned getAddrModeUPBits(unsigned Mode) { 1234 unsigned Binary = 0; 1235 1236 // Set addressing mode by modifying bits U(23) and P(24) 1237 // IA - Increment after - bit U = 1 and bit P = 0 1238 // IB - Increment before - bit U = 1 and bit P = 1 1239 // DA - Decrement after - bit U = 0 and bit P = 0 1240 // DB - Decrement before - bit U = 0 and bit P = 1 1241 switch (Mode) { 1242 default: llvm_unreachable("Unknown addressing sub-mode!"); 1243 case ARM_AM::da: break; 1244 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1245 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1246 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1247 } 1248 1249 return Binary; 1250} 1251 1252void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1253 const TargetInstrDesc &TID = MI.getDesc(); 1254 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1255 1256 // Part of binary is determined by TableGn. 1257 unsigned Binary = getBinaryCodeForInstr(MI); 1258 1259 // Set the conditional execution predicate 1260 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1261 1262 // Skip operand 0 of an instruction with base register update. 1263 unsigned OpIdx = 0; 1264 if (IsUpdating) 1265 ++OpIdx; 1266 1267 // Set base address operand 1268 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1269 1270 // Set addressing mode by modifying bits U(23) and P(24) 1271 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1272 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1273 1274 // Set bit W(21) 1275 if (IsUpdating) 1276 Binary |= 0x1 << ARMII::W_BitShift; 1277 1278 // Set registers 1279 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1280 const MachineOperand &MO = MI.getOperand(i); 1281 if (!MO.isReg() || MO.isImplicit()) 1282 break; 1283 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1284 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1285 RegNum < 16); 1286 Binary |= 0x1 << RegNum; 1287 } 1288 1289 emitWordLE(Binary); 1290} 1291 1292void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1293 const TargetInstrDesc &TID = MI.getDesc(); 1294 1295 // Part of binary is determined by TableGn. 1296 unsigned Binary = getBinaryCodeForInstr(MI); 1297 1298 // Set the conditional execution predicate 1299 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1300 1301 // Encode S bit if MI modifies CPSR. 1302 Binary |= getAddrModeSBit(MI, TID); 1303 1304 // 32x32->64bit operations have two destination registers. The number 1305 // of register definitions will tell us if that's what we're dealing with. 1306 unsigned OpIdx = 0; 1307 if (TID.getNumDefs() == 2) 1308 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1309 1310 // Encode Rd 1311 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1312 1313 // Encode Rm 1314 Binary |= getMachineOpValue(MI, OpIdx++); 1315 1316 // Encode Rs 1317 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1318 1319 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1320 // it as Rn (for multiply, that's in the same offset as RdLo. 1321 if (TID.getNumOperands() > OpIdx && 1322 !TID.OpInfo[OpIdx].isPredicate() && 1323 !TID.OpInfo[OpIdx].isOptionalDef()) 1324 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1325 1326 emitWordLE(Binary); 1327} 1328 1329void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1330 const TargetInstrDesc &TID = MI.getDesc(); 1331 1332 // Part of binary is determined by TableGn. 1333 unsigned Binary = getBinaryCodeForInstr(MI); 1334 1335 // Set the conditional execution predicate 1336 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1337 1338 unsigned OpIdx = 0; 1339 1340 // Encode Rd 1341 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1342 1343 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1344 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1345 if (MO2.isReg()) { 1346 // Two register operand form. 1347 // Encode Rn. 1348 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1349 1350 // Encode Rm. 1351 Binary |= getMachineOpValue(MI, MO2); 1352 ++OpIdx; 1353 } else { 1354 Binary |= getMachineOpValue(MI, MO1); 1355 } 1356 1357 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1358 if (MI.getOperand(OpIdx).isImm() && 1359 !TID.OpInfo[OpIdx].isPredicate() && 1360 !TID.OpInfo[OpIdx].isOptionalDef()) 1361 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1362 1363 emitWordLE(Binary); 1364} 1365 1366void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1367 const TargetInstrDesc &TID = MI.getDesc(); 1368 1369 // Part of binary is determined by TableGn. 1370 unsigned Binary = getBinaryCodeForInstr(MI); 1371 1372 // Set the conditional execution predicate 1373 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1374 1375 unsigned OpIdx = 0; 1376 1377 // Encode Rd 1378 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1379 1380 const MachineOperand &MO = MI.getOperand(OpIdx++); 1381 if (OpIdx == TID.getNumOperands() || 1382 TID.OpInfo[OpIdx].isPredicate() || 1383 TID.OpInfo[OpIdx].isOptionalDef()) { 1384 // Encode Rm and it's done. 1385 Binary |= getMachineOpValue(MI, MO); 1386 emitWordLE(Binary); 1387 return; 1388 } 1389 1390 // Encode Rn. 1391 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1392 1393 // Encode Rm. 1394 Binary |= getMachineOpValue(MI, OpIdx++); 1395 1396 // Encode shift_imm. 1397 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1398 if (TID.Opcode == ARM::PKHTB) { 1399 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1400 if (ShiftAmt == 32) 1401 ShiftAmt = 0; 1402 } 1403 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1404 Binary |= ShiftAmt << ARMII::ShiftShift; 1405 1406 emitWordLE(Binary); 1407} 1408 1409void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1410 const TargetInstrDesc &TID = MI.getDesc(); 1411 1412 // Part of binary is determined by TableGen. 1413 unsigned Binary = getBinaryCodeForInstr(MI); 1414 1415 // Set the conditional execution predicate 1416 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1417 1418 // Encode Rd 1419 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1420 1421 // Encode saturate bit position. 1422 unsigned Pos = MI.getOperand(1).getImm(); 1423 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) 1424 Pos -= 1; 1425 assert((Pos < 16 || (Pos < 32 && 1426 TID.Opcode != ARM::SSAT16 && 1427 TID.Opcode != ARM::USAT16)) && 1428 "saturate bit position out of range"); 1429 Binary |= Pos << 16; 1430 1431 // Encode Rm 1432 Binary |= getMachineOpValue(MI, 2); 1433 1434 // Encode shift_imm. 1435 if (TID.getNumOperands() == 4) { 1436 unsigned ShiftOp = MI.getOperand(3).getImm(); 1437 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1438 if (Opc == ARM_AM::asr) 1439 Binary |= (1 << 6); 1440 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1441 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1442 ShiftAmt = 0; 1443 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1444 Binary |= ShiftAmt << ARMII::ShiftShift; 1445 } 1446 1447 emitWordLE(Binary); 1448} 1449 1450void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1451 const TargetInstrDesc &TID = MI.getDesc(); 1452 1453 if (TID.Opcode == ARM::TPsoft) { 1454 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1455 } 1456 1457 // Part of binary is determined by TableGn. 1458 unsigned Binary = getBinaryCodeForInstr(MI); 1459 1460 // Set the conditional execution predicate 1461 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1462 1463 // Set signed_immed_24 field 1464 Binary |= getMachineOpValue(MI, 0); 1465 1466 emitWordLE(Binary); 1467} 1468 1469void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1470 // Remember the base address of the inline jump table. 1471 uintptr_t JTBase = MCE.getCurrentPCValue(); 1472 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1473 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1474 << '\n'); 1475 1476 // Now emit the jump table entries. 1477 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1478 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1479 if (IsPIC) 1480 // DestBB address - JT base. 1481 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1482 else 1483 // Absolute DestBB address. 1484 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1485 emitWordLE(0); 1486 } 1487} 1488 1489void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1490 const TargetInstrDesc &TID = MI.getDesc(); 1491 1492 // Handle jump tables. 1493 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1494 // First emit a ldr pc, [] instruction. 1495 emitDataProcessingInstruction(MI, ARM::PC); 1496 1497 // Then emit the inline jump table. 1498 unsigned JTIndex = 1499 (TID.Opcode == ARM::BR_JTr) 1500 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1501 emitInlineJumpTable(JTIndex); 1502 return; 1503 } else if (TID.Opcode == ARM::BR_JTm) { 1504 // First emit a ldr pc, [] instruction. 1505 emitLoadStoreInstruction(MI, ARM::PC); 1506 1507 // Then emit the inline jump table. 1508 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1509 return; 1510 } 1511 1512 // Part of binary is determined by TableGn. 1513 unsigned Binary = getBinaryCodeForInstr(MI); 1514 1515 // Set the conditional execution predicate 1516 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1517 1518 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1519 // The return register is LR. 1520 Binary |= getARMRegisterNumbering(ARM::LR); 1521 else 1522 // otherwise, set the return register 1523 Binary |= getMachineOpValue(MI, 0); 1524 1525 emitWordLE(Binary); 1526} 1527 1528static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1529 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1530 unsigned Binary = 0; 1531 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1532 RegD = getARMRegisterNumbering(RegD); 1533 if (!isSPVFP) 1534 Binary |= RegD << ARMII::RegRdShift; 1535 else { 1536 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1537 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1538 } 1539 return Binary; 1540} 1541 1542static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1543 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1544 unsigned Binary = 0; 1545 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1546 RegN = getARMRegisterNumbering(RegN); 1547 if (!isSPVFP) 1548 Binary |= RegN << ARMII::RegRnShift; 1549 else { 1550 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1551 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1552 } 1553 return Binary; 1554} 1555 1556static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1557 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1558 unsigned Binary = 0; 1559 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1560 RegM = getARMRegisterNumbering(RegM); 1561 if (!isSPVFP) 1562 Binary |= RegM; 1563 else { 1564 Binary |= ((RegM & 0x1E) >> 1); 1565 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1566 } 1567 return Binary; 1568} 1569 1570void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1571 const TargetInstrDesc &TID = MI.getDesc(); 1572 1573 // Part of binary is determined by TableGn. 1574 unsigned Binary = getBinaryCodeForInstr(MI); 1575 1576 // Set the conditional execution predicate 1577 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1578 1579 unsigned OpIdx = 0; 1580 assert((Binary & ARMII::D_BitShift) == 0 && 1581 (Binary & ARMII::N_BitShift) == 0 && 1582 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1583 1584 // Encode Dd / Sd. 1585 Binary |= encodeVFPRd(MI, OpIdx++); 1586 1587 // If this is a two-address operand, skip it, e.g. FMACD. 1588 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1589 ++OpIdx; 1590 1591 // Encode Dn / Sn. 1592 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1593 Binary |= encodeVFPRn(MI, OpIdx++); 1594 1595 if (OpIdx == TID.getNumOperands() || 1596 TID.OpInfo[OpIdx].isPredicate() || 1597 TID.OpInfo[OpIdx].isOptionalDef()) { 1598 // FCMPEZD etc. has only one operand. 1599 emitWordLE(Binary); 1600 return; 1601 } 1602 1603 // Encode Dm / Sm. 1604 Binary |= encodeVFPRm(MI, OpIdx); 1605 1606 emitWordLE(Binary); 1607} 1608 1609void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1610 const TargetInstrDesc &TID = MI.getDesc(); 1611 unsigned Form = TID.TSFlags & ARMII::FormMask; 1612 1613 // Part of binary is determined by TableGn. 1614 unsigned Binary = getBinaryCodeForInstr(MI); 1615 1616 // Set the conditional execution predicate 1617 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1618 1619 switch (Form) { 1620 default: break; 1621 case ARMII::VFPConv1Frm: 1622 case ARMII::VFPConv2Frm: 1623 case ARMII::VFPConv3Frm: 1624 // Encode Dd / Sd. 1625 Binary |= encodeVFPRd(MI, 0); 1626 break; 1627 case ARMII::VFPConv4Frm: 1628 // Encode Dn / Sn. 1629 Binary |= encodeVFPRn(MI, 0); 1630 break; 1631 case ARMII::VFPConv5Frm: 1632 // Encode Dm / Sm. 1633 Binary |= encodeVFPRm(MI, 0); 1634 break; 1635 } 1636 1637 switch (Form) { 1638 default: break; 1639 case ARMII::VFPConv1Frm: 1640 // Encode Dm / Sm. 1641 Binary |= encodeVFPRm(MI, 1); 1642 break; 1643 case ARMII::VFPConv2Frm: 1644 case ARMII::VFPConv3Frm: 1645 // Encode Dn / Sn. 1646 Binary |= encodeVFPRn(MI, 1); 1647 break; 1648 case ARMII::VFPConv4Frm: 1649 case ARMII::VFPConv5Frm: 1650 // Encode Dd / Sd. 1651 Binary |= encodeVFPRd(MI, 1); 1652 break; 1653 } 1654 1655 if (Form == ARMII::VFPConv5Frm) 1656 // Encode Dn / Sn. 1657 Binary |= encodeVFPRn(MI, 2); 1658 else if (Form == ARMII::VFPConv3Frm) 1659 // Encode Dm / Sm. 1660 Binary |= encodeVFPRm(MI, 2); 1661 1662 emitWordLE(Binary); 1663} 1664 1665void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1666 // Part of binary is determined by TableGn. 1667 unsigned Binary = getBinaryCodeForInstr(MI); 1668 1669 // Set the conditional execution predicate 1670 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1671 1672 unsigned OpIdx = 0; 1673 1674 // Encode Dd / Sd. 1675 Binary |= encodeVFPRd(MI, OpIdx++); 1676 1677 // Encode address base. 1678 const MachineOperand &Base = MI.getOperand(OpIdx++); 1679 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1680 1681 // If there is a non-zero immediate offset, encode it. 1682 if (Base.isReg()) { 1683 const MachineOperand &Offset = MI.getOperand(OpIdx); 1684 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1685 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1686 Binary |= 1 << ARMII::U_BitShift; 1687 Binary |= ImmOffs; 1688 emitWordLE(Binary); 1689 return; 1690 } 1691 } 1692 1693 // If immediate offset is omitted, default to +0. 1694 Binary |= 1 << ARMII::U_BitShift; 1695 1696 emitWordLE(Binary); 1697} 1698 1699void 1700ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1701 const TargetInstrDesc &TID = MI.getDesc(); 1702 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1703 1704 // Part of binary is determined by TableGn. 1705 unsigned Binary = getBinaryCodeForInstr(MI); 1706 1707 // Set the conditional execution predicate 1708 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1709 1710 // Skip operand 0 of an instruction with base register update. 1711 unsigned OpIdx = 0; 1712 if (IsUpdating) 1713 ++OpIdx; 1714 1715 // Set base address operand 1716 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1717 1718 // Set addressing mode by modifying bits U(23) and P(24) 1719 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1720 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1721 1722 // Set bit W(21) 1723 if (IsUpdating) 1724 Binary |= 0x1 << ARMII::W_BitShift; 1725 1726 // First register is encoded in Dd. 1727 Binary |= encodeVFPRd(MI, OpIdx+2); 1728 1729 // Count the number of registers. 1730 unsigned NumRegs = 1; 1731 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1732 const MachineOperand &MO = MI.getOperand(i); 1733 if (!MO.isReg() || MO.isImplicit()) 1734 break; 1735 ++NumRegs; 1736 } 1737 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1738 // Otherwise, it will be 0, in the case of 32-bit registers. 1739 if(Binary & 0x100) 1740 Binary |= NumRegs * 2; 1741 else 1742 Binary |= NumRegs; 1743 1744 emitWordLE(Binary); 1745} 1746 1747static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1748 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1749 unsigned Binary = 0; 1750 RegD = getARMRegisterNumbering(RegD); 1751 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1752 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1753 return Binary; 1754} 1755 1756static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1757 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1758 unsigned Binary = 0; 1759 RegN = getARMRegisterNumbering(RegN); 1760 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1761 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1762 return Binary; 1763} 1764 1765static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1766 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1767 unsigned Binary = 0; 1768 RegM = getARMRegisterNumbering(RegM); 1769 Binary |= (RegM & 0xf); 1770 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1771 return Binary; 1772} 1773 1774/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1775/// data-processing instruction to the corresponding Thumb encoding. 1776static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1777 assert((Binary & 0xfe000000) == 0xf2000000 && 1778 "not an ARM NEON data-processing instruction"); 1779 unsigned UBit = (Binary >> 24) & 1; 1780 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1781} 1782 1783void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1784 unsigned Binary = getBinaryCodeForInstr(MI); 1785 1786 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1787 const TargetInstrDesc &TID = MI.getDesc(); 1788 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1789 RegTOpIdx = 0; 1790 RegNOpIdx = 1; 1791 LnOpIdx = 2; 1792 } else { // ARMII::NSetLnFrm 1793 RegTOpIdx = 2; 1794 RegNOpIdx = 0; 1795 LnOpIdx = 3; 1796 } 1797 1798 // Set the conditional execution predicate 1799 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1800 1801 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1802 RegT = getARMRegisterNumbering(RegT); 1803 Binary |= (RegT << ARMII::RegRdShift); 1804 Binary |= encodeNEONRn(MI, RegNOpIdx); 1805 1806 unsigned LaneShift; 1807 if ((Binary & (1 << 22)) != 0) 1808 LaneShift = 0; // 8-bit elements 1809 else if ((Binary & (1 << 5)) != 0) 1810 LaneShift = 1; // 16-bit elements 1811 else 1812 LaneShift = 2; // 32-bit elements 1813 1814 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1815 unsigned Opc1 = Lane >> 2; 1816 unsigned Opc2 = Lane & 3; 1817 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1818 Binary |= (Opc1 << 21); 1819 Binary |= (Opc2 << 5); 1820 1821 emitWordLE(Binary); 1822} 1823 1824void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1825 unsigned Binary = getBinaryCodeForInstr(MI); 1826 1827 // Set the conditional execution predicate 1828 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1829 1830 unsigned RegT = MI.getOperand(1).getReg(); 1831 RegT = getARMRegisterNumbering(RegT); 1832 Binary |= (RegT << ARMII::RegRdShift); 1833 Binary |= encodeNEONRn(MI, 0); 1834 emitWordLE(Binary); 1835} 1836 1837void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1838 unsigned Binary = getBinaryCodeForInstr(MI); 1839 // Destination register is encoded in Dd. 1840 Binary |= encodeNEONRd(MI, 0); 1841 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1842 unsigned Imm = MI.getOperand(1).getImm(); 1843 unsigned Op = (Imm >> 12) & 1; 1844 unsigned Cmode = (Imm >> 8) & 0xf; 1845 unsigned I = (Imm >> 7) & 1; 1846 unsigned Imm3 = (Imm >> 4) & 0x7; 1847 unsigned Imm4 = Imm & 0xf; 1848 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1849 if (IsThumb) 1850 Binary = convertNEONDataProcToThumb(Binary); 1851 emitWordLE(Binary); 1852} 1853 1854void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1855 const TargetInstrDesc &TID = MI.getDesc(); 1856 unsigned Binary = getBinaryCodeForInstr(MI); 1857 // Destination register is encoded in Dd; source register in Dm. 1858 unsigned OpIdx = 0; 1859 Binary |= encodeNEONRd(MI, OpIdx++); 1860 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1861 ++OpIdx; 1862 Binary |= encodeNEONRm(MI, OpIdx); 1863 if (IsThumb) 1864 Binary = convertNEONDataProcToThumb(Binary); 1865 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1866 emitWordLE(Binary); 1867} 1868 1869void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1870 const TargetInstrDesc &TID = MI.getDesc(); 1871 unsigned Binary = getBinaryCodeForInstr(MI); 1872 // Destination register is encoded in Dd; source registers in Dn and Dm. 1873 unsigned OpIdx = 0; 1874 Binary |= encodeNEONRd(MI, OpIdx++); 1875 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1876 ++OpIdx; 1877 Binary |= encodeNEONRn(MI, OpIdx++); 1878 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1879 ++OpIdx; 1880 Binary |= encodeNEONRm(MI, OpIdx); 1881 if (IsThumb) 1882 Binary = convertNEONDataProcToThumb(Binary); 1883 // FIXME: This does not handle VMOVDneon or VMOVQ. 1884 emitWordLE(Binary); 1885} 1886 1887#include "ARMGenCodeEmitter.inc" 1888