ARMCodeEmitter.cpp revision 198090 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/Passes.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#ifndef NDEBUG
42#include <iomanip>
43#endif
44using namespace llvm;
45
46STATISTIC(NumEmitted, "Number of machine instructions emitted");
47
48namespace {
49
50  class ARMCodeEmitter {
51  public:
52    /// getBinaryCodeForInstr - This function, generated by the
53    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
54    /// machine instructions.
55    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
56  };
57
58  template<class CodeEmitter>
59  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
60                                    public ARMCodeEmitter {
61    ARMJITInfo                *JTI;
62    const ARMInstrInfo        *II;
63    const TargetData          *TD;
64    const ARMSubtarget        *Subtarget;
65    TargetMachine             &TM;
66    CodeEmitter               &MCE;
67    const std::vector<MachineConstantPoolEntry> *MCPEs;
68    const std::vector<MachineJumpTableEntry> *MJTEs;
69    bool IsPIC;
70
71    void getAnalysisUsage(AnalysisUsage &AU) const {
72      AU.addRequired<MachineModuleInfo>();
73      MachineFunctionPass::getAnalysisUsage(AU);
74    }
75
76  public:
77    static char ID;
78    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
79      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
80      MCE(mce), MCPEs(0), MJTEs(0),
81      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
82    Emitter(TargetMachine &tm, CodeEmitter &mce,
83            const ARMInstrInfo &ii, const TargetData &td)
84      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
85      MCE(mce), MCPEs(0), MJTEs(0),
86      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
87
88    bool runOnMachineFunction(MachineFunction &MF);
89
90    virtual const char *getPassName() const {
91      return "ARM Machine Code Emitter";
92    }
93
94    void emitInstruction(const MachineInstr &MI);
95
96  private:
97
98    void emitWordLE(unsigned Binary);
99
100    void emitDWordLE(uint64_t Binary);
101
102    void emitConstPoolInstruction(const MachineInstr &MI);
103
104    void emitMOVi2piecesInstruction(const MachineInstr &MI);
105
106    void emitLEApcrelJTInstruction(const MachineInstr &MI);
107
108    void emitPseudoMoveInstruction(const MachineInstr &MI);
109
110    void addPCLabel(unsigned LabelID);
111
112    void emitPseudoInstruction(const MachineInstr &MI);
113
114    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
115                                    const TargetInstrDesc &TID,
116                                    const MachineOperand &MO,
117                                    unsigned OpIdx);
118
119    unsigned getMachineSoImmOpValue(unsigned SoImm);
120
121    unsigned getAddrModeSBit(const MachineInstr &MI,
122                             const TargetInstrDesc &TID) const;
123
124    void emitDataProcessingInstruction(const MachineInstr &MI,
125                                       unsigned ImplicitRd = 0,
126                                       unsigned ImplicitRn = 0);
127
128    void emitLoadStoreInstruction(const MachineInstr &MI,
129                                  unsigned ImplicitRd = 0,
130                                  unsigned ImplicitRn = 0);
131
132    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
133                                      unsigned ImplicitRn = 0);
134
135    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
136
137    void emitMulFrmInstruction(const MachineInstr &MI);
138
139    void emitExtendInstruction(const MachineInstr &MI);
140
141    void emitMiscArithInstruction(const MachineInstr &MI);
142
143    void emitBranchInstruction(const MachineInstr &MI);
144
145    void emitInlineJumpTable(unsigned JTIndex);
146
147    void emitMiscBranchInstruction(const MachineInstr &MI);
148
149    void emitVFPArithInstruction(const MachineInstr &MI);
150
151    void emitVFPConversionInstruction(const MachineInstr &MI);
152
153    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
154
155    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
156
157    void emitMiscInstruction(const MachineInstr &MI);
158
159    /// getMachineOpValue - Return binary encoding of operand. If the machine
160    /// operand requires relocation, record the relocation and return zero.
161    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
162    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
163      return getMachineOpValue(MI, MI.getOperand(OpIdx));
164    }
165
166    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167    ///
168    unsigned getShiftOp(unsigned Imm) const ;
169
170    /// Routines that handle operands which add machine relocations which are
171    /// fixed up by the relocation stage.
172    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
173                           bool NeedStub,  bool Indirect, intptr_t ACPV = 0);
174    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
175    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
176    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
177    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
178                               intptr_t JTBase = 0);
179  };
180  template <class CodeEmitter>
181  char Emitter<CodeEmitter>::ID = 0;
182}
183
184/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
185/// to the specified MCE object.
186
187FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
188                                             MachineCodeEmitter &MCE) {
189  return new Emitter<MachineCodeEmitter>(TM, MCE);
190}
191FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
192                                                JITCodeEmitter &JCE) {
193  return new Emitter<JITCodeEmitter>(TM, JCE);
194}
195FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
196                                                   ObjectCodeEmitter &OCE) {
197  return new Emitter<ObjectCodeEmitter>(TM, OCE);
198}
199
200template<class CodeEmitter>
201bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
202  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
203          MF.getTarget().getRelocationModel() != Reloc::Static) &&
204         "JIT relocation model must be set to static or default!");
205  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
206  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
207  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
208  Subtarget = &TM.getSubtarget<ARMSubtarget>();
209  MCPEs = &MF.getConstantPool()->getConstants();
210  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
211  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
212  JTI->Initialize(MF, IsPIC);
213  MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
214
215  do {
216    DEBUG(errs() << "JITTing function '"
217          << MF.getFunction()->getName() << "'\n");
218    MCE.startFunction(MF);
219    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
220         MBB != E; ++MBB) {
221      MCE.StartMachineBasicBlock(MBB);
222      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
223           I != E; ++I)
224        emitInstruction(*I);
225    }
226  } while (MCE.finishFunction(MF));
227
228  return false;
229}
230
231/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
232///
233template<class CodeEmitter>
234unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
235  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
236  default: llvm_unreachable("Unknown shift opc!");
237  case ARM_AM::asr: return 2;
238  case ARM_AM::lsl: return 0;
239  case ARM_AM::lsr: return 1;
240  case ARM_AM::ror:
241  case ARM_AM::rrx: return 3;
242  }
243  return 0;
244}
245
246/// getMachineOpValue - Return binary encoding of operand. If the machine
247/// operand requires relocation, record the relocation and return zero.
248template<class CodeEmitter>
249unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
250                                                 const MachineOperand &MO) {
251  if (MO.isReg())
252    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
253  else if (MO.isImm())
254    return static_cast<unsigned>(MO.getImm());
255  else if (MO.isGlobal())
256    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
257  else if (MO.isSymbol())
258    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
259  else if (MO.isCPI()) {
260    const TargetInstrDesc &TID = MI.getDesc();
261    // For VFP load, the immediate offset is multiplied by 4.
262    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
263      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
264    emitConstPoolAddress(MO.getIndex(), Reloc);
265  } else if (MO.isJTI())
266    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
267  else if (MO.isMBB())
268    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
269  else {
270#ifndef NDEBUG
271    errs() << MO;
272#endif
273    llvm_unreachable(0);
274  }
275  return 0;
276}
277
278/// emitGlobalAddress - Emit the specified address to the code stream.
279///
280template<class CodeEmitter>
281void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
282                                             bool NeedStub, bool Indirect,
283                                             intptr_t ACPV) {
284  MachineRelocation MR = Indirect
285    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
286                                           GV, ACPV, NeedStub)
287    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
288                               GV, ACPV, NeedStub);
289  MCE.addRelocation(MR);
290}
291
292/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
293/// be emitted to the current location in the function, and allow it to be PC
294/// relative.
295template<class CodeEmitter>
296void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
297                                                     unsigned Reloc) {
298  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
299                                                 Reloc, ES));
300}
301
302/// emitConstPoolAddress - Arrange for the address of an constant pool
303/// to be emitted to the current location in the function, and allow it to be PC
304/// relative.
305template<class CodeEmitter>
306void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
307                                                unsigned Reloc) {
308  // Tell JIT emitter we'll resolve the address.
309  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
310                                                    Reloc, CPI, 0, true));
311}
312
313/// emitJumpTableAddress - Arrange for the address of a jump table to
314/// be emitted to the current location in the function, and allow it to be PC
315/// relative.
316template<class CodeEmitter>
317void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
318                                                unsigned Reloc) {
319  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
320                                                    Reloc, JTIndex, 0, true));
321}
322
323/// emitMachineBasicBlock - Emit the specified address basic block.
324template<class CodeEmitter>
325void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
326                                              unsigned Reloc, intptr_t JTBase) {
327  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
328                                             Reloc, BB, JTBase));
329}
330
331template<class CodeEmitter>
332void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
333  DEBUG(errs() << "  0x";
334        errs().write_hex(Binary) << "\n");
335  MCE.emitWordLE(Binary);
336}
337
338template<class CodeEmitter>
339void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
340  DEBUG(errs() << "  0x";
341        errs().write_hex(Binary) << "\n");
342  MCE.emitDWordLE(Binary);
343}
344
345template<class CodeEmitter>
346void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
347  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
348
349  MCE.processDebugLoc(MI.getDebugLoc(), true);
350
351  NumEmitted++;  // Keep track of the # of mi's emitted
352  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
353  default: {
354    llvm_unreachable("Unhandled instruction encoding format!");
355    break;
356  }
357  case ARMII::Pseudo:
358    emitPseudoInstruction(MI);
359    break;
360  case ARMII::DPFrm:
361  case ARMII::DPSoRegFrm:
362    emitDataProcessingInstruction(MI);
363    break;
364  case ARMII::LdFrm:
365  case ARMII::StFrm:
366    emitLoadStoreInstruction(MI);
367    break;
368  case ARMII::LdMiscFrm:
369  case ARMII::StMiscFrm:
370    emitMiscLoadStoreInstruction(MI);
371    break;
372  case ARMII::LdStMulFrm:
373    emitLoadStoreMultipleInstruction(MI);
374    break;
375  case ARMII::MulFrm:
376    emitMulFrmInstruction(MI);
377    break;
378  case ARMII::ExtFrm:
379    emitExtendInstruction(MI);
380    break;
381  case ARMII::ArithMiscFrm:
382    emitMiscArithInstruction(MI);
383    break;
384  case ARMII::BrFrm:
385    emitBranchInstruction(MI);
386    break;
387  case ARMII::BrMiscFrm:
388    emitMiscBranchInstruction(MI);
389    break;
390  // VFP instructions.
391  case ARMII::VFPUnaryFrm:
392  case ARMII::VFPBinaryFrm:
393    emitVFPArithInstruction(MI);
394    break;
395  case ARMII::VFPConv1Frm:
396  case ARMII::VFPConv2Frm:
397  case ARMII::VFPConv3Frm:
398  case ARMII::VFPConv4Frm:
399  case ARMII::VFPConv5Frm:
400    emitVFPConversionInstruction(MI);
401    break;
402  case ARMII::VFPLdStFrm:
403    emitVFPLoadStoreInstruction(MI);
404    break;
405  case ARMII::VFPLdStMulFrm:
406    emitVFPLoadStoreMultipleInstruction(MI);
407    break;
408  case ARMII::VFPMiscFrm:
409    emitMiscInstruction(MI);
410    break;
411  }
412  MCE.processDebugLoc(MI.getDebugLoc(), false);
413}
414
415template<class CodeEmitter>
416void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
417  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
418  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
419  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
420
421  // Remember the CONSTPOOL_ENTRY address for later relocation.
422  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
423
424  // Emit constpool island entry. In most cases, the actual values will be
425  // resolved and relocated after code emission.
426  if (MCPE.isMachineConstantPoolEntry()) {
427    ARMConstantPoolValue *ACPV =
428      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
429
430    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
431          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
432
433    GlobalValue *GV = ACPV->getGV();
434    if (GV) {
435      Reloc::Model RelocM = TM.getRelocationModel();
436      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
437                        isa<Function>(GV),
438                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
439                        (intptr_t)ACPV);
440     } else  {
441      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
442    }
443    emitWordLE(0);
444  } else {
445    Constant *CV = MCPE.Val.ConstVal;
446
447    DEBUG({
448        errs() << "  ** Constant pool #" << CPI << " @ "
449               << (void*)MCE.getCurrentPCValue() << " ";
450        if (const Function *F = dyn_cast<Function>(CV))
451          errs() << F->getName();
452        else
453          errs() << *CV;
454        errs() << '\n';
455      });
456
457    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
458      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
459      emitWordLE(0);
460    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
461      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
462      emitWordLE(Val);
463    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
464      if (CFP->getType()->isFloatTy())
465        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
466      else if (CFP->getType()->isDoubleTy())
467        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
468      else {
469        llvm_unreachable("Unable to handle this constantpool entry!");
470      }
471    } else {
472      llvm_unreachable("Unable to handle this constantpool entry!");
473    }
474  }
475}
476
477template<class CodeEmitter>
478void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
479  const MachineOperand &MO0 = MI.getOperand(0);
480  const MachineOperand &MO1 = MI.getOperand(1);
481  assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
482                                            "Not a valid so_imm value!");
483  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
484  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
485
486  // Emit the 'mov' instruction.
487  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
488
489  // Set the conditional execution predicate.
490  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
491
492  // Encode Rd.
493  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
494
495  // Encode so_imm.
496  // Set bit I(25) to identify this is the immediate form of <shifter_op>
497  Binary |= 1 << ARMII::I_BitShift;
498  Binary |= getMachineSoImmOpValue(V1);
499  emitWordLE(Binary);
500
501  // Now the 'orr' instruction.
502  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
503
504  // Set the conditional execution predicate.
505  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
506
507  // Encode Rd.
508  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
509
510  // Encode Rn.
511  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
512
513  // Encode so_imm.
514  // Set bit I(25) to identify this is the immediate form of <shifter_op>
515  Binary |= 1 << ARMII::I_BitShift;
516  Binary |= getMachineSoImmOpValue(V2);
517  emitWordLE(Binary);
518}
519
520template<class CodeEmitter>
521void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
522  // It's basically add r, pc, (LJTI - $+8)
523
524  const TargetInstrDesc &TID = MI.getDesc();
525
526  // Emit the 'add' instruction.
527  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
528
529  // Set the conditional execution predicate
530  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
531
532  // Encode S bit if MI modifies CPSR.
533  Binary |= getAddrModeSBit(MI, TID);
534
535  // Encode Rd.
536  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
537
538  // Encode Rn which is PC.
539  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
540
541  // Encode the displacement.
542  Binary |= 1 << ARMII::I_BitShift;
543  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
544
545  emitWordLE(Binary);
546}
547
548template<class CodeEmitter>
549void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
550  unsigned Opcode = MI.getDesc().Opcode;
551
552  // Part of binary is determined by TableGn.
553  unsigned Binary = getBinaryCodeForInstr(MI);
554
555  // Set the conditional execution predicate
556  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
557
558  // Encode S bit if MI modifies CPSR.
559  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
560    Binary |= 1 << ARMII::S_BitShift;
561
562  // Encode register def if there is one.
563  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
564
565  // Encode the shift operation.
566  switch (Opcode) {
567  default: break;
568  case ARM::MOVrx:
569    // rrx
570    Binary |= 0x6 << 4;
571    break;
572  case ARM::MOVsrl_flag:
573    // lsr #1
574    Binary |= (0x2 << 4) | (1 << 7);
575    break;
576  case ARM::MOVsra_flag:
577    // asr #1
578    Binary |= (0x4 << 4) | (1 << 7);
579    break;
580  }
581
582  // Encode register Rm.
583  Binary |= getMachineOpValue(MI, 1);
584
585  emitWordLE(Binary);
586}
587
588template<class CodeEmitter>
589void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
590  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
591        << (void*)MCE.getCurrentPCValue() << '\n');
592  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
593}
594
595template<class CodeEmitter>
596void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
597  unsigned Opcode = MI.getDesc().Opcode;
598  switch (Opcode) {
599  default:
600    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
601  // FIXME: Add support for MOVimm32.
602  case TargetInstrInfo::INLINEASM: {
603    // We allow inline assembler nodes with empty bodies - they can
604    // implicitly define registers, which is ok for JIT.
605    if (MI.getOperand(0).getSymbolName()[0]) {
606      llvm_report_error("JIT does not support inline asm!");
607    }
608    break;
609  }
610  case TargetInstrInfo::DBG_LABEL:
611  case TargetInstrInfo::EH_LABEL:
612    MCE.emitLabel(MI.getOperand(0).getImm());
613    break;
614  case TargetInstrInfo::IMPLICIT_DEF:
615  case TargetInstrInfo::KILL:
616  case ARM::DWARF_LOC:
617    // Do nothing.
618    break;
619  case ARM::CONSTPOOL_ENTRY:
620    emitConstPoolInstruction(MI);
621    break;
622  case ARM::PICADD: {
623    // Remember of the address of the PC label for relocation later.
624    addPCLabel(MI.getOperand(2).getImm());
625    // PICADD is just an add instruction that implicitly read pc.
626    emitDataProcessingInstruction(MI, 0, ARM::PC);
627    break;
628  }
629  case ARM::PICLDR:
630  case ARM::PICLDRB:
631  case ARM::PICSTR:
632  case ARM::PICSTRB: {
633    // Remember of the address of the PC label for relocation later.
634    addPCLabel(MI.getOperand(2).getImm());
635    // These are just load / store instructions that implicitly read pc.
636    emitLoadStoreInstruction(MI, 0, ARM::PC);
637    break;
638  }
639  case ARM::PICLDRH:
640  case ARM::PICLDRSH:
641  case ARM::PICLDRSB:
642  case ARM::PICSTRH: {
643    // Remember of the address of the PC label for relocation later.
644    addPCLabel(MI.getOperand(2).getImm());
645    // These are just load / store instructions that implicitly read pc.
646    emitMiscLoadStoreInstruction(MI, ARM::PC);
647    break;
648  }
649  case ARM::MOVi2pieces:
650    // Two instructions to materialize a constant.
651    emitMOVi2piecesInstruction(MI);
652    break;
653  case ARM::LEApcrelJT:
654    // Materialize jumptable address.
655    emitLEApcrelJTInstruction(MI);
656    break;
657  case ARM::MOVrx:
658  case ARM::MOVsrl_flag:
659  case ARM::MOVsra_flag:
660    emitPseudoMoveInstruction(MI);
661    break;
662  }
663}
664
665template<class CodeEmitter>
666unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
667                                                const MachineInstr &MI,
668                                                const TargetInstrDesc &TID,
669                                                const MachineOperand &MO,
670                                                unsigned OpIdx) {
671  unsigned Binary = getMachineOpValue(MI, MO);
672
673  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
674  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
675  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
676
677  // Encode the shift opcode.
678  unsigned SBits = 0;
679  unsigned Rs = MO1.getReg();
680  if (Rs) {
681    // Set shift operand (bit[7:4]).
682    // LSL - 0001
683    // LSR - 0011
684    // ASR - 0101
685    // ROR - 0111
686    // RRX - 0110 and bit[11:8] clear.
687    switch (SOpc) {
688    default: llvm_unreachable("Unknown shift opc!");
689    case ARM_AM::lsl: SBits = 0x1; break;
690    case ARM_AM::lsr: SBits = 0x3; break;
691    case ARM_AM::asr: SBits = 0x5; break;
692    case ARM_AM::ror: SBits = 0x7; break;
693    case ARM_AM::rrx: SBits = 0x6; break;
694    }
695  } else {
696    // Set shift operand (bit[6:4]).
697    // LSL - 000
698    // LSR - 010
699    // ASR - 100
700    // ROR - 110
701    switch (SOpc) {
702    default: llvm_unreachable("Unknown shift opc!");
703    case ARM_AM::lsl: SBits = 0x0; break;
704    case ARM_AM::lsr: SBits = 0x2; break;
705    case ARM_AM::asr: SBits = 0x4; break;
706    case ARM_AM::ror: SBits = 0x6; break;
707    }
708  }
709  Binary |= SBits << 4;
710  if (SOpc == ARM_AM::rrx)
711    return Binary;
712
713  // Encode the shift operation Rs or shift_imm (except rrx).
714  if (Rs) {
715    // Encode Rs bit[11:8].
716    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
717    return Binary |
718      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
719  }
720
721  // Encode shift_imm bit[11:7].
722  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
723}
724
725template<class CodeEmitter>
726unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
727  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
728  assert(SoImmVal != -1 && "Not a valid so_imm value!");
729
730  // Encode rotate_imm.
731  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
732    << ARMII::SoRotImmShift;
733
734  // Encode immed_8.
735  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
736  return Binary;
737}
738
739template<class CodeEmitter>
740unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
741                                             const TargetInstrDesc &TID) const {
742  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
743    const MachineOperand &MO = MI.getOperand(i-1);
744    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
745      return 1 << ARMII::S_BitShift;
746  }
747  return 0;
748}
749
750template<class CodeEmitter>
751void Emitter<CodeEmitter>::emitDataProcessingInstruction(
752                                                   const MachineInstr &MI,
753                                                   unsigned ImplicitRd,
754                                                   unsigned ImplicitRn) {
755  const TargetInstrDesc &TID = MI.getDesc();
756
757  if (TID.Opcode == ARM::BFC) {
758    llvm_report_error("ARMv6t2 JIT is not yet supported.");
759  }
760
761  // Part of binary is determined by TableGn.
762  unsigned Binary = getBinaryCodeForInstr(MI);
763
764  // Set the conditional execution predicate
765  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
766
767  // Encode S bit if MI modifies CPSR.
768  Binary |= getAddrModeSBit(MI, TID);
769
770  // Encode register def if there is one.
771  unsigned NumDefs = TID.getNumDefs();
772  unsigned OpIdx = 0;
773  if (NumDefs)
774    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
775  else if (ImplicitRd)
776    // Special handling for implicit use (e.g. PC).
777    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
778               << ARMII::RegRdShift);
779
780  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
781  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
782    ++OpIdx;
783
784  // Encode first non-shifter register operand if there is one.
785  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
786  if (!isUnary) {
787    if (ImplicitRn)
788      // Special handling for implicit use (e.g. PC).
789      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
790                 << ARMII::RegRnShift);
791    else {
792      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
793      ++OpIdx;
794    }
795  }
796
797  // Encode shifter operand.
798  const MachineOperand &MO = MI.getOperand(OpIdx);
799  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
800    // Encode SoReg.
801    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
802    return;
803  }
804
805  if (MO.isReg()) {
806    // Encode register Rm.
807    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
808    return;
809  }
810
811  // Encode so_imm.
812  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
813
814  emitWordLE(Binary);
815}
816
817template<class CodeEmitter>
818void Emitter<CodeEmitter>::emitLoadStoreInstruction(
819                                              const MachineInstr &MI,
820                                              unsigned ImplicitRd,
821                                              unsigned ImplicitRn) {
822  const TargetInstrDesc &TID = MI.getDesc();
823  unsigned Form = TID.TSFlags & ARMII::FormMask;
824  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
825
826  // Part of binary is determined by TableGn.
827  unsigned Binary = getBinaryCodeForInstr(MI);
828
829  // Set the conditional execution predicate
830  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
831
832  unsigned OpIdx = 0;
833
834  // Operand 0 of a pre- and post-indexed store is the address base
835  // writeback. Skip it.
836  bool Skipped = false;
837  if (IsPrePost && Form == ARMII::StFrm) {
838    ++OpIdx;
839    Skipped = true;
840  }
841
842  // Set first operand
843  if (ImplicitRd)
844    // Special handling for implicit use (e.g. PC).
845    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
846               << ARMII::RegRdShift);
847  else
848    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
849
850  // Set second operand
851  if (ImplicitRn)
852    // Special handling for implicit use (e.g. PC).
853    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
854               << ARMII::RegRnShift);
855  else
856    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
857
858  // If this is a two-address operand, skip it. e.g. LDR_PRE.
859  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
860    ++OpIdx;
861
862  const MachineOperand &MO2 = MI.getOperand(OpIdx);
863  unsigned AM2Opc = (ImplicitRn == ARM::PC)
864    ? 0 : MI.getOperand(OpIdx+1).getImm();
865
866  // Set bit U(23) according to sign of immed value (positive or negative).
867  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
868             ARMII::U_BitShift);
869  if (!MO2.getReg()) { // is immediate
870    if (ARM_AM::getAM2Offset(AM2Opc))
871      // Set the value of offset_12 field
872      Binary |= ARM_AM::getAM2Offset(AM2Opc);
873    emitWordLE(Binary);
874    return;
875  }
876
877  // Set bit I(25), because this is not in immediate enconding.
878  Binary |= 1 << ARMII::I_BitShift;
879  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
880  // Set bit[3:0] to the corresponding Rm register
881  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
882
883  // If this instr is in scaled register offset/index instruction, set
884  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
885  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
886    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
887    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
888  }
889
890  emitWordLE(Binary);
891}
892
893template<class CodeEmitter>
894void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
895                                                        unsigned ImplicitRn) {
896  const TargetInstrDesc &TID = MI.getDesc();
897  unsigned Form = TID.TSFlags & ARMII::FormMask;
898  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
899
900  // Part of binary is determined by TableGn.
901  unsigned Binary = getBinaryCodeForInstr(MI);
902
903  // Set the conditional execution predicate
904  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
905
906  unsigned OpIdx = 0;
907
908  // Operand 0 of a pre- and post-indexed store is the address base
909  // writeback. Skip it.
910  bool Skipped = false;
911  if (IsPrePost && Form == ARMII::StMiscFrm) {
912    ++OpIdx;
913    Skipped = true;
914  }
915
916  // Set first operand
917  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
918
919  // Skip LDRD and STRD's second operand.
920  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
921    ++OpIdx;
922
923  // Set second operand
924  if (ImplicitRn)
925    // Special handling for implicit use (e.g. PC).
926    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
927               << ARMII::RegRnShift);
928  else
929    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
930
931  // If this is a two-address operand, skip it. e.g. LDRH_POST.
932  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
933    ++OpIdx;
934
935  const MachineOperand &MO2 = MI.getOperand(OpIdx);
936  unsigned AM3Opc = (ImplicitRn == ARM::PC)
937    ? 0 : MI.getOperand(OpIdx+1).getImm();
938
939  // Set bit U(23) according to sign of immed value (positive or negative)
940  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
941             ARMII::U_BitShift);
942
943  // If this instr is in register offset/index encoding, set bit[3:0]
944  // to the corresponding Rm register.
945  if (MO2.getReg()) {
946    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
947    emitWordLE(Binary);
948    return;
949  }
950
951  // This instr is in immediate offset/index encoding, set bit 22 to 1.
952  Binary |= 1 << ARMII::AM3_I_BitShift;
953  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
954    // Set operands
955    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
956    Binary |= (ImmOffs & 0xF);                      // immedL
957  }
958
959  emitWordLE(Binary);
960}
961
962static unsigned getAddrModeUPBits(unsigned Mode) {
963  unsigned Binary = 0;
964
965  // Set addressing mode by modifying bits U(23) and P(24)
966  // IA - Increment after  - bit U = 1 and bit P = 0
967  // IB - Increment before - bit U = 1 and bit P = 1
968  // DA - Decrement after  - bit U = 0 and bit P = 0
969  // DB - Decrement before - bit U = 0 and bit P = 1
970  switch (Mode) {
971  default: llvm_unreachable("Unknown addressing sub-mode!");
972  case ARM_AM::da:                                     break;
973  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
974  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
975  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
976  }
977
978  return Binary;
979}
980
981template<class CodeEmitter>
982void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
983                                                       const MachineInstr &MI) {
984  // Part of binary is determined by TableGn.
985  unsigned Binary = getBinaryCodeForInstr(MI);
986
987  // Set the conditional execution predicate
988  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
989
990  // Set base address operand
991  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
992
993  // Set addressing mode by modifying bits U(23) and P(24)
994  const MachineOperand &MO = MI.getOperand(1);
995  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
996
997  // Set bit W(21)
998  if (ARM_AM::getAM4WBFlag(MO.getImm()))
999    Binary |= 0x1 << ARMII::W_BitShift;
1000
1001  // Set registers
1002  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1003    const MachineOperand &MO = MI.getOperand(i);
1004    if (!MO.isReg() || MO.isImplicit())
1005      break;
1006    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1007    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1008           RegNum < 16);
1009    Binary |= 0x1 << RegNum;
1010  }
1011
1012  emitWordLE(Binary);
1013}
1014
1015template<class CodeEmitter>
1016void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1017  const TargetInstrDesc &TID = MI.getDesc();
1018
1019  // Part of binary is determined by TableGn.
1020  unsigned Binary = getBinaryCodeForInstr(MI);
1021
1022  // Set the conditional execution predicate
1023  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1024
1025  // Encode S bit if MI modifies CPSR.
1026  Binary |= getAddrModeSBit(MI, TID);
1027
1028  // 32x32->64bit operations have two destination registers. The number
1029  // of register definitions will tell us if that's what we're dealing with.
1030  unsigned OpIdx = 0;
1031  if (TID.getNumDefs() == 2)
1032    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1033
1034  // Encode Rd
1035  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1036
1037  // Encode Rm
1038  Binary |= getMachineOpValue(MI, OpIdx++);
1039
1040  // Encode Rs
1041  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1042
1043  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1044  // it as Rn (for multiply, that's in the same offset as RdLo.
1045  if (TID.getNumOperands() > OpIdx &&
1046      !TID.OpInfo[OpIdx].isPredicate() &&
1047      !TID.OpInfo[OpIdx].isOptionalDef())
1048    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1049
1050  emitWordLE(Binary);
1051}
1052
1053template<class CodeEmitter>
1054void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1055  const TargetInstrDesc &TID = MI.getDesc();
1056
1057  // Part of binary is determined by TableGn.
1058  unsigned Binary = getBinaryCodeForInstr(MI);
1059
1060  // Set the conditional execution predicate
1061  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1062
1063  unsigned OpIdx = 0;
1064
1065  // Encode Rd
1066  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1067
1068  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1069  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1070  if (MO2.isReg()) {
1071    // Two register operand form.
1072    // Encode Rn.
1073    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1074
1075    // Encode Rm.
1076    Binary |= getMachineOpValue(MI, MO2);
1077    ++OpIdx;
1078  } else {
1079    Binary |= getMachineOpValue(MI, MO1);
1080  }
1081
1082  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1083  if (MI.getOperand(OpIdx).isImm() &&
1084      !TID.OpInfo[OpIdx].isPredicate() &&
1085      !TID.OpInfo[OpIdx].isOptionalDef())
1086    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1087
1088  emitWordLE(Binary);
1089}
1090
1091template<class CodeEmitter>
1092void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1093  const TargetInstrDesc &TID = MI.getDesc();
1094
1095  // Part of binary is determined by TableGn.
1096  unsigned Binary = getBinaryCodeForInstr(MI);
1097
1098  // Set the conditional execution predicate
1099  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1100
1101  unsigned OpIdx = 0;
1102
1103  // Encode Rd
1104  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1105
1106  const MachineOperand &MO = MI.getOperand(OpIdx++);
1107  if (OpIdx == TID.getNumOperands() ||
1108      TID.OpInfo[OpIdx].isPredicate() ||
1109      TID.OpInfo[OpIdx].isOptionalDef()) {
1110    // Encode Rm and it's done.
1111    Binary |= getMachineOpValue(MI, MO);
1112    emitWordLE(Binary);
1113    return;
1114  }
1115
1116  // Encode Rn.
1117  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1118
1119  // Encode Rm.
1120  Binary |= getMachineOpValue(MI, OpIdx++);
1121
1122  // Encode shift_imm.
1123  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1124  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1125  Binary |= ShiftAmt << ARMII::ShiftShift;
1126
1127  emitWordLE(Binary);
1128}
1129
1130template<class CodeEmitter>
1131void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1132  const TargetInstrDesc &TID = MI.getDesc();
1133
1134  if (TID.Opcode == ARM::TPsoft) {
1135    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1136  }
1137
1138  // Part of binary is determined by TableGn.
1139  unsigned Binary = getBinaryCodeForInstr(MI);
1140
1141  // Set the conditional execution predicate
1142  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1143
1144  // Set signed_immed_24 field
1145  Binary |= getMachineOpValue(MI, 0);
1146
1147  emitWordLE(Binary);
1148}
1149
1150template<class CodeEmitter>
1151void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1152  // Remember the base address of the inline jump table.
1153  uintptr_t JTBase = MCE.getCurrentPCValue();
1154  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1155  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1156               << '\n');
1157
1158  // Now emit the jump table entries.
1159  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1160  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1161    if (IsPIC)
1162      // DestBB address - JT base.
1163      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1164    else
1165      // Absolute DestBB address.
1166      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1167    emitWordLE(0);
1168  }
1169}
1170
1171template<class CodeEmitter>
1172void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1173  const TargetInstrDesc &TID = MI.getDesc();
1174
1175  // Handle jump tables.
1176  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1177    // First emit a ldr pc, [] instruction.
1178    emitDataProcessingInstruction(MI, ARM::PC);
1179
1180    // Then emit the inline jump table.
1181    unsigned JTIndex =
1182      (TID.Opcode == ARM::BR_JTr)
1183      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1184    emitInlineJumpTable(JTIndex);
1185    return;
1186  } else if (TID.Opcode == ARM::BR_JTm) {
1187    // First emit a ldr pc, [] instruction.
1188    emitLoadStoreInstruction(MI, ARM::PC);
1189
1190    // Then emit the inline jump table.
1191    emitInlineJumpTable(MI.getOperand(3).getIndex());
1192    return;
1193  }
1194
1195  // Part of binary is determined by TableGn.
1196  unsigned Binary = getBinaryCodeForInstr(MI);
1197
1198  // Set the conditional execution predicate
1199  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1200
1201  if (TID.Opcode == ARM::BX_RET)
1202    // The return register is LR.
1203    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1204  else
1205    // otherwise, set the return register
1206    Binary |= getMachineOpValue(MI, 0);
1207
1208  emitWordLE(Binary);
1209}
1210
1211static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1212  unsigned RegD = MI.getOperand(OpIdx).getReg();
1213  unsigned Binary = 0;
1214  bool isSPVFP = false;
1215  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1216  if (!isSPVFP)
1217    Binary |=   RegD               << ARMII::RegRdShift;
1218  else {
1219    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1220    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1221  }
1222  return Binary;
1223}
1224
1225static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1226  unsigned RegN = MI.getOperand(OpIdx).getReg();
1227  unsigned Binary = 0;
1228  bool isSPVFP = false;
1229  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1230  if (!isSPVFP)
1231    Binary |=   RegN               << ARMII::RegRnShift;
1232  else {
1233    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1234    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1235  }
1236  return Binary;
1237}
1238
1239static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1240  unsigned RegM = MI.getOperand(OpIdx).getReg();
1241  unsigned Binary = 0;
1242  bool isSPVFP = false;
1243  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1244  if (!isSPVFP)
1245    Binary |=   RegM;
1246  else {
1247    Binary |= ((RegM & 0x1E) >> 1);
1248    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1249  }
1250  return Binary;
1251}
1252
1253template<class CodeEmitter>
1254void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1255  const TargetInstrDesc &TID = MI.getDesc();
1256
1257  // Part of binary is determined by TableGn.
1258  unsigned Binary = getBinaryCodeForInstr(MI);
1259
1260  // Set the conditional execution predicate
1261  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1262
1263  unsigned OpIdx = 0;
1264  assert((Binary & ARMII::D_BitShift) == 0 &&
1265         (Binary & ARMII::N_BitShift) == 0 &&
1266         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1267
1268  // Encode Dd / Sd.
1269  Binary |= encodeVFPRd(MI, OpIdx++);
1270
1271  // If this is a two-address operand, skip it, e.g. FMACD.
1272  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1273    ++OpIdx;
1274
1275  // Encode Dn / Sn.
1276  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1277    Binary |= encodeVFPRn(MI, OpIdx++);
1278
1279  if (OpIdx == TID.getNumOperands() ||
1280      TID.OpInfo[OpIdx].isPredicate() ||
1281      TID.OpInfo[OpIdx].isOptionalDef()) {
1282    // FCMPEZD etc. has only one operand.
1283    emitWordLE(Binary);
1284    return;
1285  }
1286
1287  // Encode Dm / Sm.
1288  Binary |= encodeVFPRm(MI, OpIdx);
1289
1290  emitWordLE(Binary);
1291}
1292
1293template<class CodeEmitter>
1294void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1295      const MachineInstr &MI) {
1296  const TargetInstrDesc &TID = MI.getDesc();
1297  unsigned Form = TID.TSFlags & ARMII::FormMask;
1298
1299  // Part of binary is determined by TableGn.
1300  unsigned Binary = getBinaryCodeForInstr(MI);
1301
1302  // Set the conditional execution predicate
1303  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1304
1305  switch (Form) {
1306  default: break;
1307  case ARMII::VFPConv1Frm:
1308  case ARMII::VFPConv2Frm:
1309  case ARMII::VFPConv3Frm:
1310    // Encode Dd / Sd.
1311    Binary |= encodeVFPRd(MI, 0);
1312    break;
1313  case ARMII::VFPConv4Frm:
1314    // Encode Dn / Sn.
1315    Binary |= encodeVFPRn(MI, 0);
1316    break;
1317  case ARMII::VFPConv5Frm:
1318    // Encode Dm / Sm.
1319    Binary |= encodeVFPRm(MI, 0);
1320    break;
1321  }
1322
1323  switch (Form) {
1324  default: break;
1325  case ARMII::VFPConv1Frm:
1326    // Encode Dm / Sm.
1327    Binary |= encodeVFPRm(MI, 1);
1328    break;
1329  case ARMII::VFPConv2Frm:
1330  case ARMII::VFPConv3Frm:
1331    // Encode Dn / Sn.
1332    Binary |= encodeVFPRn(MI, 1);
1333    break;
1334  case ARMII::VFPConv4Frm:
1335  case ARMII::VFPConv5Frm:
1336    // Encode Dd / Sd.
1337    Binary |= encodeVFPRd(MI, 1);
1338    break;
1339  }
1340
1341  if (Form == ARMII::VFPConv5Frm)
1342    // Encode Dn / Sn.
1343    Binary |= encodeVFPRn(MI, 2);
1344  else if (Form == ARMII::VFPConv3Frm)
1345    // Encode Dm / Sm.
1346    Binary |= encodeVFPRm(MI, 2);
1347
1348  emitWordLE(Binary);
1349}
1350
1351template<class CodeEmitter>
1352void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1353  // Part of binary is determined by TableGn.
1354  unsigned Binary = getBinaryCodeForInstr(MI);
1355
1356  // Set the conditional execution predicate
1357  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1358
1359  unsigned OpIdx = 0;
1360
1361  // Encode Dd / Sd.
1362  Binary |= encodeVFPRd(MI, OpIdx++);
1363
1364  // Encode address base.
1365  const MachineOperand &Base = MI.getOperand(OpIdx++);
1366  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1367
1368  // If there is a non-zero immediate offset, encode it.
1369  if (Base.isReg()) {
1370    const MachineOperand &Offset = MI.getOperand(OpIdx);
1371    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1372      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1373        Binary |= 1 << ARMII::U_BitShift;
1374      Binary |= ImmOffs;
1375      emitWordLE(Binary);
1376      return;
1377    }
1378  }
1379
1380  // If immediate offset is omitted, default to +0.
1381  Binary |= 1 << ARMII::U_BitShift;
1382
1383  emitWordLE(Binary);
1384}
1385
1386template<class CodeEmitter>
1387void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1388                                                       const MachineInstr &MI) {
1389  // Part of binary is determined by TableGn.
1390  unsigned Binary = getBinaryCodeForInstr(MI);
1391
1392  // Set the conditional execution predicate
1393  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1394
1395  // Set base address operand
1396  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1397
1398  // Set addressing mode by modifying bits U(23) and P(24)
1399  const MachineOperand &MO = MI.getOperand(1);
1400  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1401
1402  // Set bit W(21)
1403  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1404    Binary |= 0x1 << ARMII::W_BitShift;
1405
1406  // First register is encoded in Dd.
1407  Binary |= encodeVFPRd(MI, 5);
1408
1409  // Number of registers are encoded in offset field.
1410  unsigned NumRegs = 1;
1411  for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) {
1412    const MachineOperand &MO = MI.getOperand(i);
1413    if (!MO.isReg() || MO.isImplicit())
1414      break;
1415    ++NumRegs;
1416  }
1417  Binary |= NumRegs * 2;
1418
1419  emitWordLE(Binary);
1420}
1421
1422template<class CodeEmitter>
1423void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1424  // Part of binary is determined by TableGn.
1425  unsigned Binary = getBinaryCodeForInstr(MI);
1426
1427  // Set the conditional execution predicate
1428  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1429
1430  emitWordLE(Binary);
1431}
1432
1433#include "ARMGenCodeEmitter.inc"
1434