AArch64InstrInfo.td revision 249259
1//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the AArch64 scalar instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14include "AArch64InstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// Target-specific ISD nodes and profiles 18//===----------------------------------------------------------------------===// 19 20def SDT_A64ret : SDTypeProfile<0, 0, []>; 21def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain, 22 SDNPOptInGlue, 23 SDNPVariadic]>; 24 25// (ins NZCV, Condition, Dest) 26def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>; 27def A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>; 28 29// (outs Result), (ins NZCV, IfTrue, IfFalse, Condition) 30def SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>, 31 SDTCisSameAs<0, 2>, 32 SDTCisSameAs<2, 3>]>; 33def A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>; 34 35// (outs NZCV), (ins LHS, RHS, Condition) 36def SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, 37 SDTCisSameAs<1, 2>]>; 38def A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>; 39 40 41// (outs GPR64), (ins) 42def A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 43 44// A64 compares don't care about the cond really (they set all flags) so a 45// simple binary operator is useful. 46def A64cmp : PatFrag<(ops node:$lhs, node:$rhs), 47 (A64setcc node:$lhs, node:$rhs, cond)>; 48 49 50// When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN 51// instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C 52// and V flags can be set differently by this operation. It comes down to 53// whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are 54// then everything is fine. If not then the optimization is wrong. Thus general 55// comparisons are only valid if op2 != 0. 56 57// So, finally, the only LLVM-native comparisons that don't mention C and V are 58// SETEQ and SETNE. They're the only ones we can safely use CMN for in the 59// absence of information about op2. 60def equality_cond : PatLeaf<(cond), [{ 61 return N->get() == ISD::SETEQ || N->get() == ISD::SETNE; 62}]>; 63 64def A64cmn : PatFrag<(ops node:$lhs, node:$rhs), 65 (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>; 66 67// There are two layers of indirection here, driven by the following 68// considerations. 69// + TableGen does not know CodeModel or Reloc so that decision should be 70// made for a variable/address at ISelLowering. 71// + The output of ISelLowering should be selectable (hence the Wrapper, 72// rather than a bare target opcode) 73def SDTAArch64Wrapper : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 74 SDTCisSameAs<1, 2>, 75 SDTCisVT<3, i32>, 76 SDTCisPtrTy<0>]>; 77 78def A64WrapperSmall : SDNode<"AArch64ISD::WrapperSmall", SDTAArch64Wrapper>; 79 80 81def SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 82def A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad, 83 [SDNPHasChain]>; 84 85 86// (A64BFI LHS, RHS, LSB, Width) 87def SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 88 SDTCisSameAs<1, 2>, 89 SDTCisVT<3, i64>, 90 SDTCisVT<4, i64>]>; 91 92def A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>; 93 94// (A64EXTR HiReg, LoReg, LSB) 95def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 96 SDTCisVT<3, i64>]>; 97def A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>; 98 99// (A64[SU]BFX Field, ImmR, ImmS). 100// 101// Note that ImmR and ImmS are already encoded for the actual instructions. The 102// more natural LSB and Width mix together to form ImmR and ImmS, something 103// which TableGen can't handle. 104def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 105def A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>; 106 107def A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>; 108 109//===----------------------------------------------------------------------===// 110// Call sequence pseudo-instructions 111//===----------------------------------------------------------------------===// 112 113 114def SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 115def AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call, 116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 117 118def AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call, 119 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 120 121// The TLSDESCCALL node is a variant call which goes to an indirectly calculated 122// destination but needs a relocation against a fixed symbol. As such it has two 123// certain operands: the callee and the relocated variable. 124// 125// The TLS ABI only allows it to be selected to a BLR instructin (with 126// appropriate relocation). 127def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 128 129def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall, 130 [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 131 SDNPVariadic]>; 132 133 134def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>; 135def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart, 136 [SDNPHasChain, SDNPOutGlue]>; 137 138def SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>; 139def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd, 140 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 141 142 143 144// These pseudo-instructions have special semantics by virtue of being passed to 145// the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by 146// LowerCall to (in our case) tell the back-end about stack adjustments for 147// arguments passed on the stack. Here we select those markers to 148// pseudo-instructions which explicitly set the stack, and finally in the 149// RegisterInfo we convert them to a true stack adjustment. 150let Defs = [XSP], Uses = [XSP] in { 151 def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt), 152 [(AArch64callseq_start timm:$amt)]>; 153 154 def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2), 155 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>; 156} 157 158//===----------------------------------------------------------------------===// 159// Atomic operation pseudo-instructions 160//===----------------------------------------------------------------------===// 161 162let usesCustomInserter = 1 in { 163multiclass AtomicSizes<string opname> { 164 def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr), 165 [(set i32:$dst, (!cast<SDNode>(opname # "_8") i64:$ptr, i32:$incr))]>; 166 def _I16 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr), 167 [(set i32:$dst, (!cast<SDNode>(opname # "_16") i64:$ptr, i32:$incr))]>; 168 def _I32 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr), 169 [(set i32:$dst, (!cast<SDNode>(opname # "_32") i64:$ptr, i32:$incr))]>; 170 def _I64 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$incr), 171 [(set i64:$dst, (!cast<SDNode>(opname # "_64") i64:$ptr, i64:$incr))]>; 172} 173} 174 175defm ATOMIC_LOAD_ADD : AtomicSizes<"atomic_load_add">; 176defm ATOMIC_LOAD_SUB : AtomicSizes<"atomic_load_sub">; 177defm ATOMIC_LOAD_AND : AtomicSizes<"atomic_load_and">; 178defm ATOMIC_LOAD_OR : AtomicSizes<"atomic_load_or">; 179defm ATOMIC_LOAD_XOR : AtomicSizes<"atomic_load_xor">; 180defm ATOMIC_LOAD_NAND : AtomicSizes<"atomic_load_nand">; 181defm ATOMIC_SWAP : AtomicSizes<"atomic_swap">; 182let Defs = [NZCV] in { 183 // These operations need a CMP to calculate the correct value 184 defm ATOMIC_LOAD_MIN : AtomicSizes<"atomic_load_min">; 185 defm ATOMIC_LOAD_MAX : AtomicSizes<"atomic_load_max">; 186 defm ATOMIC_LOAD_UMIN : AtomicSizes<"atomic_load_umin">; 187 defm ATOMIC_LOAD_UMAX : AtomicSizes<"atomic_load_umax">; 188} 189 190let usesCustomInserter = 1, Defs = [NZCV] in { 191def ATOMIC_CMP_SWAP_I8 192 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new), 193 [(set i32:$dst, (atomic_cmp_swap_8 i64:$ptr, i32:$old, i32:$new))]>; 194def ATOMIC_CMP_SWAP_I16 195 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new), 196 [(set i32:$dst, (atomic_cmp_swap_16 i64:$ptr, i32:$old, i32:$new))]>; 197def ATOMIC_CMP_SWAP_I32 198 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$old, GPR32:$new), 199 [(set i32:$dst, (atomic_cmp_swap_32 i64:$ptr, i32:$old, i32:$new))]>; 200def ATOMIC_CMP_SWAP_I64 201 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$old, GPR64:$new), 202 [(set i64:$dst, (atomic_cmp_swap_64 i64:$ptr, i64:$old, i64:$new))]>; 203} 204 205//===----------------------------------------------------------------------===// 206// Add-subtract (extended register) instructions 207//===----------------------------------------------------------------------===// 208// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP 209 210// The RHS of these operations is conceptually a sign/zero-extended 211// register, optionally shifted left by 1-4. The extension can be a 212// NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but 213// must be specified with one exception: 214 215// If one of the registers is sp/wsp then LSL is an alias for UXTW in 216// 32-bit instructions and UXTX in 64-bit versions, the shift amount 217// is not optional in that case (but can explicitly be 0), and the 218// entire suffix can be skipped (e.g. "add sp, x3, x2"). 219 220multiclass extend_operands<string PREFIX, string Diag> { 221 def _asmoperand : AsmOperandClass { 222 let Name = PREFIX; 223 let RenderMethod = "addRegExtendOperands"; 224 let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">"; 225 let DiagnosticType = "AddSubRegExtend" # Diag; 226 } 227 228 def _operand : Operand<i64>, 229 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> { 230 let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">"; 231 let DecoderMethod = "DecodeRegExtendOperand"; 232 let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand"); 233 } 234} 235 236defm UXTB : extend_operands<"UXTB", "Small">; 237defm UXTH : extend_operands<"UXTH", "Small">; 238defm UXTW : extend_operands<"UXTW", "Small">; 239defm UXTX : extend_operands<"UXTX", "Large">; 240defm SXTB : extend_operands<"SXTB", "Small">; 241defm SXTH : extend_operands<"SXTH", "Small">; 242defm SXTW : extend_operands<"SXTW", "Small">; 243defm SXTX : extend_operands<"SXTX", "Large">; 244 245def LSL_extasmoperand : AsmOperandClass { 246 let Name = "RegExtendLSL"; 247 let RenderMethod = "addRegExtendOperands"; 248 let DiagnosticType = "AddSubRegExtendLarge"; 249} 250 251def LSL_extoperand : Operand<i64> { 252 let ParserMatchClass = LSL_extasmoperand; 253} 254 255 256// The patterns for various sign-extensions are a little ugly and 257// non-uniform because everything has already been promoted to the 258// legal i64 and i32 types. We'll wrap the various variants up in a 259// class for use later. 260class extend_types { 261 dag uxtb; dag uxth; dag uxtw; dag uxtx; 262 dag sxtb; dag sxth; dag sxtw; dag sxtx; 263 ValueType ty; 264 RegisterClass GPR; 265} 266 267def extends_to_i64 : extend_types { 268 let uxtb = (and (anyext i32:$Rm), 255); 269 let uxth = (and (anyext i32:$Rm), 65535); 270 let uxtw = (zext i32:$Rm); 271 let uxtx = (i64 $Rm); 272 273 let sxtb = (sext_inreg (anyext i32:$Rm), i8); 274 let sxth = (sext_inreg (anyext i32:$Rm), i16); 275 let sxtw = (sext i32:$Rm); 276 let sxtx = (i64 $Rm); 277 278 let ty = i64; 279 let GPR = GPR64xsp; 280} 281 282 283def extends_to_i32 : extend_types { 284 let uxtb = (and i32:$Rm, 255); 285 let uxth = (and i32:$Rm, 65535); 286 let uxtw = (i32 i32:$Rm); 287 let uxtx = (i32 i32:$Rm); 288 289 let sxtb = (sext_inreg i32:$Rm, i8); 290 let sxth = (sext_inreg i32:$Rm, i16); 291 let sxtw = (i32 i32:$Rm); 292 let sxtx = (i32 i32:$Rm); 293 294 let ty = i32; 295 let GPR = GPR32wsp; 296} 297 298// Now, six of the extensions supported are easy and uniform: if the source size 299// is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate 300// those instructions in one block. 301 302// The uxtx/sxtx could potentially be merged in, but three facts dissuaded me: 303// + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would 304// be impossible. 305// + Patterns are very different as well. 306// + Passing different registers would be ugly (more fields in extend_types 307// would probably be the best option). 308multiclass addsub_exts<bit sf, bit op, bit S, string asmop, 309 SDPatternOperator opfrag, 310 dag outs, extend_types exts> { 311 def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000, 312 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3), 313 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 314 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))], 315 NoItinerary>; 316 def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001, 317 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3), 318 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 319 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))], 320 NoItinerary>; 321 def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010, 322 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3), 323 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 324 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))], 325 NoItinerary>; 326 327 def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100, 328 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3), 329 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 330 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))], 331 NoItinerary>; 332 def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101, 333 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3), 334 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 335 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))], 336 NoItinerary>; 337 def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110, 338 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3), 339 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 340 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))], 341 NoItinerary>; 342} 343 344// These two could be merge in with the above, but their patterns aren't really 345// necessary and the naming-scheme would necessarily break: 346multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag, 347 dag outs> { 348 def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011, 349 outs, 350 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3), 351 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 352 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))], 353 NoItinerary>; 354 355 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111, 356 outs, 357 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3), 358 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 359 [/* No Pattern: same as uxtx */], 360 NoItinerary>; 361} 362 363multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> { 364 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011, 365 outs, 366 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3), 367 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 368 [/* No pattern: probably same as uxtw */], 369 NoItinerary>; 370 371 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111, 372 outs, 373 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3), 374 !strconcat(asmop, "$Rn, $Rm, $Imm3"), 375 [/* No Pattern: probably same as uxtw */], 376 NoItinerary>; 377} 378 379class SetRD<RegisterClass RC, SDPatternOperator op> 380 : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>; 381class SetNZCV<SDPatternOperator op> 382 : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>; 383 384defm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 385 (outs GPR64xsp:$Rd), extends_to_i64>, 386 addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 387 (outs GPR64xsp:$Rd)>; 388defm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>, 389 (outs GPR32wsp:$Rd), extends_to_i32>, 390 addsub_wxtx< 0b0, 0b0, "add\t$Rd, ", 391 (outs GPR32wsp:$Rd)>; 392defm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 393 (outs GPR64xsp:$Rd), extends_to_i64>, 394 addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 395 (outs GPR64xsp:$Rd)>; 396defm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>, 397 (outs GPR32wsp:$Rd), extends_to_i32>, 398 addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ", 399 (outs GPR32wsp:$Rd)>; 400 401let Defs = [NZCV] in { 402defm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 403 (outs GPR64:$Rd), extends_to_i64>, 404 addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 405 (outs GPR64:$Rd)>; 406defm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>, 407 (outs GPR32:$Rd), extends_to_i32>, 408 addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ", 409 (outs GPR32:$Rd)>; 410defm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 411 (outs GPR64:$Rd), extends_to_i64>, 412 addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 413 (outs GPR64:$Rd)>; 414defm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>, 415 (outs GPR32:$Rd), extends_to_i32>, 416 addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ", 417 (outs GPR32:$Rd)>; 418 419 420let Rd = 0b11111, isCompare = 1 in { 421defm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 422 (outs), extends_to_i64>, 423 addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>; 424defm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 425 (outs), extends_to_i32>, 426 addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>; 427defm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 428 (outs), extends_to_i64>, 429 addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>; 430defm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 431 (outs), extends_to_i32>, 432 addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>; 433} 434} 435 436// Now patterns for the operation without a shift being needed. No patterns are 437// created for uxtx/sxtx since they're non-uniform and it's expected that 438// add/sub (shifted register) will handle those cases anyway. 439multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop, 440 extend_types exts> { 441 def : Pat<(nodeop exts.ty:$Rn, exts.uxtb), 442 (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>; 443 def : Pat<(nodeop exts.ty:$Rn, exts.uxth), 444 (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>; 445 def : Pat<(nodeop exts.ty:$Rn, exts.uxtw), 446 (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>; 447 448 def : Pat<(nodeop exts.ty:$Rn, exts.sxtb), 449 (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>; 450 def : Pat<(nodeop exts.ty:$Rn, exts.sxth), 451 (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>; 452 def : Pat<(nodeop exts.ty:$Rn, exts.sxtw), 453 (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>; 454} 455 456defm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>; 457defm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>; 458defm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>; 459defm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>; 460 461defm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>; 462defm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>; 463defm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>; 464defm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>; 465 466// An extend of "lsl #imm" is valid if and only if one of Rn and Rd is 467// sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the 468// operation. Also permitted in this case is complete omission of the argument, 469// which implies "lsl #0". 470multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd, 471 RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 472 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 473 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 474 475 def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"), 476 (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 477 478} 479 480defm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 481defm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 482defm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>; 483defm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>; 484defm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 485defm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 486defm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>; 487defm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>; 488 489// Rd cannot be sp for flag-setting variants so only half of the aliases are 490// needed. 491defm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>; 492defm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>; 493defm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>; 494defm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>; 495 496// CMP unfortunately has to be different because the instruction doesn't have a 497// dest register. 498multiclass cmp_lsl_aliases<string asmop, Instruction inst, 499 RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 500 def : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 501 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 502 503 def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"), 504 (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 505} 506 507defm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>; 508defm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>; 509defm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>; 510defm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>; 511 512//===----------------------------------------------------------------------===// 513// Add-subtract (immediate) instructions 514//===----------------------------------------------------------------------===// 515// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV 516 517// These instructions accept a 12-bit unsigned immediate, optionally shifted 518// left by 12 bits. Official assembly format specifies a 12 bit immediate with 519// one of "", "LSL #0", "LSL #12" supplementary operands. 520 521// There are surprisingly few ways to make this work with TableGen, so this 522// implementation has separate instructions for the "LSL #0" and "LSL #12" 523// variants. 524 525// If the MCInst retained a single combined immediate (which could be 0x123000, 526// for example) then both components (imm & shift) would have to be delegated to 527// a single assembly operand. This would entail a separate operand parser 528// (because the LSL would have to live in the same AArch64Operand as the 529// immediate to be accessible); assembly parsing is rather complex and 530// error-prone C++ code. 531// 532// By splitting the immediate, we can delegate handling this optional operand to 533// an InstAlias. Supporting functions to generate the correct MCInst are still 534// required, but these are essentially trivial and parsing can remain generic. 535// 536// Rejected plans with rationale: 537// ------------------------------ 538// 539// In an ideal world you'de have two first class immediate operands (in 540// InOperandList, specifying imm12 and shift). Unfortunately this is not 541// selectable by any means I could discover. 542// 543// An Instruction with two MCOperands hidden behind a single entry in 544// InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional, 545// but required more C++ code to handle encoding/decoding. Parsing (the intended 546// main beneficiary) ended up equally complex because of the optional nature of 547// "LSL #0". 548// 549// Attempting to circumvent the need for a custom OperandParser above by giving 550// InstAliases without the "lsl #0" failed. add/sub could be accommodated but 551// the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands 552// should be parsed: there was no way to accommodate an "lsl #12". 553 554let ParserMethod = "ParseImmWithLSLOperand", 555 RenderMethod = "addImmWithLSLOperands" in { 556 // Derived PredicateMethod fields are different for each 557 def addsubimm_lsl0_asmoperand : AsmOperandClass { 558 let Name = "AddSubImmLSL0"; 559 // If an error is reported against this operand, instruction could also be a 560 // register variant. 561 let DiagnosticType = "AddSubSecondSource"; 562 } 563 564 def addsubimm_lsl12_asmoperand : AsmOperandClass { 565 let Name = "AddSubImmLSL12"; 566 let DiagnosticType = "AddSubSecondSource"; 567 } 568} 569 570def shr_12_XFORM : SDNodeXForm<imm, [{ 571 return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32); 572}]>; 573 574def shr_12_neg_XFORM : SDNodeXForm<imm, [{ 575 return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32); 576}]>; 577 578def neg_XFORM : SDNodeXForm<imm, [{ 579 return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32); 580}]>; 581 582 583multiclass addsub_imm_operands<ValueType ty> { 584 let PrintMethod = "printAddSubImmLSL0Operand", 585 EncoderMethod = "getAddSubImmOpValue", 586 ParserMatchClass = addsubimm_lsl0_asmoperand in { 587 def _posimm_lsl0 : Operand<ty>, 588 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>; 589 def _negimm_lsl0 : Operand<ty>, 590 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }], 591 neg_XFORM>; 592 } 593 594 let PrintMethod = "printAddSubImmLSL12Operand", 595 EncoderMethod = "getAddSubImmOpValue", 596 ParserMatchClass = addsubimm_lsl12_asmoperand in { 597 def _posimm_lsl12 : Operand<ty>, 598 ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }], 599 shr_12_XFORM>; 600 601 def _negimm_lsl12 : Operand<ty>, 602 ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }], 603 shr_12_neg_XFORM>; 604 } 605} 606 607// The add operands don't need any transformation 608defm addsubimm_operand_i32 : addsub_imm_operands<i32>; 609defm addsubimm_operand_i64 : addsub_imm_operands<i64>; 610 611multiclass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift, 612 string asmop, string cmpasmop, 613 Operand imm_operand, Operand cmp_imm_operand, 614 RegisterClass GPR, RegisterClass GPRsp, 615 AArch64Reg ZR, ValueType Ty> { 616 // All registers for non-S variants allow SP 617 def _s : A64I_addsubimm<sf, op, 0b0, shift, 618 (outs GPRsp:$Rd), 619 (ins GPRsp:$Rn, imm_operand:$Imm12), 620 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"), 621 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))], 622 NoItinerary>; 623 624 625 // S variants can read SP but would write to ZR 626 def _S : A64I_addsubimm<sf, op, 0b1, shift, 627 (outs GPR:$Rd), 628 (ins GPRsp:$Rn, imm_operand:$Imm12), 629 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"), 630 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))], 631 NoItinerary> { 632 let Defs = [NZCV]; 633 } 634 635 // Note that the pattern here for ADDS is subtle. Canonically CMP 636 // a, b becomes SUBS a, b. If b < 0 then this is equivalent to 637 // ADDS a, (-b). This is not true in general. 638 def _cmp : A64I_addsubimm<sf, op, 0b1, shift, 639 (outs), (ins GPRsp:$Rn, imm_operand:$Imm12), 640 !strconcat(cmpasmop, " $Rn, $Imm12"), 641 [(set NZCV, 642 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))], 643 NoItinerary> { 644 let Rd = 0b11111; 645 let Defs = [NZCV]; 646 let isCompare = 1; 647 } 648} 649 650 651multiclass addsubimm_shifts<string prefix, bit sf, bit op, 652 string asmop, string cmpasmop, string operand, string cmpoperand, 653 RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR, 654 ValueType Ty> { 655 defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00, 656 asmop, cmpasmop, 657 !cast<Operand>(operand # "_lsl0"), 658 !cast<Operand>(cmpoperand # "_lsl0"), 659 GPR, GPRsp, ZR, Ty>; 660 661 defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01, 662 asmop, cmpasmop, 663 !cast<Operand>(operand # "_lsl12"), 664 !cast<Operand>(cmpoperand # "_lsl12"), 665 GPR, GPRsp, ZR, Ty>; 666} 667 668defm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn", 669 "addsubimm_operand_i32_posimm", 670 "addsubimm_operand_i32_negimm", 671 GPR32, GPR32wsp, WZR, i32>; 672defm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn", 673 "addsubimm_operand_i64_posimm", 674 "addsubimm_operand_i64_negimm", 675 GPR64, GPR64xsp, XZR, i64>; 676defm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp", 677 "addsubimm_operand_i32_negimm", 678 "addsubimm_operand_i32_posimm", 679 GPR32, GPR32wsp, WZR, i32>; 680defm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp", 681 "addsubimm_operand_i64_negimm", 682 "addsubimm_operand_i64_posimm", 683 GPR64, GPR64xsp, XZR, i64>; 684 685multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> { 686 def _fromsp : InstAlias<"mov $Rd, $Rn", 687 (addop GPRsp:$Rd, SP:$Rn, 0), 688 0b1>; 689 690 def _tosp : InstAlias<"mov $Rd, $Rn", 691 (addop SP:$Rd, GPRsp:$Rn, 0), 692 0b1>; 693} 694 695// Recall Rxsp is a RegisterClass containing *just* xsp. 696defm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>; 697defm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>; 698 699//===----------------------------------------------------------------------===// 700// Add-subtract (shifted register) instructions 701//===----------------------------------------------------------------------===// 702// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS 703 704//===------------------------------- 705// 1. The "shifed register" operands. Shared with logical insts. 706//===------------------------------- 707 708multiclass shift_operands<string prefix, string form> { 709 def _asmoperand_i32 : AsmOperandClass { 710 let Name = "Shift" # form # "i32"; 711 let RenderMethod = "addShiftOperands"; 712 let PredicateMethod = "isShift<A64SE::" # form # ", false>"; 713 let DiagnosticType = "AddSubRegShift32"; 714 } 715 716 // Note that the operand type is intentionally i64 because the DAGCombiner 717 // puts these into a canonical form. 718 def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 719 let ParserMatchClass 720 = !cast<AsmOperandClass>(prefix # "_asmoperand_i32"); 721 let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 722 let DecoderMethod = "Decode32BitShiftOperand"; 723 } 724 725 def _asmoperand_i64 : AsmOperandClass { 726 let Name = "Shift" # form # "i64"; 727 let RenderMethod = "addShiftOperands"; 728 let PredicateMethod = "isShift<A64SE::" # form # ", true>"; 729 let DiagnosticType = "AddSubRegShift64"; 730 } 731 732 def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 733 let ParserMatchClass 734 = !cast<AsmOperandClass>(prefix # "_asmoperand_i64"); 735 let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 736 } 737} 738 739defm lsl_operand : shift_operands<"lsl_operand", "LSL">; 740defm lsr_operand : shift_operands<"lsr_operand", "LSR">; 741defm asr_operand : shift_operands<"asr_operand", "ASR">; 742 743// Not used for add/sub, but defined here for completeness. The "logical 744// (shifted register)" instructions *do* have an ROR variant. 745defm ror_operand : shift_operands<"ror_operand", "ROR">; 746 747//===------------------------------- 748// 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions. 749//===------------------------------- 750 751// N.b. the commutable parameter is just !N. It will be first against the wall 752// when the revolution comes. 753multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable, 754 string asmop, SDPatternOperator opfrag, ValueType ty, 755 RegisterClass GPR, list<Register> defs> { 756 let isCommutable = commutable, Defs = defs in { 757 def _lsl : A64I_addsubshift<sf, op, s, 0b00, 758 (outs GPR:$Rd), 759 (ins GPR:$Rn, GPR:$Rm, 760 !cast<Operand>("lsl_operand_" # ty):$Imm6), 761 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 762 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 763 !cast<Operand>("lsl_operand_" # ty):$Imm6)) 764 )], 765 NoItinerary>; 766 767 def _lsr : A64I_addsubshift<sf, op, s, 0b01, 768 (outs GPR:$Rd), 769 (ins GPR:$Rn, GPR:$Rm, 770 !cast<Operand>("lsr_operand_" # ty):$Imm6), 771 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 772 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 773 !cast<Operand>("lsr_operand_" # ty):$Imm6)) 774 )], 775 NoItinerary>; 776 777 def _asr : A64I_addsubshift<sf, op, s, 0b10, 778 (outs GPR:$Rd), 779 (ins GPR:$Rn, GPR:$Rm, 780 !cast<Operand>("asr_operand_" # ty):$Imm6), 781 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 782 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 783 !cast<Operand>("asr_operand_" # ty):$Imm6)) 784 )], 785 NoItinerary>; 786 } 787 788 def _noshift 789 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 790 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 791 GPR:$Rm, 0)>; 792 793 def : Pat<(opfrag ty:$Rn, ty:$Rm), 794 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 795} 796 797multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable, 798 string asmop, SDPatternOperator opfrag, 799 list<Register> defs> { 800 defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s, 801 commutable, asmop, opfrag, i64, GPR64, defs>; 802 defm www : addsub_shifts<prefix # "www", 0b0, op, s, 803 commutable, asmop, opfrag, i32, GPR32, defs>; 804} 805 806 807defm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>; 808defm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>; 809 810defm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>; 811defm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>; 812 813//===------------------------------- 814// 1. The NEG/NEGS aliases 815//===------------------------------- 816 817multiclass neg_alias<Instruction INST, RegisterClass GPR, Register ZR, 818 ValueType ty, Operand shift_operand, SDNode shiftop> { 819 def : InstAlias<"neg $Rd, $Rm, $Imm6", 820 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 821 822 def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)), 823 (INST ZR, $Rm, shift_operand:$Imm6)>; 824} 825 826defm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>; 827defm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>; 828defm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>; 829def : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 830def : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>; 831 832defm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>; 833defm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>; 834defm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>; 835def : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 836def : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>; 837 838// NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to 839// be involved. 840class negs_alias<Instruction INST, RegisterClass GPR, 841 Register ZR, Operand shift_operand, SDNode shiftop> 842 : InstAlias<"negs $Rd, $Rm, $Imm6", 843 (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 844 845def : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>; 846def : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>; 847def : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>; 848def : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 849 850def : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>; 851def : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>; 852def : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>; 853def : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 854 855//===------------------------------- 856// 1. The CMP/CMN aliases 857//===------------------------------- 858 859multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable, 860 string asmop, SDPatternOperator opfrag, ValueType ty, 861 RegisterClass GPR> { 862 let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in { 863 def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00, 864 (outs), 865 (ins GPR:$Rn, GPR:$Rm, 866 !cast<Operand>("lsl_operand_" # ty):$Imm6), 867 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 868 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm, 869 !cast<Operand>("lsl_operand_" # ty):$Imm6)) 870 )], 871 NoItinerary>; 872 873 def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01, 874 (outs), 875 (ins GPR:$Rn, GPR:$Rm, 876 !cast<Operand>("lsr_operand_" # ty):$Imm6), 877 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 878 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm, 879 !cast<Operand>("lsr_operand_" # ty):$Imm6)) 880 )], 881 NoItinerary>; 882 883 def _asr : A64I_addsubshift<sf, op, 0b1, 0b10, 884 (outs), 885 (ins GPR:$Rn, GPR:$Rm, 886 !cast<Operand>("asr_operand_" # ty):$Imm6), 887 !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 888 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm, 889 !cast<Operand>("asr_operand_" # ty):$Imm6)) 890 )], 891 NoItinerary>; 892 } 893 894 def _noshift 895 : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 896 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 897 898 def : Pat<(opfrag ty:$Rn, ty:$Rm), 899 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 900} 901 902defm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>; 903defm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>; 904 905defm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>; 906defm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>; 907 908//===----------------------------------------------------------------------===// 909// Add-subtract (with carry) instructions 910//===----------------------------------------------------------------------===// 911// Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS 912 913multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> { 914 let Uses = [NZCV] in { 915 def www : A64I_addsubcarry<0b0, op, s, 0b000000, 916 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm), 917 !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 918 [], NoItinerary>; 919 920 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000, 921 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm), 922 !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 923 [], NoItinerary>; 924 } 925} 926 927let isCommutable = 1 in { 928 defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">; 929} 930 931defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">; 932 933let Defs = [NZCV] in { 934 let isCommutable = 1 in { 935 defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">; 936 } 937 938 defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">; 939} 940 941def : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>; 942def : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 943def : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>; 944def : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 945 946// Note that adde and sube can form a chain longer than two (e.g. for 256-bit 947// addition). So the flag-setting instructions are appropriate. 948def : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>; 949def : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>; 950def : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>; 951def : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>; 952 953//===----------------------------------------------------------------------===// 954// Bitfield 955//===----------------------------------------------------------------------===// 956// Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL, 957// UBFIZ, UBFX 958 959// Because of the rather complicated nearly-overlapping aliases, the decoding of 960// this range of instructions is handled manually. The architectural 961// instructions are BFM, SBFM and UBFM but a disassembler should never produce 962// these. 963// 964// In the end, the best option was to use BFM instructions for decoding under 965// almost all circumstances, but to create aliasing *Instructions* for each of 966// the canonical forms and specify a completely custom decoder which would 967// substitute the correct MCInst as needed. 968// 969// This also simplifies instruction selection, parsing etc because the MCInsts 970// have a shape that's closer to their use in code. 971 972//===------------------------------- 973// 1. The architectural BFM instructions 974//===------------------------------- 975 976def uimm5_asmoperand : AsmOperandClass { 977 let Name = "UImm5"; 978 let PredicateMethod = "isUImm<5>"; 979 let RenderMethod = "addImmOperands"; 980 let DiagnosticType = "UImm5"; 981} 982 983def uimm6_asmoperand : AsmOperandClass { 984 let Name = "UImm6"; 985 let PredicateMethod = "isUImm<6>"; 986 let RenderMethod = "addImmOperands"; 987 let DiagnosticType = "UImm6"; 988} 989 990def bitfield32_imm : Operand<i64>, 991 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> { 992 let ParserMatchClass = uimm5_asmoperand; 993 994 let DecoderMethod = "DecodeBitfield32ImmOperand"; 995} 996 997 998def bitfield64_imm : Operand<i64>, 999 ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> { 1000 let ParserMatchClass = uimm6_asmoperand; 1001 1002 // Default decoder works in 64-bit case: the 6-bit field can take any value. 1003} 1004 1005multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> { 1006 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1007 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1008 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1009 [], NoItinerary> { 1010 let DecoderMethod = "DecodeBitfieldInstruction"; 1011 } 1012 1013 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1014 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1015 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1016 [], NoItinerary> { 1017 let DecoderMethod = "DecodeBitfieldInstruction"; 1018 } 1019} 1020 1021defm SBFM : A64I_bitfieldSizes<0b00, "sbfm">; 1022defm UBFM : A64I_bitfieldSizes<0b10, "ubfm">; 1023 1024// BFM instructions modify the destination register rather than defining it 1025// completely. 1026def BFMwwii : 1027 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1028 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1029 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1030 let DecoderMethod = "DecodeBitfieldInstruction"; 1031 let Constraints = "$src = $Rd"; 1032} 1033 1034def BFMxxii : 1035 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1036 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1037 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1038 let DecoderMethod = "DecodeBitfieldInstruction"; 1039 let Constraints = "$src = $Rd"; 1040} 1041 1042 1043//===------------------------------- 1044// 2. Extend aliases to 64-bit dest 1045//===------------------------------- 1046 1047// Unfortunately the extensions that end up as 64-bits cannot be handled by an 1048// instruction alias: their syntax is (for example) "SXTB x0, w0", which needs 1049// to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is 1050// not capable of such a map as far as I'm aware 1051 1052// Note that these instructions are strictly more specific than the 1053// BFM ones (in ImmR) so they can handle their own decoding. 1054class A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty, 1055 string asmop, bits<6> imms, dag pattern> 1056 : A64I_bitfield<sf, opc, sf, 1057 (outs GPRDest:$Rd), (ins GPR32:$Rn), 1058 !strconcat(asmop, "\t$Rd, $Rn"), 1059 [(set dty:$Rd, pattern)], NoItinerary> { 1060 let ImmR = 0b000000; 1061 let ImmS = imms; 1062} 1063 1064// Signed extensions 1065def SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7, 1066 (sext_inreg (anyext i32:$Rn), i8)>; 1067def SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7, 1068 (sext_inreg i32:$Rn, i8)>; 1069def SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15, 1070 (sext_inreg (anyext i32:$Rn), i16)>; 1071def SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15, 1072 (sext_inreg i32:$Rn, i16)>; 1073def SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>; 1074 1075// Unsigned extensions 1076def UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7, 1077 (and i32:$Rn, 255)>; 1078def UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15, 1079 (and i32:$Rn, 65535)>; 1080 1081// The 64-bit unsigned variants are not strictly architectural but recommended 1082// for consistency. 1083let isAsmParserOnly = 1 in { 1084 def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7, 1085 (and (anyext i32:$Rn), 255)>; 1086 def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15, 1087 (and (anyext i32:$Rn), 65535)>; 1088} 1089 1090// Extra patterns for when the source register is actually 64-bits 1091// too. There's no architectural difference here, it's just LLVM 1092// shinanigans. There's no need for equivalent zero-extension patterns 1093// because they'll already be caught by logical (immediate) matching. 1094def : Pat<(sext_inreg i64:$Rn, i8), 1095 (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>; 1096def : Pat<(sext_inreg i64:$Rn, i16), 1097 (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>; 1098def : Pat<(sext_inreg i64:$Rn, i32), 1099 (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>; 1100 1101 1102//===------------------------------- 1103// 3. Aliases for ASR and LSR (the simple shifts) 1104//===------------------------------- 1105 1106// These also handle their own decoding because ImmS being set makes 1107// them take precedence over BFM. 1108multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> { 1109 def wwi : A64I_bitfield<0b0, opc, 0b0, 1110 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR), 1111 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1112 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))], 1113 NoItinerary> { 1114 let ImmS = 31; 1115 } 1116 1117 def xxi : A64I_bitfield<0b1, opc, 0b1, 1118 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR), 1119 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1120 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))], 1121 NoItinerary> { 1122 let ImmS = 63; 1123 } 1124 1125} 1126 1127defm ASR : A64I_shift<0b00, "asr", sra>; 1128defm LSR : A64I_shift<0b10, "lsr", srl>; 1129 1130//===------------------------------- 1131// 4. Aliases for LSL 1132//===------------------------------- 1133 1134// Unfortunately LSL and subsequent aliases are much more complicated. We need 1135// to be able to say certain output instruction fields depend in a complex 1136// manner on combinations of input assembly fields). 1137// 1138// MIOperandInfo *might* have been able to do it, but at the cost of 1139// significantly more C++ code. 1140 1141// N.b. contrary to usual practice these operands store the shift rather than 1142// the machine bits in an MCInst. The complexity overhead of consistency 1143// outweighed the benefits in this case (custom asmparser, printer and selection 1144// vs custom encoder). 1145def bitfield32_lsl_imm : Operand<i64>, 1146 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1147 let ParserMatchClass = uimm5_asmoperand; 1148 let EncoderMethod = "getBitfield32LSLOpValue"; 1149} 1150 1151def bitfield64_lsl_imm : Operand<i64>, 1152 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1153 let ParserMatchClass = uimm6_asmoperand; 1154 let EncoderMethod = "getBitfield64LSLOpValue"; 1155} 1156 1157class A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty, 1158 Operand operand> 1159 : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm), 1160 "lsl\t$Rd, $Rn, $FullImm", 1161 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))], 1162 NoItinerary> { 1163 bits<12> FullImm; 1164 let ImmR = FullImm{5-0}; 1165 let ImmS = FullImm{11-6}; 1166 1167 // No disassembler allowed because it would overlap with BFM which does the 1168 // actual work. 1169 let isAsmParserOnly = 1; 1170} 1171 1172def LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>; 1173def LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>; 1174 1175//===------------------------------- 1176// 5. Aliases for bitfield extract instructions 1177//===------------------------------- 1178 1179def bfx32_width_asmoperand : AsmOperandClass { 1180 let Name = "BFX32Width"; 1181 let PredicateMethod = "isBitfieldWidth<32>"; 1182 let RenderMethod = "addBFXWidthOperands"; 1183 let DiagnosticType = "Width32"; 1184} 1185 1186def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> { 1187 let PrintMethod = "printBFXWidthOperand"; 1188 let ParserMatchClass = bfx32_width_asmoperand; 1189} 1190 1191def bfx64_width_asmoperand : AsmOperandClass { 1192 let Name = "BFX64Width"; 1193 let PredicateMethod = "isBitfieldWidth<64>"; 1194 let RenderMethod = "addBFXWidthOperands"; 1195 let DiagnosticType = "Width64"; 1196} 1197 1198def bfx64_width : Operand<i64> { 1199 let PrintMethod = "printBFXWidthOperand"; 1200 let ParserMatchClass = bfx64_width_asmoperand; 1201} 1202 1203 1204multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> { 1205 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1206 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1207 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1208 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))], 1209 NoItinerary> { 1210 // As above, no disassembler allowed. 1211 let isAsmParserOnly = 1; 1212 } 1213 1214 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1215 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1216 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1217 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))], 1218 NoItinerary> { 1219 // As above, no disassembler allowed. 1220 let isAsmParserOnly = 1; 1221 } 1222} 1223 1224defm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>; 1225defm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>; 1226 1227// Again, variants based on BFM modify Rd so need it as an input too. 1228def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1229 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1230 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1231 // As above, no disassembler allowed. 1232 let isAsmParserOnly = 1; 1233 let Constraints = "$src = $Rd"; 1234} 1235 1236def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1237 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1238 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1239 // As above, no disassembler allowed. 1240 let isAsmParserOnly = 1; 1241 let Constraints = "$src = $Rd"; 1242} 1243 1244// SBFX instructions can do a 1-instruction sign-extension of boolean values. 1245def : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>; 1246def : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>; 1247def : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)), 1248 (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>; 1249 1250// UBFX makes sense as an implementation of a 64-bit zero-extension too. Could 1251// use either 64-bit or 32-bit variant, but 32-bit might be more efficient. 1252def : Pat<(zext i32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31), 1253 sub_32)>; 1254 1255//===------------------------------- 1256// 6. Aliases for bitfield insert instructions 1257//===------------------------------- 1258 1259def bfi32_lsb_asmoperand : AsmOperandClass { 1260 let Name = "BFI32LSB"; 1261 let PredicateMethod = "isUImm<5>"; 1262 let RenderMethod = "addBFILSBOperands<32>"; 1263 let DiagnosticType = "UImm5"; 1264} 1265 1266def bfi32_lsb : Operand<i64>, 1267 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1268 let PrintMethod = "printBFILSBOperand<32>"; 1269 let ParserMatchClass = bfi32_lsb_asmoperand; 1270} 1271 1272def bfi64_lsb_asmoperand : AsmOperandClass { 1273 let Name = "BFI64LSB"; 1274 let PredicateMethod = "isUImm<6>"; 1275 let RenderMethod = "addBFILSBOperands<64>"; 1276 let DiagnosticType = "UImm6"; 1277} 1278 1279def bfi64_lsb : Operand<i64>, 1280 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1281 let PrintMethod = "printBFILSBOperand<64>"; 1282 let ParserMatchClass = bfi64_lsb_asmoperand; 1283} 1284 1285// Width verification is performed during conversion so width operand can be 1286// shared between 32/64-bit cases. Still needed for the print method though 1287// because ImmR encodes "width - 1". 1288def bfi32_width_asmoperand : AsmOperandClass { 1289 let Name = "BFI32Width"; 1290 let PredicateMethod = "isBitfieldWidth<32>"; 1291 let RenderMethod = "addBFIWidthOperands"; 1292 let DiagnosticType = "Width32"; 1293} 1294 1295def bfi32_width : Operand<i64>, 1296 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> { 1297 let PrintMethod = "printBFIWidthOperand"; 1298 let ParserMatchClass = bfi32_width_asmoperand; 1299} 1300 1301def bfi64_width_asmoperand : AsmOperandClass { 1302 let Name = "BFI64Width"; 1303 let PredicateMethod = "isBitfieldWidth<64>"; 1304 let RenderMethod = "addBFIWidthOperands"; 1305 let DiagnosticType = "Width64"; 1306} 1307 1308def bfi64_width : Operand<i64>, 1309 ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> { 1310 let PrintMethod = "printBFIWidthOperand"; 1311 let ParserMatchClass = bfi64_width_asmoperand; 1312} 1313 1314multiclass A64I_bitfield_insert<bits<2> opc, string asmop> { 1315 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1316 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1317 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1318 [], NoItinerary> { 1319 // As above, no disassembler allowed. 1320 let isAsmParserOnly = 1; 1321 } 1322 1323 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1324 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1325 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1326 [], NoItinerary> { 1327 // As above, no disassembler allowed. 1328 let isAsmParserOnly = 1; 1329 } 1330} 1331 1332defm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">; 1333defm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">; 1334 1335 1336def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1337 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1338 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1339 // As above, no disassembler allowed. 1340 let isAsmParserOnly = 1; 1341 let Constraints = "$src = $Rd"; 1342} 1343 1344def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1345 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1346 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1347 // As above, no disassembler allowed. 1348 let isAsmParserOnly = 1; 1349 let Constraints = "$src = $Rd"; 1350} 1351 1352//===----------------------------------------------------------------------===// 1353// Compare and branch (immediate) 1354//===----------------------------------------------------------------------===// 1355// Contains: CBZ, CBNZ 1356 1357class label_asmoperand<int width, int scale> : AsmOperandClass { 1358 let Name = "Label" # width # "_" # scale; 1359 let PredicateMethod = "isLabel<" # width # "," # scale # ">"; 1360 let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">"; 1361 let DiagnosticType = "Label"; 1362} 1363 1364def label_wid19_scal4_asmoperand : label_asmoperand<19, 4>; 1365 1366// All conditional immediate branches are the same really: 19 signed bits scaled 1367// by the instruction-size (4). 1368def bcc_target : Operand<OtherVT> { 1369 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 1370 let ParserMatchClass = label_wid19_scal4_asmoperand; 1371 let PrintMethod = "printLabelOperand<19, 4>"; 1372 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>"; 1373 let OperandType = "OPERAND_PCREL"; 1374} 1375 1376multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> { 1377 let isBranch = 1, isTerminator = 1 in { 1378 def x : A64I_cmpbr<0b1, op, 1379 (outs), 1380 (ins GPR64:$Rt, bcc_target:$Label), 1381 !strconcat(asmop,"\t$Rt, $Label"), 1382 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)], 1383 NoItinerary>; 1384 1385 def w : A64I_cmpbr<0b0, op, 1386 (outs), 1387 (ins GPR32:$Rt, bcc_target:$Label), 1388 !strconcat(asmop,"\t$Rt, $Label"), 1389 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)], 1390 NoItinerary>; 1391 } 1392} 1393 1394defm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{ 1395 return Imm == A64CC::EQ; 1396}]> >; 1397defm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{ 1398 return Imm == A64CC::NE; 1399}]> >; 1400 1401//===----------------------------------------------------------------------===// 1402// Conditional branch (immediate) instructions 1403//===----------------------------------------------------------------------===// 1404// Contains: B.cc 1405 1406def cond_code_asmoperand : AsmOperandClass { 1407 let Name = "CondCode"; 1408 let DiagnosticType = "CondCode"; 1409} 1410 1411def cond_code : Operand<i32>, ImmLeaf<i32, [{ 1412 return Imm >= 0 && Imm <= 15; 1413}]> { 1414 let PrintMethod = "printCondCodeOperand"; 1415 let ParserMatchClass = cond_code_asmoperand; 1416} 1417 1418def Bcc : A64I_condbr<0b0, 0b0, (outs), 1419 (ins cond_code:$Cond, bcc_target:$Label), 1420 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)], 1421 NoItinerary> { 1422 let Uses = [NZCV]; 1423 let isBranch = 1; 1424 let isTerminator = 1; 1425} 1426 1427//===----------------------------------------------------------------------===// 1428// Conditional compare (immediate) instructions 1429//===----------------------------------------------------------------------===// 1430// Contains: CCMN, CCMP 1431 1432def uimm4_asmoperand : AsmOperandClass { 1433 let Name = "UImm4"; 1434 let PredicateMethod = "isUImm<4>"; 1435 let RenderMethod = "addImmOperands"; 1436 let DiagnosticType = "UImm4"; 1437} 1438 1439def uimm4 : Operand<i32> { 1440 let ParserMatchClass = uimm4_asmoperand; 1441} 1442 1443def uimm5 : Operand<i32> { 1444 let ParserMatchClass = uimm5_asmoperand; 1445} 1446 1447// The only difference between this operand and the one for instructions like 1448// B.cc is that it's parsed manually. The other get parsed implicitly as part of 1449// the mnemonic handling. 1450def cond_code_op_asmoperand : AsmOperandClass { 1451 let Name = "CondCodeOp"; 1452 let RenderMethod = "addCondCodeOperands"; 1453 let PredicateMethod = "isCondCode"; 1454 let ParserMethod = "ParseCondCodeOperand"; 1455 let DiagnosticType = "CondCode"; 1456} 1457 1458def cond_code_op : Operand<i32> { 1459 let PrintMethod = "printCondCodeOperand"; 1460 let ParserMatchClass = cond_code_op_asmoperand; 1461} 1462 1463class A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1464 : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs), 1465 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond), 1466 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"), 1467 [], NoItinerary> { 1468 let Defs = [NZCV]; 1469} 1470 1471def CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">; 1472def CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">; 1473def CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">; 1474def CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">; 1475 1476//===----------------------------------------------------------------------===// 1477// Conditional compare (register) instructions 1478//===----------------------------------------------------------------------===// 1479// Contains: CCMN, CCMP 1480 1481class A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1482 : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1, 1483 (outs), 1484 (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 1485 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 1486 [], NoItinerary> { 1487 let Defs = [NZCV]; 1488} 1489 1490def CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">; 1491def CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">; 1492def CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">; 1493def CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">; 1494 1495//===----------------------------------------------------------------------===// 1496// Conditional select instructions 1497//===----------------------------------------------------------------------===// 1498// Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG 1499 1500// Condition code which is encoded as the inversion (semantically rather than 1501// bitwise) in the instruction. 1502def inv_cond_code_op_asmoperand : AsmOperandClass { 1503 let Name = "InvCondCodeOp"; 1504 let RenderMethod = "addInvCondCodeOperands"; 1505 let PredicateMethod = "isCondCode"; 1506 let ParserMethod = "ParseCondCodeOperand"; 1507 let DiagnosticType = "CondCode"; 1508} 1509 1510def inv_cond_code_op : Operand<i32> { 1511 let ParserMatchClass = inv_cond_code_op_asmoperand; 1512} 1513 1514// Having a separate operand for the selectable use-case is debatable, but gives 1515// consistency with cond_code. 1516def inv_cond_XFORM : SDNodeXForm<imm, [{ 1517 A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue()); 1518 return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32); 1519}]>; 1520 1521def inv_cond_code 1522 : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>; 1523 1524 1525multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop, 1526 SDPatternOperator select> { 1527 let Uses = [NZCV] in { 1528 def wwwc : A64I_condsel<0b0, op, 0b0, op2, 1529 (outs GPR32:$Rd), 1530 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond), 1531 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1532 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))], 1533 NoItinerary>; 1534 1535 1536 def xxxc : A64I_condsel<0b1, op, 0b0, op2, 1537 (outs GPR64:$Rd), 1538 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond), 1539 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1540 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))], 1541 NoItinerary>; 1542 } 1543} 1544 1545def simple_select 1546 : PatFrag<(ops node:$lhs, node:$rhs), 1547 (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>; 1548 1549class complex_select<SDPatternOperator opnode> 1550 : PatFrag<(ops node:$lhs, node:$rhs), 1551 (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>; 1552 1553 1554defm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>; 1555defm CSINC : A64I_condselSizes<0b0, 0b01, "csinc", 1556 complex_select<PatFrag<(ops node:$val), 1557 (add node:$val, 1)>>>; 1558defm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>; 1559defm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>; 1560 1561// Now the instruction aliases, which fit nicely into LLVM's model: 1562 1563def : InstAlias<"cset $Rd, $Cond", 1564 (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1565def : InstAlias<"cset $Rd, $Cond", 1566 (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1567def : InstAlias<"csetm $Rd, $Cond", 1568 (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1569def : InstAlias<"csetm $Rd, $Cond", 1570 (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1571def : InstAlias<"cinc $Rd, $Rn, $Cond", 1572 (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1573def : InstAlias<"cinc $Rd, $Rn, $Cond", 1574 (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1575def : InstAlias<"cinv $Rd, $Rn, $Cond", 1576 (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1577def : InstAlias<"cinv $Rd, $Rn, $Cond", 1578 (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1579def : InstAlias<"cneg $Rd, $Rn, $Cond", 1580 (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1581def : InstAlias<"cneg $Rd, $Rn, $Cond", 1582 (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1583 1584// Finally some helper patterns. 1585 1586// For CSET (a.k.a. zero-extension of icmp) 1587def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1588 (CSINCwwwc WZR, WZR, cond_code:$Cond)>; 1589def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1590 (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>; 1591 1592def : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1593 (CSINCxxxc XZR, XZR, cond_code:$Cond)>; 1594def : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1595 (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>; 1596 1597// For CSETM (a.k.a. sign-extension of icmp) 1598def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1599 (CSINVwwwc WZR, WZR, cond_code:$Cond)>; 1600def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1601 (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>; 1602 1603def : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1604 (CSINVxxxc XZR, XZR, cond_code:$Cond)>; 1605def : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1606 (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>; 1607 1608// CINC, CINV and CNEG get dealt with automatically, which leaves the issue of 1609// commutativity. The instructions are to complex for isCommutable to be used, 1610// so we have to create the patterns manually: 1611 1612// No commutable pattern for CSEL since the commuted version is isomorphic. 1613 1614// CSINC 1615def :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond), 1616 (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1617def :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond), 1618 (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1619 1620// CSINV 1621def :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1622 (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1623def :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1624 (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1625 1626// CSNEG 1627def :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1628 (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1629def :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1630 (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1631 1632//===----------------------------------------------------------------------===// 1633// Data Processing (1 source) instructions 1634//===----------------------------------------------------------------------===// 1635// Contains: RBIT, REV16, REV, REV32, CLZ, CLS. 1636 1637// We define an unary operator which always fails. We will use this to 1638// define unary operators that cannot be matched. 1639 1640class A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop, 1641 list<dag> patterns, RegisterClass GPRrc, 1642 InstrItinClass itin>: 1643 A64I_dp_1src<sf, 1644 0, 1645 0b00000, 1646 opcode, 1647 !strconcat(asmop, "\t$Rd, $Rn"), 1648 (outs GPRrc:$Rd), 1649 (ins GPRrc:$Rn), 1650 patterns, 1651 itin>; 1652 1653multiclass A64I_dp_1src <bits<6> opcode, string asmop> { 1654 let hasSideEffects = 0 in { 1655 def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>; 1656 def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>; 1657 } 1658} 1659 1660defm RBIT : A64I_dp_1src<0b000000, "rbit">; 1661defm CLS : A64I_dp_1src<0b000101, "cls">; 1662defm CLZ : A64I_dp_1src<0b000100, "clz">; 1663 1664def : Pat<(ctlz i32:$Rn), (CLZww $Rn)>; 1665def : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>; 1666def : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>; 1667def : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>; 1668 1669def : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>; 1670def : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>; 1671def : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>; 1672def : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>; 1673 1674 1675def REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev", 1676 [(set i32:$Rd, (bswap i32:$Rn))], 1677 GPR32, NoItinerary>; 1678def REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev", 1679 [(set i64:$Rd, (bswap i64:$Rn))], 1680 GPR64, NoItinerary>; 1681def REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32", 1682 [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))], 1683 GPR64, NoItinerary>; 1684def REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16", 1685 [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))], 1686 GPR32, 1687 NoItinerary>; 1688def REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>; 1689 1690//===----------------------------------------------------------------------===// 1691// Data Processing (2 sources) instructions 1692//===----------------------------------------------------------------------===// 1693// Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL, 1694// LSR, ASR, ROR 1695 1696 1697class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns, 1698 RegisterClass GPRsp, 1699 InstrItinClass itin>: 1700 A64I_dp_2src<sf, 1701 opcode, 1702 0, 1703 !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 1704 (outs GPRsp:$Rd), 1705 (ins GPRsp:$Rn, GPRsp:$Rm), 1706 patterns, 1707 itin>; 1708 1709multiclass dp_2src_crc<bit c, string asmop> { 1710 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0}, 1711 !strconcat(asmop, "b"), [], GPR32, NoItinerary>; 1712 def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1}, 1713 !strconcat(asmop, "h"), [], GPR32, NoItinerary>; 1714 def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0}, 1715 !strconcat(asmop, "w"), [], GPR32, NoItinerary>; 1716 def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0, 1717 !strconcat(asmop, "x\t$Rd, $Rn, $Rm"), 1718 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [], 1719 NoItinerary>; 1720} 1721 1722multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> { 1723 def www : dp_2src_impl<0b0, 1724 opcode, 1725 asmop, 1726 [(set i32:$Rd, 1727 (op i32:$Rn, (i64 (zext i32:$Rm))))], 1728 GPR32, 1729 NoItinerary>; 1730 def xxx : dp_2src_impl<0b1, 1731 opcode, 1732 asmop, 1733 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1734 GPR64, 1735 NoItinerary>; 1736} 1737 1738 1739multiclass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> { 1740 def www : dp_2src_impl<0b0, 1741 opcode, 1742 asmop, 1743 [(set i32:$Rd, (op i32:$Rn, i32:$Rm))], 1744 GPR32, 1745 NoItinerary>; 1746 def xxx : dp_2src_impl<0b1, 1747 opcode, 1748 asmop, 1749 [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1750 GPR64, 1751 NoItinerary>; 1752} 1753 1754// Here we define the data processing 2 source instructions. 1755defm CRC32 : dp_2src_crc<0b0, "crc32">; 1756defm CRC32C : dp_2src_crc<0b1, "crc32c">; 1757 1758defm UDIV : dp_2src<0b000010, "udiv", udiv>; 1759defm SDIV : dp_2src<0b000011, "sdiv", sdiv>; 1760 1761defm LSLV : dp_2src_zext<0b001000, "lsl", shl>; 1762defm LSRV : dp_2src_zext<0b001001, "lsr", srl>; 1763defm ASRV : dp_2src_zext<0b001010, "asr", sra>; 1764defm RORV : dp_2src_zext<0b001011, "ror", rotr>; 1765 1766// Extra patterns for an incoming 64-bit value for a 32-bit 1767// operation. Since the LLVM operations are undefined (as in C) if the 1768// RHS is out of range, it's perfectly permissible to discard the high 1769// bits of the GPR64. 1770def : Pat<(shl i32:$Rn, i64:$Rm), 1771 (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1772def : Pat<(srl i32:$Rn, i64:$Rm), 1773 (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1774def : Pat<(sra i32:$Rn, i64:$Rm), 1775 (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1776def : Pat<(rotr i32:$Rn, i64:$Rm), 1777 (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1778 1779// Here we define the aliases for the data processing 2 source instructions. 1780def LSL_mnemonic : MnemonicAlias<"lslv", "lsl">; 1781def LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">; 1782def ASR_menmonic : MnemonicAlias<"asrv", "asr">; 1783def ROR_menmonic : MnemonicAlias<"rorv", "ror">; 1784 1785//===----------------------------------------------------------------------===// 1786// Data Processing (3 sources) instructions 1787//===----------------------------------------------------------------------===// 1788// Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH 1789// + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL 1790 1791class A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg, 1792 ValueType AccTy, RegisterClass SrcReg, 1793 string asmop, dag pattern> 1794 : A64I_dp3<sf, opcode, 1795 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra), 1796 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"), 1797 [(set AccTy:$Rd, pattern)], NoItinerary> { 1798 RegisterClass AccGPR = AccReg; 1799 RegisterClass SrcGPR = SrcReg; 1800} 1801 1802def MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd", 1803 (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1804def MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd", 1805 (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1806 1807def MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub", 1808 (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1809def MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub", 1810 (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1811 1812def SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl", 1813 (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1814def SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl", 1815 (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1816 1817def UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl", 1818 (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1819def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl", 1820 (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1821 1822let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in { 1823 def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd), 1824 (ins GPR64:$Rn, GPR64:$Rm), 1825 "umulh\t$Rd, $Rn, $Rm", 1826 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))], 1827 NoItinerary>; 1828 1829 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd), 1830 (ins GPR64:$Rn, GPR64:$Rm), 1831 "smulh\t$Rd, $Rn, $Rm", 1832 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))], 1833 NoItinerary>; 1834} 1835 1836multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST, 1837 Register ZR, dag pattern> { 1838 def : InstAlias<asmop # " $Rd, $Rn, $Rm", 1839 (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>; 1840 1841 def : Pat<pattern, (INST $Rn, $Rm, ZR)>; 1842} 1843 1844defm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>; 1845defm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>; 1846 1847defm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR, 1848 (sub 0, (mul i32:$Rn, i32:$Rm))>; 1849defm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR, 1850 (sub 0, (mul i64:$Rn, i64:$Rm))>; 1851 1852defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR, 1853 (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>; 1854defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR, 1855 (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1856 1857defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR, 1858 (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>; 1859defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR, 1860 (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1861 1862 1863//===----------------------------------------------------------------------===// 1864// Exception generation 1865//===----------------------------------------------------------------------===// 1866// Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3 1867 1868def uimm16_asmoperand : AsmOperandClass { 1869 let Name = "UImm16"; 1870 let PredicateMethod = "isUImm<16>"; 1871 let RenderMethod = "addImmOperands"; 1872 let DiagnosticType = "UImm16"; 1873} 1874 1875def uimm16 : Operand<i32> { 1876 let ParserMatchClass = uimm16_asmoperand; 1877} 1878 1879class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop> 1880 : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16), 1881 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> { 1882 let isBranch = 1; 1883 let isTerminator = 1; 1884} 1885 1886def SVCi : A64I_exceptImpl<0b000, 0b01, "svc">; 1887def HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">; 1888def SMCi : A64I_exceptImpl<0b000, 0b11, "smc">; 1889def BRKi : A64I_exceptImpl<0b001, 0b00, "brk">; 1890def HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">; 1891 1892def DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">; 1893def DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">; 1894def DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">; 1895 1896// The immediate is optional for the DCPS instructions, defaulting to 0. 1897def : InstAlias<"dcps1", (DCPS1i 0)>; 1898def : InstAlias<"dcps2", (DCPS2i 0)>; 1899def : InstAlias<"dcps3", (DCPS3i 0)>; 1900 1901//===----------------------------------------------------------------------===// 1902// Extract (immediate) 1903//===----------------------------------------------------------------------===// 1904// Contains: EXTR + alias ROR 1905 1906def EXTRwwwi : A64I_extract<0b0, 0b000, 0b0, 1907 (outs GPR32:$Rd), 1908 (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB), 1909 "extr\t$Rd, $Rn, $Rm, $LSB", 1910 [(set i32:$Rd, 1911 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))], 1912 NoItinerary>; 1913def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1, 1914 (outs GPR64:$Rd), 1915 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB), 1916 "extr\t$Rd, $Rn, $Rm, $LSB", 1917 [(set i64:$Rd, 1918 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))], 1919 NoItinerary>; 1920 1921def : InstAlias<"ror $Rd, $Rs, $LSB", 1922 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>; 1923def : InstAlias<"ror $Rd, $Rs, $LSB", 1924 (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>; 1925 1926def : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB), 1927 (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>; 1928def : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB), 1929 (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>; 1930 1931//===----------------------------------------------------------------------===// 1932// Floating-point compare instructions 1933//===----------------------------------------------------------------------===// 1934// Contains: FCMP, FCMPE 1935 1936def fpzero_asmoperand : AsmOperandClass { 1937 let Name = "FPZero"; 1938 let ParserMethod = "ParseFPImmOperand"; 1939 let DiagnosticType = "FPZero"; 1940} 1941 1942def fpz32 : Operand<f32>, 1943 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> { 1944 let ParserMatchClass = fpzero_asmoperand; 1945 let PrintMethod = "printFPZeroOperand"; 1946 let DecoderMethod = "DecodeFPZeroOperand"; 1947} 1948 1949def fpz64 : Operand<f64>, 1950 ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { 1951 let ParserMatchClass = fpzero_asmoperand; 1952 let PrintMethod = "printFPZeroOperand"; 1953 let DecoderMethod = "DecodeFPZeroOperand"; 1954} 1955 1956multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> { 1957 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0}, 1958 (outs), ins, "fcmp\t$Rn, $Rm", [pattern], 1959 NoItinerary> { 1960 let Defs = [NZCV]; 1961 } 1962 1963 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0}, 1964 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> { 1965 let Defs = [NZCV]; 1966 } 1967} 1968 1969defm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), 1970 (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>; 1971defm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), 1972 (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>; 1973 1974// What would be Rm should be written as 0; note that even though it's called 1975// "$Rm" here to fit in with the InstrFormats, it's actually an immediate. 1976defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm), 1977 (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>; 1978 1979defm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm), 1980 (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>; 1981 1982 1983//===----------------------------------------------------------------------===// 1984// Floating-point conditional compare instructions 1985//===----------------------------------------------------------------------===// 1986// Contains: FCCMP, FCCMPE 1987 1988class A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop> 1989 : A64I_fpccmp<0b0, 0b0, type, op, 1990 (outs), 1991 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 1992 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 1993 [], NoItinerary> { 1994 let Defs = [NZCV]; 1995} 1996 1997def FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">; 1998def FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">; 1999def FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">; 2000def FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">; 2001 2002//===----------------------------------------------------------------------===// 2003// Floating-point conditional select instructions 2004//===----------------------------------------------------------------------===// 2005// Contains: FCSEL 2006 2007let Uses = [NZCV] in { 2008 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd), 2009 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond), 2010 "fcsel\t$Rd, $Rn, $Rm, $Cond", 2011 [(set f32:$Rd, 2012 (simple_select f32:$Rn, f32:$Rm))], 2013 NoItinerary>; 2014 2015 2016 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd), 2017 (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond), 2018 "fcsel\t$Rd, $Rn, $Rm, $Cond", 2019 [(set f64:$Rd, 2020 (simple_select f64:$Rn, f64:$Rm))], 2021 NoItinerary>; 2022} 2023 2024//===----------------------------------------------------------------------===// 2025// Floating-point data-processing (1 source) 2026//===----------------------------------------------------------------------===// 2027// Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI]. 2028 2029def FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val), 2030 [{ (void)N; return false; }]>; 2031 2032// First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d" 2033// syntax. Default to no pattern because most are odd enough not to have one. 2034multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr, 2035 SDPatternOperator opnode = FPNoUnop> { 2036 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn), 2037 !strconcat(asmstr, "\t$Rd, $Rn"), 2038 [(set f32:$Rd, (opnode f32:$Rn))], 2039 NoItinerary>; 2040 2041 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn), 2042 !strconcat(asmstr, "\t$Rd, $Rn"), 2043 [(set f64:$Rd, (opnode f64:$Rn))], 2044 NoItinerary>; 2045} 2046 2047defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">; 2048defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>; 2049defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>; 2050defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>; 2051 2052defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">; 2053defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>; 2054defm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>; 2055defm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>; 2056defm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">; 2057defm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>; 2058defm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>; 2059 2060// The FCVT instrucitons have different source and destination register-types, 2061// but the fields are uniform everywhere a D-register (say) crops up. Package 2062// this information in a Record. 2063class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> { 2064 RegisterClass Class = rc; 2065 ValueType VT = vt; 2066 bit t1 = fld{1}; 2067 bit t0 = fld{0}; 2068} 2069 2070def FCVT16 : FCVTRegType<FPR16, 0b11, f16>; 2071def FCVT32 : FCVTRegType<FPR32, 0b00, f32>; 2072def FCVT64 : FCVTRegType<FPR64, 0b01, f64>; 2073 2074class A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode> 2075 : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0}, 2076 {0,0,0,1, DestReg.t1, DestReg.t0}, 2077 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn), 2078 "fcvt\t$Rd, $Rn", 2079 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>; 2080 2081def FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>; 2082def FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>; 2083def FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>; 2084def FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>; 2085def FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>; 2086def FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>; 2087 2088 2089//===----------------------------------------------------------------------===// 2090// Floating-point data-processing (2 sources) instructions 2091//===----------------------------------------------------------------------===// 2092// Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL 2093 2094def FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs), 2095 [{ (void)N; return false; }]>; 2096 2097multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr, 2098 SDPatternOperator opnode> { 2099 def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode, 2100 (outs FPR32:$Rd), 2101 (ins FPR32:$Rn, FPR32:$Rm), 2102 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2103 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))], 2104 NoItinerary>; 2105 2106 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode, 2107 (outs FPR64:$Rd), 2108 (ins FPR64:$Rn, FPR64:$Rm), 2109 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2110 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))], 2111 NoItinerary>; 2112} 2113 2114let isCommutable = 1 in { 2115 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>; 2116 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>; 2117 2118 // No patterns for these. 2119 defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>; 2120 defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>; 2121 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>; 2122 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>; 2123 2124 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul", 2125 PatFrag<(ops node:$lhs, node:$rhs), 2126 (fneg (fmul node:$lhs, node:$rhs))> >; 2127} 2128 2129defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>; 2130defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>; 2131 2132//===----------------------------------------------------------------------===// 2133// Floating-point data-processing (3 sources) instructions 2134//===----------------------------------------------------------------------===// 2135// Contains: FMADD, FMSUB, FNMADD, FNMSUB 2136 2137def fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2138 (fma (fneg node:$Rn), node:$Rm, node:$Ra)>; 2139def fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2140 (fma node:$Rn, node:$Rm, (fneg node:$Ra))>; 2141def fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2142 (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>; 2143 2144class A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT, 2145 bits<2> type, bit o1, bit o0, SDPatternOperator fmakind> 2146 : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd), 2147 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra), 2148 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"), 2149 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))], 2150 NoItinerary>; 2151 2152def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>; 2153def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>; 2154def FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>; 2155def FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>; 2156 2157def FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>; 2158def FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>; 2159def FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>; 2160def FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>; 2161 2162//===----------------------------------------------------------------------===// 2163// Floating-point <-> fixed-point conversion instructions 2164//===----------------------------------------------------------------------===// 2165// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2166 2167// #1-#32 allowed, encoded as "64 - <specified imm> 2168def fixedpos_asmoperand_i32 : AsmOperandClass { 2169 let Name = "CVTFixedPos32"; 2170 let RenderMethod = "addCVTFixedPosOperands"; 2171 let PredicateMethod = "isCVTFixedPos<32>"; 2172 let DiagnosticType = "CVTFixedPos32"; 2173} 2174 2175// Also encoded as "64 - <specified imm>" but #1-#64 allowed. 2176def fixedpos_asmoperand_i64 : AsmOperandClass { 2177 let Name = "CVTFixedPos64"; 2178 let RenderMethod = "addCVTFixedPosOperands"; 2179 let PredicateMethod = "isCVTFixedPos<64>"; 2180 let DiagnosticType = "CVTFixedPos64"; 2181} 2182 2183// We need the cartesian product of f32/f64 i32/i64 operands for 2184// conversions: 2185// + Selection needs to use operands of correct floating type 2186// + Assembly parsing and decoding depend on integer width 2187class cvtfix_i32_op<ValueType FloatVT> 2188 : Operand<FloatVT>, 2189 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> { 2190 let ParserMatchClass = fixedpos_asmoperand_i32; 2191 let DecoderMethod = "DecodeCVT32FixedPosOperand"; 2192 let PrintMethod = "printCVTFixedPosOperand"; 2193} 2194 2195class cvtfix_i64_op<ValueType FloatVT> 2196 : Operand<FloatVT>, 2197 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> { 2198 let ParserMatchClass = fixedpos_asmoperand_i64; 2199 let PrintMethod = "printCVTFixedPosOperand"; 2200} 2201 2202// Because of the proliferation of weird operands, it's not really 2203// worth going for a multiclass here. Oh well. 2204 2205class A64I_fptofix<bit sf, bits<2> type, bits<3> opcode, 2206 RegisterClass GPR, RegisterClass FPR, 2207 ValueType DstTy, ValueType SrcTy, 2208 Operand scale_op, string asmop, SDNode cvtop> 2209 : A64I_fpfixed<sf, 0b0, type, 0b11, opcode, 2210 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale), 2211 !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2212 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))], 2213 NoItinerary>; 2214 2215def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32, 2216 cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>; 2217def FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32, 2218 cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>; 2219def FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32, 2220 cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>; 2221def FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32, 2222 cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>; 2223 2224def FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64, 2225 cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>; 2226def FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64, 2227 cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>; 2228def FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64, 2229 cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>; 2230def FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64, 2231 cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>; 2232 2233 2234class A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode, 2235 RegisterClass FPR, RegisterClass GPR, 2236 ValueType DstTy, ValueType SrcTy, 2237 Operand scale_op, string asmop, SDNode cvtop> 2238 : A64I_fpfixed<sf, 0b0, type, 0b00, opcode, 2239 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale), 2240 !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2241 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))], 2242 NoItinerary>; 2243 2244def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32, 2245 cvtfix_i32_op<f32>, "scvtf", sint_to_fp>; 2246def SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64, 2247 cvtfix_i64_op<f32>, "scvtf", sint_to_fp>; 2248def UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32, 2249 cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>; 2250def UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64, 2251 cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>; 2252def SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32, 2253 cvtfix_i32_op<f64>, "scvtf", sint_to_fp>; 2254def SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64, 2255 cvtfix_i64_op<f64>, "scvtf", sint_to_fp>; 2256def UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32, 2257 cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>; 2258def UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64, 2259 cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>; 2260 2261//===----------------------------------------------------------------------===// 2262// Floating-point <-> integer conversion instructions 2263//===----------------------------------------------------------------------===// 2264// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2265 2266class A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode, 2267 RegisterClass DestPR, RegisterClass SrcPR, string asmop> 2268 : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn), 2269 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>; 2270 2271multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> { 2272 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0}, 2273 GPR32, FPR32, asmop # "s">; 2274 def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0}, 2275 GPR64, FPR32, asmop # "s">; 2276 def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1}, 2277 GPR32, FPR32, asmop # "u">; 2278 def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1}, 2279 GPR64, FPR32, asmop # "u">; 2280 2281 def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0}, 2282 GPR32, FPR64, asmop # "s">; 2283 def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0}, 2284 GPR64, FPR64, asmop # "s">; 2285 def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1}, 2286 GPR32, FPR64, asmop # "u">; 2287 def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1}, 2288 GPR64, FPR64, asmop # "u">; 2289} 2290 2291defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">; 2292defm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">; 2293defm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">; 2294defm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">; 2295defm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">; 2296 2297def : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>; 2298def : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>; 2299def : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>; 2300def : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>; 2301def : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>; 2302def : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>; 2303def : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>; 2304def : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>; 2305 2306multiclass A64I_inttofp<bit o0, string asmop> { 2307 def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>; 2308 def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>; 2309 def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>; 2310 def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>; 2311} 2312 2313defm S : A64I_inttofp<0b0, "scvtf">; 2314defm U : A64I_inttofp<0b1, "ucvtf">; 2315 2316def : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>; 2317def : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>; 2318def : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>; 2319def : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>; 2320def : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>; 2321def : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>; 2322def : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>; 2323def : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>; 2324 2325def FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">; 2326def FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">; 2327def FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">; 2328def FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">; 2329 2330def : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>; 2331def : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>; 2332def : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>; 2333def : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>; 2334 2335def lane1_asmoperand : AsmOperandClass { 2336 let Name = "Lane1"; 2337 let RenderMethod = "addImmOperands"; 2338 let DiagnosticType = "Lane1"; 2339} 2340 2341def lane1 : Operand<i32> { 2342 let ParserMatchClass = lane1_asmoperand; 2343 let PrintMethod = "printBareImmOperand"; 2344} 2345 2346let DecoderMethod = "DecodeFMOVLaneInstruction" in { 2347 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110, 2348 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane), 2349 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>; 2350 2351 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111, 2352 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane), 2353 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>; 2354} 2355 2356def : InstAlias<"fmov $Rd, $Rn.2d[$Lane]", 2357 (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>; 2358 2359def : InstAlias<"fmov $Rd.2d[$Lane], $Rn", 2360 (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>; 2361 2362//===----------------------------------------------------------------------===// 2363// Floating-point immediate instructions 2364//===----------------------------------------------------------------------===// 2365// Contains: FMOV 2366 2367def fpimm_asmoperand : AsmOperandClass { 2368 let Name = "FMOVImm"; 2369 let ParserMethod = "ParseFPImmOperand"; 2370 let DiagnosticType = "FPImm"; 2371} 2372 2373// The MCOperand for these instructions are the encoded 8-bit values. 2374def SDXF_fpimm : SDNodeXForm<fpimm, [{ 2375 uint32_t Imm8; 2376 A64Imms::isFPImm(N->getValueAPF(), Imm8); 2377 return CurDAG->getTargetConstant(Imm8, MVT::i32); 2378}]>; 2379 2380class fmov_operand<ValueType FT> 2381 : Operand<i32>, 2382 PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }], 2383 SDXF_fpimm> { 2384 let PrintMethod = "printFPImmOperand"; 2385 let ParserMatchClass = fpimm_asmoperand; 2386} 2387 2388def fmov32_operand : fmov_operand<f32>; 2389def fmov64_operand : fmov_operand<f64>; 2390 2391class A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT, 2392 Operand fmov_operand> 2393 : A64I_fpimm<0b0, 0b0, type, 0b00000, 2394 (outs Reg:$Rd), 2395 (ins fmov_operand:$Imm8), 2396 "fmov\t$Rd, $Imm8", 2397 [(set VT:$Rd, fmov_operand:$Imm8)], 2398 NoItinerary>; 2399 2400def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>; 2401def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>; 2402 2403//===----------------------------------------------------------------------===// 2404// Load-register (literal) instructions 2405//===----------------------------------------------------------------------===// 2406// Contains: LDR, LDRSW, PRFM 2407 2408def ldrlit_label_asmoperand : AsmOperandClass { 2409 let Name = "LoadLitLabel"; 2410 let RenderMethod = "addLabelOperands<19, 4>"; 2411 let DiagnosticType = "Label"; 2412} 2413 2414def ldrlit_label : Operand<i64> { 2415 let EncoderMethod = "getLoadLitLabelOpValue"; 2416 2417 // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 2418 let PrintMethod = "printLabelOperand<19, 4>"; 2419 let ParserMatchClass = ldrlit_label_asmoperand; 2420 let OperandType = "OPERAND_PCREL"; 2421} 2422 2423// Various instructions take an immediate value (which can always be used), 2424// where some numbers have a symbolic name to make things easier. These operands 2425// and the associated functions abstract away the differences. 2426multiclass namedimm<string prefix, string mapper> { 2427 def _asmoperand : AsmOperandClass { 2428 let Name = "NamedImm" # prefix; 2429 let PredicateMethod = "isUImm"; 2430 let RenderMethod = "addImmOperands"; 2431 let ParserMethod = "ParseNamedImmOperand<" # mapper # ">"; 2432 let DiagnosticType = "NamedImm_" # prefix; 2433 } 2434 2435 def _op : Operand<i32> { 2436 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 2437 let PrintMethod = "printNamedImmOperand<" # mapper # ">"; 2438 let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">"; 2439 } 2440} 2441 2442defm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">; 2443 2444class A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg, 2445 list<dag> patterns = []> 2446 : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19), 2447 "ldr\t$Rt, $Imm19", patterns, NoItinerary>; 2448 2449let mayLoad = 1 in { 2450 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>; 2451 def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>; 2452} 2453 2454def LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>; 2455def LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>; 2456 2457let mayLoad = 1 in { 2458 def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>; 2459 2460 2461 def LDRSWx_lit : A64I_LDRlit<0b10, 0b0, 2462 (outs GPR64:$Rt), 2463 (ins ldrlit_label:$Imm19), 2464 "ldrsw\t$Rt, $Imm19", 2465 [], NoItinerary>; 2466 2467 def PRFM_lit : A64I_LDRlit<0b11, 0b0, 2468 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19), 2469 "prfm\t$Rt, $Imm19", 2470 [], NoItinerary>; 2471} 2472 2473//===----------------------------------------------------------------------===// 2474// Load-store exclusive instructions 2475//===----------------------------------------------------------------------===// 2476// Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB, 2477// STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB, 2478// STLRH, STLR, LDARB, LDARH, LDAR 2479 2480// Since these instructions have the undefined register bits set to 1 in 2481// their canonical form, we need a post encoder method to set those bits 2482// to 1 when encoding these instructions. We do this using the 2483// fixLoadStoreExclusive function. This function has template parameters: 2484// 2485// fixLoadStoreExclusive<int hasRs, int hasRt2> 2486// 2487// hasRs indicates that the instruction uses the Rs field, so we won't set 2488// it to 1 (and the same for Rt2). We don't need template parameters for 2489// the other register fiels since Rt and Rn are always used. 2490 2491// This operand parses a GPR64xsp register, followed by an optional immediate 2492// #0. 2493def GPR64xsp0_asmoperand : AsmOperandClass { 2494 let Name = "GPR64xsp0"; 2495 let PredicateMethod = "isWrappedReg"; 2496 let RenderMethod = "addRegOperands"; 2497 let ParserMethod = "ParseLSXAddressOperand"; 2498 // Diagnostics are provided by ParserMethod 2499} 2500 2501def GPR64xsp0 : RegisterOperand<GPR64xsp> { 2502 let ParserMatchClass = GPR64xsp0_asmoperand; 2503} 2504 2505//===---------------------------------- 2506// Store-exclusive (releasing & normal) 2507//===---------------------------------- 2508 2509class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2510 dag ins, list<dag> pat, 2511 InstrItinClass itin> : 2512 A64I_LDSTex_stn <size, 2513 opcode{2}, 0, opcode{1}, opcode{0}, 2514 outs, ins, 2515 !strconcat(asm, "\t$Rs, $Rt, [$Rn]"), 2516 pat, itin> { 2517 let mayStore = 1; 2518 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; 2519} 2520 2521multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { 2522 def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2523 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2524 [], NoItinerary>; 2525 2526 def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2527 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2528 [],NoItinerary>; 2529 2530 def _word: A64I_SRexs_impl<0b10, opcode, asmstr, 2531 (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2532 [], NoItinerary>; 2533 2534 def _dword: A64I_SRexs_impl<0b11, opcode, asmstr, 2535 (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2536 [], NoItinerary>; 2537} 2538 2539defm STXR : A64I_SRex<"stxr", 0b000, "STXR">; 2540defm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">; 2541 2542//===---------------------------------- 2543// Loads 2544//===---------------------------------- 2545 2546class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2547 dag ins, list<dag> pat, 2548 InstrItinClass itin> : 2549 A64I_LDSTex_tn <size, 2550 opcode{2}, 1, opcode{1}, opcode{0}, 2551 outs, ins, 2552 !strconcat(asm, "\t$Rt, [$Rn]"), 2553 pat, itin> { 2554 let mayLoad = 1; 2555 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2556} 2557 2558multiclass A64I_LRex<string asmstr, bits<3> opcode> { 2559 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2560 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2561 [], NoItinerary>; 2562 2563 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2564 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2565 [], NoItinerary>; 2566 2567 def _word: A64I_LRexs_impl<0b10, opcode, asmstr, 2568 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2569 [], NoItinerary>; 2570 2571 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr, 2572 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn), 2573 [], NoItinerary>; 2574} 2575 2576defm LDXR : A64I_LRex<"ldxr", 0b000>; 2577defm LDAXR : A64I_LRex<"ldaxr", 0b001>; 2578defm LDAR : A64I_LRex<"ldar", 0b101>; 2579 2580class acquiring_load<PatFrag base> 2581 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 2582 return cast<AtomicSDNode>(N)->getOrdering() == Acquire; 2583}]>; 2584 2585def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 2586def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 2587def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 2588def atomic_load_acquire_64 : acquiring_load<atomic_load_64>; 2589 2590def : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>; 2591def : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>; 2592def : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>; 2593def : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>; 2594 2595//===---------------------------------- 2596// Store-release (no exclusivity) 2597//===---------------------------------- 2598 2599class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2600 dag ins, list<dag> pat, 2601 InstrItinClass itin> : 2602 A64I_LDSTex_tn <size, 2603 opcode{2}, 0, opcode{1}, opcode{0}, 2604 outs, ins, 2605 !strconcat(asm, "\t$Rt, [$Rn]"), 2606 pat, itin> { 2607 let mayStore = 1; 2608 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2609} 2610 2611class releasing_store<PatFrag base> 2612 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 2613 return cast<AtomicSDNode>(N)->getOrdering() == Release; 2614}]>; 2615 2616def atomic_store_release_8 : releasing_store<atomic_store_8>; 2617def atomic_store_release_16 : releasing_store<atomic_store_16>; 2618def atomic_store_release_32 : releasing_store<atomic_store_32>; 2619def atomic_store_release_64 : releasing_store<atomic_store_64>; 2620 2621multiclass A64I_SLex<string asmstr, bits<3> opcode, string prefix> { 2622 def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2623 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2624 [(atomic_store_release_8 i64:$Rn, i32:$Rt)], 2625 NoItinerary>; 2626 2627 def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2628 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2629 [(atomic_store_release_16 i64:$Rn, i32:$Rt)], 2630 NoItinerary>; 2631 2632 def _word: A64I_SLexs_impl<0b10, opcode, asmstr, 2633 (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2634 [(atomic_store_release_32 i64:$Rn, i32:$Rt)], 2635 NoItinerary>; 2636 2637 def _dword: A64I_SLexs_impl<0b11, opcode, asmstr, 2638 (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2639 [(atomic_store_release_64 i64:$Rn, i64:$Rt)], 2640 NoItinerary>; 2641} 2642 2643defm STLR : A64I_SLex<"stlr", 0b101, "STLR">; 2644 2645//===---------------------------------- 2646// Store-exclusive pair (releasing & normal) 2647//===---------------------------------- 2648 2649class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2650 dag ins, list<dag> pat, 2651 InstrItinClass itin> : 2652 A64I_LDSTex_stt2n <size, 2653 opcode{2}, 0, opcode{1}, opcode{0}, 2654 outs, ins, 2655 !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"), 2656 pat, itin> { 2657 let mayStore = 1; 2658} 2659 2660 2661multiclass A64I_SPex<string asmstr, bits<3> opcode> { 2662 def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs), 2663 (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2, 2664 GPR64xsp0:$Rn), 2665 [], NoItinerary>; 2666 2667 def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs), 2668 (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2, 2669 GPR64xsp0:$Rn), 2670 [], NoItinerary>; 2671} 2672 2673defm STXP : A64I_SPex<"stxp", 0b010>; 2674defm STLXP : A64I_SPex<"stlxp", 0b011>; 2675 2676//===---------------------------------- 2677// Load-exclusive pair (acquiring & normal) 2678//===---------------------------------- 2679 2680class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2681 dag ins, list<dag> pat, 2682 InstrItinClass itin> : 2683 A64I_LDSTex_tt2n <size, 2684 opcode{2}, 1, opcode{1}, opcode{0}, 2685 outs, ins, 2686 !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"), 2687 pat, itin>{ 2688 let mayLoad = 1; 2689 let DecoderMethod = "DecodeLoadPairExclusiveInstruction"; 2690 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; 2691} 2692 2693multiclass A64I_LPex<string asmstr, bits<3> opcode> { 2694 def _word: A64I_LPexs_impl<0b10, opcode, asmstr, 2695 (outs GPR32:$Rt, GPR32:$Rt2), 2696 (ins GPR64xsp0:$Rn), 2697 [], NoItinerary>; 2698 2699 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr, 2700 (outs GPR64:$Rt, GPR64:$Rt2), 2701 (ins GPR64xsp0:$Rn), 2702 [], NoItinerary>; 2703} 2704 2705defm LDXP : A64I_LPex<"ldxp", 0b010>; 2706defm LDAXP : A64I_LPex<"ldaxp", 0b011>; 2707 2708//===----------------------------------------------------------------------===// 2709// Load-store register (unscaled immediate) instructions 2710//===----------------------------------------------------------------------===// 2711// Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM 2712// 2713// and 2714// 2715//===----------------------------------------------------------------------===// 2716// Load-store register (register offset) instructions 2717//===----------------------------------------------------------------------===// 2718// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2719// 2720// and 2721// 2722//===----------------------------------------------------------------------===// 2723// Load-store register (unsigned immediate) instructions 2724//===----------------------------------------------------------------------===// 2725// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2726// 2727// and 2728// 2729//===----------------------------------------------------------------------===// 2730// Load-store register (immediate post-indexed) instructions 2731//===----------------------------------------------------------------------===// 2732// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2733// 2734// and 2735// 2736//===----------------------------------------------------------------------===// 2737// Load-store register (immediate pre-indexed) instructions 2738//===----------------------------------------------------------------------===// 2739// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2740 2741// Note that patterns are much later on in a completely separate section (they 2742// need ADRPxi to be defined). 2743 2744//===------------------------------- 2745// 1. Various operands needed 2746//===------------------------------- 2747 2748//===------------------------------- 2749// 1.1 Unsigned 12-bit immediate operands 2750//===------------------------------- 2751// The addressing mode for these instructions consists of an unsigned 12-bit 2752// immediate which is scaled by the size of the memory access. 2753// 2754// We represent this in the MC layer by two operands: 2755// 1. A base register. 2756// 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]" 2757// would have '1' in this field. 2758// This means that separate functions are needed for converting representations 2759// which *are* aware of the intended access size. 2760 2761// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 2762// know the access size via some means. An isolated operand does not have this 2763// information unless told from here, which means we need separate tablegen 2764// Operands for each access size. This multiclass takes care of instantiating 2765// the correct template functions in the rest of the backend. 2766 2767//===------------------------------- 2768// 1.1 Unsigned 12-bit immediate operands 2769//===------------------------------- 2770 2771multiclass offsets_uimm12<int MemSize, string prefix> { 2772 def uimm12_asmoperand : AsmOperandClass { 2773 let Name = "OffsetUImm12_" # MemSize; 2774 let PredicateMethod = "isOffsetUImm12<" # MemSize # ">"; 2775 let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">"; 2776 let DiagnosticType = "LoadStoreUImm12_" # MemSize; 2777 } 2778 2779 // Pattern is really no more than an ImmLeaf, but predicated on MemSize which 2780 // complicates things beyond TableGen's ken. 2781 def uimm12 : Operand<i64>, 2782 ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> { 2783 let ParserMatchClass 2784 = !cast<AsmOperandClass>(prefix # uimm12_asmoperand); 2785 2786 let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">"; 2787 let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">"; 2788 } 2789} 2790 2791defm byte_ : offsets_uimm12<1, "byte_">; 2792defm hword_ : offsets_uimm12<2, "hword_">; 2793defm word_ : offsets_uimm12<4, "word_">; 2794defm dword_ : offsets_uimm12<8, "dword_">; 2795defm qword_ : offsets_uimm12<16, "qword_">; 2796 2797//===------------------------------- 2798// 1.1 Signed 9-bit immediate operands 2799//===------------------------------- 2800 2801// The MCInst is expected to store the bit-wise encoding of the value, 2802// which amounts to lopping off the extended sign bits. 2803def SDXF_simm9 : SDNodeXForm<imm, [{ 2804 return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32); 2805}]>; 2806 2807def simm9_asmoperand : AsmOperandClass { 2808 let Name = "SImm9"; 2809 let PredicateMethod = "isSImm<9>"; 2810 let RenderMethod = "addSImmOperands<9>"; 2811 let DiagnosticType = "LoadStoreSImm9"; 2812} 2813 2814def simm9 : Operand<i64>, 2815 ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }], 2816 SDXF_simm9> { 2817 let PrintMethod = "printOffsetSImm9Operand"; 2818 let ParserMatchClass = simm9_asmoperand; 2819} 2820 2821 2822//===------------------------------- 2823// 1.3 Register offset extensions 2824//===------------------------------- 2825 2826// The assembly-syntax for these addressing-modes is: 2827// [<Xn|SP>, <R><m> {, <extend> {<amount>}}] 2828// 2829// The essential semantics are: 2830// + <amount> is a shift: #<log(transfer size)> or #0 2831// + <R> can be W or X. 2832// + If <R> is W, <extend> can be UXTW or SXTW 2833// + If <R> is X, <extend> can be LSL or SXTX 2834// 2835// The trickiest of those constraints is that Rm can be either GPR32 or GPR64, 2836// which will need separate instructions for LLVM type-consistency. We'll also 2837// need separate operands, of course. 2838multiclass regexts<int MemSize, int RmSize, RegisterClass GPR, 2839 string Rm, string prefix> { 2840 def regext_asmoperand : AsmOperandClass { 2841 let Name = "AddrRegExtend_" # MemSize # "_" # Rm; 2842 let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">"; 2843 let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">"; 2844 let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize; 2845 } 2846 2847 def regext : Operand<i64> { 2848 let PrintMethod 2849 = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">"; 2850 2851 let DecoderMethod = "DecodeAddrRegExtendOperand"; 2852 let ParserMatchClass 2853 = !cast<AsmOperandClass>(prefix # regext_asmoperand); 2854 } 2855} 2856 2857multiclass regexts_wx<int MemSize, string prefix> { 2858 // Rm is an X-register if LSL or SXTX are specified as the shift. 2859 defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">; 2860 2861 // Rm is a W-register if UXTW or SXTW are specified as the shift. 2862 defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">; 2863} 2864 2865defm byte_ : regexts_wx<1, "byte_">; 2866defm hword_ : regexts_wx<2, "hword_">; 2867defm word_ : regexts_wx<4, "word_">; 2868defm dword_ : regexts_wx<8, "dword_">; 2869defm qword_ : regexts_wx<16, "qword_">; 2870 2871 2872//===------------------------------ 2873// 2. The instructions themselves. 2874//===------------------------------ 2875 2876// We have the following instructions to implement: 2877// | | B | H | W | X | 2878// |-----------------+-------+-------+-------+--------| 2879// | unsigned str | STRB | STRH | STR | STR | 2880// | unsigned ldr | LDRB | LDRH | LDR | LDR | 2881// | signed ldr to W | LDRSB | LDRSH | - | - | 2882// | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) | 2883 2884// This will instantiate the LDR/STR instructions you'd expect to use for an 2885// unsigned datatype (first two rows above) or floating-point register, which is 2886// reasonably uniform across all access sizes. 2887 2888 2889//===------------------------------ 2890// 2.1 Regular instructions 2891//===------------------------------ 2892 2893// This class covers the basic unsigned or irrelevantly-signed loads and stores, 2894// to general-purpose and floating-point registers. 2895 2896class AddrParams<string prefix> { 2897 Operand uimm12 = !cast<Operand>(prefix # "_uimm12"); 2898 2899 Operand regextWm = !cast<Operand>(prefix # "_Wm_regext"); 2900 Operand regextXm = !cast<Operand>(prefix # "_Xm_regext"); 2901} 2902 2903def byte_addrparams : AddrParams<"byte">; 2904def hword_addrparams : AddrParams<"hword">; 2905def word_addrparams : AddrParams<"word">; 2906def dword_addrparams : AddrParams<"dword">; 2907def qword_addrparams : AddrParams<"qword">; 2908 2909multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v, 2910 bit high_opc, string asmsuffix, 2911 RegisterClass GPR, AddrParams params> { 2912 // Unsigned immediate 2913 def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0}, 2914 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12), 2915 "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2916 [], NoItinerary> { 2917 let mayStore = 1; 2918 } 2919 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]", 2920 (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2921 2922 def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1}, 2923 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 2924 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2925 [], NoItinerary> { 2926 let mayLoad = 1; 2927 } 2928 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]", 2929 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2930 2931 // Register offset (four of these: load/store and Wm/Xm). 2932 let mayLoad = 1 in { 2933 def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0, 2934 (outs GPR:$Rt), 2935 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 2936 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2937 [], NoItinerary>; 2938 2939 def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1, 2940 (outs GPR:$Rt), 2941 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 2942 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2943 [], NoItinerary>; 2944 } 2945 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]", 2946 (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn, 2947 GPR64:$Rm, 2)>; 2948 2949 let mayStore = 1 in { 2950 def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0, 2951 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm, 2952 params.regextWm:$Ext), 2953 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2954 [], NoItinerary>; 2955 2956 def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1, 2957 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2958 params.regextXm:$Ext), 2959 "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2960 [], NoItinerary>; 2961 } 2962 def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]", 2963 (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn, 2964 GPR64:$Rm, 2)>; 2965 2966 // Unaligned immediate 2967 def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0}, 2968 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 2969 "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 2970 [], NoItinerary> { 2971 let mayStore = 1; 2972 } 2973 def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]", 2974 (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2975 2976 def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1}, 2977 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 2978 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 2979 [], NoItinerary> { 2980 let mayLoad = 1; 2981 } 2982 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]", 2983 (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2984 2985 // Post-indexed 2986 def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0}, 2987 (outs GPR64xsp:$Rn_wb), 2988 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 2989 "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 2990 [], NoItinerary> { 2991 let Constraints = "$Rn = $Rn_wb"; 2992 let mayStore = 1; 2993 2994 // Decoder only needed for unpredictability checking (FIXME). 2995 let DecoderMethod = "DecodeSingleIndexedInstruction"; 2996 } 2997 2998 def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1}, 2999 (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3000 (ins GPR64xsp:$Rn, simm9:$SImm9), 3001 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3002 [], NoItinerary> { 3003 let mayLoad = 1; 3004 let Constraints = "$Rn = $Rn_wb"; 3005 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3006 } 3007 3008 // Pre-indexed 3009 def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0}, 3010 (outs GPR64xsp:$Rn_wb), 3011 (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3012 "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3013 [], NoItinerary> { 3014 let Constraints = "$Rn = $Rn_wb"; 3015 let mayStore = 1; 3016 3017 // Decoder only needed for unpredictability checking (FIXME). 3018 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3019 } 3020 3021 def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1}, 3022 (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3023 (ins GPR64xsp:$Rn, simm9:$SImm9), 3024 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3025 [], NoItinerary> { 3026 let mayLoad = 1; 3027 let Constraints = "$Rn = $Rn_wb"; 3028 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3029 } 3030 3031} 3032 3033// STRB/LDRB: First define the instructions 3034defm LS8 3035 : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>; 3036 3037// STRH/LDRH 3038defm LS16 3039 : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>; 3040 3041 3042// STR/LDR to/from a W register 3043defm LS32 3044 : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>; 3045 3046// STR/LDR to/from an X register 3047defm LS64 3048 : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>; 3049 3050// STR/LDR to/from a B register 3051defm LSFP8 3052 : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>; 3053 3054// STR/LDR to/from an H register 3055defm LSFP16 3056 : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>; 3057 3058// STR/LDR to/from an S register 3059defm LSFP32 3060 : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>; 3061// STR/LDR to/from a D register 3062defm LSFP64 3063 : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>; 3064// STR/LDR to/from a Q register 3065defm LSFP128 3066 : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128, 3067 qword_addrparams>; 3068 3069//===------------------------------ 3070// 2.3 Signed loads 3071//===------------------------------ 3072 3073// Byte and half-word signed loads can both go into either an X or a W register, 3074// so it's worth factoring out. Signed word loads don't fit because there is no 3075// W version. 3076multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params, 3077 string prefix> { 3078 // Unsigned offset 3079 def w : A64I_LSunsigimm<size, 0b0, 0b11, 3080 (outs GPR32:$Rt), 3081 (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3082 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3083 [], NoItinerary> { 3084 let mayLoad = 1; 3085 } 3086 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3087 (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3088 3089 def x : A64I_LSunsigimm<size, 0b0, 0b10, 3090 (outs GPR64:$Rt), 3091 (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3092 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3093 [], NoItinerary> { 3094 let mayLoad = 1; 3095 } 3096 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3097 (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3098 3099 // Register offset 3100 let mayLoad = 1 in { 3101 def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0, 3102 (outs GPR32:$Rt), 3103 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3104 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3105 [], NoItinerary>; 3106 3107 def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1, 3108 (outs GPR32:$Rt), 3109 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3110 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3111 [], NoItinerary>; 3112 3113 def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0, 3114 (outs GPR64:$Rt), 3115 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3116 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3117 [], NoItinerary>; 3118 3119 def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1, 3120 (outs GPR64:$Rt), 3121 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3122 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3123 [], NoItinerary>; 3124 } 3125 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3126 (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn, 3127 GPR64:$Rm, 2)>; 3128 3129 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3130 (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn, 3131 GPR64:$Rm, 2)>; 3132 3133 3134 let mayLoad = 1 in { 3135 // Unaligned offset 3136 def w_U : A64I_LSunalimm<size, 0b0, 0b11, 3137 (outs GPR32:$Rt), 3138 (ins GPR64xsp:$Rn, simm9:$SImm9), 3139 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3140 [], NoItinerary>; 3141 3142 def x_U : A64I_LSunalimm<size, 0b0, 0b10, 3143 (outs GPR64:$Rt), 3144 (ins GPR64xsp:$Rn, simm9:$SImm9), 3145 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3146 [], NoItinerary>; 3147 3148 3149 // Post-indexed 3150 def w_PostInd : A64I_LSpostind<size, 0b0, 0b11, 3151 (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3152 (ins GPR64xsp:$Rn, simm9:$SImm9), 3153 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3154 [], NoItinerary> { 3155 let Constraints = "$Rn = $Rn_wb"; 3156 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3157 } 3158 3159 def x_PostInd : A64I_LSpostind<size, 0b0, 0b10, 3160 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3161 (ins GPR64xsp:$Rn, simm9:$SImm9), 3162 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3163 [], NoItinerary> { 3164 let Constraints = "$Rn = $Rn_wb"; 3165 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3166 } 3167 3168 // Pre-indexed 3169 def w_PreInd : A64I_LSpreind<size, 0b0, 0b11, 3170 (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3171 (ins GPR64xsp:$Rn, simm9:$SImm9), 3172 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3173 [], NoItinerary> { 3174 let Constraints = "$Rn = $Rn_wb"; 3175 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3176 } 3177 3178 def x_PreInd : A64I_LSpreind<size, 0b0, 0b10, 3179 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3180 (ins GPR64xsp:$Rn, simm9:$SImm9), 3181 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3182 [], NoItinerary> { 3183 let Constraints = "$Rn = $Rn_wb"; 3184 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3185 } 3186 } // let mayLoad = 1 3187} 3188 3189// LDRSB 3190defm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">; 3191// LDRSH 3192defm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">; 3193 3194// LDRSW: load a 32-bit register, sign-extending to 64-bits. 3195def LDRSWx 3196 : A64I_LSunsigimm<0b10, 0b0, 0b10, 3197 (outs GPR64:$Rt), 3198 (ins GPR64xsp:$Rn, word_uimm12:$UImm12), 3199 "ldrsw\t$Rt, [$Rn, $UImm12]", 3200 [], NoItinerary> { 3201 let mayLoad = 1; 3202} 3203def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3204 3205let mayLoad = 1 in { 3206 def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0, 3207 (outs GPR64:$Rt), 3208 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext), 3209 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3210 [], NoItinerary>; 3211 3212 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1, 3213 (outs GPR64:$Rt), 3214 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext), 3215 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3216 [], NoItinerary>; 3217} 3218def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]", 3219 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>; 3220 3221 3222def LDURSWx 3223 : A64I_LSunalimm<0b10, 0b0, 0b10, 3224 (outs GPR64:$Rt), 3225 (ins GPR64xsp:$Rn, simm9:$SImm9), 3226 "ldursw\t$Rt, [$Rn, $SImm9]", 3227 [], NoItinerary> { 3228 let mayLoad = 1; 3229} 3230def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3231 3232def LDRSWx_PostInd 3233 : A64I_LSpostind<0b10, 0b0, 0b10, 3234 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3235 (ins GPR64xsp:$Rn, simm9:$SImm9), 3236 "ldrsw\t$Rt, [$Rn], $SImm9", 3237 [], NoItinerary> { 3238 let mayLoad = 1; 3239 let Constraints = "$Rn = $Rn_wb"; 3240 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3241} 3242 3243def LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10, 3244 (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3245 (ins GPR64xsp:$Rn, simm9:$SImm9), 3246 "ldrsw\t$Rt, [$Rn, $SImm9]!", 3247 [], NoItinerary> { 3248 let mayLoad = 1; 3249 let Constraints = "$Rn = $Rn_wb"; 3250 let DecoderMethod = "DecodeSingleIndexedInstruction"; 3251} 3252 3253//===------------------------------ 3254// 2.4 Prefetch operations 3255//===------------------------------ 3256 3257def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs), 3258 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12), 3259 "prfm\t$Rt, [$Rn, $UImm12]", 3260 [], NoItinerary> { 3261 let mayLoad = 1; 3262} 3263def : InstAlias<"prfm $Rt, [$Rn]", 3264 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3265 3266let mayLoad = 1 in { 3267 def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs), 3268 (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3269 GPR32:$Rm, dword_Wm_regext:$Ext), 3270 "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3271 [], NoItinerary>; 3272 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs), 3273 (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3274 GPR64:$Rm, dword_Xm_regext:$Ext), 3275 "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3276 [], NoItinerary>; 3277} 3278 3279def : InstAlias<"prfm $Rt, [$Rn, $Rm]", 3280 (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn, 3281 GPR64:$Rm, 2)>; 3282 3283 3284def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs), 3285 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3286 "prfum\t$Rt, [$Rn, $SImm9]", 3287 [], NoItinerary> { 3288 let mayLoad = 1; 3289} 3290def : InstAlias<"prfum $Rt, [$Rn]", 3291 (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3292 3293//===----------------------------------------------------------------------===// 3294// Load-store register (unprivileged) instructions 3295//===----------------------------------------------------------------------===// 3296// Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH 3297 3298// These instructions very much mirror the "unscaled immediate" loads, but since 3299// there are no floating-point variants we need to split them out into their own 3300// section to avoid instantiation of "ldtr d0, [sp]" etc. 3301 3302multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR, 3303 string prefix> { 3304 def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00, 3305 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3306 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3307 [], NoItinerary> { 3308 let mayStore = 1; 3309 } 3310 3311 def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]", 3312 (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3313 3314 def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01, 3315 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 3316 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3317 [], NoItinerary> { 3318 let mayLoad = 1; 3319 } 3320 3321 def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]", 3322 (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3323 3324} 3325 3326// STTRB/LDTRB: First define the instructions 3327defm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">; 3328 3329// STTRH/LDTRH 3330defm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">; 3331 3332// STTR/LDTR to/from a W register 3333defm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">; 3334 3335// STTR/LDTR to/from an X register 3336defm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">; 3337 3338// Now a class for the signed instructions that can go to either 32 or 64 3339// bits... 3340multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> { 3341 let mayLoad = 1 in { 3342 def w : A64I_LSunpriv<size, 0b0, 0b11, 3343 (outs GPR32:$Rt), 3344 (ins GPR64xsp:$Rn, simm9:$SImm9), 3345 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3346 [], NoItinerary>; 3347 3348 def x : A64I_LSunpriv<size, 0b0, 0b10, 3349 (outs GPR64:$Rt), 3350 (ins GPR64xsp:$Rn, simm9:$SImm9), 3351 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3352 [], NoItinerary>; 3353 } 3354 3355 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3356 (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3357 3358 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3359 (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3360 3361} 3362 3363// LDTRSB 3364defm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">; 3365// LDTRSH 3366defm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">; 3367 3368// And finally LDTRSW which only goes to 64 bits. 3369def LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10, 3370 (outs GPR64:$Rt), 3371 (ins GPR64xsp:$Rn, simm9:$SImm9), 3372 "ldtrsw\t$Rt, [$Rn, $SImm9]", 3373 [], NoItinerary> { 3374 let mayLoad = 1; 3375} 3376def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3377 3378//===----------------------------------------------------------------------===// 3379// Load-store register pair (offset) instructions 3380//===----------------------------------------------------------------------===// 3381// 3382// and 3383// 3384//===----------------------------------------------------------------------===// 3385// Load-store register pair (post-indexed) instructions 3386//===----------------------------------------------------------------------===// 3387// Contains: STP, LDP, LDPSW 3388// 3389// and 3390// 3391//===----------------------------------------------------------------------===// 3392// Load-store register pair (pre-indexed) instructions 3393//===----------------------------------------------------------------------===// 3394// Contains: STP, LDP, LDPSW 3395// 3396// and 3397// 3398//===----------------------------------------------------------------------===// 3399// Load-store non-temporal register pair (offset) instructions 3400//===----------------------------------------------------------------------===// 3401// Contains: STNP, LDNP 3402 3403 3404// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 3405// know the access size via some means. An isolated operand does not have this 3406// information unless told from here, which means we need separate tablegen 3407// Operands for each access size. This multiclass takes care of instantiating 3408// the correct template functions in the rest of the backend. 3409 3410multiclass offsets_simm7<string MemSize, string prefix> { 3411 // The bare signed 7-bit immediate is used in post-indexed instructions, but 3412 // because of the scaling performed a generic "simm7" operand isn't 3413 // appropriate here either. 3414 def simm7_asmoperand : AsmOperandClass { 3415 let Name = "SImm7_Scaled" # MemSize; 3416 let PredicateMethod = "isSImm7Scaled<" # MemSize # ">"; 3417 let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">"; 3418 let DiagnosticType = "LoadStoreSImm7_" # MemSize; 3419 } 3420 3421 def simm7 : Operand<i64> { 3422 let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">"; 3423 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand"); 3424 } 3425} 3426 3427defm word_ : offsets_simm7<"4", "word_">; 3428defm dword_ : offsets_simm7<"8", "dword_">; 3429defm qword_ : offsets_simm7<"16", "qword_">; 3430 3431multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg, 3432 Operand simm7, string prefix> { 3433 def _STR : A64I_LSPoffset<opc, v, 0b0, (outs), 3434 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3435 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3436 let mayStore = 1; 3437 let DecoderMethod = "DecodeLDSTPairInstruction"; 3438 } 3439 def : InstAlias<"stp $Rt, $Rt2, [$Rn]", 3440 (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt, 3441 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3442 3443 def _LDR : A64I_LSPoffset<opc, v, 0b1, 3444 (outs SomeReg:$Rt, SomeReg:$Rt2), 3445 (ins GPR64xsp:$Rn, simm7:$SImm7), 3446 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3447 let mayLoad = 1; 3448 let DecoderMethod = "DecodeLDSTPairInstruction"; 3449 } 3450 def : InstAlias<"ldp $Rt, $Rt2, [$Rn]", 3451 (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt, 3452 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3453 3454 def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0, 3455 (outs GPR64xsp:$Rn_wb), 3456 (ins SomeReg:$Rt, SomeReg:$Rt2, 3457 GPR64xsp:$Rn, 3458 simm7:$SImm7), 3459 "stp\t$Rt, $Rt2, [$Rn], $SImm7", 3460 [], NoItinerary> { 3461 let mayStore = 1; 3462 let Constraints = "$Rn = $Rn_wb"; 3463 3464 // Decoder only needed for unpredictability checking (FIXME). 3465 let DecoderMethod = "DecodeLDSTPairInstruction"; 3466 } 3467 3468 def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1, 3469 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3470 (ins GPR64xsp:$Rn, simm7:$SImm7), 3471 "ldp\t$Rt, $Rt2, [$Rn], $SImm7", 3472 [], NoItinerary> { 3473 let mayLoad = 1; 3474 let Constraints = "$Rn = $Rn_wb"; 3475 let DecoderMethod = "DecodeLDSTPairInstruction"; 3476 } 3477 3478 def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb), 3479 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3480 "stp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3481 [], NoItinerary> { 3482 let mayStore = 1; 3483 let Constraints = "$Rn = $Rn_wb"; 3484 let DecoderMethod = "DecodeLDSTPairInstruction"; 3485 } 3486 3487 def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1, 3488 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3489 (ins GPR64xsp:$Rn, simm7:$SImm7), 3490 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3491 [], NoItinerary> { 3492 let mayLoad = 1; 3493 let Constraints = "$Rn = $Rn_wb"; 3494 let DecoderMethod = "DecodeLDSTPairInstruction"; 3495 } 3496 3497 def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs), 3498 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3499 "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3500 let mayStore = 1; 3501 let DecoderMethod = "DecodeLDSTPairInstruction"; 3502 } 3503 def : InstAlias<"stnp $Rt, $Rt2, [$Rn]", 3504 (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt, 3505 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3506 3507 def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1, 3508 (outs SomeReg:$Rt, SomeReg:$Rt2), 3509 (ins GPR64xsp:$Rn, simm7:$SImm7), 3510 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3511 let mayLoad = 1; 3512 let DecoderMethod = "DecodeLDSTPairInstruction"; 3513 } 3514 def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]", 3515 (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt, 3516 SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3517 3518} 3519 3520 3521defm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">; 3522defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">; 3523defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">; 3524defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">; 3525defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7, 3526 "LSFPPair128">; 3527 3528 3529def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1, 3530 (outs GPR64:$Rt, GPR64:$Rt2), 3531 (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3532 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3533 let mayLoad = 1; 3534 let DecoderMethod = "DecodeLDSTPairInstruction"; 3535} 3536def : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]", 3537 (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>; 3538 3539def LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1, 3540 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3541 (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3542 "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7", 3543 [], NoItinerary> { 3544 let mayLoad = 1; 3545 let Constraints = "$Rn = $Rn_wb"; 3546 let DecoderMethod = "DecodeLDSTPairInstruction"; 3547} 3548 3549def LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1, 3550 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3551 (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3552 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!", 3553 [], NoItinerary> { 3554 let mayLoad = 1; 3555 let Constraints = "$Rn = $Rn_wb"; 3556 let DecoderMethod = "DecodeLDSTPairInstruction"; 3557} 3558 3559//===----------------------------------------------------------------------===// 3560// Logical (immediate) instructions 3561//===----------------------------------------------------------------------===// 3562// Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV 3563 3564multiclass logical_imm_operands<string prefix, string note, 3565 int size, ValueType VT> { 3566 def _asmoperand : AsmOperandClass { 3567 let Name = "LogicalImm" # note # size; 3568 let PredicateMethod = "isLogicalImm" # note # "<" # size # ">"; 3569 let RenderMethod = "addLogicalImmOperands<" # size # ">"; 3570 let DiagnosticType = "LogicalSecondSource"; 3571 } 3572 3573 def _operand 3574 : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> { 3575 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 3576 let PrintMethod = "printLogicalImmOperand<" # size # ">"; 3577 let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">"; 3578 } 3579} 3580 3581defm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>; 3582defm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>; 3583 3584// The mov versions only differ in assembly parsing, where they 3585// exclude values representable with either MOVZ or MOVN. 3586defm logical_imm32_mov 3587 : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>; 3588defm logical_imm64_mov 3589 : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>; 3590 3591 3592multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> { 3593 def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd), 3594 (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3595 !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3596 [(set i32:$Rd, 3597 (opnode i32:$Rn, logical_imm32_operand:$Imm))], 3598 NoItinerary>; 3599 3600 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd), 3601 (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3602 !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3603 [(set i64:$Rd, 3604 (opnode i64:$Rn, logical_imm64_operand:$Imm))], 3605 NoItinerary>; 3606} 3607 3608defm AND : A64I_logimmSizes<0b00, "and", and>; 3609defm ORR : A64I_logimmSizes<0b01, "orr", or>; 3610defm EOR : A64I_logimmSizes<0b10, "eor", xor>; 3611 3612let Defs = [NZCV] in { 3613 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd), 3614 (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3615 "ands\t$Rd, $Rn, $Imm", 3616 [], NoItinerary>; 3617 3618 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd), 3619 (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3620 "ands\t$Rd, $Rn, $Imm", 3621 [], NoItinerary>; 3622} 3623 3624 3625def : InstAlias<"tst $Rn, $Imm", 3626 (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>; 3627def : InstAlias<"tst $Rn, $Imm", 3628 (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>; 3629def : InstAlias<"mov $Rd, $Imm", 3630 (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>; 3631def : InstAlias<"mov $Rd, $Imm", 3632 (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>; 3633 3634//===----------------------------------------------------------------------===// 3635// Logical (shifted register) instructions 3636//===----------------------------------------------------------------------===// 3637// Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV 3638 3639// Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS" 3640// behaves differently for unsigned comparisons, so we defensively only allow 3641// signed or n/a as the operand. In practice "unsigned greater than 0" is "not 3642// equal to 0" and LLVM gives us this. 3643def signed_cond : PatLeaf<(cond), [{ 3644 return !isUnsignedIntSetCC(N->get()); 3645}]>; 3646 3647 3648// These instructions share their "shift" operands with add/sub (shifted 3649// register instructions). They are defined there. 3650 3651// N.b. the commutable parameter is just !N. It will be first against the wall 3652// when the revolution comes. 3653multiclass logical_shifts<string prefix, bit sf, bits<2> opc, 3654 bit N, bit commutable, 3655 string asmop, SDPatternOperator opfrag, ValueType ty, 3656 RegisterClass GPR, list<Register> defs> { 3657 let isCommutable = commutable, Defs = defs in { 3658 def _lsl : A64I_logicalshift<sf, opc, 0b00, N, 3659 (outs GPR:$Rd), 3660 (ins GPR:$Rn, GPR:$Rm, 3661 !cast<Operand>("lsl_operand_" # ty):$Imm6), 3662 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3663 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 3664 !cast<Operand>("lsl_operand_" # ty):$Imm6)) 3665 )], 3666 NoItinerary>; 3667 3668 def _lsr : A64I_logicalshift<sf, opc, 0b01, N, 3669 (outs GPR:$Rd), 3670 (ins GPR:$Rn, GPR:$Rm, 3671 !cast<Operand>("lsr_operand_" # ty):$Imm6), 3672 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3673 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 3674 !cast<Operand>("lsr_operand_" # ty):$Imm6)) 3675 )], 3676 NoItinerary>; 3677 3678 def _asr : A64I_logicalshift<sf, opc, 0b10, N, 3679 (outs GPR:$Rd), 3680 (ins GPR:$Rn, GPR:$Rm, 3681 !cast<Operand>("asr_operand_" # ty):$Imm6), 3682 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3683 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 3684 !cast<Operand>("asr_operand_" # ty):$Imm6)) 3685 )], 3686 NoItinerary>; 3687 3688 def _ror : A64I_logicalshift<sf, opc, 0b11, N, 3689 (outs GPR:$Rd), 3690 (ins GPR:$Rn, GPR:$Rm, 3691 !cast<Operand>("ror_operand_" # ty):$Imm6), 3692 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3693 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm, 3694 !cast<Operand>("ror_operand_" # ty):$Imm6)) 3695 )], 3696 NoItinerary>; 3697 } 3698 3699 def _noshift 3700 : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 3701 (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 3702 GPR:$Rm, 0)>; 3703 3704 def : Pat<(opfrag ty:$Rn, ty:$Rm), 3705 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3706} 3707 3708multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable, 3709 string asmop, SDPatternOperator opfrag, 3710 list<Register> defs> { 3711 defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N, 3712 commutable, asmop, opfrag, i64, GPR64, defs>; 3713 defm www : logical_shifts<prefix # "www", 0b0, opc, N, 3714 commutable, asmop, opfrag, i32, GPR32, defs>; 3715} 3716 3717 3718defm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>; 3719defm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>; 3720defm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>; 3721defm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands", 3722 PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), 3723 [{ (void)N; return false; }]>, 3724 [NZCV]>; 3725 3726defm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic", 3727 PatFrag<(ops node:$lhs, node:$rhs), 3728 (and node:$lhs, (not node:$rhs))>, []>; 3729defm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn", 3730 PatFrag<(ops node:$lhs, node:$rhs), 3731 (or node:$lhs, (not node:$rhs))>, []>; 3732defm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon", 3733 PatFrag<(ops node:$lhs, node:$rhs), 3734 (xor node:$lhs, (not node:$rhs))>, []>; 3735defm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics", 3736 PatFrag<(ops node:$lhs, node:$rhs), 3737 (and node:$lhs, (not node:$rhs)), 3738 [{ (void)N; return false; }]>, 3739 [NZCV]>; 3740 3741multiclass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3742 let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in { 3743 def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0, 3744 (outs), 3745 (ins GPR:$Rn, GPR:$Rm, 3746 !cast<Operand>("lsl_operand_" # ty):$Imm6), 3747 "tst\t$Rn, $Rm, $Imm6", 3748 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm, 3749 !cast<Operand>("lsl_operand_" # ty):$Imm6)), 3750 0, signed_cond))], 3751 NoItinerary>; 3752 3753 3754 def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0, 3755 (outs), 3756 (ins GPR:$Rn, GPR:$Rm, 3757 !cast<Operand>("lsr_operand_" # ty):$Imm6), 3758 "tst\t$Rn, $Rm, $Imm6", 3759 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm, 3760 !cast<Operand>("lsr_operand_" # ty):$Imm6)), 3761 0, signed_cond))], 3762 NoItinerary>; 3763 3764 def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0, 3765 (outs), 3766 (ins GPR:$Rn, GPR:$Rm, 3767 !cast<Operand>("asr_operand_" # ty):$Imm6), 3768 "tst\t$Rn, $Rm, $Imm6", 3769 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm, 3770 !cast<Operand>("asr_operand_" # ty):$Imm6)), 3771 0, signed_cond))], 3772 NoItinerary>; 3773 3774 def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0, 3775 (outs), 3776 (ins GPR:$Rn, GPR:$Rm, 3777 !cast<Operand>("ror_operand_" # ty):$Imm6), 3778 "tst\t$Rn, $Rm, $Imm6", 3779 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm, 3780 !cast<Operand>("ror_operand_" # ty):$Imm6)), 3781 0, signed_cond))], 3782 NoItinerary>; 3783 } 3784 3785 def _noshift : InstAlias<"tst $Rn, $Rm", 3786 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3787 3788 def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond), 3789 (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3790} 3791 3792defm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>; 3793defm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>; 3794 3795 3796multiclass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3797 let isCommutable = 0, Rn = 0b11111 in { 3798 def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1, 3799 (outs GPR:$Rd), 3800 (ins GPR:$Rm, 3801 !cast<Operand>("lsl_operand_" # ty):$Imm6), 3802 "mvn\t$Rd, $Rm, $Imm6", 3803 [(set ty:$Rd, (not (shl ty:$Rm, 3804 !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3805 NoItinerary>; 3806 3807 3808 def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1, 3809 (outs GPR:$Rd), 3810 (ins GPR:$Rm, 3811 !cast<Operand>("lsr_operand_" # ty):$Imm6), 3812 "mvn\t$Rd, $Rm, $Imm6", 3813 [(set ty:$Rd, (not (srl ty:$Rm, 3814 !cast<Operand>("lsr_operand_" # ty):$Imm6)))], 3815 NoItinerary>; 3816 3817 def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1, 3818 (outs GPR:$Rd), 3819 (ins GPR:$Rm, 3820 !cast<Operand>("asr_operand_" # ty):$Imm6), 3821 "mvn\t$Rd, $Rm, $Imm6", 3822 [(set ty:$Rd, (not (sra ty:$Rm, 3823 !cast<Operand>("asr_operand_" # ty):$Imm6)))], 3824 NoItinerary>; 3825 3826 def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1, 3827 (outs GPR:$Rd), 3828 (ins GPR:$Rm, 3829 !cast<Operand>("ror_operand_" # ty):$Imm6), 3830 "mvn\t$Rd, $Rm, $Imm6", 3831 [(set ty:$Rd, (not (rotr ty:$Rm, 3832 !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3833 NoItinerary>; 3834 } 3835 3836 def _noshift : InstAlias<"mvn $Rn, $Rm", 3837 (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3838 3839 def : Pat<(not ty:$Rm), 3840 (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>; 3841} 3842 3843defm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>; 3844defm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>; 3845 3846def MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 3847def MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 3848 3849//===----------------------------------------------------------------------===// 3850// Move wide (immediate) instructions 3851//===----------------------------------------------------------------------===// 3852// Contains: MOVN, MOVZ, MOVK + MOV aliases 3853 3854// A wide variety of different relocations are needed for variants of these 3855// instructions, so it turns out that we need a different operand for all of 3856// them. 3857multiclass movw_operands<string prefix, string instname, int width> { 3858 def _imm_asmoperand : AsmOperandClass { 3859 let Name = instname # width # "Shifted" # shift; 3860 let PredicateMethod = "is" # instname # width # "Imm"; 3861 let RenderMethod = "addMoveWideImmOperands"; 3862 let ParserMethod = "ParseImmWithLSLOperand"; 3863 let DiagnosticType = "MOVWUImm16"; 3864 } 3865 3866 def _imm : Operand<i32> { 3867 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand"); 3868 let PrintMethod = "printMoveWideImmOperand"; 3869 let EncoderMethod = "getMoveWideImmOpValue"; 3870 let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">"; 3871 3872 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3873 } 3874} 3875 3876defm movn32 : movw_operands<"movn32", "MOVN", 32>; 3877defm movn64 : movw_operands<"movn64", "MOVN", 64>; 3878defm movz32 : movw_operands<"movz32", "MOVZ", 32>; 3879defm movz64 : movw_operands<"movz64", "MOVZ", 64>; 3880defm movk32 : movw_operands<"movk32", "MOVK", 32>; 3881defm movk64 : movw_operands<"movk64", "MOVK", 64>; 3882 3883multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit, 3884 dag ins64bit> { 3885 3886 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit, 3887 !strconcat(asmop, "\t$Rd, $FullImm"), 3888 [], NoItinerary> { 3889 bits<18> FullImm; 3890 let UImm16 = FullImm{15-0}; 3891 let Shift = FullImm{17-16}; 3892 } 3893 3894 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit, 3895 !strconcat(asmop, "\t$Rd, $FullImm"), 3896 [], NoItinerary> { 3897 bits<18> FullImm; 3898 let UImm16 = FullImm{15-0}; 3899 let Shift = FullImm{17-16}; 3900 } 3901} 3902 3903let isMoveImm = 1, isReMaterializable = 1, 3904 isAsCheapAsAMove = 1, hasSideEffects = 0 in { 3905 defm MOVN : A64I_movwSizes<0b00, "movn", 3906 (ins movn32_imm:$FullImm), 3907 (ins movn64_imm:$FullImm)>; 3908 3909 // Some relocations are able to convert between a MOVZ and a MOVN. If these 3910 // are applied the instruction must be emitted with the corresponding bits as 3911 // 0, which means a MOVZ needs to override that bit from the default. 3912 let PostEncoderMethod = "fixMOVZ" in 3913 defm MOVZ : A64I_movwSizes<0b10, "movz", 3914 (ins movz32_imm:$FullImm), 3915 (ins movz64_imm:$FullImm)>; 3916} 3917 3918let Constraints = "$src = $Rd" in 3919defm MOVK : A64I_movwSizes<0b11, "movk", 3920 (ins GPR32:$src, movk32_imm:$FullImm), 3921 (ins GPR64:$src, movk64_imm:$FullImm)>; 3922 3923 3924// And now the "MOV" aliases. These also need their own operands because what 3925// they accept is completely different to what the base instructions accept. 3926multiclass movalias_operand<string prefix, string basename, 3927 string immpredicate, int width> { 3928 def _asmoperand : AsmOperandClass { 3929 let Name = basename # width # "MovAlias"; 3930 let PredicateMethod 3931 = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">"; 3932 let RenderMethod 3933 = "addMoveWideMovAliasOperands<" # width # ", " 3934 # "A64Imms::" # immpredicate # ">"; 3935 } 3936 3937 def _movimm : Operand<i32> { 3938 let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 3939 3940 let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3941 } 3942} 3943 3944defm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>; 3945defm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>; 3946defm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>; 3947defm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>; 3948 3949// FIXME: these are officially canonical aliases, but TableGen is too limited to 3950// print them at the moment. I believe in this case an "AliasPredicate" method 3951// will need to be implemented. to allow it, as well as the more generally 3952// useful handling of non-register, non-constant operands. 3953class movalias<Instruction INST, RegisterClass GPR, Operand operand> 3954 : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>; 3955 3956def : movalias<MOVZwii, GPR32, movz32_movimm>; 3957def : movalias<MOVZxii, GPR64, movz64_movimm>; 3958def : movalias<MOVNwii, GPR32, movn32_movimm>; 3959def : movalias<MOVNxii, GPR64, movn64_movimm>; 3960 3961//===----------------------------------------------------------------------===// 3962// PC-relative addressing instructions 3963//===----------------------------------------------------------------------===// 3964// Contains: ADR, ADRP 3965 3966def adr_label : Operand<i64> { 3967 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>"; 3968 3969 // This label is a 21-bit offset from PC, unscaled 3970 let PrintMethod = "printLabelOperand<21, 1>"; 3971 let ParserMatchClass = label_asmoperand<21, 1>; 3972 let OperandType = "OPERAND_PCREL"; 3973} 3974 3975def adrp_label_asmoperand : AsmOperandClass { 3976 let Name = "AdrpLabel"; 3977 let RenderMethod = "addLabelOperands<21, 4096>"; 3978 let DiagnosticType = "Label"; 3979} 3980 3981def adrp_label : Operand<i64> { 3982 let EncoderMethod = "getAdrpLabelOpValue"; 3983 3984 // This label is a 21-bit offset from PC, scaled by the page-size: 4096. 3985 let PrintMethod = "printLabelOperand<21, 4096>"; 3986 let ParserMatchClass = adrp_label_asmoperand; 3987 let OperandType = "OPERAND_PCREL"; 3988} 3989 3990let hasSideEffects = 0 in { 3991 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label), 3992 "adr\t$Rd, $Label", [], NoItinerary>; 3993 3994 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label), 3995 "adrp\t$Rd, $Label", [], NoItinerary>; 3996} 3997 3998//===----------------------------------------------------------------------===// 3999// System instructions 4000//===----------------------------------------------------------------------===// 4001// Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS 4002// + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL 4003 4004// Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values. 4005def uimm3_asmoperand : AsmOperandClass { 4006 let Name = "UImm3"; 4007 let PredicateMethod = "isUImm<3>"; 4008 let RenderMethod = "addImmOperands"; 4009 let DiagnosticType = "UImm3"; 4010} 4011 4012def uimm3 : Operand<i32> { 4013 let ParserMatchClass = uimm3_asmoperand; 4014} 4015 4016// The HINT alias can accept a simple unsigned 7-bit immediate. 4017def uimm7_asmoperand : AsmOperandClass { 4018 let Name = "UImm7"; 4019 let PredicateMethod = "isUImm<7>"; 4020 let RenderMethod = "addImmOperands"; 4021 let DiagnosticType = "UImm7"; 4022} 4023 4024def uimm7 : Operand<i32> { 4025 let ParserMatchClass = uimm7_asmoperand; 4026} 4027 4028// Multiclass namedimm is defined with the prefetch operands. Most of these fit 4029// into the NamedImmMapper scheme well: they either accept a named operand or 4030// any immediate under a particular value (which may be 0, implying no immediate 4031// is allowed). 4032defm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">; 4033defm isb : namedimm<"isb", "A64ISB::ISBMapper">; 4034defm ic : namedimm<"ic", "A64IC::ICMapper">; 4035defm dc : namedimm<"dc", "A64DC::DCMapper">; 4036defm at : namedimm<"at", "A64AT::ATMapper">; 4037defm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">; 4038 4039// However, MRS and MSR are more complicated for a few reasons: 4040// * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an 4041// implementation-defined effect 4042// * Most registers are shared, but some are read-only or write-only. 4043// * There is a variant of MSR which accepts the same register name (SPSel), 4044// but which would have a different encoding. 4045 4046// In principle these could be resolved in with more complicated subclasses of 4047// NamedImmMapper, however that imposes an overhead on other "named 4048// immediates". Both in concrete terms with virtual tables and in unnecessary 4049// abstraction. 4050 4051// The solution adopted here is to take the MRS/MSR Mappers out of the usual 4052// hierarchy (they're not derived from NamedImmMapper) and to add logic for 4053// their special situation. 4054def mrs_asmoperand : AsmOperandClass { 4055 let Name = "MRS"; 4056 let ParserMethod = "ParseSysRegOperand"; 4057 let DiagnosticType = "MRS"; 4058} 4059 4060def mrs_op : Operand<i32> { 4061 let ParserMatchClass = mrs_asmoperand; 4062 let PrintMethod = "printMRSOperand"; 4063 let DecoderMethod = "DecodeMRSOperand"; 4064} 4065 4066def msr_asmoperand : AsmOperandClass { 4067 let Name = "MSRWithReg"; 4068 4069 // Note that SPSel is valid for both this and the pstate operands, but with 4070 // different immediate encodings. This is why these operands provide a string 4071 // AArch64Operand rather than an immediate. The overlap is small enough that 4072 // it could be resolved with hackery now, but who can say in future? 4073 let ParserMethod = "ParseSysRegOperand"; 4074 let DiagnosticType = "MSR"; 4075} 4076 4077def msr_op : Operand<i32> { 4078 let ParserMatchClass = msr_asmoperand; 4079 let PrintMethod = "printMSROperand"; 4080 let DecoderMethod = "DecodeMSROperand"; 4081} 4082 4083def pstate_asmoperand : AsmOperandClass { 4084 let Name = "MSRPState"; 4085 // See comment above about parser. 4086 let ParserMethod = "ParseSysRegOperand"; 4087 let DiagnosticType = "MSR"; 4088} 4089 4090def pstate_op : Operand<i32> { 4091 let ParserMatchClass = pstate_asmoperand; 4092 let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>"; 4093 let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>"; 4094} 4095 4096// When <CRn> is specified, an assembler should accept something like "C4", not 4097// the usual "#4" immediate. 4098def CRx_asmoperand : AsmOperandClass { 4099 let Name = "CRx"; 4100 let PredicateMethod = "isUImm<4>"; 4101 let RenderMethod = "addImmOperands"; 4102 let ParserMethod = "ParseCRxOperand"; 4103 // Diagnostics are handled in all cases by ParseCRxOperand. 4104} 4105 4106def CRx : Operand<i32> { 4107 let ParserMatchClass = CRx_asmoperand; 4108 let PrintMethod = "printCRxOperand"; 4109} 4110 4111 4112// Finally, we can start defining the instructions. 4113 4114// HINT is straightforward, with a few aliases. 4115def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7", 4116 [], NoItinerary> { 4117 bits<7> UImm7; 4118 let CRm = UImm7{6-3}; 4119 let Op2 = UImm7{2-0}; 4120 4121 let Op0 = 0b00; 4122 let Op1 = 0b011; 4123 let CRn = 0b0010; 4124 let Rt = 0b11111; 4125} 4126 4127def : InstAlias<"nop", (HINTi 0)>; 4128def : InstAlias<"yield", (HINTi 1)>; 4129def : InstAlias<"wfe", (HINTi 2)>; 4130def : InstAlias<"wfi", (HINTi 3)>; 4131def : InstAlias<"sev", (HINTi 4)>; 4132def : InstAlias<"sevl", (HINTi 5)>; 4133 4134// Quite a few instructions then follow a similar pattern of fixing common 4135// fields in the bitpattern, we'll define a helper-class for them. 4136class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2, 4137 Operand operand, string asmop> 4138 : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"), 4139 [], NoItinerary> { 4140 let Op0 = op0; 4141 let Op1 = op1; 4142 let CRn = crn; 4143 let Op2 = op2; 4144 let Rt = 0b11111; 4145} 4146 4147 4148def CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">; 4149def DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">; 4150def DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">; 4151def ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">; 4152 4153def : InstAlias<"clrex", (CLREXi 0b1111)>; 4154def : InstAlias<"isb", (ISBi 0b1111)>; 4155 4156// (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP 4157// configurations at least. 4158def : Pat<(atomic_fence imm, imm), (DMBi 0xb)>; 4159 4160// Any SYS bitpattern can be represented with a complex and opaque "SYS" 4161// instruction. 4162def SYSiccix : A64I_system<0b0, (outs), 4163 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, 4164 uimm3:$Op2, GPR64:$Rt), 4165 "sys\t$Op1, $CRn, $CRm, $Op2, $Rt", 4166 [], NoItinerary> { 4167 let Op0 = 0b01; 4168} 4169 4170// You can skip the Xt argument whether it makes sense or not for the generic 4171// SYS instruction. 4172def : InstAlias<"sys $Op1, $CRn, $CRm, $Op2", 4173 (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>; 4174 4175 4176// But many have aliases, which obviously don't fit into 4177class SYSalias<dag ins, string asmstring> 4178 : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> { 4179 let isAsmParserOnly = 1; 4180 4181 bits<14> SysOp; 4182 let Op0 = 0b01; 4183 let Op1 = SysOp{13-11}; 4184 let CRn = SysOp{10-7}; 4185 let CRm = SysOp{6-3}; 4186 let Op2 = SysOp{2-0}; 4187} 4188 4189def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">; 4190 4191def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> { 4192 let Rt = 0b11111; 4193} 4194 4195def DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">; 4196def ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">; 4197 4198def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">; 4199 4200def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> { 4201 let Rt = 0b11111; 4202} 4203 4204 4205def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt), 4206 (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2), 4207 "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2", 4208 [], NoItinerary> { 4209 let Op0 = 0b01; 4210} 4211 4212// The instructions themselves are rather simple for MSR and MRS. 4213def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt), 4214 "msr\t$SysReg, $Rt", [], NoItinerary> { 4215 bits<16> SysReg; 4216 let Op0 = SysReg{15-14}; 4217 let Op1 = SysReg{13-11}; 4218 let CRn = SysReg{10-7}; 4219 let CRm = SysReg{6-3}; 4220 let Op2 = SysReg{2-0}; 4221} 4222 4223def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg), 4224 "mrs\t$Rt, $SysReg", [], NoItinerary> { 4225 bits<16> SysReg; 4226 let Op0 = SysReg{15-14}; 4227 let Op1 = SysReg{13-11}; 4228 let CRn = SysReg{10-7}; 4229 let CRm = SysReg{6-3}; 4230 let Op2 = SysReg{2-0}; 4231} 4232 4233def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm), 4234 "msr\t$PState, $CRm", [], NoItinerary> { 4235 bits<6> PState; 4236 4237 let Op0 = 0b00; 4238 let Op1 = PState{5-3}; 4239 let CRn = 0b0100; 4240 let Op2 = PState{2-0}; 4241 let Rt = 0b11111; 4242} 4243 4244//===----------------------------------------------------------------------===// 4245// Test & branch (immediate) instructions 4246//===----------------------------------------------------------------------===// 4247// Contains: TBZ, TBNZ 4248 4249// The bit to test is a simple unsigned 6-bit immediate in the X-register 4250// versions. 4251def uimm6 : Operand<i64> { 4252 let ParserMatchClass = uimm6_asmoperand; 4253} 4254 4255def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>; 4256 4257def tbimm_target : Operand<OtherVT> { 4258 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>"; 4259 4260 // This label is a 14-bit offset from PC, scaled by the instruction-width: 4. 4261 let PrintMethod = "printLabelOperand<14, 4>"; 4262 let ParserMatchClass = label_wid14_scal4_asmoperand; 4263 4264 let OperandType = "OPERAND_PCREL"; 4265} 4266 4267def A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>; 4268def A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>; 4269 4270// These instructions correspond to patterns involving "and" with a power of 4271// two, which we need to be able to select. 4272def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">; 4273def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">; 4274 4275let isBranch = 1, isTerminator = 1 in { 4276 def TBZxii : A64I_TBimm<0b0, (outs), 4277 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4278 "tbz\t$Rt, $Imm, $Label", 4279 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4280 A64eq, bb:$Label)], 4281 NoItinerary>; 4282 4283 def TBNZxii : A64I_TBimm<0b1, (outs), 4284 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4285 "tbnz\t$Rt, $Imm, $Label", 4286 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4287 A64ne, bb:$Label)], 4288 NoItinerary>; 4289 4290 4291 // Note, these instructions overlap with the above 64-bit patterns. This is 4292 // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both 4293 // do the same thing and are both permitted assembly. They also both have 4294 // sensible DAG patterns. 4295 def TBZwii : A64I_TBimm<0b0, (outs), 4296 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4297 "tbz\t$Rt, $Imm, $Label", 4298 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4299 A64eq, bb:$Label)], 4300 NoItinerary> { 4301 let Imm{5} = 0b0; 4302 } 4303 4304 def TBNZwii : A64I_TBimm<0b1, (outs), 4305 (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4306 "tbnz\t$Rt, $Imm, $Label", 4307 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4308 A64ne, bb:$Label)], 4309 NoItinerary> { 4310 let Imm{5} = 0b0; 4311 } 4312} 4313 4314//===----------------------------------------------------------------------===// 4315// Unconditional branch (immediate) instructions 4316//===----------------------------------------------------------------------===// 4317// Contains: B, BL 4318 4319def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>; 4320 4321def bimm_target : Operand<OtherVT> { 4322 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>"; 4323 4324 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4325 let PrintMethod = "printLabelOperand<26, 4>"; 4326 let ParserMatchClass = label_wid26_scal4_asmoperand; 4327 4328 let OperandType = "OPERAND_PCREL"; 4329} 4330 4331def blimm_target : Operand<i64> { 4332 let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>"; 4333 4334 // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4335 let PrintMethod = "printLabelOperand<26, 4>"; 4336 let ParserMatchClass = label_wid26_scal4_asmoperand; 4337 4338 let OperandType = "OPERAND_PCREL"; 4339} 4340 4341class A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type> 4342 : A64I_Bimm<op, (outs), (ins lbl_type:$Label), 4343 !strconcat(asmop, "\t$Label"), patterns, 4344 NoItinerary>; 4345 4346let isBranch = 1 in { 4347 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> { 4348 let isTerminator = 1; 4349 let isBarrier = 1; 4350 } 4351 4352 def BLimm : A64I_BimmImpl<0b1, "bl", 4353 [(AArch64Call tglobaladdr:$Label)], blimm_target> { 4354 let isCall = 1; 4355 let Defs = [X30]; 4356 } 4357} 4358 4359def : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>; 4360 4361//===----------------------------------------------------------------------===// 4362// Unconditional branch (register) instructions 4363//===----------------------------------------------------------------------===// 4364// Contains: BR, BLR, RET, ERET, DRP. 4365 4366// Most of the notional opcode fields in the A64I_Breg format are fixed in A64 4367// at the moment. 4368class A64I_BregImpl<bits<4> opc, 4369 dag outs, dag ins, string asmstr, list<dag> patterns, 4370 InstrItinClass itin = NoItinerary> 4371 : A64I_Breg<opc, 0b11111, 0b000000, 0b00000, 4372 outs, ins, asmstr, patterns, itin> { 4373 let isBranch = 1; 4374 let isIndirectBranch = 1; 4375} 4376 4377// Note that these are not marked isCall or isReturn because as far as LLVM is 4378// concerned they're not. "ret" is just another jump unless it has been selected 4379// by LLVM as the function's return. 4380 4381let isBranch = 1 in { 4382 def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn), 4383 "br\t$Rn", [(brind i64:$Rn)]> { 4384 let isBarrier = 1; 4385 let isTerminator = 1; 4386 } 4387 4388 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn), 4389 "blr\t$Rn", [(AArch64Call i64:$Rn)]> { 4390 let isBarrier = 0; 4391 let isCall = 1; 4392 let Defs = [X30]; 4393 } 4394 4395 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn), 4396 "ret\t$Rn", []> { 4397 let isBarrier = 1; 4398 let isTerminator = 1; 4399 let isReturn = 1; 4400 } 4401 4402 // Create a separate pseudo-instruction for codegen to use so that we don't 4403 // flag x30 as used in every function. It'll be restored before the RET by the 4404 // epilogue if it's legitimately used. 4405 def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> { 4406 let isTerminator = 1; 4407 let isBarrier = 1; 4408 let isReturn = 1; 4409 } 4410 4411 def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> { 4412 let Rn = 0b11111; 4413 let isBarrier = 1; 4414 let isTerminator = 1; 4415 let isReturn = 1; 4416 } 4417 4418 def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> { 4419 let Rn = 0b11111; 4420 let isBarrier = 1; 4421 } 4422} 4423 4424def RETAlias : InstAlias<"ret", (RETx X30)>; 4425 4426 4427//===----------------------------------------------------------------------===// 4428// Address generation patterns 4429//===----------------------------------------------------------------------===// 4430 4431// Primary method of address generation for the small/absolute memory model is 4432// an ADRP/ADR pair: 4433// ADRP x0, some_variable 4434// ADD x0, x0, #:lo12:some_variable 4435// 4436// The load/store elision of the ADD is accomplished when selecting 4437// addressing-modes. This just mops up the cases where that doesn't work and we 4438// really need an address in some register. 4439 4440// This wrapper applies a LO12 modifier to the address. Otherwise we could just 4441// use the same address. 4442 4443class ADRP_ADD<SDNode Wrapper, SDNode addrop> 4444 : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)), 4445 (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>; 4446 4447def : ADRP_ADD<A64WrapperSmall, tblockaddress>; 4448def : ADRP_ADD<A64WrapperSmall, texternalsym>; 4449def : ADRP_ADD<A64WrapperSmall, tglobaladdr>; 4450def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>; 4451def : ADRP_ADD<A64WrapperSmall, tjumptable>; 4452 4453//===----------------------------------------------------------------------===// 4454// GOT access patterns 4455//===----------------------------------------------------------------------===// 4456 4457// FIXME: Wibble 4458 4459class GOTLoadSmall<SDNode addrfrag> 4460 : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)), 4461 (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>; 4462 4463def : GOTLoadSmall<texternalsym>; 4464def : GOTLoadSmall<tglobaladdr>; 4465def : GOTLoadSmall<tglobaltlsaddr>; 4466 4467//===----------------------------------------------------------------------===// 4468// Tail call handling 4469//===----------------------------------------------------------------------===// 4470 4471let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in { 4472 def TC_RETURNdi 4473 : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff), 4474 [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>; 4475 4476 def TC_RETURNxi 4477 : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), 4478 [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>; 4479} 4480 4481let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 4482 Uses = [XSP] in { 4483 def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [], 4484 (Bimm bimm_target:$Label)>; 4485 4486 def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [], 4487 (BRx GPR64:$Rd)>; 4488} 4489 4490 4491def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 4492 (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>; 4493 4494//===----------------------------------------------------------------------===// 4495// Thread local storage 4496//===----------------------------------------------------------------------===// 4497 4498// This is a pseudo-instruction representing the ".tlsdesccall" directive in 4499// assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the 4500// current location. It should always be immediately followed by a BLR 4501// instruction, and is intended solely for relaxation by the linker. 4502 4503def : Pat<(A64threadpointer), (MRSxi 0xde82)>; 4504 4505def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> { 4506 let hasSideEffects = 1; 4507} 4508 4509def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var), 4510 [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> { 4511 let isCall = 1; 4512 let Defs = [X30]; 4513} 4514 4515def : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var), 4516 (TLSDESC_BLRx $Rn, texternalsym:$Var)>; 4517 4518//===----------------------------------------------------------------------===// 4519// Bitfield patterns 4520//===----------------------------------------------------------------------===// 4521 4522def bfi32_lsb_to_immr : SDNodeXForm<imm, [{ 4523 return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64); 4524}]>; 4525 4526def bfi64_lsb_to_immr : SDNodeXForm<imm, [{ 4527 return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64); 4528}]>; 4529 4530def bfi_width_to_imms : SDNodeXForm<imm, [{ 4531 return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64); 4532}]>; 4533 4534 4535// The simpler patterns deal with cases where no AND mask is actually needed 4536// (either all bits are used or the low 32 bits are used). 4537let AddedComplexity = 10 in { 4538 4539def : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4540 (BFIxxii $src, $Rn, 4541 (bfi64_lsb_to_immr (i64 imm:$ImmR)), 4542 (bfi_width_to_imms (i64 imm:$ImmS)))>; 4543 4544def : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS), 4545 (BFIwwii $src, $Rn, 4546 (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4547 (bfi_width_to_imms (i64 imm:$ImmS)))>; 4548 4549 4550def : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4551 (i64 4294967295)), 4552 (SUBREG_TO_REG (i64 0), 4553 (BFIwwii (EXTRACT_SUBREG $src, sub_32), 4554 (EXTRACT_SUBREG $Rn, sub_32), 4555 (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4556 (bfi_width_to_imms (i64 imm:$ImmS))), 4557 sub_32)>; 4558 4559} 4560 4561//===----------------------------------------------------------------------===// 4562// Miscellaneous patterns 4563//===----------------------------------------------------------------------===// 4564 4565// Truncation from 64 to 32-bits just involves renaming your register. 4566def : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>; 4567 4568// Similarly, extension where we don't care about the high bits is 4569// just a rename. 4570def : Pat<(i64 (anyext i32:$val)), 4571 (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>; 4572 4573// SELECT instructions providing f128 types need to be handled by a 4574// pseudo-instruction since the eventual code will need to introduce basic 4575// blocks and control flow. 4576def F128CSEL : PseudoInst<(outs FPR128:$Rd), 4577 (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond), 4578 [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> { 4579 let Uses = [NZCV]; 4580 let usesCustomInserter = 1; 4581} 4582 4583//===----------------------------------------------------------------------===// 4584// Load/store patterns 4585//===----------------------------------------------------------------------===// 4586 4587// There are lots of patterns here, because we need to allow at least three 4588// parameters to vary independently. 4589// 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ... 4590// 2. LLVM source: zextloadi8, anyextloadi8, ... 4591// 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ... 4592// 4593// The biggest problem turns out to be the address-generation variable. At the 4594// point of instantiation we need to produce two DAGs, one for the pattern and 4595// one for the instruction. Doing this at the lowest level of classes doesn't 4596// work. 4597// 4598// Consider the simple uimm12 addressing mode, and the desire to match both (add 4599// GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the 4600// instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or 4601// "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this 4602// operation, and PatFrags are for selection not output. 4603// 4604// As a result, the address-generation patterns are the final 4605// instantiations. However, we do still need to vary the operand for the address 4606// further down (At the point we're deciding A64WrapperSmall, we don't know 4607// the memory width of the operation). 4608 4609//===------------------------------ 4610// 1. Basic infrastructural defs 4611//===------------------------------ 4612 4613// First, some simple classes for !foreach and !subst to use: 4614class Decls { 4615 dag pattern; 4616} 4617 4618def decls : Decls; 4619def ALIGN; 4620def INST; 4621def OFFSET; 4622def SHIFT; 4623 4624// You can't use !subst on an actual immediate, but you *can* use it on an 4625// operand record that happens to match a single immediate. So we do. 4626def imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>; 4627def imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>; 4628def imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>; 4629def imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>; 4630def imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>; 4631 4632// If the low bits of a pointer are known to be 0 then an "or" is just as good 4633// as addition for computing an offset. This fragment forwards that check for 4634// TableGen's use. 4635def add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs), 4636[{ 4637 return CurDAG->isBaseWithConstantOffset(SDValue(N, 0)); 4638}]>; 4639 4640// Load/store (unsigned immediate) operations with relocations against global 4641// symbols (for lo12) are only valid if those symbols have correct alignment 4642// (since the immediate offset is divided by the access scale, it can't have a 4643// remainder). 4644// 4645// The guaranteed alignment is provided as part of the WrapperSmall 4646// operation, and checked against one of these. 4647def any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>; 4648def min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>; 4649def min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>; 4650def min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>; 4651def min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>; 4652 4653// "Normal" load/store instructions can be used on atomic operations, provided 4654// the ordering parameter is at most "monotonic". Anything above that needs 4655// special handling with acquire/release instructions. 4656class simple_load<PatFrag base> 4657 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4658 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4659}]>; 4660 4661def atomic_load_simple_i8 : simple_load<atomic_load_8>; 4662def atomic_load_simple_i16 : simple_load<atomic_load_16>; 4663def atomic_load_simple_i32 : simple_load<atomic_load_32>; 4664def atomic_load_simple_i64 : simple_load<atomic_load_64>; 4665 4666class simple_store<PatFrag base> 4667 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4668 return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4669}]>; 4670 4671def atomic_store_simple_i8 : simple_store<atomic_store_8>; 4672def atomic_store_simple_i16 : simple_store<atomic_store_16>; 4673def atomic_store_simple_i32 : simple_store<atomic_store_32>; 4674def atomic_store_simple_i64 : simple_store<atomic_store_64>; 4675 4676//===------------------------------ 4677// 2. UImm12 and SImm9 4678//===------------------------------ 4679 4680// These instructions have two operands providing the address so they can be 4681// treated similarly for most purposes. 4682 4683//===------------------------------ 4684// 2.1 Base patterns covering extend/truncate semantics 4685//===------------------------------ 4686 4687// Atomic patterns can be shared between integer operations of all sizes, a 4688// quick multiclass here allows reuse. 4689multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 4690 dag Offset, dag address, ValueType transty, 4691 ValueType sty> { 4692 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 4693 (LOAD Base, Offset)>; 4694 4695 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 4696 (STORE $Rt, Base, Offset)>; 4697} 4698 4699// Instructions accessing a memory chunk smaller than a register (or, in a 4700// pinch, the same size) have a characteristic set of patterns they want to 4701// match: extending loads and truncating stores. This class deals with the 4702// sign-neutral version of those patterns. 4703// 4704// It will be instantiated across multiple addressing-modes. 4705multiclass ls_small_pats<Instruction LOAD, Instruction STORE, 4706 dag Base, dag Offset, 4707 dag address, ValueType sty> 4708 : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> { 4709 def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>; 4710 4711 def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>; 4712 4713 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 4714 // register was actually set. 4715 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 4716 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4717 4718 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 4719 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4720 4721 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 4722 (STORE $Rt, Base, Offset)>; 4723 4724 // For truncating store from 64-bits, we have to manually tell LLVM to 4725 // ignore the high bits of the x register. 4726 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 4727 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4728} 4729 4730// Next come patterns for sign-extending loads. 4731multiclass load_signed_pats<string T, string U, dag Base, dag Offset, 4732 dag address, ValueType sty> { 4733 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 4734 (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>; 4735 4736 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 4737 (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>; 4738 4739} 4740 4741// and finally "natural-width" loads and stores come next. 4742multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4743 dag Offset, dag address, ValueType sty> { 4744 def : Pat<(sty (load address)), (LOAD Base, Offset)>; 4745 def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>; 4746} 4747 4748// Integer operations also get atomic instructions to select for. 4749multiclass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4750 dag Offset, dag address, ValueType sty> 4751 : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>, 4752 ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>; 4753 4754//===------------------------------ 4755// 2.2. Addressing-mode instantiations 4756//===------------------------------ 4757 4758multiclass uimm12_pats<dag address, dag Base, dag Offset> { 4759 defm : ls_small_pats<LS8_LDR, LS8_STR, Base, 4760 !foreach(decls.pattern, Offset, 4761 !subst(OFFSET, byte_uimm12, decls.pattern)), 4762 !foreach(decls.pattern, address, 4763 !subst(OFFSET, byte_uimm12, 4764 !subst(ALIGN, any_align, decls.pattern))), 4765 i8>; 4766 defm : ls_small_pats<LS16_LDR, LS16_STR, Base, 4767 !foreach(decls.pattern, Offset, 4768 !subst(OFFSET, hword_uimm12, decls.pattern)), 4769 !foreach(decls.pattern, address, 4770 !subst(OFFSET, hword_uimm12, 4771 !subst(ALIGN, min_align2, decls.pattern))), 4772 i16>; 4773 defm : ls_small_pats<LS32_LDR, LS32_STR, Base, 4774 !foreach(decls.pattern, Offset, 4775 !subst(OFFSET, word_uimm12, decls.pattern)), 4776 !foreach(decls.pattern, address, 4777 !subst(OFFSET, word_uimm12, 4778 !subst(ALIGN, min_align4, decls.pattern))), 4779 i32>; 4780 4781 defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base, 4782 !foreach(decls.pattern, Offset, 4783 !subst(OFFSET, word_uimm12, decls.pattern)), 4784 !foreach(decls.pattern, address, 4785 !subst(OFFSET, word_uimm12, 4786 !subst(ALIGN, min_align4, decls.pattern))), 4787 i32>; 4788 4789 defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base, 4790 !foreach(decls.pattern, Offset, 4791 !subst(OFFSET, dword_uimm12, decls.pattern)), 4792 !foreach(decls.pattern, address, 4793 !subst(OFFSET, dword_uimm12, 4794 !subst(ALIGN, min_align8, decls.pattern))), 4795 i64>; 4796 4797 defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base, 4798 !foreach(decls.pattern, Offset, 4799 !subst(OFFSET, hword_uimm12, decls.pattern)), 4800 !foreach(decls.pattern, address, 4801 !subst(OFFSET, hword_uimm12, 4802 !subst(ALIGN, min_align2, decls.pattern))), 4803 f16>; 4804 4805 defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base, 4806 !foreach(decls.pattern, Offset, 4807 !subst(OFFSET, word_uimm12, decls.pattern)), 4808 !foreach(decls.pattern, address, 4809 !subst(OFFSET, word_uimm12, 4810 !subst(ALIGN, min_align4, decls.pattern))), 4811 f32>; 4812 4813 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base, 4814 !foreach(decls.pattern, Offset, 4815 !subst(OFFSET, dword_uimm12, decls.pattern)), 4816 !foreach(decls.pattern, address, 4817 !subst(OFFSET, dword_uimm12, 4818 !subst(ALIGN, min_align8, decls.pattern))), 4819 f64>; 4820 4821 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base, 4822 !foreach(decls.pattern, Offset, 4823 !subst(OFFSET, qword_uimm12, decls.pattern)), 4824 !foreach(decls.pattern, address, 4825 !subst(OFFSET, qword_uimm12, 4826 !subst(ALIGN, min_align16, decls.pattern))), 4827 f128>; 4828 4829 defm : load_signed_pats<"B", "", Base, 4830 !foreach(decls.pattern, Offset, 4831 !subst(OFFSET, byte_uimm12, decls.pattern)), 4832 !foreach(decls.pattern, address, 4833 !subst(OFFSET, byte_uimm12, 4834 !subst(ALIGN, any_align, decls.pattern))), 4835 i8>; 4836 4837 defm : load_signed_pats<"H", "", Base, 4838 !foreach(decls.pattern, Offset, 4839 !subst(OFFSET, hword_uimm12, decls.pattern)), 4840 !foreach(decls.pattern, address, 4841 !subst(OFFSET, hword_uimm12, 4842 !subst(ALIGN, min_align2, decls.pattern))), 4843 i16>; 4844 4845 def : Pat<(sextloadi32 !foreach(decls.pattern, address, 4846 !subst(OFFSET, word_uimm12, 4847 !subst(ALIGN, min_align4, decls.pattern)))), 4848 (LDRSWx Base, !foreach(decls.pattern, Offset, 4849 !subst(OFFSET, word_uimm12, decls.pattern)))>; 4850} 4851 4852// Straightforward patterns of last resort: a pointer with or without an 4853// appropriate offset. 4854defm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>; 4855defm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12), 4856 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4857 4858// The offset could be hidden behind an "or", of course: 4859defm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12), 4860 (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4861 4862// Global addresses under the small-absolute model should use these 4863// instructions. There are ELF relocations specifically for it. 4864defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN), 4865 (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>; 4866 4867defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12, 4868 ALIGN), 4869 (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>; 4870 4871// External symbols that make it this far should also get standard relocations. 4872defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12, 4873 ALIGN), 4874 (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>; 4875 4876defm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN), 4877 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>; 4878 4879// We also want to use uimm12 instructions for local variables at the moment. 4880def tframeindex_XFORM : SDNodeXForm<frameindex, [{ 4881 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 4882 return CurDAG->getTargetFrameIndex(FI, MVT::i64); 4883}]>; 4884 4885defm : uimm12_pats<(i64 frameindex:$Rn), 4886 (tframeindex_XFORM tframeindex:$Rn), (i64 0)>; 4887 4888// These can be much simpler than uimm12 because we don't to change the operand 4889// type (e.g. LDURB and LDURH take the same operands). 4890multiclass simm9_pats<dag address, dag Base, dag Offset> { 4891 defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>; 4892 defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>; 4893 4894 defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>; 4895 defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>; 4896 4897 defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>; 4898 defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>; 4899 defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>; 4900 defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address, 4901 f128>; 4902 4903 def : Pat<(i64 (zextloadi32 address)), 4904 (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>; 4905 4906 def : Pat<(truncstorei32 i64:$Rt, address), 4907 (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4908 4909 defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>; 4910 defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>; 4911 def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>; 4912} 4913 4914defm : simm9_pats<(add i64:$Rn, simm9:$SImm9), 4915 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 4916 4917defm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9), 4918 (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 4919 4920 4921//===------------------------------ 4922// 3. Register offset patterns 4923//===------------------------------ 4924 4925// Atomic patterns can be shared between integer operations of all sizes, a 4926// quick multiclass here allows reuse. 4927multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 4928 dag Offset, dag Extend, dag address, 4929 ValueType transty, ValueType sty> { 4930 def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 4931 (LOAD Base, Offset, Extend)>; 4932 4933 def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 4934 (STORE $Rt, Base, Offset, Extend)>; 4935} 4936 4937// The register offset instructions take three operands giving the instruction, 4938// and have an annoying split between instructions where Rm is 32-bit and 4939// 64-bit. So we need a special hierarchy to describe them. Other than that the 4940// same operations should be supported as for simm9 and uimm12 addressing. 4941 4942multiclass ro_small_pats<Instruction LOAD, Instruction STORE, 4943 dag Base, dag Offset, dag Extend, 4944 dag address, ValueType sty> 4945 : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> { 4946 def : Pat<(!cast<SDNode>(zextload # sty) address), 4947 (LOAD Base, Offset, Extend)>; 4948 4949 def : Pat<(!cast<SDNode>(extload # sty) address), 4950 (LOAD Base, Offset, Extend)>; 4951 4952 // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 4953 // register was actually set. 4954 def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 4955 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 4956 4957 def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 4958 (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 4959 4960 def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 4961 (STORE $Rt, Base, Offset, Extend)>; 4962 4963 // For truncating store from 64-bits, we have to manually tell LLVM to 4964 // ignore the high bits of the x register. 4965 def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 4966 (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>; 4967 4968} 4969 4970// Next come patterns for sign-extending loads. 4971multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend, 4972 dag address, ValueType sty> { 4973 def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 4974 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset") 4975 Base, Offset, Extend)>; 4976 4977 def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 4978 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset") 4979 Base, Offset, Extend)>; 4980} 4981 4982// and finally "natural-width" loads and stores come next. 4983multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE, 4984 dag Base, dag Offset, dag Extend, dag address, 4985 ValueType sty> { 4986 def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>; 4987 def : Pat<(store sty:$Rt, address), 4988 (STORE $Rt, Base, Offset, Extend)>; 4989} 4990 4991multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE, 4992 dag Base, dag Offset, dag Extend, dag address, 4993 ValueType sty> 4994 : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>, 4995 ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>; 4996 4997multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset, 4998 dag Extend> { 4999 defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"), 5000 !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"), 5001 Base, Offset, Extend, 5002 !foreach(decls.pattern, address, 5003 !subst(SHIFT, imm_eq0, decls.pattern)), 5004 i8>; 5005 defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"), 5006 !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"), 5007 Base, Offset, Extend, 5008 !foreach(decls.pattern, address, 5009 !subst(SHIFT, imm_eq1, decls.pattern)), 5010 i16>; 5011 defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5012 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5013 Base, Offset, Extend, 5014 !foreach(decls.pattern, address, 5015 !subst(SHIFT, imm_eq2, decls.pattern)), 5016 i32>; 5017 5018 defm : ro_int_neutral_pats< 5019 !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5020 !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5021 Base, Offset, Extend, 5022 !foreach(decls.pattern, address, 5023 !subst(SHIFT, imm_eq2, decls.pattern)), 5024 i32>; 5025 5026 defm : ro_int_neutral_pats< 5027 !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"), 5028 !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"), 5029 Base, Offset, Extend, 5030 !foreach(decls.pattern, address, 5031 !subst(SHIFT, imm_eq3, decls.pattern)), 5032 i64>; 5033 5034 defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"), 5035 !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"), 5036 Base, Offset, Extend, 5037 !foreach(decls.pattern, address, 5038 !subst(SHIFT, imm_eq1, decls.pattern)), 5039 f16>; 5040 5041 defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"), 5042 !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"), 5043 Base, Offset, Extend, 5044 !foreach(decls.pattern, address, 5045 !subst(SHIFT, imm_eq2, decls.pattern)), 5046 f32>; 5047 5048 defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"), 5049 !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"), 5050 Base, Offset, Extend, 5051 !foreach(decls.pattern, address, 5052 !subst(SHIFT, imm_eq3, decls.pattern)), 5053 f64>; 5054 5055 defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"), 5056 !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"), 5057 Base, Offset, Extend, 5058 !foreach(decls.pattern, address, 5059 !subst(SHIFT, imm_eq4, decls.pattern)), 5060 f128>; 5061 5062 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend, 5063 !foreach(decls.pattern, address, 5064 !subst(SHIFT, imm_eq0, decls.pattern)), 5065 i8>; 5066 5067 defm : ro_signed_pats<"H", Rm, Base, Offset, Extend, 5068 !foreach(decls.pattern, address, 5069 !subst(SHIFT, imm_eq1, decls.pattern)), 5070 i16>; 5071 5072 def : Pat<(sextloadi32 !foreach(decls.pattern, address, 5073 !subst(SHIFT, imm_eq2, decls.pattern))), 5074 (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset") 5075 Base, Offset, Extend)>; 5076} 5077 5078 5079// Finally we're in a position to tell LLVM exactly what addresses are reachable 5080// using register-offset instructions. Essentially a base plus a possibly 5081// extended, possibly shifted (by access size) offset. 5082 5083defm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)), 5084 (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>; 5085 5086defm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)), 5087 (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>; 5088 5089defm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)), 5090 (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>; 5091 5092defm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)), 5093 (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>; 5094 5095defm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm), 5096 (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>; 5097 5098defm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)), 5099 (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>; 5100