1193323Sed//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This implements the TargetLowering class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "llvm/Target/TargetLowering.h" 15249423Sdim#include "llvm/ADT/BitVector.h" 16249423Sdim#include "llvm/ADT/STLExtras.h" 17210299Sed#include "llvm/CodeGen/Analysis.h" 18193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 19249423Sdim#include "llvm/CodeGen/MachineFunction.h" 20203954Srdivacky#include "llvm/CodeGen/MachineJumpTableInfo.h" 21193323Sed#include "llvm/CodeGen/SelectionDAG.h" 22249423Sdim#include "llvm/IR/DataLayout.h" 23249423Sdim#include "llvm/IR/DerivedTypes.h" 24249423Sdim#include "llvm/IR/GlobalVariable.h" 25249423Sdim#include "llvm/MC/MCAsmInfo.h" 26249423Sdim#include "llvm/MC/MCExpr.h" 27223017Sdim#include "llvm/Support/CommandLine.h" 28198090Srdivacky#include "llvm/Support/ErrorHandling.h" 29193323Sed#include "llvm/Support/MathExtras.h" 30249423Sdim#include "llvm/Target/TargetLoweringObjectFile.h" 31249423Sdim#include "llvm/Target/TargetMachine.h" 32249423Sdim#include "llvm/Target/TargetRegisterInfo.h" 33218893Sdim#include <cctype> 34193323Sedusing namespace llvm; 35193323Sed 36198090Srdivacky/// NOTE: The constructor takes ownership of TLOF. 37207618SrdivackyTargetLowering::TargetLowering(const TargetMachine &tm, 38207618Srdivacky const TargetLoweringObjectFile *tlof) 39249423Sdim : TargetLoweringBase(tm, tlof) {} 40193323Sed 41249423Sdimconst char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 42249423Sdim return NULL; 43193323Sed} 44193323Sed 45249423Sdim/// Check whether a given call node is in tail position within its function. If 46249423Sdim/// so, it sets Chain to the input chain of the tail call. 47249423Sdimbool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 48249423Sdim SDValue &Chain) const { 49249423Sdim const Function *F = DAG.getMachineFunction().getFunction(); 50193323Sed 51249423Sdim // Conservatively require the attributes of the call to match those of 52249423Sdim // the return. Ignore noalias because it doesn't affect the call sequence. 53249423Sdim AttributeSet CallerAttrs = F->getAttributes(); 54249423Sdim if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex) 55249423Sdim .removeAttribute(Attribute::NoAlias).hasAttributes()) 56249423Sdim return false; 57219077Sdim 58249423Sdim // It's not safe to eliminate the sign / zero extension of the return value. 59249423Sdim if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) || 60249423Sdim CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 61203954Srdivacky return false; 62249423Sdim 63249423Sdim // Check if the only use is a function return node. 64249423Sdim return isUsedByReturnOnly(Node, Chain); 65203954Srdivacky} 66203954Srdivacky 67263508Sdim/// \brief Set CallLoweringInfo attribute flags based on a call instruction 68263508Sdim/// and called function attributes. 69263508Sdimvoid TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS, 70263508Sdim unsigned AttrIdx) { 71263508Sdim isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); 72263508Sdim isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); 73263508Sdim isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); 74263508Sdim isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet); 75263508Sdim isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest); 76263508Sdim isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal); 77263508Sdim isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned); 78263508Sdim Alignment = CS->getParamAlignment(AttrIdx); 79263508Sdim} 80203954Srdivacky 81249423Sdim/// Generate a libcall taking the given operands as arguments and returning a 82249423Sdim/// result of type RetVT. 83263508Sdimstd::pair<SDValue, SDValue> 84263508SdimTargetLowering::makeLibCall(SelectionDAG &DAG, 85263508Sdim RTLIB::Libcall LC, EVT RetVT, 86263508Sdim const SDValue *Ops, unsigned NumOps, 87263508Sdim bool isSigned, SDLoc dl, 88263508Sdim bool doesNotReturn, 89263508Sdim bool isReturnValueUsed) const { 90249423Sdim TargetLowering::ArgListTy Args; 91249423Sdim Args.reserve(NumOps); 92218893Sdim 93249423Sdim TargetLowering::ArgListEntry Entry; 94249423Sdim for (unsigned i = 0; i != NumOps; ++i) { 95249423Sdim Entry.Node = Ops[i]; 96249423Sdim Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 97249423Sdim Entry.isSExt = isSigned; 98249423Sdim Entry.isZExt = !isSigned; 99249423Sdim Args.push_back(Entry); 100198090Srdivacky } 101249423Sdim SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); 102218893Sdim 103249423Sdim Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 104249423Sdim TargetLowering:: 105249423Sdim CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 106249423Sdim false, 0, getLibcallCallingConv(LC), 107249423Sdim /*isTailCall=*/false, 108263508Sdim doesNotReturn, isReturnValueUsed, Callee, Args, 109263508Sdim DAG, dl); 110263508Sdim return LowerCallTo(CLI); 111198090Srdivacky} 112198090Srdivacky 113212904Sdim 114249423Sdim/// SoftenSetCCOperands - Soften the operands of a comparison. This code is 115249423Sdim/// shared among BR_CC, SELECT_CC, and SETCC handlers. 116249423Sdimvoid TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, 117249423Sdim SDValue &NewLHS, SDValue &NewRHS, 118249423Sdim ISD::CondCode &CCCode, 119263508Sdim SDLoc dl) const { 120249423Sdim assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) 121249423Sdim && "Unsupported setcc type!"); 122239462Sdim 123249423Sdim // Expand into one or more soft-fp libcall(s). 124249423Sdim RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 125249423Sdim switch (CCCode) { 126249423Sdim case ISD::SETEQ: 127249423Sdim case ISD::SETOEQ: 128249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 129249423Sdim (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 130249423Sdim break; 131249423Sdim case ISD::SETNE: 132249423Sdim case ISD::SETUNE: 133249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : 134249423Sdim (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; 135249423Sdim break; 136249423Sdim case ISD::SETGE: 137249423Sdim case ISD::SETOGE: 138249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 139249423Sdim (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 140249423Sdim break; 141249423Sdim case ISD::SETLT: 142249423Sdim case ISD::SETOLT: 143249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 144249423Sdim (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 145249423Sdim break; 146249423Sdim case ISD::SETLE: 147249423Sdim case ISD::SETOLE: 148249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 149249423Sdim (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 150249423Sdim break; 151249423Sdim case ISD::SETGT: 152249423Sdim case ISD::SETOGT: 153249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 154249423Sdim (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 155249423Sdim break; 156249423Sdim case ISD::SETUO: 157249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 158249423Sdim (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 159249423Sdim break; 160249423Sdim case ISD::SETO: 161249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : 162249423Sdim (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128; 163249423Sdim break; 164249423Sdim default: 165249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 166249423Sdim (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 167249423Sdim switch (CCCode) { 168249423Sdim case ISD::SETONE: 169249423Sdim // SETONE = SETOLT | SETOGT 170249423Sdim LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 171249423Sdim (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 172249423Sdim // Fallthrough 173249423Sdim case ISD::SETUGT: 174249423Sdim LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 175249423Sdim (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 176193323Sed break; 177249423Sdim case ISD::SETUGE: 178249423Sdim LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 179249423Sdim (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 180249423Sdim break; 181249423Sdim case ISD::SETULT: 182249423Sdim LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 183249423Sdim (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 184249423Sdim break; 185249423Sdim case ISD::SETULE: 186249423Sdim LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 187249423Sdim (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 188249423Sdim break; 189249423Sdim case ISD::SETUEQ: 190249423Sdim LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 191249423Sdim (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 192249423Sdim break; 193249423Sdim default: llvm_unreachable("Do not know how to soften this setcc!"); 194193323Sed } 195193323Sed } 196193323Sed 197249423Sdim // Use the target specific return value for comparions lib calls. 198249423Sdim EVT RetVT = getCmpLibcallReturnType(); 199249423Sdim SDValue Ops[2] = { NewLHS, NewRHS }; 200263508Sdim NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, 201263508Sdim dl).first; 202249423Sdim NewRHS = DAG.getConstant(0, RetVT); 203249423Sdim CCCode = getCmpLibcallCC(LC1); 204249423Sdim if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 205263508Sdim SDValue Tmp = DAG.getNode(ISD::SETCC, dl, 206263508Sdim getSetCCResultType(*DAG.getContext(), RetVT), 207249423Sdim NewLHS, NewRHS, DAG.getCondCode(CCCode)); 208263508Sdim NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, 209263508Sdim dl).first; 210263508Sdim NewLHS = DAG.getNode(ISD::SETCC, dl, 211263508Sdim getSetCCResultType(*DAG.getContext(), RetVT), NewLHS, 212249423Sdim NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); 213249423Sdim NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); 214249423Sdim NewRHS = SDValue(); 215218893Sdim } 216193323Sed} 217193323Sed 218203954Srdivacky/// getJumpTableEncoding - Return the entry encoding for a jump table in the 219203954Srdivacky/// current function. The returned value is a member of the 220203954Srdivacky/// MachineJumpTableInfo::JTEntryKind enum. 221203954Srdivackyunsigned TargetLowering::getJumpTableEncoding() const { 222203954Srdivacky // In non-pic modes, just use the address of a block. 223203954Srdivacky if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 224203954Srdivacky return MachineJumpTableInfo::EK_BlockAddress; 225218893Sdim 226203954Srdivacky // In PIC mode, if the target supports a GPRel32 directive, use it. 227203954Srdivacky if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 228203954Srdivacky return MachineJumpTableInfo::EK_GPRel32BlockAddress; 229218893Sdim 230203954Srdivacky // Otherwise, use a label difference. 231203954Srdivacky return MachineJumpTableInfo::EK_LabelDifference32; 232203954Srdivacky} 233203954Srdivacky 234193323SedSDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 235193323Sed SelectionDAG &DAG) const { 236203954Srdivacky // If our PIC model is GP relative, use the global offset table as the base. 237234353Sdim unsigned JTEncoding = getJumpTableEncoding(); 238234353Sdim 239234353Sdim if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 240234353Sdim (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 241243830Sdim return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); 242234353Sdim 243193323Sed return Table; 244193323Sed} 245193323Sed 246203954Srdivacky/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 247203954Srdivacky/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 248203954Srdivacky/// MCExpr. 249203954Srdivackyconst MCExpr * 250203954SrdivackyTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 251203954Srdivacky unsigned JTI,MCContext &Ctx) const{ 252203954Srdivacky // The normal PIC reloc base is the label at the start of the jump table. 253203954Srdivacky return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 254203954Srdivacky} 255203954Srdivacky 256193323Sedbool 257193323SedTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 258193323Sed // Assume that everything is safe in static mode. 259193323Sed if (getTargetMachine().getRelocationModel() == Reloc::Static) 260193323Sed return true; 261193323Sed 262193323Sed // In dynamic-no-pic mode, assume that known defined values are safe. 263193323Sed if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 264193323Sed GA && 265193323Sed !GA->getGlobal()->isDeclaration() && 266193323Sed !GA->getGlobal()->isWeakForLinker()) 267193323Sed return true; 268193323Sed 269193323Sed // Otherwise assume nothing is safe. 270193323Sed return false; 271193323Sed} 272193323Sed 273193323Sed//===----------------------------------------------------------------------===// 274193323Sed// Optimization Methods 275193323Sed//===----------------------------------------------------------------------===// 276193323Sed 277218893Sdim/// ShrinkDemandedConstant - Check to see if the specified operand of the 278193323Sed/// specified instruction is a constant integer. If so, check to see if there 279193323Sed/// are any bits set in the constant that are not demanded. If so, shrink the 280193323Sed/// constant and return true. 281218893Sdimbool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 282193323Sed const APInt &Demanded) { 283263508Sdim SDLoc dl(Op); 284193323Sed 285193323Sed // FIXME: ISD::SELECT, ISD::SELECT_CC 286193323Sed switch (Op.getOpcode()) { 287193323Sed default: break; 288193323Sed case ISD::XOR: 289193323Sed case ISD::AND: 290193323Sed case ISD::OR: { 291193323Sed ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 292193323Sed if (!C) return false; 293193323Sed 294193323Sed if (Op.getOpcode() == ISD::XOR && 295193323Sed (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 296193323Sed return false; 297193323Sed 298193323Sed // if we can expand it to have all bits set, do it 299193323Sed if (C->getAPIntValue().intersects(~Demanded)) { 300198090Srdivacky EVT VT = Op.getValueType(); 301193323Sed SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 302193323Sed DAG.getConstant(Demanded & 303218893Sdim C->getAPIntValue(), 304193323Sed VT)); 305193323Sed return CombineTo(Op, New); 306193323Sed } 307193323Sed 308193323Sed break; 309193323Sed } 310193323Sed } 311193323Sed 312193323Sed return false; 313193323Sed} 314193323Sed 315193323Sed/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 316193323Sed/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 317193323Sed/// cast, but it could be generalized for targets with other types of 318193323Sed/// implicit widening casts. 319193323Sedbool 320193323SedTargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 321193323Sed unsigned BitWidth, 322193323Sed const APInt &Demanded, 323263508Sdim SDLoc dl) { 324193323Sed assert(Op.getNumOperands() == 2 && 325193323Sed "ShrinkDemandedOp only supports binary operators!"); 326193323Sed assert(Op.getNode()->getNumValues() == 1 && 327193323Sed "ShrinkDemandedOp only supports nodes with one result!"); 328193323Sed 329193323Sed // Don't do this if the node has another user, which may require the 330193323Sed // full value. 331193323Sed if (!Op.getNode()->hasOneUse()) 332193323Sed return false; 333193323Sed 334193323Sed // Search for the smallest integer type with free casts to and from 335193323Sed // Op's type. For expedience, just check power-of-2 integer types. 336193323Sed const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 337249423Sdim unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros(); 338249423Sdim unsigned SmallVTBits = DemandedSize; 339193323Sed if (!isPowerOf2_32(SmallVTBits)) 340193323Sed SmallVTBits = NextPowerOf2(SmallVTBits); 341193323Sed for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 342198090Srdivacky EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 343193323Sed if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 344193323Sed TLI.isZExtFree(SmallVT, Op.getValueType())) { 345193323Sed // We found a type with free casts. 346193323Sed SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 347193323Sed DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 348193323Sed Op.getNode()->getOperand(0)), 349193323Sed DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 350193323Sed Op.getNode()->getOperand(1))); 351249423Sdim bool NeedZext = DemandedSize > SmallVTBits; 352249423Sdim SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, 353249423Sdim dl, Op.getValueType(), X); 354193323Sed return CombineTo(Op, Z); 355193323Sed } 356193323Sed } 357193323Sed return false; 358193323Sed} 359193323Sed 360193323Sed/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 361193323Sed/// DemandedMask bits of the result of Op are ever used downstream. If we can 362193323Sed/// use this information to simplify Op, create a new simplified DAG node and 363193323Sed/// return true, returning the original and new nodes in Old and New. Otherwise, 364193323Sed/// analyze the expression and return a mask of KnownOne and KnownZero bits for 365193323Sed/// the expression (used to simplify the caller). The KnownZero/One bits may 366193323Sed/// only be accurate for those bits in the DemandedMask. 367193323Sedbool TargetLowering::SimplifyDemandedBits(SDValue Op, 368193323Sed const APInt &DemandedMask, 369193323Sed APInt &KnownZero, 370193323Sed APInt &KnownOne, 371193323Sed TargetLoweringOpt &TLO, 372193323Sed unsigned Depth) const { 373193323Sed unsigned BitWidth = DemandedMask.getBitWidth(); 374200581Srdivacky assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 375193323Sed "Mask size mismatches value type size!"); 376193323Sed APInt NewMask = DemandedMask; 377263508Sdim SDLoc dl(Op); 378193323Sed 379193323Sed // Don't know anything. 380193323Sed KnownZero = KnownOne = APInt(BitWidth, 0); 381193323Sed 382193323Sed // Other users may use these bits. 383218893Sdim if (!Op.getNode()->hasOneUse()) { 384193323Sed if (Depth != 0) { 385218893Sdim // If not at the root, Just compute the KnownZero/KnownOne bits to 386193323Sed // simplify things downstream. 387234353Sdim TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 388193323Sed return false; 389193323Sed } 390193323Sed // If this is the root being simplified, allow it to have multiple uses, 391193323Sed // just set the NewMask to all bits. 392193323Sed NewMask = APInt::getAllOnesValue(BitWidth); 393218893Sdim } else if (DemandedMask == 0) { 394193323Sed // Not demanding any bits from Op. 395193323Sed if (Op.getOpcode() != ISD::UNDEF) 396193323Sed return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 397193323Sed return false; 398193323Sed } else if (Depth == 6) { // Limit search depth. 399193323Sed return false; 400193323Sed } 401193323Sed 402193323Sed APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 403193323Sed switch (Op.getOpcode()) { 404193323Sed case ISD::Constant: 405193323Sed // We know all of the bits for a constant! 406234353Sdim KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 407234353Sdim KnownZero = ~KnownOne; 408193323Sed return false; // Don't fall through, will infinitely loop. 409193323Sed case ISD::AND: 410193323Sed // If the RHS is a constant, check to see if the LHS would be zero without 411193323Sed // using the bits from the RHS. Below, we use knowledge about the RHS to 412193323Sed // simplify the LHS, here we're using information from the LHS to simplify 413193323Sed // the RHS. 414193323Sed if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 415193323Sed APInt LHSZero, LHSOne; 416218893Sdim // Do not increment Depth here; that can cause an infinite loop. 417234353Sdim TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 418193323Sed // If the LHS already has zeros where RHSC does, this and is dead. 419193323Sed if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 420193323Sed return TLO.CombineTo(Op, Op.getOperand(0)); 421193323Sed // If any of the set bits in the RHS are known zero on the LHS, shrink 422193323Sed // the constant. 423193323Sed if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 424193323Sed return true; 425193323Sed } 426218893Sdim 427193323Sed if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 428193323Sed KnownOne, TLO, Depth+1)) 429193323Sed return true; 430218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 431193323Sed if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 432193323Sed KnownZero2, KnownOne2, TLO, Depth+1)) 433193323Sed return true; 434218893Sdim assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 435218893Sdim 436193323Sed // If all of the demanded bits are known one on one side, return the other. 437193323Sed // These bits cannot contribute to the result of the 'and'. 438193323Sed if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 439193323Sed return TLO.CombineTo(Op, Op.getOperand(0)); 440193323Sed if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 441193323Sed return TLO.CombineTo(Op, Op.getOperand(1)); 442193323Sed // If all of the demanded bits in the inputs are known zeros, return zero. 443193323Sed if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 444193323Sed return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 445193323Sed // If the RHS is a constant, see if we can simplify it. 446193323Sed if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 447193323Sed return true; 448193323Sed // If the operation can be done in a smaller type, do so. 449210299Sed if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 450193323Sed return true; 451193323Sed 452193323Sed // Output known-1 bits are only known if set in both the LHS & RHS. 453193323Sed KnownOne &= KnownOne2; 454193323Sed // Output known-0 are known to be clear if zero in either the LHS | RHS. 455193323Sed KnownZero |= KnownZero2; 456193323Sed break; 457193323Sed case ISD::OR: 458218893Sdim if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 459193323Sed KnownOne, TLO, Depth+1)) 460193323Sed return true; 461218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 462193323Sed if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 463193323Sed KnownZero2, KnownOne2, TLO, Depth+1)) 464193323Sed return true; 465218893Sdim assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 466218893Sdim 467193323Sed // If all of the demanded bits are known zero on one side, return the other. 468193323Sed // These bits cannot contribute to the result of the 'or'. 469193323Sed if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 470193323Sed return TLO.CombineTo(Op, Op.getOperand(0)); 471193323Sed if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 472193323Sed return TLO.CombineTo(Op, Op.getOperand(1)); 473193323Sed // If all of the potentially set bits on one side are known to be set on 474193323Sed // the other side, just use the 'other' side. 475193323Sed if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 476193323Sed return TLO.CombineTo(Op, Op.getOperand(0)); 477193323Sed if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 478193323Sed return TLO.CombineTo(Op, Op.getOperand(1)); 479193323Sed // If the RHS is a constant, see if we can simplify it. 480193323Sed if (TLO.ShrinkDemandedConstant(Op, NewMask)) 481193323Sed return true; 482193323Sed // If the operation can be done in a smaller type, do so. 483210299Sed if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 484193323Sed return true; 485193323Sed 486193323Sed // Output known-0 bits are only known if clear in both the LHS & RHS. 487193323Sed KnownZero &= KnownZero2; 488193323Sed // Output known-1 are known to be set if set in either the LHS | RHS. 489193323Sed KnownOne |= KnownOne2; 490193323Sed break; 491193323Sed case ISD::XOR: 492218893Sdim if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 493193323Sed KnownOne, TLO, Depth+1)) 494193323Sed return true; 495218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 496193323Sed if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 497193323Sed KnownOne2, TLO, Depth+1)) 498193323Sed return true; 499218893Sdim assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 500218893Sdim 501193323Sed // If all of the demanded bits are known zero on one side, return the other. 502193323Sed // These bits cannot contribute to the result of the 'xor'. 503193323Sed if ((KnownZero & NewMask) == NewMask) 504193323Sed return TLO.CombineTo(Op, Op.getOperand(0)); 505193323Sed if ((KnownZero2 & NewMask) == NewMask) 506193323Sed return TLO.CombineTo(Op, Op.getOperand(1)); 507193323Sed // If the operation can be done in a smaller type, do so. 508210299Sed if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 509193323Sed return true; 510193323Sed 511193323Sed // If all of the unknown bits are known to be zero on one side or the other 512193323Sed // (but not both) turn this into an *inclusive* or. 513193323Sed // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 514193323Sed if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 515193323Sed return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 516193323Sed Op.getOperand(0), 517193323Sed Op.getOperand(1))); 518218893Sdim 519193323Sed // Output known-0 bits are known if clear or set in both the LHS & RHS. 520193323Sed KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 521193323Sed // Output known-1 are known to be set if set in only one of the LHS, RHS. 522193323Sed KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 523218893Sdim 524193323Sed // If all of the demanded bits on one side are known, and all of the set 525193323Sed // bits on that side are also known to be set on the other side, turn this 526193323Sed // into an AND, as we know the bits will be cleared. 527193323Sed // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 528234982Sdim // NB: it is okay if more bits are known than are requested 529263508Sdim if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 530234982Sdim if (KnownOne == KnownOne2) { // set bits are the same on both sides 531198090Srdivacky EVT VT = Op.getValueType(); 532193323Sed SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 533218893Sdim return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 534193323Sed Op.getOperand(0), ANDC)); 535193323Sed } 536193323Sed } 537218893Sdim 538193323Sed // If the RHS is a constant, see if we can simplify it. 539193323Sed // for XOR, we prefer to force bits to 1 if they will make a -1. 540193323Sed // if we can't force bits, try to shrink constant 541193323Sed if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 542193323Sed APInt Expanded = C->getAPIntValue() | (~NewMask); 543193323Sed // if we can expand it to have all bits set, do it 544193323Sed if (Expanded.isAllOnesValue()) { 545193323Sed if (Expanded != C->getAPIntValue()) { 546198090Srdivacky EVT VT = Op.getValueType(); 547193323Sed SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 548193323Sed TLO.DAG.getConstant(Expanded, VT)); 549193323Sed return TLO.CombineTo(Op, New); 550193323Sed } 551193323Sed // if it already has all the bits set, nothing to change 552193323Sed // but don't shrink either! 553193323Sed } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 554193323Sed return true; 555193323Sed } 556193323Sed } 557193323Sed 558193323Sed KnownZero = KnownZeroOut; 559193323Sed KnownOne = KnownOneOut; 560193323Sed break; 561193323Sed case ISD::SELECT: 562218893Sdim if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 563193323Sed KnownOne, TLO, Depth+1)) 564193323Sed return true; 565193323Sed if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 566193323Sed KnownOne2, TLO, Depth+1)) 567193323Sed return true; 568218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 569218893Sdim assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 570218893Sdim 571193323Sed // If the operands are constants, see if we can simplify them. 572193323Sed if (TLO.ShrinkDemandedConstant(Op, NewMask)) 573193323Sed return true; 574218893Sdim 575193323Sed // Only known if known in both the LHS and RHS. 576193323Sed KnownOne &= KnownOne2; 577193323Sed KnownZero &= KnownZero2; 578193323Sed break; 579193323Sed case ISD::SELECT_CC: 580218893Sdim if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 581193323Sed KnownOne, TLO, Depth+1)) 582193323Sed return true; 583193323Sed if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 584193323Sed KnownOne2, TLO, Depth+1)) 585193323Sed return true; 586218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 587218893Sdim assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 588218893Sdim 589193323Sed // If the operands are constants, see if we can simplify them. 590193323Sed if (TLO.ShrinkDemandedConstant(Op, NewMask)) 591193323Sed return true; 592218893Sdim 593193323Sed // Only known if known in both the LHS and RHS. 594193323Sed KnownOne &= KnownOne2; 595193323Sed KnownZero &= KnownZero2; 596193323Sed break; 597193323Sed case ISD::SHL: 598193323Sed if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 599193323Sed unsigned ShAmt = SA->getZExtValue(); 600193323Sed SDValue InOp = Op.getOperand(0); 601193323Sed 602193323Sed // If the shift count is an invalid immediate, don't do anything. 603193323Sed if (ShAmt >= BitWidth) 604193323Sed break; 605193323Sed 606193323Sed // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 607193323Sed // single shift. We can do this if the bottom bits (which are shifted 608193323Sed // out) are never demanded. 609193323Sed if (InOp.getOpcode() == ISD::SRL && 610193323Sed isa<ConstantSDNode>(InOp.getOperand(1))) { 611193323Sed if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 612193323Sed unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 613193323Sed unsigned Opc = ISD::SHL; 614193323Sed int Diff = ShAmt-C1; 615193323Sed if (Diff < 0) { 616193323Sed Diff = -Diff; 617193323Sed Opc = ISD::SRL; 618218893Sdim } 619218893Sdim 620218893Sdim SDValue NewSA = 621193323Sed TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 622198090Srdivacky EVT VT = Op.getValueType(); 623193323Sed return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 624193323Sed InOp.getOperand(0), NewSA)); 625193323Sed } 626218893Sdim } 627218893Sdim 628212904Sdim if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 629193323Sed KnownZero, KnownOne, TLO, Depth+1)) 630193323Sed return true; 631212904Sdim 632212904Sdim // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 633212904Sdim // are not demanded. This will likely allow the anyext to be folded away. 634212904Sdim if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 635212904Sdim SDValue InnerOp = InOp.getNode()->getOperand(0); 636212904Sdim EVT InnerVT = InnerOp.getValueType(); 637234353Sdim unsigned InnerBits = InnerVT.getSizeInBits(); 638234353Sdim if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 639212904Sdim isTypeDesirableForOp(ISD::SHL, InnerVT)) { 640219077Sdim EVT ShTy = getShiftAmountTy(InnerVT); 641212904Sdim if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 642212904Sdim ShTy = InnerVT; 643212904Sdim SDValue NarrowShl = 644212904Sdim TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 645212904Sdim TLO.DAG.getConstant(ShAmt, ShTy)); 646212904Sdim return 647212904Sdim TLO.CombineTo(Op, 648212904Sdim TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 649212904Sdim NarrowShl)); 650212904Sdim } 651263508Sdim // Repeat the SHL optimization above in cases where an extension 652263508Sdim // intervenes: (shl (anyext (shr x, c1)), c2) to 653263508Sdim // (shl (anyext x), c2-c1). This requires that the bottom c1 bits 654263508Sdim // aren't demanded (as above) and that the shifted upper c1 bits of 655263508Sdim // x aren't demanded. 656263508Sdim if (InOp.hasOneUse() && 657263508Sdim InnerOp.getOpcode() == ISD::SRL && 658263508Sdim InnerOp.hasOneUse() && 659263508Sdim isa<ConstantSDNode>(InnerOp.getOperand(1))) { 660263508Sdim uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) 661263508Sdim ->getZExtValue(); 662263508Sdim if (InnerShAmt < ShAmt && 663263508Sdim InnerShAmt < InnerBits && 664263508Sdim NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && 665263508Sdim NewMask.trunc(ShAmt) == 0) { 666263508Sdim SDValue NewSA = 667263508Sdim TLO.DAG.getConstant(ShAmt - InnerShAmt, 668263508Sdim Op.getOperand(1).getValueType()); 669263508Sdim EVT VT = Op.getValueType(); 670263508Sdim SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, 671263508Sdim InnerOp.getOperand(0)); 672263508Sdim return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, 673263508Sdim NewExt, NewSA)); 674263508Sdim } 675263508Sdim } 676212904Sdim } 677212904Sdim 678193323Sed KnownZero <<= SA->getZExtValue(); 679193323Sed KnownOne <<= SA->getZExtValue(); 680193323Sed // low bits known zero. 681193323Sed KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 682193323Sed } 683193323Sed break; 684193323Sed case ISD::SRL: 685193323Sed if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 686198090Srdivacky EVT VT = Op.getValueType(); 687193323Sed unsigned ShAmt = SA->getZExtValue(); 688193323Sed unsigned VTSize = VT.getSizeInBits(); 689193323Sed SDValue InOp = Op.getOperand(0); 690218893Sdim 691193323Sed // If the shift count is an invalid immediate, don't do anything. 692193323Sed if (ShAmt >= BitWidth) 693193323Sed break; 694193323Sed 695193323Sed // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 696193323Sed // single shift. We can do this if the top bits (which are shifted out) 697193323Sed // are never demanded. 698193323Sed if (InOp.getOpcode() == ISD::SHL && 699193323Sed isa<ConstantSDNode>(InOp.getOperand(1))) { 700193323Sed if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 701193323Sed unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 702193323Sed unsigned Opc = ISD::SRL; 703193323Sed int Diff = ShAmt-C1; 704193323Sed if (Diff < 0) { 705193323Sed Diff = -Diff; 706193323Sed Opc = ISD::SHL; 707218893Sdim } 708218893Sdim 709193323Sed SDValue NewSA = 710193323Sed TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 711193323Sed return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 712193323Sed InOp.getOperand(0), NewSA)); 713193323Sed } 714218893Sdim } 715218893Sdim 716193323Sed // Compute the new bits that are at the top now. 717193323Sed if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 718193323Sed KnownZero, KnownOne, TLO, Depth+1)) 719193323Sed return true; 720218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 721193323Sed KnownZero = KnownZero.lshr(ShAmt); 722193323Sed KnownOne = KnownOne.lshr(ShAmt); 723193323Sed 724193323Sed APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 725193323Sed KnownZero |= HighBits; // High bits known zero. 726193323Sed } 727193323Sed break; 728193323Sed case ISD::SRA: 729193323Sed // If this is an arithmetic shift right and only the low-bit is set, we can 730193323Sed // always convert this into a logical shr, even if the shift amount is 731193323Sed // variable. The low bit of the shift cannot be an input sign bit unless 732193323Sed // the shift amount is >= the size of the datatype, which is undefined. 733234353Sdim if (NewMask == 1) 734207618Srdivacky return TLO.CombineTo(Op, 735207618Srdivacky TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 736207618Srdivacky Op.getOperand(0), Op.getOperand(1))); 737193323Sed 738193323Sed if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 739198090Srdivacky EVT VT = Op.getValueType(); 740193323Sed unsigned ShAmt = SA->getZExtValue(); 741218893Sdim 742193323Sed // If the shift count is an invalid immediate, don't do anything. 743193323Sed if (ShAmt >= BitWidth) 744193323Sed break; 745193323Sed 746193323Sed APInt InDemandedMask = (NewMask << ShAmt); 747193323Sed 748193323Sed // If any of the demanded bits are produced by the sign extension, we also 749193323Sed // demand the input sign bit. 750193323Sed APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 751193323Sed if (HighBits.intersects(NewMask)) 752200581Srdivacky InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 753218893Sdim 754193323Sed if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 755193323Sed KnownZero, KnownOne, TLO, Depth+1)) 756193323Sed return true; 757218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 758193323Sed KnownZero = KnownZero.lshr(ShAmt); 759193323Sed KnownOne = KnownOne.lshr(ShAmt); 760218893Sdim 761193323Sed // Handle the sign bit, adjusted to where it is now in the mask. 762193323Sed APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 763218893Sdim 764193323Sed // If the input sign bit is known to be zero, or if none of the top bits 765193323Sed // are demanded, turn this into an unsigned shift right. 766263508Sdim if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) 767218893Sdim return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 768193323Sed Op.getOperand(0), 769193323Sed Op.getOperand(1))); 770263508Sdim 771263508Sdim int Log2 = NewMask.exactLogBase2(); 772263508Sdim if (Log2 >= 0) { 773263508Sdim // The bit must come from the sign. 774263508Sdim SDValue NewSA = 775263508Sdim TLO.DAG.getConstant(BitWidth - 1 - Log2, 776263508Sdim Op.getOperand(1).getValueType()); 777263508Sdim return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 778263508Sdim Op.getOperand(0), NewSA)); 779263508Sdim } 780263508Sdim 781263508Sdim if (KnownOne.intersects(SignBit)) 782263508Sdim // New bits are known one. 783193323Sed KnownOne |= HighBits; 784193323Sed } 785193323Sed break; 786193323Sed case ISD::SIGN_EXTEND_INREG: { 787234353Sdim EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 788193323Sed 789234353Sdim APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 790234353Sdim // If we only care about the highest bit, don't bother shifting right. 791234353Sdim if (MsbMask == DemandedMask) { 792234353Sdim unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 793234353Sdim SDValue InOp = Op.getOperand(0); 794234353Sdim 795234353Sdim // Compute the correct shift amount type, which must be getShiftAmountTy 796234353Sdim // for scalar types after legalization. 797234353Sdim EVT ShiftAmtTy = Op.getValueType(); 798234353Sdim if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 799234353Sdim ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 800234353Sdim 801234353Sdim SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 802234353Sdim return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 803234353Sdim Op.getValueType(), InOp, ShiftAmt)); 804234353Sdim } 805234353Sdim 806218893Sdim // Sign extension. Compute the demanded bits in the result that are not 807193323Sed // present in the input. 808202375Srdivacky APInt NewBits = 809202375Srdivacky APInt::getHighBitsSet(BitWidth, 810234353Sdim BitWidth - ExVT.getScalarType().getSizeInBits()); 811218893Sdim 812193323Sed // If none of the extended bits are demanded, eliminate the sextinreg. 813212904Sdim if ((NewBits & NewMask) == 0) 814193323Sed return TLO.CombineTo(Op, Op.getOperand(0)); 815193323Sed 816218893Sdim APInt InSignBit = 817234353Sdim APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 818202375Srdivacky APInt InputDemandedBits = 819202375Srdivacky APInt::getLowBitsSet(BitWidth, 820234353Sdim ExVT.getScalarType().getSizeInBits()) & 821202375Srdivacky NewMask; 822218893Sdim 823193323Sed // Since the sign extended bits are demanded, we know that the sign 824193323Sed // bit is demanded. 825193323Sed InputDemandedBits |= InSignBit; 826193323Sed 827193323Sed if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 828193323Sed KnownZero, KnownOne, TLO, Depth+1)) 829193323Sed return true; 830218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 831193323Sed 832193323Sed // If the sign bit of the input is known set or clear, then we know the 833193323Sed // top bits of the result. 834218893Sdim 835193323Sed // If the input sign bit is known zero, convert this into a zero extension. 836193323Sed if (KnownZero.intersects(InSignBit)) 837218893Sdim return TLO.CombineTo(Op, 838234353Sdim TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 839218893Sdim 840193323Sed if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 841193323Sed KnownOne |= NewBits; 842193323Sed KnownZero &= ~NewBits; 843193323Sed } else { // Input sign bit unknown 844193323Sed KnownZero &= ~NewBits; 845193323Sed KnownOne &= ~NewBits; 846193323Sed } 847193323Sed break; 848193323Sed } 849193323Sed case ISD::ZERO_EXTEND: { 850202375Srdivacky unsigned OperandBitWidth = 851202375Srdivacky Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 852218893Sdim APInt InMask = NewMask.trunc(OperandBitWidth); 853218893Sdim 854193323Sed // If none of the top bits are demanded, convert this into an any_extend. 855193323Sed APInt NewBits = 856193323Sed APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 857193323Sed if (!NewBits.intersects(NewMask)) 858193323Sed return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 859218893Sdim Op.getValueType(), 860193323Sed Op.getOperand(0))); 861218893Sdim 862193323Sed if (SimplifyDemandedBits(Op.getOperand(0), InMask, 863193323Sed KnownZero, KnownOne, TLO, Depth+1)) 864193323Sed return true; 865218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 866218893Sdim KnownZero = KnownZero.zext(BitWidth); 867218893Sdim KnownOne = KnownOne.zext(BitWidth); 868193323Sed KnownZero |= NewBits; 869193323Sed break; 870193323Sed } 871193323Sed case ISD::SIGN_EXTEND: { 872198090Srdivacky EVT InVT = Op.getOperand(0).getValueType(); 873202375Srdivacky unsigned InBits = InVT.getScalarType().getSizeInBits(); 874193323Sed APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 875193323Sed APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 876193323Sed APInt NewBits = ~InMask & NewMask; 877218893Sdim 878193323Sed // If none of the top bits are demanded, convert this into an any_extend. 879193323Sed if (NewBits == 0) 880193323Sed return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 881193323Sed Op.getValueType(), 882193323Sed Op.getOperand(0))); 883218893Sdim 884193323Sed // Since some of the sign extended bits are demanded, we know that the sign 885193323Sed // bit is demanded. 886193323Sed APInt InDemandedBits = InMask & NewMask; 887193323Sed InDemandedBits |= InSignBit; 888218893Sdim InDemandedBits = InDemandedBits.trunc(InBits); 889218893Sdim 890218893Sdim if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 891193323Sed KnownOne, TLO, Depth+1)) 892193323Sed return true; 893218893Sdim KnownZero = KnownZero.zext(BitWidth); 894218893Sdim KnownOne = KnownOne.zext(BitWidth); 895218893Sdim 896193323Sed // If the sign bit is known zero, convert this to a zero extend. 897193323Sed if (KnownZero.intersects(InSignBit)) 898193323Sed return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 899218893Sdim Op.getValueType(), 900193323Sed Op.getOperand(0))); 901218893Sdim 902193323Sed // If the sign bit is known one, the top bits match. 903193323Sed if (KnownOne.intersects(InSignBit)) { 904234353Sdim KnownOne |= NewBits; 905234353Sdim assert((KnownZero & NewBits) == 0); 906193323Sed } else { // Otherwise, top bits aren't known. 907234353Sdim assert((KnownOne & NewBits) == 0); 908234353Sdim assert((KnownZero & NewBits) == 0); 909193323Sed } 910193323Sed break; 911193323Sed } 912193323Sed case ISD::ANY_EXTEND: { 913202375Srdivacky unsigned OperandBitWidth = 914202375Srdivacky Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 915218893Sdim APInt InMask = NewMask.trunc(OperandBitWidth); 916193323Sed if (SimplifyDemandedBits(Op.getOperand(0), InMask, 917193323Sed KnownZero, KnownOne, TLO, Depth+1)) 918193323Sed return true; 919218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 920218893Sdim KnownZero = KnownZero.zext(BitWidth); 921218893Sdim KnownOne = KnownOne.zext(BitWidth); 922193323Sed break; 923193323Sed } 924193323Sed case ISD::TRUNCATE: { 925193323Sed // Simplify the input, using demanded bit information, and compute the known 926193323Sed // zero/one bits live out. 927204642Srdivacky unsigned OperandBitWidth = 928204642Srdivacky Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 929218893Sdim APInt TruncMask = NewMask.zext(OperandBitWidth); 930193323Sed if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 931193323Sed KnownZero, KnownOne, TLO, Depth+1)) 932193323Sed return true; 933218893Sdim KnownZero = KnownZero.trunc(BitWidth); 934218893Sdim KnownOne = KnownOne.trunc(BitWidth); 935218893Sdim 936193323Sed // If the input is only used by this truncate, see if we can shrink it based 937193323Sed // on the known demanded bits. 938193323Sed if (Op.getOperand(0).getNode()->hasOneUse()) { 939193323Sed SDValue In = Op.getOperand(0); 940193323Sed switch (In.getOpcode()) { 941193323Sed default: break; 942193323Sed case ISD::SRL: 943193323Sed // Shrink SRL by a constant if none of the high bits shifted in are 944193323Sed // demanded. 945207618Srdivacky if (TLO.LegalTypes() && 946207618Srdivacky !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 947207618Srdivacky // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 948207618Srdivacky // undesirable. 949207618Srdivacky break; 950207618Srdivacky ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 951207618Srdivacky if (!ShAmt) 952207618Srdivacky break; 953221345Sdim SDValue Shift = In.getOperand(1); 954221345Sdim if (TLO.LegalTypes()) { 955221345Sdim uint64_t ShVal = ShAmt->getZExtValue(); 956221345Sdim Shift = 957221345Sdim TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 958221345Sdim } 959221345Sdim 960207618Srdivacky APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 961207618Srdivacky OperandBitWidth - BitWidth); 962218893Sdim HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 963207618Srdivacky 964207618Srdivacky if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 965207618Srdivacky // None of the shifted in bits are needed. Add a truncate of the 966207618Srdivacky // shift input, then shift it. 967207618Srdivacky SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 968218893Sdim Op.getValueType(), 969207618Srdivacky In.getOperand(0)); 970207618Srdivacky return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 971207618Srdivacky Op.getValueType(), 972218893Sdim NewTrunc, 973221345Sdim Shift)); 974193323Sed } 975193323Sed break; 976193323Sed } 977193323Sed } 978218893Sdim 979218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 980193323Sed break; 981193323Sed } 982193323Sed case ISD::AssertZext: { 983226633Sdim // AssertZext demands all of the high bits, plus any of the low bits 984226633Sdim // demanded by its users. 985226633Sdim EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 986226633Sdim APInt InMask = APInt::getLowBitsSet(BitWidth, 987226633Sdim VT.getSizeInBits()); 988226633Sdim if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 989210299Sed KnownZero, KnownOne, TLO, Depth+1)) 990210299Sed return true; 991218893Sdim assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 992210299Sed 993193323Sed KnownZero |= ~InMask & NewMask; 994193323Sed break; 995193323Sed } 996218893Sdim case ISD::BITCAST: 997223017Sdim // If this is an FP->Int bitcast and if the sign bit is the only 998223017Sdim // thing demanded, turn this into a FGETSIGN. 999234353Sdim if (!TLO.LegalOperations() && 1000234353Sdim !Op.getValueType().isVector() && 1001234353Sdim !Op.getOperand(0).getValueType().isVector() && 1002224145Sdim NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1003224145Sdim Op.getOperand(0).getValueType().isFloatingPoint()) { 1004223017Sdim bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1005223017Sdim bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1006223017Sdim if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1007223017Sdim EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1008193323Sed // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1009193323Sed // place. We expect the SHL to be eliminated by other optimizations. 1010223017Sdim SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1011223017Sdim unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1012223017Sdim if (!OpVTLegal && OpVTSizeInBits > 32) 1013223017Sdim Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1014193323Sed unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1015223017Sdim SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1016223017Sdim return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1017223017Sdim Op.getValueType(), 1018193323Sed Sign, ShAmt)); 1019193323Sed } 1020193323Sed } 1021193323Sed break; 1022193323Sed case ISD::ADD: 1023193323Sed case ISD::MUL: 1024193323Sed case ISD::SUB: { 1025193323Sed // Add, Sub, and Mul don't demand any bits in positions beyond that 1026193323Sed // of the highest bit demanded of them. 1027193323Sed APInt LoMask = APInt::getLowBitsSet(BitWidth, 1028193323Sed BitWidth - NewMask.countLeadingZeros()); 1029193323Sed if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1030193323Sed KnownOne2, TLO, Depth+1)) 1031193323Sed return true; 1032193323Sed if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1033193323Sed KnownOne2, TLO, Depth+1)) 1034193323Sed return true; 1035193323Sed // See if the operation should be performed at a smaller bit width. 1036210299Sed if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1037193323Sed return true; 1038193323Sed } 1039193323Sed // FALL THROUGH 1040193323Sed default: 1041193323Sed // Just use ComputeMaskedBits to compute output bits. 1042234353Sdim TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1043193323Sed break; 1044193323Sed } 1045218893Sdim 1046193323Sed // If we know the value of all of the demanded bits, return this as a 1047193323Sed // constant. 1048193323Sed if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1049193323Sed return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1050218893Sdim 1051193323Sed return false; 1052193323Sed} 1053193323Sed 1054218893Sdim/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1055218893Sdim/// in Mask are known to be either zero or one and return them in the 1056193323Sed/// KnownZero/KnownOne bitsets. 1057218893Sdimvoid TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1058218893Sdim APInt &KnownZero, 1059193323Sed APInt &KnownOne, 1060193323Sed const SelectionDAG &DAG, 1061193323Sed unsigned Depth) const { 1062193323Sed assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1063193323Sed Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1064193323Sed Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1065193323Sed Op.getOpcode() == ISD::INTRINSIC_VOID) && 1066193323Sed "Should use MaskedValueIsZero if you don't know whether Op" 1067193323Sed " is a target node!"); 1068234353Sdim KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1069193323Sed} 1070193323Sed 1071193323Sed/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1072193323Sed/// targets that want to expose additional information about sign bits to the 1073193323Sed/// DAG Combiner. 1074193323Sedunsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1075193323Sed unsigned Depth) const { 1076193323Sed assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1077193323Sed Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1078193323Sed Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1079193323Sed Op.getOpcode() == ISD::INTRINSIC_VOID) && 1080193323Sed "Should use ComputeNumSignBits if you don't know whether Op" 1081193323Sed " is a target node!"); 1082193323Sed return 1; 1083193323Sed} 1084193323Sed 1085193323Sed/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1086193323Sed/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1087193323Sed/// determine which bit is set. 1088193323Sed/// 1089193323Sedstatic bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1090193323Sed // A left-shift of a constant one will have exactly one bit set, because 1091193323Sed // shifting the bit off the end is undefined. 1092193323Sed if (Val.getOpcode() == ISD::SHL) 1093193323Sed if (ConstantSDNode *C = 1094193323Sed dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1095193323Sed if (C->getAPIntValue() == 1) 1096193323Sed return true; 1097193323Sed 1098193323Sed // Similarly, a right-shift of a constant sign-bit will have exactly 1099193323Sed // one bit set. 1100193323Sed if (Val.getOpcode() == ISD::SRL) 1101193323Sed if (ConstantSDNode *C = 1102193323Sed dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1103193323Sed if (C->getAPIntValue().isSignBit()) 1104193323Sed return true; 1105193323Sed 1106193323Sed // More could be done here, though the above checks are enough 1107193323Sed // to handle some common cases. 1108193323Sed 1109193323Sed // Fall back to ComputeMaskedBits to catch other known cases. 1110198090Srdivacky EVT OpVT = Val.getValueType(); 1111204642Srdivacky unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1112193323Sed APInt KnownZero, KnownOne; 1113234353Sdim DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1114193323Sed return (KnownZero.countPopulation() == BitWidth - 1) && 1115193323Sed (KnownOne.countPopulation() == 1); 1116193323Sed} 1117193323Sed 1118218893Sdim/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1119193323Sed/// and cc. If it is unable to simplify it, return a null SDValue. 1120193323SedSDValue 1121198090SrdivackyTargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1122193323Sed ISD::CondCode Cond, bool foldBooleans, 1123263508Sdim DAGCombinerInfo &DCI, SDLoc dl) const { 1124193323Sed SelectionDAG &DAG = DCI.DAG; 1125193323Sed 1126193323Sed // These setcc operations always fold. 1127193323Sed switch (Cond) { 1128193323Sed default: break; 1129193323Sed case ISD::SETFALSE: 1130193323Sed case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1131193323Sed case ISD::SETTRUE: 1132263508Sdim case ISD::SETTRUE2: { 1133263508Sdim TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector()); 1134263508Sdim return DAG.getConstant( 1135263508Sdim Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT); 1136193323Sed } 1137263508Sdim } 1138193323Sed 1139221345Sdim // Ensure that the constant occurs on the RHS, and fold constant 1140221345Sdim // comparisons. 1141263508Sdim ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); 1142263508Sdim if (isa<ConstantSDNode>(N0.getNode()) && 1143263508Sdim (DCI.isBeforeLegalizeOps() || 1144263508Sdim isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) 1145263508Sdim return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); 1146224145Sdim 1147193323Sed if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1148193323Sed const APInt &C1 = N1C->getAPIntValue(); 1149198090Srdivacky 1150198090Srdivacky // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1151198090Srdivacky // equality comparison, then we're just comparing whether X itself is 1152198090Srdivacky // zero. 1153198090Srdivacky if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1154198090Srdivacky N0.getOperand(0).getOpcode() == ISD::CTLZ && 1155198090Srdivacky N0.getOperand(1).getOpcode() == ISD::Constant) { 1156202375Srdivacky const APInt &ShAmt 1157202375Srdivacky = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1158198090Srdivacky if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1159198090Srdivacky ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1160198090Srdivacky if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1161198090Srdivacky // (srl (ctlz x), 5) == 0 -> X != 0 1162198090Srdivacky // (srl (ctlz x), 5) != 1 -> X != 0 1163198090Srdivacky Cond = ISD::SETNE; 1164198090Srdivacky } else { 1165198090Srdivacky // (srl (ctlz x), 5) != 0 -> X == 0 1166198090Srdivacky // (srl (ctlz x), 5) == 1 -> X == 0 1167198090Srdivacky Cond = ISD::SETEQ; 1168193323Sed } 1169198090Srdivacky SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1170198090Srdivacky return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1171198090Srdivacky Zero, Cond); 1172193323Sed } 1173198090Srdivacky } 1174193323Sed 1175218893Sdim SDValue CTPOP = N0; 1176218893Sdim // Look through truncs that don't change the value of a ctpop. 1177218893Sdim if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1178218893Sdim CTPOP = N0.getOperand(0); 1179218893Sdim 1180218893Sdim if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1181218893Sdim (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1182218893Sdim Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1183218893Sdim EVT CTVT = CTPOP.getValueType(); 1184218893Sdim SDValue CTOp = CTPOP.getOperand(0); 1185218893Sdim 1186218893Sdim // (ctpop x) u< 2 -> (x & x-1) == 0 1187218893Sdim // (ctpop x) u> 1 -> (x & x-1) != 0 1188218893Sdim if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1189218893Sdim SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1190218893Sdim DAG.getConstant(1, CTVT)); 1191218893Sdim SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1192218893Sdim ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1193218893Sdim return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1194218893Sdim } 1195218893Sdim 1196218893Sdim // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1197218893Sdim } 1198218893Sdim 1199221345Sdim // (zext x) == C --> x == (trunc C) 1200221345Sdim if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1201221345Sdim (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1202221345Sdim unsigned MinBits = N0.getValueSizeInBits(); 1203221345Sdim SDValue PreZExt; 1204221345Sdim if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1205221345Sdim // ZExt 1206221345Sdim MinBits = N0->getOperand(0).getValueSizeInBits(); 1207221345Sdim PreZExt = N0->getOperand(0); 1208221345Sdim } else if (N0->getOpcode() == ISD::AND) { 1209221345Sdim // DAGCombine turns costly ZExts into ANDs 1210221345Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1211221345Sdim if ((C->getAPIntValue()+1).isPowerOf2()) { 1212221345Sdim MinBits = C->getAPIntValue().countTrailingOnes(); 1213221345Sdim PreZExt = N0->getOperand(0); 1214221345Sdim } 1215221345Sdim } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1216221345Sdim // ZEXTLOAD 1217221345Sdim if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1218221345Sdim MinBits = LN0->getMemoryVT().getSizeInBits(); 1219221345Sdim PreZExt = N0; 1220221345Sdim } 1221221345Sdim } 1222221345Sdim 1223239462Sdim // Make sure we're not losing bits from the constant. 1224263508Sdim if (MinBits > 0 && 1225263508Sdim MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) { 1226221345Sdim EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1227221345Sdim if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1228221345Sdim // Will get folded away. 1229221345Sdim SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 1230221345Sdim SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1231221345Sdim return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1232221345Sdim } 1233221345Sdim } 1234221345Sdim } 1235221345Sdim 1236198090Srdivacky // If the LHS is '(and load, const)', the RHS is 0, 1237198090Srdivacky // the test is for equality or unsigned, and all 1 bits of the const are 1238198090Srdivacky // in the same partial word, see if we can shorten the load. 1239198090Srdivacky if (DCI.isBeforeLegalize() && 1240263508Sdim !ISD::isSignedIntSetCC(Cond) && 1241198090Srdivacky N0.getOpcode() == ISD::AND && C1 == 0 && 1242198090Srdivacky N0.getNode()->hasOneUse() && 1243198090Srdivacky isa<LoadSDNode>(N0.getOperand(0)) && 1244198090Srdivacky N0.getOperand(0).getNode()->hasOneUse() && 1245198090Srdivacky isa<ConstantSDNode>(N0.getOperand(1))) { 1246198090Srdivacky LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1247202375Srdivacky APInt bestMask; 1248198090Srdivacky unsigned bestWidth = 0, bestOffset = 0; 1249202375Srdivacky if (!Lod->isVolatile() && Lod->isUnindexed()) { 1250198090Srdivacky unsigned origWidth = N0.getValueType().getSizeInBits(); 1251202375Srdivacky unsigned maskWidth = origWidth; 1252218893Sdim // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1253198090Srdivacky // 8 bits, but have to be careful... 1254198090Srdivacky if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1255198090Srdivacky origWidth = Lod->getMemoryVT().getSizeInBits(); 1256202375Srdivacky const APInt &Mask = 1257202375Srdivacky cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1258198090Srdivacky for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1259202375Srdivacky APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1260198090Srdivacky for (unsigned offset=0; offset<origWidth/width; offset++) { 1261198090Srdivacky if ((newMask & Mask) == Mask) { 1262249423Sdim if (!getDataLayout()->isLittleEndian()) 1263198090Srdivacky bestOffset = (origWidth/width - offset - 1) * (width/8); 1264198090Srdivacky else 1265198090Srdivacky bestOffset = (uint64_t)offset * (width/8); 1266202375Srdivacky bestMask = Mask.lshr(offset * (width/8) * 8); 1267198090Srdivacky bestWidth = width; 1268198090Srdivacky break; 1269193323Sed } 1270198090Srdivacky newMask = newMask << width; 1271193323Sed } 1272193323Sed } 1273198090Srdivacky } 1274198090Srdivacky if (bestWidth) { 1275221345Sdim EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 1276198090Srdivacky if (newVT.isRound()) { 1277198090Srdivacky EVT PtrType = Lod->getOperand(1).getValueType(); 1278198090Srdivacky SDValue Ptr = Lod->getBasePtr(); 1279198090Srdivacky if (bestOffset != 0) 1280198090Srdivacky Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1281198090Srdivacky DAG.getConstant(bestOffset, PtrType)); 1282198090Srdivacky unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1283198090Srdivacky SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1284218893Sdim Lod->getPointerInfo().getWithOffset(bestOffset), 1285234353Sdim false, false, false, NewAlign); 1286218893Sdim return DAG.getSetCC(dl, VT, 1287198090Srdivacky DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1288202375Srdivacky DAG.getConstant(bestMask.trunc(bestWidth), 1289202375Srdivacky newVT)), 1290198090Srdivacky DAG.getConstant(0LL, newVT), Cond); 1291193323Sed } 1292193323Sed } 1293198090Srdivacky } 1294193323Sed 1295198090Srdivacky // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1296198090Srdivacky if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1297198090Srdivacky unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1298193323Sed 1299198090Srdivacky // If the comparison constant has bits in the upper part, the 1300198090Srdivacky // zero-extended value could never match. 1301198090Srdivacky if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1302198090Srdivacky C1.getBitWidth() - InSize))) { 1303193323Sed switch (Cond) { 1304193323Sed case ISD::SETUGT: 1305193323Sed case ISD::SETUGE: 1306198090Srdivacky case ISD::SETEQ: return DAG.getConstant(0, VT); 1307193323Sed case ISD::SETULT: 1308193323Sed case ISD::SETULE: 1309198090Srdivacky case ISD::SETNE: return DAG.getConstant(1, VT); 1310198090Srdivacky case ISD::SETGT: 1311198090Srdivacky case ISD::SETGE: 1312198090Srdivacky // True if the sign bit of C1 is set. 1313198090Srdivacky return DAG.getConstant(C1.isNegative(), VT); 1314198090Srdivacky case ISD::SETLT: 1315198090Srdivacky case ISD::SETLE: 1316198090Srdivacky // True if the sign bit of C1 isn't set. 1317198090Srdivacky return DAG.getConstant(C1.isNonNegative(), VT); 1318193323Sed default: 1319198090Srdivacky break; 1320193323Sed } 1321198090Srdivacky } 1322193323Sed 1323198090Srdivacky // Otherwise, we can perform the comparison with the low bits. 1324198090Srdivacky switch (Cond) { 1325198090Srdivacky case ISD::SETEQ: 1326198090Srdivacky case ISD::SETNE: 1327198090Srdivacky case ISD::SETUGT: 1328198090Srdivacky case ISD::SETUGE: 1329198090Srdivacky case ISD::SETULT: 1330198090Srdivacky case ISD::SETULE: { 1331198090Srdivacky EVT newVT = N0.getOperand(0).getValueType(); 1332198090Srdivacky if (DCI.isBeforeLegalizeOps() || 1333198090Srdivacky (isOperationLegal(ISD::SETCC, newVT) && 1334249423Sdim getCondCodeAction(Cond, newVT.getSimpleVT())==Legal)) 1335198090Srdivacky return DAG.getSetCC(dl, VT, N0.getOperand(0), 1336218893Sdim DAG.getConstant(C1.trunc(InSize), newVT), 1337198090Srdivacky Cond); 1338198090Srdivacky break; 1339193323Sed } 1340198090Srdivacky default: 1341198090Srdivacky break; // todo, be more careful with signed comparisons 1342198090Srdivacky } 1343198090Srdivacky } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1344204642Srdivacky (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1345198090Srdivacky EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1346198090Srdivacky unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1347198090Srdivacky EVT ExtDstTy = N0.getValueType(); 1348198090Srdivacky unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1349198090Srdivacky 1350212904Sdim // If the constant doesn't fit into the number of bits for the source of 1351212904Sdim // the sign extension, it is impossible for both sides to be equal. 1352212904Sdim if (C1.getMinSignedBits() > ExtSrcTyBits) 1353198090Srdivacky return DAG.getConstant(Cond == ISD::SETNE, VT); 1354218893Sdim 1355198090Srdivacky SDValue ZextOp; 1356198090Srdivacky EVT Op0Ty = N0.getOperand(0).getValueType(); 1357198090Srdivacky if (Op0Ty == ExtSrcTy) { 1358198090Srdivacky ZextOp = N0.getOperand(0); 1359193323Sed } else { 1360198090Srdivacky APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1361198090Srdivacky ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1362198090Srdivacky DAG.getConstant(Imm, Op0Ty)); 1363193323Sed } 1364198090Srdivacky if (!DCI.isCalledByLegalizer()) 1365198090Srdivacky DCI.AddToWorklist(ZextOp.getNode()); 1366198090Srdivacky // Otherwise, make this a use of a zext. 1367218893Sdim return DAG.getSetCC(dl, VT, ZextOp, 1368198090Srdivacky DAG.getConstant(C1 & APInt::getLowBitsSet( 1369198090Srdivacky ExtDstTyBits, 1370218893Sdim ExtSrcTyBits), 1371198090Srdivacky ExtDstTy), 1372198090Srdivacky Cond); 1373198090Srdivacky } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1374198090Srdivacky (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1375198090Srdivacky // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1376204642Srdivacky if (N0.getOpcode() == ISD::SETCC && 1377204642Srdivacky isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1378202375Srdivacky bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1379198090Srdivacky if (TrueWhenTrue) 1380218893Sdim return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1381198090Srdivacky // Invert the condition. 1382198090Srdivacky ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1383218893Sdim CC = ISD::getSetCCInverse(CC, 1384198090Srdivacky N0.getOperand(0).getValueType().isInteger()); 1385263508Sdim if (DCI.isBeforeLegalizeOps() || 1386263508Sdim isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) 1387263508Sdim return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1388193323Sed } 1389204642Srdivacky 1390198090Srdivacky if ((N0.getOpcode() == ISD::XOR || 1391218893Sdim (N0.getOpcode() == ISD::AND && 1392198090Srdivacky N0.getOperand(0).getOpcode() == ISD::XOR && 1393198090Srdivacky N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1394198090Srdivacky isa<ConstantSDNode>(N0.getOperand(1)) && 1395198090Srdivacky cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1396198090Srdivacky // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1397198090Srdivacky // can only do this if the top bits are known zero. 1398198090Srdivacky unsigned BitWidth = N0.getValueSizeInBits(); 1399198090Srdivacky if (DAG.MaskedValueIsZero(N0, 1400198090Srdivacky APInt::getHighBitsSet(BitWidth, 1401198090Srdivacky BitWidth-1))) { 1402198090Srdivacky // Okay, get the un-inverted input value. 1403198090Srdivacky SDValue Val; 1404198090Srdivacky if (N0.getOpcode() == ISD::XOR) 1405198090Srdivacky Val = N0.getOperand(0); 1406198090Srdivacky else { 1407218893Sdim assert(N0.getOpcode() == ISD::AND && 1408198090Srdivacky N0.getOperand(0).getOpcode() == ISD::XOR); 1409198090Srdivacky // ((X^1)&1)^1 -> X & 1 1410198090Srdivacky Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1411198090Srdivacky N0.getOperand(0).getOperand(0), 1412198090Srdivacky N0.getOperand(1)); 1413198090Srdivacky } 1414204642Srdivacky 1415198090Srdivacky return DAG.getSetCC(dl, VT, Val, N1, 1416198090Srdivacky Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1417198090Srdivacky } 1418204642Srdivacky } else if (N1C->getAPIntValue() == 1 && 1419204642Srdivacky (VT == MVT::i1 || 1420226633Sdim getBooleanContents(false) == ZeroOrOneBooleanContent)) { 1421204642Srdivacky SDValue Op0 = N0; 1422204642Srdivacky if (Op0.getOpcode() == ISD::TRUNCATE) 1423204642Srdivacky Op0 = Op0.getOperand(0); 1424204642Srdivacky 1425204642Srdivacky if ((Op0.getOpcode() == ISD::XOR) && 1426204642Srdivacky Op0.getOperand(0).getOpcode() == ISD::SETCC && 1427204642Srdivacky Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1428204642Srdivacky // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1429204642Srdivacky Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1430204642Srdivacky return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1431204642Srdivacky Cond); 1432249423Sdim } 1433249423Sdim if (Op0.getOpcode() == ISD::AND && 1434249423Sdim isa<ConstantSDNode>(Op0.getOperand(1)) && 1435249423Sdim cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1436204642Srdivacky // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1437207618Srdivacky if (Op0.getValueType().bitsGT(VT)) 1438204642Srdivacky Op0 = DAG.getNode(ISD::AND, dl, VT, 1439204642Srdivacky DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1440204642Srdivacky DAG.getConstant(1, VT)); 1441207618Srdivacky else if (Op0.getValueType().bitsLT(VT)) 1442207618Srdivacky Op0 = DAG.getNode(ISD::AND, dl, VT, 1443207618Srdivacky DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1444207618Srdivacky DAG.getConstant(1, VT)); 1445207618Srdivacky 1446204642Srdivacky return DAG.getSetCC(dl, VT, Op0, 1447204642Srdivacky DAG.getConstant(0, Op0.getValueType()), 1448204642Srdivacky Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1449204642Srdivacky } 1450249423Sdim if (Op0.getOpcode() == ISD::AssertZext && 1451249423Sdim cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) 1452249423Sdim return DAG.getSetCC(dl, VT, Op0, 1453249423Sdim DAG.getConstant(0, Op0.getValueType()), 1454249423Sdim Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1455193323Sed } 1456198090Srdivacky } 1457218893Sdim 1458198090Srdivacky APInt MinVal, MaxVal; 1459198090Srdivacky unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1460198090Srdivacky if (ISD::isSignedIntSetCC(Cond)) { 1461198090Srdivacky MinVal = APInt::getSignedMinValue(OperandBitSize); 1462198090Srdivacky MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1463198090Srdivacky } else { 1464198090Srdivacky MinVal = APInt::getMinValue(OperandBitSize); 1465198090Srdivacky MaxVal = APInt::getMaxValue(OperandBitSize); 1466198090Srdivacky } 1467193323Sed 1468198090Srdivacky // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1469198090Srdivacky if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1470198090Srdivacky if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1471198090Srdivacky // X >= C0 --> X > (C0-1) 1472218893Sdim return DAG.getSetCC(dl, VT, N0, 1473198090Srdivacky DAG.getConstant(C1-1, N1.getValueType()), 1474198090Srdivacky (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1475198090Srdivacky } 1476193323Sed 1477198090Srdivacky if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1478198090Srdivacky if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1479198090Srdivacky // X <= C0 --> X < (C0+1) 1480218893Sdim return DAG.getSetCC(dl, VT, N0, 1481198090Srdivacky DAG.getConstant(C1+1, N1.getValueType()), 1482198090Srdivacky (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1483198090Srdivacky } 1484193323Sed 1485198090Srdivacky if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1486198090Srdivacky return DAG.getConstant(0, VT); // X < MIN --> false 1487198090Srdivacky if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1488198090Srdivacky return DAG.getConstant(1, VT); // X >= MIN --> true 1489198090Srdivacky if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1490198090Srdivacky return DAG.getConstant(0, VT); // X > MAX --> false 1491198090Srdivacky if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1492198090Srdivacky return DAG.getConstant(1, VT); // X <= MAX --> true 1493193323Sed 1494198090Srdivacky // Canonicalize setgt X, Min --> setne X, Min 1495198090Srdivacky if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1496198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1497198090Srdivacky // Canonicalize setlt X, Max --> setne X, Max 1498198090Srdivacky if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1499198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1500193323Sed 1501198090Srdivacky // If we have setult X, 1, turn it into seteq X, 0 1502198090Srdivacky if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1503218893Sdim return DAG.getSetCC(dl, VT, N0, 1504218893Sdim DAG.getConstant(MinVal, N0.getValueType()), 1505198090Srdivacky ISD::SETEQ); 1506198090Srdivacky // If we have setugt X, Max-1, turn it into seteq X, Max 1507249423Sdim if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1508218893Sdim return DAG.getSetCC(dl, VT, N0, 1509198090Srdivacky DAG.getConstant(MaxVal, N0.getValueType()), 1510198090Srdivacky ISD::SETEQ); 1511193323Sed 1512198090Srdivacky // If we have "setcc X, C0", check to see if we can shrink the immediate 1513198090Srdivacky // by changing cc. 1514193323Sed 1515198090Srdivacky // SETUGT X, SINTMAX -> SETLT X, 0 1516218893Sdim if (Cond == ISD::SETUGT && 1517198090Srdivacky C1 == APInt::getSignedMaxValue(OperandBitSize)) 1518218893Sdim return DAG.getSetCC(dl, VT, N0, 1519198090Srdivacky DAG.getConstant(0, N1.getValueType()), 1520198090Srdivacky ISD::SETLT); 1521198090Srdivacky 1522198090Srdivacky // SETULT X, SINTMIN -> SETGT X, -1 1523198090Srdivacky if (Cond == ISD::SETULT && 1524198090Srdivacky C1 == APInt::getSignedMinValue(OperandBitSize)) { 1525198090Srdivacky SDValue ConstMinusOne = 1526198090Srdivacky DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1527198090Srdivacky N1.getValueType()); 1528198090Srdivacky return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1529198090Srdivacky } 1530198090Srdivacky 1531198090Srdivacky // Fold bit comparisons when we can. 1532198090Srdivacky if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1533202375Srdivacky (VT == N0.getValueType() || 1534202375Srdivacky (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1535202375Srdivacky N0.getOpcode() == ISD::AND) 1536198090Srdivacky if (ConstantSDNode *AndRHS = 1537198090Srdivacky dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1538239462Sdim EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1539219077Sdim getPointerTy() : getShiftAmountTy(N0.getValueType()); 1540198090Srdivacky if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1541198090Srdivacky // Perform the xform if the AND RHS is a single bit. 1542202375Srdivacky if (AndRHS->getAPIntValue().isPowerOf2()) { 1543202375Srdivacky return DAG.getNode(ISD::TRUNCATE, dl, VT, 1544202375Srdivacky DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1545202375Srdivacky DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1546193323Sed } 1547202375Srdivacky } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1548198090Srdivacky // (X & 8) == 8 --> (X & 8) >> 3 1549198090Srdivacky // Perform the xform if C1 is a single bit. 1550198090Srdivacky if (C1.isPowerOf2()) { 1551202375Srdivacky return DAG.getNode(ISD::TRUNCATE, dl, VT, 1552202375Srdivacky DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1553202375Srdivacky DAG.getConstant(C1.logBase2(), ShiftTy))); 1554198090Srdivacky } 1555193323Sed } 1556198090Srdivacky } 1557239462Sdim 1558239462Sdim if (C1.getMinSignedBits() <= 64 && 1559239462Sdim !isLegalICmpImmediate(C1.getSExtValue())) { 1560239462Sdim // (X & -256) == 256 -> (X >> 8) == 1 1561239462Sdim if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1562239462Sdim N0.getOpcode() == ISD::AND && N0.hasOneUse()) { 1563239462Sdim if (ConstantSDNode *AndRHS = 1564239462Sdim dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1565239462Sdim const APInt &AndRHSC = AndRHS->getAPIntValue(); 1566239462Sdim if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { 1567239462Sdim unsigned ShiftBits = AndRHSC.countTrailingZeros(); 1568239462Sdim EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1569239462Sdim getPointerTy() : getShiftAmountTy(N0.getValueType()); 1570239462Sdim EVT CmpTy = N0.getValueType(); 1571239462Sdim SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), 1572239462Sdim DAG.getConstant(ShiftBits, ShiftTy)); 1573239462Sdim SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); 1574239462Sdim return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 1575239462Sdim } 1576239462Sdim } 1577239462Sdim } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || 1578239462Sdim Cond == ISD::SETULE || Cond == ISD::SETUGT) { 1579239462Sdim bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); 1580239462Sdim // X < 0x100000000 -> (X >> 32) < 1 1581239462Sdim // X >= 0x100000000 -> (X >> 32) >= 1 1582239462Sdim // X <= 0x0ffffffff -> (X >> 32) < 1 1583239462Sdim // X > 0x0ffffffff -> (X >> 32) >= 1 1584239462Sdim unsigned ShiftBits; 1585239462Sdim APInt NewC = C1; 1586239462Sdim ISD::CondCode NewCond = Cond; 1587239462Sdim if (AdjOne) { 1588239462Sdim ShiftBits = C1.countTrailingOnes(); 1589239462Sdim NewC = NewC + 1; 1590239462Sdim NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1591239462Sdim } else { 1592239462Sdim ShiftBits = C1.countTrailingZeros(); 1593239462Sdim } 1594239462Sdim NewC = NewC.lshr(ShiftBits); 1595239462Sdim if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { 1596239462Sdim EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1597239462Sdim getPointerTy() : getShiftAmountTy(N0.getValueType()); 1598239462Sdim EVT CmpTy = N0.getValueType(); 1599239462Sdim SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, 1600239462Sdim DAG.getConstant(ShiftBits, ShiftTy)); 1601239462Sdim SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); 1602239462Sdim return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 1603239462Sdim } 1604239462Sdim } 1605239462Sdim } 1606193323Sed } 1607193323Sed 1608193323Sed if (isa<ConstantFPSDNode>(N0.getNode())) { 1609193323Sed // Constant fold or commute setcc. 1610193323Sed SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1611193323Sed if (O.getNode()) return O; 1612193323Sed } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1613193323Sed // If the RHS of an FP comparison is a constant, simplify it away in 1614193323Sed // some cases. 1615193323Sed if (CFP->getValueAPF().isNaN()) { 1616193323Sed // If an operand is known to be a nan, we can fold it. 1617193323Sed switch (ISD::getUnorderedFlavor(Cond)) { 1618198090Srdivacky default: llvm_unreachable("Unknown flavor!"); 1619193323Sed case 0: // Known false. 1620193323Sed return DAG.getConstant(0, VT); 1621193323Sed case 1: // Known true. 1622193323Sed return DAG.getConstant(1, VT); 1623193323Sed case 2: // Undefined. 1624193323Sed return DAG.getUNDEF(VT); 1625193323Sed } 1626193323Sed } 1627218893Sdim 1628193323Sed // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1629193323Sed // constant if knowing that the operand is non-nan is enough. We prefer to 1630193323Sed // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1631193323Sed // materialize 0.0. 1632193323Sed if (Cond == ISD::SETO || Cond == ISD::SETUO) 1633193323Sed return DAG.getSetCC(dl, VT, N0, N0, Cond); 1634198090Srdivacky 1635198090Srdivacky // If the condition is not legal, see if we can find an equivalent one 1636198090Srdivacky // which is legal. 1637249423Sdim if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1638198090Srdivacky // If the comparison was an awkward floating-point == or != and one of 1639198090Srdivacky // the comparison operands is infinity or negative infinity, convert the 1640198090Srdivacky // condition to a less-awkward <= or >=. 1641198090Srdivacky if (CFP->getValueAPF().isInfinity()) { 1642198090Srdivacky if (CFP->getValueAPF().isNegative()) { 1643198090Srdivacky if (Cond == ISD::SETOEQ && 1644249423Sdim isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1645198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 1646198090Srdivacky if (Cond == ISD::SETUEQ && 1647249423Sdim isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1648198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 1649198090Srdivacky if (Cond == ISD::SETUNE && 1650249423Sdim isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1651198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 1652198090Srdivacky if (Cond == ISD::SETONE && 1653249423Sdim isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1654198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 1655198090Srdivacky } else { 1656198090Srdivacky if (Cond == ISD::SETOEQ && 1657249423Sdim isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1658198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 1659198090Srdivacky if (Cond == ISD::SETUEQ && 1660249423Sdim isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1661198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 1662198090Srdivacky if (Cond == ISD::SETUNE && 1663249423Sdim isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1664198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 1665198090Srdivacky if (Cond == ISD::SETONE && 1666249423Sdim isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1667198090Srdivacky return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 1668198090Srdivacky } 1669198090Srdivacky } 1670198090Srdivacky } 1671193323Sed } 1672193323Sed 1673193323Sed if (N0 == N1) { 1674239462Sdim // The sext(setcc()) => setcc() optimization relies on the appropriate 1675239462Sdim // constant being emitted. 1676243830Sdim uint64_t EqVal = 0; 1677239462Sdim switch (getBooleanContents(N0.getValueType().isVector())) { 1678239462Sdim case UndefinedBooleanContent: 1679239462Sdim case ZeroOrOneBooleanContent: 1680239462Sdim EqVal = ISD::isTrueWhenEqual(Cond); 1681239462Sdim break; 1682239462Sdim case ZeroOrNegativeOneBooleanContent: 1683239462Sdim EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; 1684239462Sdim break; 1685239462Sdim } 1686239462Sdim 1687193323Sed // We can always fold X == X for integer setcc's. 1688234353Sdim if (N0.getValueType().isInteger()) { 1689239462Sdim return DAG.getConstant(EqVal, VT); 1690234353Sdim } 1691193323Sed unsigned UOF = ISD::getUnorderedFlavor(Cond); 1692193323Sed if (UOF == 2) // FP operators that are undefined on NaNs. 1693239462Sdim return DAG.getConstant(EqVal, VT); 1694193323Sed if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1695239462Sdim return DAG.getConstant(EqVal, VT); 1696193323Sed // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1697193323Sed // if it is not already. 1698193323Sed ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1699239462Sdim if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || 1700249423Sdim getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) 1701193323Sed return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1702193323Sed } 1703193323Sed 1704193323Sed if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1705193323Sed N0.getValueType().isInteger()) { 1706193323Sed if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1707193323Sed N0.getOpcode() == ISD::XOR) { 1708193323Sed // Simplify (X+Y) == (X+Z) --> Y == Z 1709193323Sed if (N0.getOpcode() == N1.getOpcode()) { 1710193323Sed if (N0.getOperand(0) == N1.getOperand(0)) 1711193323Sed return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1712193323Sed if (N0.getOperand(1) == N1.getOperand(1)) 1713193323Sed return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1714193323Sed if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1715193323Sed // If X op Y == Y op X, try other combinations. 1716193323Sed if (N0.getOperand(0) == N1.getOperand(1)) 1717218893Sdim return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1718193323Sed Cond); 1719193323Sed if (N0.getOperand(1) == N1.getOperand(0)) 1720218893Sdim return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1721193323Sed Cond); 1722193323Sed } 1723193323Sed } 1724218893Sdim 1725234353Sdim // If RHS is a legal immediate value for a compare instruction, we need 1726234353Sdim // to be careful about increasing register pressure needlessly. 1727234353Sdim bool LegalRHSImm = false; 1728234353Sdim 1729193323Sed if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1730193323Sed if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1731193323Sed // Turn (X+C1) == C2 --> X == C2-C1 1732193323Sed if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1733193323Sed return DAG.getSetCC(dl, VT, N0.getOperand(0), 1734193323Sed DAG.getConstant(RHSC->getAPIntValue()- 1735193323Sed LHSR->getAPIntValue(), 1736193323Sed N0.getValueType()), Cond); 1737193323Sed } 1738218893Sdim 1739193323Sed // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1740193323Sed if (N0.getOpcode() == ISD::XOR) 1741193323Sed // If we know that all of the inverted bits are zero, don't bother 1742193323Sed // performing the inversion. 1743193323Sed if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1744193323Sed return 1745193323Sed DAG.getSetCC(dl, VT, N0.getOperand(0), 1746193323Sed DAG.getConstant(LHSR->getAPIntValue() ^ 1747193323Sed RHSC->getAPIntValue(), 1748193323Sed N0.getValueType()), 1749193323Sed Cond); 1750193323Sed } 1751218893Sdim 1752193323Sed // Turn (C1-X) == C2 --> X == C1-C2 1753193323Sed if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1754193323Sed if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1755193323Sed return 1756193323Sed DAG.getSetCC(dl, VT, N0.getOperand(1), 1757193323Sed DAG.getConstant(SUBC->getAPIntValue() - 1758193323Sed RHSC->getAPIntValue(), 1759193323Sed N0.getValueType()), 1760193323Sed Cond); 1761193323Sed } 1762218893Sdim } 1763234353Sdim 1764234353Sdim // Could RHSC fold directly into a compare? 1765234353Sdim if (RHSC->getValueType(0).getSizeInBits() <= 64) 1766234353Sdim LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 1767193323Sed } 1768193323Sed 1769193323Sed // Simplify (X+Z) == X --> Z == 0 1770234353Sdim // Don't do this if X is an immediate that can fold into a cmp 1771234353Sdim // instruction and X+Z has other uses. It could be an induction variable 1772234353Sdim // chain, and the transform would increase register pressure. 1773234353Sdim if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 1774234353Sdim if (N0.getOperand(0) == N1) 1775234353Sdim return DAG.getSetCC(dl, VT, N0.getOperand(1), 1776234353Sdim DAG.getConstant(0, N0.getValueType()), Cond); 1777234353Sdim if (N0.getOperand(1) == N1) { 1778234353Sdim if (DAG.isCommutativeBinOp(N0.getOpcode())) 1779234353Sdim return DAG.getSetCC(dl, VT, N0.getOperand(0), 1780234353Sdim DAG.getConstant(0, N0.getValueType()), Cond); 1781249423Sdim if (N0.getNode()->hasOneUse()) { 1782234353Sdim assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1783234353Sdim // (Z-X) == X --> Z == X<<1 1784234353Sdim SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 1785219077Sdim DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 1786234353Sdim if (!DCI.isCalledByLegalizer()) 1787234353Sdim DCI.AddToWorklist(SH.getNode()); 1788234353Sdim return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1789234353Sdim } 1790193323Sed } 1791193323Sed } 1792193323Sed } 1793193323Sed 1794193323Sed if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1795193323Sed N1.getOpcode() == ISD::XOR) { 1796193323Sed // Simplify X == (X+Z) --> Z == 0 1797249423Sdim if (N1.getOperand(0) == N0) 1798193323Sed return DAG.getSetCC(dl, VT, N1.getOperand(1), 1799193323Sed DAG.getConstant(0, N1.getValueType()), Cond); 1800249423Sdim if (N1.getOperand(1) == N0) { 1801249423Sdim if (DAG.isCommutativeBinOp(N1.getOpcode())) 1802193323Sed return DAG.getSetCC(dl, VT, N1.getOperand(0), 1803193323Sed DAG.getConstant(0, N1.getValueType()), Cond); 1804249423Sdim if (N1.getNode()->hasOneUse()) { 1805193323Sed assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1806193323Sed // X == (Z-X) --> X<<1 == Z 1807218893Sdim SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1808219077Sdim DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 1809193323Sed if (!DCI.isCalledByLegalizer()) 1810193323Sed DCI.AddToWorklist(SH.getNode()); 1811193323Sed return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1812193323Sed } 1813193323Sed } 1814193323Sed } 1815193323Sed 1816193323Sed // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1817193323Sed // Note that where y is variable and is known to have at most 1818193323Sed // one bit set (for example, if it is z&1) we cannot do this; 1819193323Sed // the expressions are not equivalent when y==0. 1820193323Sed if (N0.getOpcode() == ISD::AND) 1821193323Sed if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1822193323Sed if (ValueHasExactlyOneBitSet(N1, DAG)) { 1823193323Sed Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1824263508Sdim if (DCI.isBeforeLegalizeOps() || 1825263508Sdim isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1826263508Sdim SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1827263508Sdim return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1828263508Sdim } 1829193323Sed } 1830193323Sed } 1831193323Sed if (N1.getOpcode() == ISD::AND) 1832193323Sed if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1833193323Sed if (ValueHasExactlyOneBitSet(N0, DAG)) { 1834193323Sed Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1835263508Sdim if (DCI.isBeforeLegalizeOps() || 1836263508Sdim isCondCodeLegal(Cond, N1.getSimpleValueType())) { 1837263508Sdim SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1838263508Sdim return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1839263508Sdim } 1840193323Sed } 1841193323Sed } 1842193323Sed } 1843193323Sed 1844193323Sed // Fold away ALL boolean setcc's. 1845193323Sed SDValue Temp; 1846193323Sed if (N0.getValueType() == MVT::i1 && foldBooleans) { 1847193323Sed switch (Cond) { 1848198090Srdivacky default: llvm_unreachable("Unknown integer setcc!"); 1849193323Sed case ISD::SETEQ: // X == Y -> ~(X^Y) 1850193323Sed Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1851193323Sed N0 = DAG.getNOT(dl, Temp, MVT::i1); 1852193323Sed if (!DCI.isCalledByLegalizer()) 1853193323Sed DCI.AddToWorklist(Temp.getNode()); 1854193323Sed break; 1855193323Sed case ISD::SETNE: // X != Y --> (X^Y) 1856193323Sed N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1857193323Sed break; 1858193323Sed case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1859193323Sed case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1860193323Sed Temp = DAG.getNOT(dl, N0, MVT::i1); 1861193323Sed N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 1862193323Sed if (!DCI.isCalledByLegalizer()) 1863193323Sed DCI.AddToWorklist(Temp.getNode()); 1864193323Sed break; 1865193323Sed case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1866193323Sed case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1867193323Sed Temp = DAG.getNOT(dl, N1, MVT::i1); 1868193323Sed N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 1869193323Sed if (!DCI.isCalledByLegalizer()) 1870193323Sed DCI.AddToWorklist(Temp.getNode()); 1871193323Sed break; 1872193323Sed case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 1873193323Sed case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 1874193323Sed Temp = DAG.getNOT(dl, N0, MVT::i1); 1875193323Sed N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 1876193323Sed if (!DCI.isCalledByLegalizer()) 1877193323Sed DCI.AddToWorklist(Temp.getNode()); 1878193323Sed break; 1879193323Sed case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 1880193323Sed case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 1881193323Sed Temp = DAG.getNOT(dl, N1, MVT::i1); 1882193323Sed N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 1883193323Sed break; 1884193323Sed } 1885193323Sed if (VT != MVT::i1) { 1886193323Sed if (!DCI.isCalledByLegalizer()) 1887193323Sed DCI.AddToWorklist(N0.getNode()); 1888193323Sed // FIXME: If running after legalize, we probably can't do this. 1889193323Sed N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 1890193323Sed } 1891193323Sed return N0; 1892193323Sed } 1893193323Sed 1894193323Sed // Could not fold it. 1895193323Sed return SDValue(); 1896193323Sed} 1897193323Sed 1898193323Sed/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1899193323Sed/// node is a GlobalAddress + offset. 1900218893Sdimbool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 1901193323Sed int64_t &Offset) const { 1902193323Sed if (isa<GlobalAddressSDNode>(N)) { 1903193323Sed GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1904193323Sed GA = GASD->getGlobal(); 1905193323Sed Offset += GASD->getOffset(); 1906193323Sed return true; 1907193323Sed } 1908193323Sed 1909193323Sed if (N->getOpcode() == ISD::ADD) { 1910193323Sed SDValue N1 = N->getOperand(0); 1911193323Sed SDValue N2 = N->getOperand(1); 1912193323Sed if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1913193323Sed ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1914193323Sed if (V) { 1915193323Sed Offset += V->getSExtValue(); 1916193323Sed return true; 1917193323Sed } 1918193323Sed } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1919193323Sed ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1920193323Sed if (V) { 1921193323Sed Offset += V->getSExtValue(); 1922193323Sed return true; 1923193323Sed } 1924193323Sed } 1925193323Sed } 1926219077Sdim 1927193323Sed return false; 1928193323Sed} 1929193323Sed 1930193323Sed 1931193323SedSDValue TargetLowering:: 1932193323SedPerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1933193323Sed // Default implementation: no optimization. 1934193323Sed return SDValue(); 1935193323Sed} 1936193323Sed 1937193323Sed//===----------------------------------------------------------------------===// 1938193323Sed// Inline Assembler Implementation Methods 1939193323Sed//===----------------------------------------------------------------------===// 1940193323Sed 1941193323Sed 1942193323SedTargetLowering::ConstraintType 1943193323SedTargetLowering::getConstraintType(const std::string &Constraint) const { 1944249423Sdim unsigned S = Constraint.size(); 1945249423Sdim 1946249423Sdim if (S == 1) { 1947193323Sed switch (Constraint[0]) { 1948193323Sed default: break; 1949193323Sed case 'r': return C_RegisterClass; 1950193323Sed case 'm': // memory 1951193323Sed case 'o': // offsetable 1952193323Sed case 'V': // not offsetable 1953193323Sed return C_Memory; 1954193323Sed case 'i': // Simple Integer or Relocatable Constant 1955193323Sed case 'n': // Simple Integer 1956218893Sdim case 'E': // Floating Point Constant 1957218893Sdim case 'F': // Floating Point Constant 1958193323Sed case 's': // Relocatable Constant 1959218893Sdim case 'p': // Address. 1960193323Sed case 'X': // Allow ANY value. 1961193323Sed case 'I': // Target registers. 1962193323Sed case 'J': 1963193323Sed case 'K': 1964193323Sed case 'L': 1965193323Sed case 'M': 1966193323Sed case 'N': 1967193323Sed case 'O': 1968193323Sed case 'P': 1969218893Sdim case '<': 1970218893Sdim case '>': 1971193323Sed return C_Other; 1972193323Sed } 1973193323Sed } 1974218893Sdim 1975249423Sdim if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { 1976249423Sdim if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}" 1977249423Sdim return C_Memory; 1978193323Sed return C_Register; 1979249423Sdim } 1980193323Sed return C_Unknown; 1981193323Sed} 1982193323Sed 1983193323Sed/// LowerXConstraint - try to replace an X constraint, which matches anything, 1984193323Sed/// with another that has more specific requirements based on the type of the 1985193323Sed/// corresponding operand. 1986198090Srdivackyconst char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 1987193323Sed if (ConstraintVT.isInteger()) 1988193323Sed return "r"; 1989193323Sed if (ConstraintVT.isFloatingPoint()) 1990193323Sed return "f"; // works for many targets 1991193323Sed return 0; 1992193323Sed} 1993193323Sed 1994193323Sed/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1995193323Sed/// vector. If it is invalid, don't add anything to Ops. 1996193323Sedvoid TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1997223017Sdim std::string &Constraint, 1998193323Sed std::vector<SDValue> &Ops, 1999193323Sed SelectionDAG &DAG) const { 2000224145Sdim 2001223017Sdim if (Constraint.length() > 1) return; 2002224145Sdim 2003223017Sdim char ConstraintLetter = Constraint[0]; 2004193323Sed switch (ConstraintLetter) { 2005193323Sed default: break; 2006193323Sed case 'X': // Allows any operand; labels (basic block) use this. 2007193323Sed if (Op.getOpcode() == ISD::BasicBlock) { 2008193323Sed Ops.push_back(Op); 2009193323Sed return; 2010193323Sed } 2011193323Sed // fall through 2012193323Sed case 'i': // Simple Integer or Relocatable Constant 2013193323Sed case 'n': // Simple Integer 2014193323Sed case 's': { // Relocatable Constant 2015193323Sed // These operands are interested in values of the form (GV+C), where C may 2016193323Sed // be folded in as an offset of GV, or it may be explicitly added. Also, it 2017193323Sed // is possible and fine if either GV or C are missing. 2018193323Sed ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2019193323Sed GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2020218893Sdim 2021193323Sed // If we have "(add GV, C)", pull out GV/C 2022193323Sed if (Op.getOpcode() == ISD::ADD) { 2023193323Sed C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2024193323Sed GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2025193323Sed if (C == 0 || GA == 0) { 2026193323Sed C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2027193323Sed GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2028193323Sed } 2029193323Sed if (C == 0 || GA == 0) 2030193323Sed C = 0, GA = 0; 2031193323Sed } 2032218893Sdim 2033193323Sed // If we find a valid operand, map to the TargetXXX version so that the 2034193323Sed // value itself doesn't get selected. 2035193323Sed if (GA) { // Either &GV or &GV+C 2036193323Sed if (ConstraintLetter != 'n') { 2037193323Sed int64_t Offs = GA->getOffset(); 2038193323Sed if (C) Offs += C->getZExtValue(); 2039218893Sdim Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2040263508Sdim C ? SDLoc(C) : SDLoc(), 2041193323Sed Op.getValueType(), Offs)); 2042193323Sed return; 2043193323Sed } 2044193323Sed } 2045193323Sed if (C) { // just C, no GV. 2046193323Sed // Simple constants are not allowed for 's'. 2047193323Sed if (ConstraintLetter != 's') { 2048193323Sed // gcc prints these as sign extended. Sign extend value to 64 bits 2049193323Sed // now; without this it would get ZExt'd later in 2050193323Sed // ScheduleDAGSDNodes::EmitNode, which is very generic. 2051193323Sed Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2052193323Sed MVT::i64)); 2053193323Sed return; 2054193323Sed } 2055193323Sed } 2056193323Sed break; 2057193323Sed } 2058193323Sed } 2059193323Sed} 2060193323Sed 2061193323Sedstd::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2062193323SedgetRegForInlineAsmConstraint(const std::string &Constraint, 2063263508Sdim MVT VT) const { 2064263508Sdim if (Constraint.empty() || Constraint[0] != '{') 2065208599Srdivacky return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2066193323Sed assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2067193323Sed 2068193323Sed // Remove the braces from around the name. 2069199481Srdivacky StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2070193323Sed 2071249423Sdim std::pair<unsigned, const TargetRegisterClass*> R = 2072249423Sdim std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2073249423Sdim 2074193323Sed // Figure out which register class contains this reg. 2075249423Sdim const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo(); 2076193323Sed for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2077193323Sed E = RI->regclass_end(); RCI != E; ++RCI) { 2078193323Sed const TargetRegisterClass *RC = *RCI; 2079218893Sdim 2080218893Sdim // If none of the value types for this register class are valid, we 2081193323Sed // can't use it. For example, 64-bit reg classes on 32-bit targets. 2082226633Sdim if (!isLegalRC(RC)) 2083226633Sdim continue; 2084218893Sdim 2085218893Sdim for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2086193323Sed I != E; ++I) { 2087249423Sdim if (RegName.equals_lower(RI->getName(*I))) { 2088249423Sdim std::pair<unsigned, const TargetRegisterClass*> S = 2089249423Sdim std::make_pair(*I, RC); 2090249423Sdim 2091249423Sdim // If this register class has the requested value type, return it, 2092249423Sdim // otherwise keep searching and return the first class found 2093249423Sdim // if no other is found which explicitly has the requested type. 2094249423Sdim if (RC->hasType(VT)) 2095249423Sdim return S; 2096249423Sdim else if (!R.second) 2097249423Sdim R = S; 2098249423Sdim } 2099193323Sed } 2100193323Sed } 2101218893Sdim 2102249423Sdim return R; 2103193323Sed} 2104193323Sed 2105193323Sed//===----------------------------------------------------------------------===// 2106193323Sed// Constraint Selection. 2107193323Sed 2108193323Sed/// isMatchingInputConstraint - Return true of this is an input operand that is 2109193323Sed/// a matching constraint like "4". 2110193323Sedbool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2111193323Sed assert(!ConstraintCode.empty() && "No known constraint!"); 2112249423Sdim return isdigit(static_cast<unsigned char>(ConstraintCode[0])); 2113193323Sed} 2114193323Sed 2115193323Sed/// getMatchedOperand - If this is an input matching constraint, this method 2116193323Sed/// returns the output operand it matches. 2117193323Sedunsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2118193323Sed assert(!ConstraintCode.empty() && "No known constraint!"); 2119193323Sed return atoi(ConstraintCode.c_str()); 2120193323Sed} 2121193323Sed 2122193323Sed 2123218893Sdim/// ParseConstraints - Split up the constraint string from the inline 2124218893Sdim/// assembly value into the specific constraints and their prefixes, 2125218893Sdim/// and also tie in the associated operand values. 2126218893Sdim/// If this returns an empty vector, and if the constraint string itself 2127218893Sdim/// isn't empty, there was an error parsing. 2128218893SdimTargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2129218893Sdim ImmutableCallSite CS) const { 2130218893Sdim /// ConstraintOperands - Information about all of the constraints. 2131218893Sdim AsmOperandInfoVector ConstraintOperands; 2132218893Sdim const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2133218893Sdim unsigned maCount = 0; // Largest number of multiple alternative constraints. 2134218893Sdim 2135218893Sdim // Do a prepass over the constraints, canonicalizing them, and building up the 2136218893Sdim // ConstraintOperands list. 2137218893Sdim InlineAsm::ConstraintInfoVector 2138218893Sdim ConstraintInfos = IA->ParseConstraints(); 2139218893Sdim 2140218893Sdim unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2141218893Sdim unsigned ResNo = 0; // ResNo - The result number of the next output. 2142218893Sdim 2143218893Sdim for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2144218893Sdim ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2145218893Sdim AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2146218893Sdim 2147218893Sdim // Update multiple alternative constraint count. 2148218893Sdim if (OpInfo.multipleAlternatives.size() > maCount) 2149218893Sdim maCount = OpInfo.multipleAlternatives.size(); 2150218893Sdim 2151218893Sdim OpInfo.ConstraintVT = MVT::Other; 2152218893Sdim 2153218893Sdim // Compute the value type for each operand. 2154218893Sdim switch (OpInfo.Type) { 2155218893Sdim case InlineAsm::isOutput: 2156218893Sdim // Indirect outputs just consume an argument. 2157218893Sdim if (OpInfo.isIndirect) { 2158218893Sdim OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2159218893Sdim break; 2160218893Sdim } 2161218893Sdim 2162218893Sdim // The return value of the call is this value. As such, there is no 2163218893Sdim // corresponding argument. 2164218893Sdim assert(!CS.getType()->isVoidTy() && 2165218893Sdim "Bad inline asm!"); 2166226633Sdim if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2167249423Sdim OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo)); 2168218893Sdim } else { 2169218893Sdim assert(ResNo == 0 && "Asm only has one result!"); 2170249423Sdim OpInfo.ConstraintVT = getSimpleValueType(CS.getType()); 2171218893Sdim } 2172218893Sdim ++ResNo; 2173218893Sdim break; 2174218893Sdim case InlineAsm::isInput: 2175218893Sdim OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2176218893Sdim break; 2177218893Sdim case InlineAsm::isClobber: 2178218893Sdim // Nothing to do. 2179218893Sdim break; 2180218893Sdim } 2181218893Sdim 2182218893Sdim if (OpInfo.CallOperandVal) { 2183226633Sdim llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2184218893Sdim if (OpInfo.isIndirect) { 2185226633Sdim llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2186218893Sdim if (!PtrTy) 2187218893Sdim report_fatal_error("Indirect operand for inline asm not a pointer!"); 2188218893Sdim OpTy = PtrTy->getElementType(); 2189218893Sdim } 2190224145Sdim 2191223017Sdim // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2192226633Sdim if (StructType *STy = dyn_cast<StructType>(OpTy)) 2193223017Sdim if (STy->getNumElements() == 1) 2194223017Sdim OpTy = STy->getElementType(0); 2195223017Sdim 2196218893Sdim // If OpTy is not a single value, it may be a struct/union that we 2197218893Sdim // can tile with integers. 2198218893Sdim if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2199249423Sdim unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy); 2200218893Sdim switch (BitSize) { 2201218893Sdim default: break; 2202218893Sdim case 1: 2203218893Sdim case 8: 2204218893Sdim case 16: 2205218893Sdim case 32: 2206218893Sdim case 64: 2207218893Sdim case 128: 2208218893Sdim OpInfo.ConstraintVT = 2209249423Sdim MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2210218893Sdim break; 2211218893Sdim } 2212243830Sdim } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { 2213263508Sdim unsigned PtrSize 2214263508Sdim = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace()); 2215263508Sdim OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); 2216218893Sdim } else { 2217249423Sdim OpInfo.ConstraintVT = MVT::getVT(OpTy, true); 2218218893Sdim } 2219218893Sdim } 2220218893Sdim } 2221218893Sdim 2222218893Sdim // If we have multiple alternative constraints, select the best alternative. 2223218893Sdim if (ConstraintInfos.size()) { 2224218893Sdim if (maCount) { 2225218893Sdim unsigned bestMAIndex = 0; 2226218893Sdim int bestWeight = -1; 2227218893Sdim // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2228218893Sdim int weight = -1; 2229218893Sdim unsigned maIndex; 2230218893Sdim // Compute the sums of the weights for each alternative, keeping track 2231218893Sdim // of the best (highest weight) one so far. 2232218893Sdim for (maIndex = 0; maIndex < maCount; ++maIndex) { 2233218893Sdim int weightSum = 0; 2234218893Sdim for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2235218893Sdim cIndex != eIndex; ++cIndex) { 2236218893Sdim AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2237218893Sdim if (OpInfo.Type == InlineAsm::isClobber) 2238218893Sdim continue; 2239218893Sdim 2240218893Sdim // If this is an output operand with a matching input operand, 2241218893Sdim // look up the matching input. If their types mismatch, e.g. one 2242218893Sdim // is an integer, the other is floating point, or their sizes are 2243218893Sdim // different, flag it as an maCantMatch. 2244218893Sdim if (OpInfo.hasMatchingInput()) { 2245218893Sdim AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2246218893Sdim if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2247218893Sdim if ((OpInfo.ConstraintVT.isInteger() != 2248218893Sdim Input.ConstraintVT.isInteger()) || 2249218893Sdim (OpInfo.ConstraintVT.getSizeInBits() != 2250218893Sdim Input.ConstraintVT.getSizeInBits())) { 2251218893Sdim weightSum = -1; // Can't match. 2252218893Sdim break; 2253218893Sdim } 2254218893Sdim } 2255218893Sdim } 2256218893Sdim weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2257218893Sdim if (weight == -1) { 2258218893Sdim weightSum = -1; 2259218893Sdim break; 2260218893Sdim } 2261218893Sdim weightSum += weight; 2262218893Sdim } 2263218893Sdim // Update best. 2264218893Sdim if (weightSum > bestWeight) { 2265218893Sdim bestWeight = weightSum; 2266218893Sdim bestMAIndex = maIndex; 2267218893Sdim } 2268218893Sdim } 2269218893Sdim 2270218893Sdim // Now select chosen alternative in each constraint. 2271218893Sdim for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2272218893Sdim cIndex != eIndex; ++cIndex) { 2273218893Sdim AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2274218893Sdim if (cInfo.Type == InlineAsm::isClobber) 2275218893Sdim continue; 2276218893Sdim cInfo.selectAlternative(bestMAIndex); 2277218893Sdim } 2278218893Sdim } 2279218893Sdim } 2280218893Sdim 2281218893Sdim // Check and hook up tied operands, choose constraint code to use. 2282218893Sdim for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2283218893Sdim cIndex != eIndex; ++cIndex) { 2284218893Sdim AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2285218893Sdim 2286218893Sdim // If this is an output operand with a matching input operand, look up the 2287218893Sdim // matching input. If their types mismatch, e.g. one is an integer, the 2288218893Sdim // other is floating point, or their sizes are different, flag it as an 2289218893Sdim // error. 2290218893Sdim if (OpInfo.hasMatchingInput()) { 2291218893Sdim AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2292218893Sdim 2293218893Sdim if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2294239462Sdim std::pair<unsigned, const TargetRegisterClass*> MatchRC = 2295239462Sdim getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 2296239462Sdim OpInfo.ConstraintVT); 2297239462Sdim std::pair<unsigned, const TargetRegisterClass*> InputRC = 2298239462Sdim getRegForInlineAsmConstraint(Input.ConstraintCode, 2299239462Sdim Input.ConstraintVT); 2300218893Sdim if ((OpInfo.ConstraintVT.isInteger() != 2301218893Sdim Input.ConstraintVT.isInteger()) || 2302224145Sdim (MatchRC.second != InputRC.second)) { 2303218893Sdim report_fatal_error("Unsupported asm: input constraint" 2304218893Sdim " with a matching output constraint of" 2305218893Sdim " incompatible type!"); 2306218893Sdim } 2307218893Sdim } 2308218893Sdim 2309218893Sdim } 2310218893Sdim } 2311218893Sdim 2312218893Sdim return ConstraintOperands; 2313218893Sdim} 2314218893Sdim 2315218893Sdim 2316193323Sed/// getConstraintGenerality - Return an integer indicating how general CT 2317193323Sed/// is. 2318193323Sedstatic unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2319193323Sed switch (CT) { 2320193323Sed case TargetLowering::C_Other: 2321193323Sed case TargetLowering::C_Unknown: 2322193323Sed return 0; 2323193323Sed case TargetLowering::C_Register: 2324193323Sed return 1; 2325193323Sed case TargetLowering::C_RegisterClass: 2326193323Sed return 2; 2327193323Sed case TargetLowering::C_Memory: 2328193323Sed return 3; 2329193323Sed } 2330234353Sdim llvm_unreachable("Invalid constraint type"); 2331193323Sed} 2332193323Sed 2333218893Sdim/// Examine constraint type and operand type and determine a weight value. 2334218893Sdim/// This object must already have been set up with the operand type 2335218893Sdim/// and the current alternative constraint selected. 2336218893SdimTargetLowering::ConstraintWeight 2337218893Sdim TargetLowering::getMultipleConstraintMatchWeight( 2338218893Sdim AsmOperandInfo &info, int maIndex) const { 2339218893Sdim InlineAsm::ConstraintCodeVector *rCodes; 2340218893Sdim if (maIndex >= (int)info.multipleAlternatives.size()) 2341218893Sdim rCodes = &info.Codes; 2342218893Sdim else 2343218893Sdim rCodes = &info.multipleAlternatives[maIndex].Codes; 2344218893Sdim ConstraintWeight BestWeight = CW_Invalid; 2345218893Sdim 2346218893Sdim // Loop over the options, keeping track of the most general one. 2347218893Sdim for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2348218893Sdim ConstraintWeight weight = 2349218893Sdim getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2350218893Sdim if (weight > BestWeight) 2351218893Sdim BestWeight = weight; 2352218893Sdim } 2353218893Sdim 2354218893Sdim return BestWeight; 2355218893Sdim} 2356218893Sdim 2357218893Sdim/// Examine constraint type and operand type and determine a weight value. 2358218893Sdim/// This object must already have been set up with the operand type 2359218893Sdim/// and the current alternative constraint selected. 2360218893SdimTargetLowering::ConstraintWeight 2361218893Sdim TargetLowering::getSingleConstraintMatchWeight( 2362218893Sdim AsmOperandInfo &info, const char *constraint) const { 2363218893Sdim ConstraintWeight weight = CW_Invalid; 2364218893Sdim Value *CallOperandVal = info.CallOperandVal; 2365218893Sdim // If we don't have a value, we can't do a match, 2366218893Sdim // but allow it at the lowest weight. 2367218893Sdim if (CallOperandVal == NULL) 2368218893Sdim return CW_Default; 2369218893Sdim // Look at the constraint type. 2370218893Sdim switch (*constraint) { 2371218893Sdim case 'i': // immediate integer. 2372218893Sdim case 'n': // immediate integer with a known value. 2373218893Sdim if (isa<ConstantInt>(CallOperandVal)) 2374218893Sdim weight = CW_Constant; 2375218893Sdim break; 2376218893Sdim case 's': // non-explicit intregal immediate. 2377218893Sdim if (isa<GlobalValue>(CallOperandVal)) 2378218893Sdim weight = CW_Constant; 2379218893Sdim break; 2380218893Sdim case 'E': // immediate float if host format. 2381218893Sdim case 'F': // immediate float. 2382218893Sdim if (isa<ConstantFP>(CallOperandVal)) 2383218893Sdim weight = CW_Constant; 2384218893Sdim break; 2385218893Sdim case '<': // memory operand with autodecrement. 2386218893Sdim case '>': // memory operand with autoincrement. 2387218893Sdim case 'm': // memory operand. 2388218893Sdim case 'o': // offsettable memory operand 2389218893Sdim case 'V': // non-offsettable memory operand 2390218893Sdim weight = CW_Memory; 2391218893Sdim break; 2392218893Sdim case 'r': // general register. 2393218893Sdim case 'g': // general register, memory operand or immediate integer. 2394218893Sdim // note: Clang converts "g" to "imr". 2395218893Sdim if (CallOperandVal->getType()->isIntegerTy()) 2396218893Sdim weight = CW_Register; 2397218893Sdim break; 2398218893Sdim case 'X': // any operand. 2399218893Sdim default: 2400218893Sdim weight = CW_Default; 2401218893Sdim break; 2402218893Sdim } 2403218893Sdim return weight; 2404218893Sdim} 2405218893Sdim 2406193323Sed/// ChooseConstraint - If there are multiple different constraints that we 2407193323Sed/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2408193323Sed/// This is somewhat tricky: constraints fall into four classes: 2409193323Sed/// Other -> immediates and magic values 2410193323Sed/// Register -> one specific register 2411193323Sed/// RegisterClass -> a group of regs 2412193323Sed/// Memory -> memory 2413193323Sed/// Ideally, we would pick the most specific constraint possible: if we have 2414193323Sed/// something that fits into a register, we would pick it. The problem here 2415193323Sed/// is that if we have something that could either be in a register or in 2416193323Sed/// memory that use of the register could cause selection of *other* 2417193323Sed/// operands to fail: they might only succeed if we pick memory. Because of 2418193323Sed/// this the heuristic we use is: 2419193323Sed/// 2420193323Sed/// 1) If there is an 'other' constraint, and if the operand is valid for 2421193323Sed/// that constraint, use it. This makes us take advantage of 'i' 2422193323Sed/// constraints when available. 2423193323Sed/// 2) Otherwise, pick the most general constraint present. This prefers 2424193323Sed/// 'm' over 'r', for example. 2425193323Sed/// 2426193323Sedstatic void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2427210299Sed const TargetLowering &TLI, 2428193323Sed SDValue Op, SelectionDAG *DAG) { 2429193323Sed assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2430193323Sed unsigned BestIdx = 0; 2431193323Sed TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2432193323Sed int BestGenerality = -1; 2433210299Sed 2434193323Sed // Loop over the options, keeping track of the most general one. 2435193323Sed for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2436193323Sed TargetLowering::ConstraintType CType = 2437193323Sed TLI.getConstraintType(OpInfo.Codes[i]); 2438210299Sed 2439193323Sed // If this is an 'other' constraint, see if the operand is valid for it. 2440193323Sed // For example, on X86 we might have an 'rI' constraint. If the operand 2441193323Sed // is an integer in the range [0..31] we want to use I (saving a load 2442193323Sed // of a register), otherwise we must use 'r'. 2443193323Sed if (CType == TargetLowering::C_Other && Op.getNode()) { 2444193323Sed assert(OpInfo.Codes[i].size() == 1 && 2445193323Sed "Unhandled multi-letter 'other' constraint"); 2446193323Sed std::vector<SDValue> ResultOps; 2447223017Sdim TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 2448193323Sed ResultOps, *DAG); 2449193323Sed if (!ResultOps.empty()) { 2450193323Sed BestType = CType; 2451193323Sed BestIdx = i; 2452193323Sed break; 2453193323Sed } 2454193323Sed } 2455218893Sdim 2456210299Sed // Things with matching constraints can only be registers, per gcc 2457210299Sed // documentation. This mainly affects "g" constraints. 2458210299Sed if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2459210299Sed continue; 2460218893Sdim 2461193323Sed // This constraint letter is more general than the previous one, use it. 2462193323Sed int Generality = getConstraintGenerality(CType); 2463193323Sed if (Generality > BestGenerality) { 2464193323Sed BestType = CType; 2465193323Sed BestIdx = i; 2466193323Sed BestGenerality = Generality; 2467193323Sed } 2468193323Sed } 2469218893Sdim 2470193323Sed OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2471193323Sed OpInfo.ConstraintType = BestType; 2472193323Sed} 2473193323Sed 2474193323Sed/// ComputeConstraintToUse - Determines the constraint code and constraint 2475193323Sed/// type to use for the specific AsmOperandInfo, setting 2476193323Sed/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2477193323Sedvoid TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2478218893Sdim SDValue Op, 2479193323Sed SelectionDAG *DAG) const { 2480193323Sed assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2481218893Sdim 2482193323Sed // Single-letter constraints ('r') are very common. 2483193323Sed if (OpInfo.Codes.size() == 1) { 2484193323Sed OpInfo.ConstraintCode = OpInfo.Codes[0]; 2485193323Sed OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2486193323Sed } else { 2487210299Sed ChooseConstraint(OpInfo, *this, Op, DAG); 2488193323Sed } 2489218893Sdim 2490193323Sed // 'X' matches anything. 2491193323Sed if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2492193323Sed // Labels and constants are handled elsewhere ('X' is the only thing 2493198090Srdivacky // that matches labels). For Functions, the type here is the type of 2494198090Srdivacky // the result, which is not what we want to look at; leave them alone. 2495198090Srdivacky Value *v = OpInfo.CallOperandVal; 2496198090Srdivacky if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2497198090Srdivacky OpInfo.CallOperandVal = v; 2498193323Sed return; 2499198090Srdivacky } 2500218893Sdim 2501193323Sed // Otherwise, try to resolve it to something we know about by looking at 2502193323Sed // the actual operand type. 2503193323Sed if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2504193323Sed OpInfo.ConstraintCode = Repl; 2505193323Sed OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2506193323Sed } 2507193323Sed } 2508193323Sed} 2509193323Sed 2510263508Sdim/// \brief Given an exact SDIV by a constant, create a multiplication 2511224145Sdim/// with the multiplicative inverse of the constant. 2512263508SdimSDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2513224145Sdim SelectionDAG &DAG) const { 2514224145Sdim ConstantSDNode *C = cast<ConstantSDNode>(Op2); 2515224145Sdim APInt d = C->getAPIntValue(); 2516224145Sdim assert(d != 0 && "Division by zero!"); 2517224145Sdim 2518224145Sdim // Shift the value upfront if it is even, so the LSB is one. 2519224145Sdim unsigned ShAmt = d.countTrailingZeros(); 2520224145Sdim if (ShAmt) { 2521224145Sdim // TODO: For UDIV use SRL instead of SRA. 2522224145Sdim SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 2523224145Sdim Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 2524224145Sdim d = d.ashr(ShAmt); 2525224145Sdim } 2526224145Sdim 2527224145Sdim // Calculate the multiplicative inverse, using Newton's method. 2528224145Sdim APInt t, xn = d; 2529224145Sdim while ((t = d*xn) != 1) 2530224145Sdim xn *= APInt(d.getBitWidth(), 2) - t; 2531224145Sdim 2532224145Sdim Op2 = DAG.getConstant(xn, Op1.getValueType()); 2533224145Sdim return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 2534224145Sdim} 2535224145Sdim 2536263508Sdim/// \brief Given an ISD::SDIV node expressing a divide by constant, 2537193323Sed/// return a DAG expression to select that will generate the same value by 2538193323Sed/// multiplying by a magic number. See: 2539193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2540234353SdimSDValue TargetLowering:: 2541234353SdimBuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2542249423Sdim std::vector<SDNode*> *Created) const { 2543198090Srdivacky EVT VT = N->getValueType(0); 2544263508Sdim SDLoc dl(N); 2545218893Sdim 2546193323Sed // Check to see if we can do this. 2547193323Sed // FIXME: We should be more aggressive here. 2548193323Sed if (!isTypeLegal(VT)) 2549193323Sed return SDValue(); 2550218893Sdim 2551193323Sed APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2552193323Sed APInt::ms magics = d.magic(); 2553218893Sdim 2554193323Sed // Multiply the numerator (operand 0) by the magic value 2555193323Sed // FIXME: We should support doing a MUL in a wider type 2556193323Sed SDValue Q; 2557234353Sdim if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 2558234353Sdim isOperationLegalOrCustom(ISD::MULHS, VT)) 2559193323Sed Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2560193323Sed DAG.getConstant(magics.m, VT)); 2561234353Sdim else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 2562234353Sdim isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2563193323Sed Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2564193323Sed N->getOperand(0), 2565193323Sed DAG.getConstant(magics.m, VT)).getNode(), 1); 2566193323Sed else 2567193323Sed return SDValue(); // No mulhs or equvialent 2568193323Sed // If d > 0 and m < 0, add the numerator 2569218893Sdim if (d.isStrictlyPositive() && magics.m.isNegative()) { 2570193323Sed Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2571193323Sed if (Created) 2572193323Sed Created->push_back(Q.getNode()); 2573193323Sed } 2574193323Sed // If d < 0 and m > 0, subtract the numerator. 2575193323Sed if (d.isNegative() && magics.m.isStrictlyPositive()) { 2576193323Sed Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2577193323Sed if (Created) 2578193323Sed Created->push_back(Q.getNode()); 2579193323Sed } 2580193323Sed // Shift right algebraic if shift value is nonzero 2581193323Sed if (magics.s > 0) { 2582218893Sdim Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2583219077Sdim DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2584193323Sed if (Created) 2585193323Sed Created->push_back(Q.getNode()); 2586193323Sed } 2587193323Sed // Extract the sign bit and add it to the quotient 2588193323Sed SDValue T = 2589193323Sed DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2590219077Sdim getShiftAmountTy(Q.getValueType()))); 2591193323Sed if (Created) 2592193323Sed Created->push_back(T.getNode()); 2593193323Sed return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2594193323Sed} 2595193323Sed 2596263508Sdim/// \brief Given an ISD::UDIV node expressing a divide by constant, 2597193323Sed/// return a DAG expression to select that will generate the same value by 2598193323Sed/// multiplying by a magic number. See: 2599193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2600234353SdimSDValue TargetLowering:: 2601234353SdimBuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2602249423Sdim std::vector<SDNode*> *Created) const { 2603198090Srdivacky EVT VT = N->getValueType(0); 2604263508Sdim SDLoc dl(N); 2605193323Sed 2606193323Sed // Check to see if we can do this. 2607193323Sed // FIXME: We should be more aggressive here. 2608193323Sed if (!isTypeLegal(VT)) 2609193323Sed return SDValue(); 2610193323Sed 2611193323Sed // FIXME: We should use a narrower constant when the upper 2612193323Sed // bits are known to be zero. 2613221345Sdim const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2614221345Sdim APInt::mu magics = N1C.magicu(); 2615193323Sed 2616221345Sdim SDValue Q = N->getOperand(0); 2617221345Sdim 2618221345Sdim // If the divisor is even, we can avoid using the expensive fixup by shifting 2619221345Sdim // the divided value upfront. 2620221345Sdim if (magics.a != 0 && !N1C[0]) { 2621221345Sdim unsigned Shift = N1C.countTrailingZeros(); 2622221345Sdim Q = DAG.getNode(ISD::SRL, dl, VT, Q, 2623221345Sdim DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 2624221345Sdim if (Created) 2625221345Sdim Created->push_back(Q.getNode()); 2626221345Sdim 2627221345Sdim // Get magic number for the shifted divisor. 2628221345Sdim magics = N1C.lshr(Shift).magicu(Shift); 2629221345Sdim assert(magics.a == 0 && "Should use cheap fixup now"); 2630221345Sdim } 2631221345Sdim 2632193323Sed // Multiply the numerator (operand 0) by the magic value 2633193323Sed // FIXME: We should support doing a MUL in a wider type 2634234353Sdim if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 2635234353Sdim isOperationLegalOrCustom(ISD::MULHU, VT)) 2636221345Sdim Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 2637234353Sdim else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 2638234353Sdim isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2639221345Sdim Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 2640221345Sdim DAG.getConstant(magics.m, VT)).getNode(), 1); 2641193323Sed else 2642193323Sed return SDValue(); // No mulhu or equvialent 2643193323Sed if (Created) 2644193323Sed Created->push_back(Q.getNode()); 2645193323Sed 2646193323Sed if (magics.a == 0) { 2647221345Sdim assert(magics.s < N1C.getBitWidth() && 2648193323Sed "We shouldn't generate an undefined shift!"); 2649218893Sdim return DAG.getNode(ISD::SRL, dl, VT, Q, 2650219077Sdim DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2651193323Sed } else { 2652193323Sed SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2653193323Sed if (Created) 2654193323Sed Created->push_back(NPQ.getNode()); 2655218893Sdim NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2656219077Sdim DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 2657193323Sed if (Created) 2658193323Sed Created->push_back(NPQ.getNode()); 2659193323Sed NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2660193323Sed if (Created) 2661193323Sed Created->push_back(NPQ.getNode()); 2662218893Sdim return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2663219077Sdim DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 2664193323Sed } 2665193323Sed} 2666