SelectionDAGISel.cpp revision 251662
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/TargetTransformInfo.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/FunctionLoweringInfo.h" 25#include "llvm/CodeGen/GCMetadata.h" 26#include "llvm/CodeGen/GCStrategy.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33#include "llvm/CodeGen/SchedulerRegistry.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/DebugInfo.h" 36#include "llvm/IR/Constants.h" 37#include "llvm/IR/Function.h" 38#include "llvm/IR/InlineAsm.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/IntrinsicInst.h" 41#include "llvm/IR/Intrinsics.h" 42#include "llvm/IR/LLVMContext.h" 43#include "llvm/IR/Module.h" 44#include "llvm/Support/Compiler.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/ErrorHandling.h" 47#include "llvm/Support/Timer.h" 48#include "llvm/Support/raw_ostream.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLibraryInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetMachine.h" 54#include "llvm/Target/TargetOptions.h" 55#include "llvm/Target/TargetRegisterInfo.h" 56#include "llvm/Target/TargetSubtargetInfo.h" 57#include "llvm/Transforms/Utils/BasicBlockUtils.h" 58#include <algorithm> 59using namespace llvm; 60 61STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 62STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 63STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 64STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 65STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 67STATISTIC(NumFastIselFailLowerArguments, 68 "Number of entry blocks where fast isel failed to lower arguments"); 69 70#ifndef NDEBUG 71static cl::opt<bool> 72EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 73 cl::desc("Enable extra verbose messages in the \"fast\" " 74 "instruction selector")); 75 76 // Terminators 77STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 78STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 79STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 80STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 81STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 82STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 83STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 84 85 // Standard binary operators... 86STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 87STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 88STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 89STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 90STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 91STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 92STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 93STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 94STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 95STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 96STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 97STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 98 99 // Logical operators... 100STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 101STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 102STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 103 104 // Memory instructions... 105STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 106STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 107STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 108STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 109STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 110STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 111STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 112 113 // Convert instructions... 114STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 115STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 116STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 117STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 118STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 119STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 120STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 121STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 122STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 123STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 124STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 125STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 126 127 // Other instructions... 128STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 129STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 130STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 131STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 132STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 133STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 134STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 135STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 136STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 137STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 138STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 139STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 140STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 141STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 142STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 143#endif 144 145static cl::opt<bool> 146EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 147 cl::desc("Enable verbose messages in the \"fast\" " 148 "instruction selector")); 149static cl::opt<bool> 150EnableFastISelAbort("fast-isel-abort", cl::Hidden, 151 cl::desc("Enable abort calls when \"fast\" instruction selection " 152 "fails to lower an instruction")); 153static cl::opt<bool> 154EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 155 cl::desc("Enable abort calls when \"fast\" instruction selection " 156 "fails to lower a formal argument")); 157 158static cl::opt<bool> 159UseMBPI("use-mbpi", 160 cl::desc("use Machine Branch Probability Info"), 161 cl::init(true), cl::Hidden); 162 163#ifndef NDEBUG 164static cl::opt<bool> 165ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 166 cl::desc("Pop up a window to show dags before the first " 167 "dag combine pass")); 168static cl::opt<bool> 169ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 170 cl::desc("Pop up a window to show dags before legalize types")); 171static cl::opt<bool> 172ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 173 cl::desc("Pop up a window to show dags before legalize")); 174static cl::opt<bool> 175ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 176 cl::desc("Pop up a window to show dags before the second " 177 "dag combine pass")); 178static cl::opt<bool> 179ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 180 cl::desc("Pop up a window to show dags before the post legalize types" 181 " dag combine pass")); 182static cl::opt<bool> 183ViewISelDAGs("view-isel-dags", cl::Hidden, 184 cl::desc("Pop up a window to show isel dags as they are selected")); 185static cl::opt<bool> 186ViewSchedDAGs("view-sched-dags", cl::Hidden, 187 cl::desc("Pop up a window to show sched dags as they are processed")); 188static cl::opt<bool> 189ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 190 cl::desc("Pop up a window to show SUnit dags after they are processed")); 191#else 192static const bool ViewDAGCombine1 = false, 193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 194 ViewDAGCombine2 = false, 195 ViewDAGCombineLT = false, 196 ViewISelDAGs = false, ViewSchedDAGs = false, 197 ViewSUnitDAGs = false; 198#endif 199 200//===---------------------------------------------------------------------===// 201/// 202/// RegisterScheduler class - Track the registration of instruction schedulers. 203/// 204//===---------------------------------------------------------------------===// 205MachinePassRegistry RegisterScheduler::Registry; 206 207//===---------------------------------------------------------------------===// 208/// 209/// ISHeuristic command line option for instruction schedulers. 210/// 211//===---------------------------------------------------------------------===// 212static cl::opt<RegisterScheduler::FunctionPassCtor, false, 213 RegisterPassParser<RegisterScheduler> > 214ISHeuristic("pre-RA-sched", 215 cl::init(&createDefaultScheduler), 216 cl::desc("Instruction schedulers available (before register" 217 " allocation):")); 218 219static RegisterScheduler 220defaultListDAGScheduler("default", "Best scheduler for the target", 221 createDefaultScheduler); 222 223namespace llvm { 224 //===--------------------------------------------------------------------===// 225 /// createDefaultScheduler - This creates an instruction scheduler appropriate 226 /// for the target. 227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 228 CodeGenOpt::Level OptLevel) { 229 const TargetLowering &TLI = IS->getTargetLowering(); 230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 231 232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 233 TLI.getSchedulingPreference() == Sched::Source) 234 return createSourceListDAGScheduler(IS, OptLevel); 235 if (TLI.getSchedulingPreference() == Sched::RegPressure) 236 return createBURRListDAGScheduler(IS, OptLevel); 237 if (TLI.getSchedulingPreference() == Sched::Hybrid) 238 return createHybridListDAGScheduler(IS, OptLevel); 239 if (TLI.getSchedulingPreference() == Sched::VLIW) 240 return createVLIWDAGScheduler(IS, OptLevel); 241 assert(TLI.getSchedulingPreference() == Sched::ILP && 242 "Unknown sched type!"); 243 return createILPListDAGScheduler(IS, OptLevel); 244 } 245} 246 247// EmitInstrWithCustomInserter - This method should be implemented by targets 248// that mark instructions with the 'usesCustomInserter' flag. These 249// instructions are special in various ways, which require special support to 250// insert. The specified MachineInstr is created but not inserted into any 251// basic blocks, and this method is called to expand it into a sequence of 252// instructions, potentially also creating new basic blocks and control flow. 253// When new basic blocks are inserted and the edges from MBB to its successors 254// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 255// DenseMap. 256MachineBasicBlock * 257TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 258 MachineBasicBlock *MBB) const { 259#ifndef NDEBUG 260 dbgs() << "If a target marks an instruction with " 261 "'usesCustomInserter', it must implement " 262 "TargetLowering::EmitInstrWithCustomInserter!"; 263#endif 264 llvm_unreachable(0); 265} 266 267void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 268 SDNode *Node) const { 269 assert(!MI->hasPostISelHook() && 270 "If a target marks an instruction with 'hasPostISelHook', " 271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 272} 273 274//===----------------------------------------------------------------------===// 275// SelectionDAGISel code 276//===----------------------------------------------------------------------===// 277 278SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 279 CodeGenOpt::Level OL) : 280 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 281 FuncInfo(new FunctionLoweringInfo(TLI)), 282 CurDAG(new SelectionDAG(tm, OL)), 283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 284 GFI(), 285 OptLevel(OL), 286 DAGSize(0) { 287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 291 } 292 293SelectionDAGISel::~SelectionDAGISel() { 294 delete SDB; 295 delete CurDAG; 296 delete FuncInfo; 297} 298 299void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 300 AU.addRequired<AliasAnalysis>(); 301 AU.addPreserved<AliasAnalysis>(); 302 AU.addRequired<GCModuleInfo>(); 303 AU.addPreserved<GCModuleInfo>(); 304 AU.addRequired<TargetLibraryInfo>(); 305 if (UseMBPI && OptLevel != CodeGenOpt::None) 306 AU.addRequired<BranchProbabilityInfo>(); 307 MachineFunctionPass::getAnalysisUsage(AU); 308} 309 310/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 311/// may trap on it. In this case we have to split the edge so that the path 312/// through the predecessor block that doesn't go to the phi block doesn't 313/// execute the possibly trapping instruction. 314/// 315/// This is required for correctness, so it must be done at -O0. 316/// 317static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 318 // Loop for blocks with phi nodes. 319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 320 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 321 if (PN == 0) continue; 322 323 ReprocessBlock: 324 // For each block with a PHI node, check to see if any of the input values 325 // are potentially trapping constant expressions. Constant expressions are 326 // the only potentially trapping value that can occur as the argument to a 327 // PHI. 328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 331 if (CE == 0 || !CE->canTrap()) continue; 332 333 // The only case we have to worry about is when the edge is critical. 334 // Since this block has a PHI Node, we assume it has multiple input 335 // edges: check to see if the pred has multiple successors. 336 BasicBlock *Pred = PN->getIncomingBlock(i); 337 if (Pred->getTerminator()->getNumSuccessors() == 1) 338 continue; 339 340 // Okay, we have to split this edge. 341 SplitCriticalEdge(Pred->getTerminator(), 342 GetSuccessorNumber(Pred, BB), SDISel, true); 343 goto ReprocessBlock; 344 } 345 } 346} 347 348bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 349 // Do some sanity-checking on the command-line options. 350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 351 "-fast-isel-verbose requires -fast-isel"); 352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 353 "-fast-isel-abort requires -fast-isel"); 354 355 const Function &Fn = *mf.getFunction(); 356 const TargetInstrInfo &TII = *TM.getInstrInfo(); 357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 358 359 MF = &mf; 360 RegInfo = &MF->getRegInfo(); 361 AA = &getAnalysis<AliasAnalysis>(); 362 LibInfo = &getAnalysis<TargetLibraryInfo>(); 363 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 365 366 TargetSubtargetInfo &ST = 367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 368 ST.resetSubtargetFeatures(MF); 369 TM.resetTargetOptions(MF); 370 371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 372 373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 374 375 CurDAG->init(*MF, TTI); 376 FuncInfo->set(Fn, *MF); 377 378 if (UseMBPI && OptLevel != CodeGenOpt::None) 379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 380 else 381 FuncInfo->BPI = 0; 382 383 SDB->init(GFI, *AA, LibInfo); 384 385 MF->setHasMSInlineAsm(false); 386 SelectAllBasicBlocks(Fn); 387 388 // If the first basic block in the function has live ins that need to be 389 // copied into vregs, emit the copies into the top of the block before 390 // emitting the code for the block. 391 MachineBasicBlock *EntryMBB = MF->begin(); 392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 393 394 DenseMap<unsigned, unsigned> LiveInMap; 395 if (!FuncInfo->ArgDbgValues.empty()) 396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 397 E = RegInfo->livein_end(); LI != E; ++LI) 398 if (LI->second) 399 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 400 401 // Insert DBG_VALUE instructions for function arguments to the entry block. 402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 404 unsigned Reg = MI->getOperand(0).getReg(); 405 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 406 EntryMBB->insert(EntryMBB->begin(), MI); 407 else { 408 MachineInstr *Def = RegInfo->getVRegDef(Reg); 409 MachineBasicBlock::iterator InsertPos = Def; 410 // FIXME: VR def may not be in entry block. 411 Def->getParent()->insert(llvm::next(InsertPos), MI); 412 } 413 414 // If Reg is live-in then update debug info to track its copy in a vreg. 415 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 416 if (LDI != LiveInMap.end()) { 417 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 418 MachineBasicBlock::iterator InsertPos = Def; 419 const MDNode *Variable = 420 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 421 unsigned Offset = MI->getOperand(1).getImm(); 422 // Def is never a terminator here, so it is ok to increment InsertPos. 423 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 424 TII.get(TargetOpcode::DBG_VALUE)) 425 .addReg(LDI->second, RegState::Debug) 426 .addImm(Offset).addMetadata(Variable); 427 428 // If this vreg is directly copied into an exported register then 429 // that COPY instructions also need DBG_VALUE, if it is the only 430 // user of LDI->second. 431 MachineInstr *CopyUseMI = NULL; 432 for (MachineRegisterInfo::use_iterator 433 UI = RegInfo->use_begin(LDI->second); 434 MachineInstr *UseMI = UI.skipInstruction();) { 435 if (UseMI->isDebugValue()) continue; 436 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 437 CopyUseMI = UseMI; continue; 438 } 439 // Otherwise this is another use or second copy use. 440 CopyUseMI = NULL; break; 441 } 442 if (CopyUseMI) { 443 MachineInstr *NewMI = 444 BuildMI(*MF, CopyUseMI->getDebugLoc(), 445 TII.get(TargetOpcode::DBG_VALUE)) 446 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 447 .addImm(Offset).addMetadata(Variable); 448 MachineBasicBlock::iterator Pos = CopyUseMI; 449 EntryMBB->insertAfter(Pos, NewMI); 450 } 451 } 452 } 453 454 // Determine if there are any calls in this machine function. 455 MachineFrameInfo *MFI = MF->getFrameInfo(); 456 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 457 ++I) { 458 459 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 460 break; 461 462 const MachineBasicBlock *MBB = I; 463 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 464 II != IE; ++II) { 465 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 466 if ((MCID.isCall() && !MCID.isReturn()) || 467 II->isStackAligningInlineAsm()) { 468 MFI->setHasCalls(true); 469 } 470 if (II->isMSInlineAsm()) { 471 MF->setHasMSInlineAsm(true); 472 } 473 } 474 } 475 476 // Determine if there is a call to setjmp in the machine function. 477 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 478 479 // Replace forward-declared registers with the registers containing 480 // the desired value. 481 MachineRegisterInfo &MRI = MF->getRegInfo(); 482 for (DenseMap<unsigned, unsigned>::iterator 483 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 484 I != E; ++I) { 485 unsigned From = I->first; 486 unsigned To = I->second; 487 // If To is also scheduled to be replaced, find what its ultimate 488 // replacement is. 489 for (;;) { 490 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 491 if (J == E) break; 492 To = J->second; 493 } 494 // Replace it. 495 MRI.replaceRegWith(From, To); 496 } 497 498 // Freeze the set of reserved registers now that MachineFrameInfo has been 499 // set up. All the information required by getReservedRegs() should be 500 // available now. 501 MRI.freezeReservedRegs(*MF); 502 503 // Release function-specific state. SDB and CurDAG are already cleared 504 // at this point. 505 FuncInfo->clear(); 506 507 return true; 508} 509 510void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 511 BasicBlock::const_iterator End, 512 bool &HadTailCall) { 513 // Lower all of the non-terminator instructions. If a call is emitted 514 // as a tail call, cease emitting nodes for this block. Terminators 515 // are handled below. 516 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 517 SDB->visit(*I); 518 519 // Make sure the root of the DAG is up-to-date. 520 CurDAG->setRoot(SDB->getControlRoot()); 521 HadTailCall = SDB->HasTailCall; 522 SDB->clear(); 523 524 // Final step, emit the lowered DAG as machine code. 525 CodeGenAndEmitDAG(); 526} 527 528void SelectionDAGISel::ComputeLiveOutVRegInfo() { 529 SmallPtrSet<SDNode*, 128> VisitedNodes; 530 SmallVector<SDNode*, 128> Worklist; 531 532 Worklist.push_back(CurDAG->getRoot().getNode()); 533 534 APInt KnownZero; 535 APInt KnownOne; 536 537 do { 538 SDNode *N = Worklist.pop_back_val(); 539 540 // If we've already seen this node, ignore it. 541 if (!VisitedNodes.insert(N)) 542 continue; 543 544 // Otherwise, add all chain operands to the worklist. 545 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 546 if (N->getOperand(i).getValueType() == MVT::Other) 547 Worklist.push_back(N->getOperand(i).getNode()); 548 549 // If this is a CopyToReg with a vreg dest, process it. 550 if (N->getOpcode() != ISD::CopyToReg) 551 continue; 552 553 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 554 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 555 continue; 556 557 // Ignore non-scalar or non-integer values. 558 SDValue Src = N->getOperand(2); 559 EVT SrcVT = Src.getValueType(); 560 if (!SrcVT.isInteger() || SrcVT.isVector()) 561 continue; 562 563 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 564 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 565 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 566 } while (!Worklist.empty()); 567} 568 569void SelectionDAGISel::CodeGenAndEmitDAG() { 570 std::string GroupName; 571 if (TimePassesIsEnabled) 572 GroupName = "Instruction Selection and Scheduling"; 573 std::string BlockName; 574 int BlockNumber = -1; 575 (void)BlockNumber; 576#ifdef NDEBUG 577 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 578 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 579 ViewSUnitDAGs) 580#endif 581 { 582 BlockNumber = FuncInfo->MBB->getNumber(); 583 BlockName = MF->getName().str() + ":" + 584 FuncInfo->MBB->getBasicBlock()->getName().str(); 585 } 586 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 587 << " '" << BlockName << "'\n"; CurDAG->dump()); 588 589 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 590 591 // Run the DAG combiner in pre-legalize mode. 592 { 593 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 594 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 595 } 596 597 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 598 << " '" << BlockName << "'\n"; CurDAG->dump()); 599 600 // Second step, hack on the DAG until it only uses operations and types that 601 // the target supports. 602 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 603 BlockName); 604 605 bool Changed; 606 { 607 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 608 Changed = CurDAG->LegalizeTypes(); 609 } 610 611 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 612 << " '" << BlockName << "'\n"; CurDAG->dump()); 613 614 if (Changed) { 615 if (ViewDAGCombineLT) 616 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 617 618 // Run the DAG combiner in post-type-legalize mode. 619 { 620 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 621 TimePassesIsEnabled); 622 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 623 } 624 625 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 626 << " '" << BlockName << "'\n"; CurDAG->dump()); 627 } 628 629 { 630 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 631 Changed = CurDAG->LegalizeVectors(); 632 } 633 634 if (Changed) { 635 { 636 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 637 CurDAG->LegalizeTypes(); 638 } 639 640 if (ViewDAGCombineLT) 641 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 642 643 // Run the DAG combiner in post-type-legalize mode. 644 { 645 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 646 TimePassesIsEnabled); 647 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 648 } 649 650 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 651 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 652 } 653 654 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 655 656 { 657 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 658 CurDAG->Legalize(); 659 } 660 661 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 662 << " '" << BlockName << "'\n"; CurDAG->dump()); 663 664 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 665 666 // Run the DAG combiner in post-legalize mode. 667 { 668 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 669 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 670 } 671 672 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 673 << " '" << BlockName << "'\n"; CurDAG->dump()); 674 675 if (OptLevel != CodeGenOpt::None) 676 ComputeLiveOutVRegInfo(); 677 678 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 679 680 // Third, instruction select all of the operations to machine code, adding the 681 // code to the MachineBasicBlock. 682 { 683 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 684 DoInstructionSelection(); 685 } 686 687 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 688 << " '" << BlockName << "'\n"; CurDAG->dump()); 689 690 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 691 692 // Schedule machine code. 693 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 694 { 695 NamedRegionTimer T("Instruction Scheduling", GroupName, 696 TimePassesIsEnabled); 697 Scheduler->Run(CurDAG, FuncInfo->MBB); 698 } 699 700 if (ViewSUnitDAGs) Scheduler->viewGraph(); 701 702 // Emit machine code to BB. This can change 'BB' to the last block being 703 // inserted into. 704 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 705 { 706 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 707 708 // FuncInfo->InsertPt is passed by reference and set to the end of the 709 // scheduled instructions. 710 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 711 } 712 713 // If the block was split, make sure we update any references that are used to 714 // update PHI nodes later on. 715 if (FirstMBB != LastMBB) 716 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 717 718 // Free the scheduler state. 719 { 720 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 721 TimePassesIsEnabled); 722 delete Scheduler; 723 } 724 725 // Free the SelectionDAG state, now that we're finished with it. 726 CurDAG->clear(); 727} 728 729namespace { 730/// ISelUpdater - helper class to handle updates of the instruction selection 731/// graph. 732class ISelUpdater : public SelectionDAG::DAGUpdateListener { 733 SelectionDAG::allnodes_iterator &ISelPosition; 734public: 735 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 736 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 737 738 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 739 /// deleted is the current ISelPosition node, update ISelPosition. 740 /// 741 virtual void NodeDeleted(SDNode *N, SDNode *E) { 742 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 743 ++ISelPosition; 744 } 745}; 746} // end anonymous namespace 747 748void SelectionDAGISel::DoInstructionSelection() { 749 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 750 << FuncInfo->MBB->getNumber() 751 << " '" << FuncInfo->MBB->getName() << "'\n"); 752 753 PreprocessISelDAG(); 754 755 // Select target instructions for the DAG. 756 { 757 // Number all nodes with a topological order and set DAGSize. 758 DAGSize = CurDAG->AssignTopologicalOrder(); 759 760 // Create a dummy node (which is not added to allnodes), that adds 761 // a reference to the root node, preventing it from being deleted, 762 // and tracking any changes of the root. 763 HandleSDNode Dummy(CurDAG->getRoot()); 764 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 765 ++ISelPosition; 766 767 // Make sure that ISelPosition gets properly updated when nodes are deleted 768 // in calls made from this function. 769 ISelUpdater ISU(*CurDAG, ISelPosition); 770 771 // The AllNodes list is now topological-sorted. Visit the 772 // nodes by starting at the end of the list (the root of the 773 // graph) and preceding back toward the beginning (the entry 774 // node). 775 while (ISelPosition != CurDAG->allnodes_begin()) { 776 SDNode *Node = --ISelPosition; 777 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 778 // but there are currently some corner cases that it misses. Also, this 779 // makes it theoretically possible to disable the DAGCombiner. 780 if (Node->use_empty()) 781 continue; 782 783 SDNode *ResNode = Select(Node); 784 785 // FIXME: This is pretty gross. 'Select' should be changed to not return 786 // anything at all and this code should be nuked with a tactical strike. 787 788 // If node should not be replaced, continue with the next one. 789 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 790 continue; 791 // Replace node. 792 if (ResNode) { 793 // Propagate ordering 794 CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node)); 795 796 ReplaceUses(Node, ResNode); 797 } 798 799 // If after the replacement this node is not used any more, 800 // remove this dead node. 801 if (Node->use_empty()) // Don't delete EntryToken, etc. 802 CurDAG->RemoveDeadNode(Node); 803 } 804 805 CurDAG->setRoot(Dummy.getValue()); 806 } 807 808 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 809 810 PostprocessISelDAG(); 811} 812 813/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 814/// do other setup for EH landing-pad blocks. 815void SelectionDAGISel::PrepareEHLandingPad() { 816 MachineBasicBlock *MBB = FuncInfo->MBB; 817 818 // Add a label to mark the beginning of the landing pad. Deletion of the 819 // landing pad can thus be detected via the MachineModuleInfo. 820 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 821 822 // Assign the call site to the landing pad's begin label. 823 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 824 825 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 826 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 827 .addSym(Label); 828 829 // Mark exception register as live in. 830 unsigned Reg = TLI.getExceptionPointerRegister(); 831 if (Reg) MBB->addLiveIn(Reg); 832 833 // Mark exception selector register as live in. 834 Reg = TLI.getExceptionSelectorRegister(); 835 if (Reg) MBB->addLiveIn(Reg); 836} 837 838/// isFoldedOrDeadInstruction - Return true if the specified instruction is 839/// side-effect free and is either dead or folded into a generated instruction. 840/// Return false if it needs to be emitted. 841static bool isFoldedOrDeadInstruction(const Instruction *I, 842 FunctionLoweringInfo *FuncInfo) { 843 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 844 !isa<TerminatorInst>(I) && // Terminators aren't folded. 845 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 846 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 847 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 848} 849 850#ifndef NDEBUG 851// Collect per Instruction statistics for fast-isel misses. Only those 852// instructions that cause the bail are accounted for. It does not account for 853// instructions higher in the block. Thus, summing the per instructions stats 854// will not add up to what is reported by NumFastIselFailures. 855static void collectFailStats(const Instruction *I) { 856 switch (I->getOpcode()) { 857 default: assert (0 && "<Invalid operator> "); 858 859 // Terminators 860 case Instruction::Ret: NumFastIselFailRet++; return; 861 case Instruction::Br: NumFastIselFailBr++; return; 862 case Instruction::Switch: NumFastIselFailSwitch++; return; 863 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 864 case Instruction::Invoke: NumFastIselFailInvoke++; return; 865 case Instruction::Resume: NumFastIselFailResume++; return; 866 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 867 868 // Standard binary operators... 869 case Instruction::Add: NumFastIselFailAdd++; return; 870 case Instruction::FAdd: NumFastIselFailFAdd++; return; 871 case Instruction::Sub: NumFastIselFailSub++; return; 872 case Instruction::FSub: NumFastIselFailFSub++; return; 873 case Instruction::Mul: NumFastIselFailMul++; return; 874 case Instruction::FMul: NumFastIselFailFMul++; return; 875 case Instruction::UDiv: NumFastIselFailUDiv++; return; 876 case Instruction::SDiv: NumFastIselFailSDiv++; return; 877 case Instruction::FDiv: NumFastIselFailFDiv++; return; 878 case Instruction::URem: NumFastIselFailURem++; return; 879 case Instruction::SRem: NumFastIselFailSRem++; return; 880 case Instruction::FRem: NumFastIselFailFRem++; return; 881 882 // Logical operators... 883 case Instruction::And: NumFastIselFailAnd++; return; 884 case Instruction::Or: NumFastIselFailOr++; return; 885 case Instruction::Xor: NumFastIselFailXor++; return; 886 887 // Memory instructions... 888 case Instruction::Alloca: NumFastIselFailAlloca++; return; 889 case Instruction::Load: NumFastIselFailLoad++; return; 890 case Instruction::Store: NumFastIselFailStore++; return; 891 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 892 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 893 case Instruction::Fence: NumFastIselFailFence++; return; 894 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 895 896 // Convert instructions... 897 case Instruction::Trunc: NumFastIselFailTrunc++; return; 898 case Instruction::ZExt: NumFastIselFailZExt++; return; 899 case Instruction::SExt: NumFastIselFailSExt++; return; 900 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 901 case Instruction::FPExt: NumFastIselFailFPExt++; return; 902 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 903 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 904 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 905 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 906 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 907 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 908 case Instruction::BitCast: NumFastIselFailBitCast++; return; 909 910 // Other instructions... 911 case Instruction::ICmp: NumFastIselFailICmp++; return; 912 case Instruction::FCmp: NumFastIselFailFCmp++; return; 913 case Instruction::PHI: NumFastIselFailPHI++; return; 914 case Instruction::Select: NumFastIselFailSelect++; return; 915 case Instruction::Call: NumFastIselFailCall++; return; 916 case Instruction::Shl: NumFastIselFailShl++; return; 917 case Instruction::LShr: NumFastIselFailLShr++; return; 918 case Instruction::AShr: NumFastIselFailAShr++; return; 919 case Instruction::VAArg: NumFastIselFailVAArg++; return; 920 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 921 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 922 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 923 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 924 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 925 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 926 } 927} 928#endif 929 930void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 931 // Initialize the Fast-ISel state, if needed. 932 FastISel *FastIS = 0; 933 if (TM.Options.EnableFastISel) 934 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 935 936 // Iterate over all basic blocks in the function. 937 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 938 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 939 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 940 const BasicBlock *LLVMBB = *I; 941 942 if (OptLevel != CodeGenOpt::None) { 943 bool AllPredsVisited = true; 944 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 945 PI != PE; ++PI) { 946 if (!FuncInfo->VisitedBBs.count(*PI)) { 947 AllPredsVisited = false; 948 break; 949 } 950 } 951 952 if (AllPredsVisited) { 953 for (BasicBlock::const_iterator I = LLVMBB->begin(); 954 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 955 FuncInfo->ComputePHILiveOutRegInfo(PN); 956 } else { 957 for (BasicBlock::const_iterator I = LLVMBB->begin(); 958 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 959 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 960 } 961 962 FuncInfo->VisitedBBs.insert(LLVMBB); 963 } 964 965 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 966 BasicBlock::const_iterator const End = LLVMBB->end(); 967 BasicBlock::const_iterator BI = End; 968 969 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 970 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 971 972 // Setup an EH landing-pad block. 973 if (FuncInfo->MBB->isLandingPad()) 974 PrepareEHLandingPad(); 975 976 // Before doing SelectionDAG ISel, see if FastISel has been requested. 977 if (FastIS) { 978 FastIS->startNewBlock(); 979 980 // Emit code for any incoming arguments. This must happen before 981 // beginning FastISel on the entry block. 982 if (LLVMBB == &Fn.getEntryBlock()) { 983 ++NumEntryBlocks; 984 985 // Lower any arguments needed in this block if this is the entry block. 986 if (!FastIS->LowerArguments()) { 987 // Fast isel failed to lower these arguments 988 ++NumFastIselFailLowerArguments; 989 if (EnableFastISelAbortArgs) 990 llvm_unreachable("FastISel didn't lower all arguments"); 991 992 // Use SelectionDAG argument lowering 993 LowerArguments(Fn); 994 CurDAG->setRoot(SDB->getControlRoot()); 995 SDB->clear(); 996 CodeGenAndEmitDAG(); 997 } 998 999 // If we inserted any instructions at the beginning, make a note of 1000 // where they are, so we can be sure to emit subsequent instructions 1001 // after them. 1002 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1003 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1004 else 1005 FastIS->setLastLocalValue(0); 1006 } 1007 1008 unsigned NumFastIselRemaining = std::distance(Begin, End); 1009 // Do FastISel on as many instructions as possible. 1010 for (; BI != Begin; --BI) { 1011 const Instruction *Inst = llvm::prior(BI); 1012 1013 // If we no longer require this instruction, skip it. 1014 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1015 --NumFastIselRemaining; 1016 continue; 1017 } 1018 1019 // Bottom-up: reset the insert pos at the top, after any local-value 1020 // instructions. 1021 FastIS->recomputeInsertPt(); 1022 1023 // Try to select the instruction with FastISel. 1024 if (FastIS->SelectInstruction(Inst)) { 1025 --NumFastIselRemaining; 1026 ++NumFastIselSuccess; 1027 // If fast isel succeeded, skip over all the folded instructions, and 1028 // then see if there is a load right before the selected instructions. 1029 // Try to fold the load if so. 1030 const Instruction *BeforeInst = Inst; 1031 while (BeforeInst != Begin) { 1032 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1033 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1034 break; 1035 } 1036 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1037 BeforeInst->hasOneUse() && 1038 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1039 // If we succeeded, don't re-select the load. 1040 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1041 --NumFastIselRemaining; 1042 ++NumFastIselSuccess; 1043 } 1044 continue; 1045 } 1046 1047#ifndef NDEBUG 1048 if (EnableFastISelVerbose2) 1049 collectFailStats(Inst); 1050#endif 1051 1052 // Then handle certain instructions as single-LLVM-Instruction blocks. 1053 if (isa<CallInst>(Inst)) { 1054 1055 if (EnableFastISelVerbose || EnableFastISelAbort) { 1056 dbgs() << "FastISel missed call: "; 1057 Inst->dump(); 1058 } 1059 1060 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1061 unsigned &R = FuncInfo->ValueMap[Inst]; 1062 if (!R) 1063 R = FuncInfo->CreateRegs(Inst->getType()); 1064 } 1065 1066 bool HadTailCall = false; 1067 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1068 SelectBasicBlock(Inst, BI, HadTailCall); 1069 1070 // If the call was emitted as a tail call, we're done with the block. 1071 // We also need to delete any previously emitted instructions. 1072 if (HadTailCall) { 1073 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1074 --BI; 1075 break; 1076 } 1077 1078 // Recompute NumFastIselRemaining as Selection DAG instruction 1079 // selection may have handled the call, input args, etc. 1080 unsigned RemainingNow = std::distance(Begin, BI); 1081 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1082 NumFastIselRemaining = RemainingNow; 1083 continue; 1084 } 1085 1086 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1087 // Don't abort, and use a different message for terminator misses. 1088 NumFastIselFailures += NumFastIselRemaining; 1089 if (EnableFastISelVerbose || EnableFastISelAbort) { 1090 dbgs() << "FastISel missed terminator: "; 1091 Inst->dump(); 1092 } 1093 } else { 1094 NumFastIselFailures += NumFastIselRemaining; 1095 if (EnableFastISelVerbose || EnableFastISelAbort) { 1096 dbgs() << "FastISel miss: "; 1097 Inst->dump(); 1098 } 1099 if (EnableFastISelAbort) 1100 // The "fast" selector couldn't handle something and bailed. 1101 // For the purpose of debugging, just abort. 1102 llvm_unreachable("FastISel didn't select the entire block"); 1103 } 1104 break; 1105 } 1106 1107 FastIS->recomputeInsertPt(); 1108 } else { 1109 // Lower any arguments needed in this block if this is the entry block. 1110 if (LLVMBB == &Fn.getEntryBlock()) { 1111 ++NumEntryBlocks; 1112 LowerArguments(Fn); 1113 } 1114 } 1115 1116 if (Begin != BI) 1117 ++NumDAGBlocks; 1118 else 1119 ++NumFastIselBlocks; 1120 1121 if (Begin != BI) { 1122 // Run SelectionDAG instruction selection on the remainder of the block 1123 // not handled by FastISel. If FastISel is not run, this is the entire 1124 // block. 1125 bool HadTailCall; 1126 SelectBasicBlock(Begin, BI, HadTailCall); 1127 } 1128 1129 FinishBasicBlock(); 1130 FuncInfo->PHINodesToUpdate.clear(); 1131 } 1132 1133 delete FastIS; 1134 SDB->clearDanglingDebugInfo(); 1135} 1136 1137void 1138SelectionDAGISel::FinishBasicBlock() { 1139 1140 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1141 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1142 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1143 dbgs() << "Node " << i << " : (" 1144 << FuncInfo->PHINodesToUpdate[i].first 1145 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1146 1147 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1148 // PHI nodes in successors. 1149 if (SDB->SwitchCases.empty() && 1150 SDB->JTCases.empty() && 1151 SDB->BitTestCases.empty()) { 1152 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1153 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1154 assert(PHI->isPHI() && 1155 "This is not a machine PHI node that we are updating!"); 1156 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1157 continue; 1158 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1159 } 1160 return; 1161 } 1162 1163 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1164 // Lower header first, if it wasn't already lowered 1165 if (!SDB->BitTestCases[i].Emitted) { 1166 // Set the current basic block to the mbb we wish to insert the code into 1167 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1168 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1169 // Emit the code 1170 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1171 CurDAG->setRoot(SDB->getRoot()); 1172 SDB->clear(); 1173 CodeGenAndEmitDAG(); 1174 } 1175 1176 uint32_t UnhandledWeight = 0; 1177 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1178 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1179 1180 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1181 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1182 // Set the current basic block to the mbb we wish to insert the code into 1183 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1184 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1185 // Emit the code 1186 if (j+1 != ej) 1187 SDB->visitBitTestCase(SDB->BitTestCases[i], 1188 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1189 UnhandledWeight, 1190 SDB->BitTestCases[i].Reg, 1191 SDB->BitTestCases[i].Cases[j], 1192 FuncInfo->MBB); 1193 else 1194 SDB->visitBitTestCase(SDB->BitTestCases[i], 1195 SDB->BitTestCases[i].Default, 1196 UnhandledWeight, 1197 SDB->BitTestCases[i].Reg, 1198 SDB->BitTestCases[i].Cases[j], 1199 FuncInfo->MBB); 1200 1201 1202 CurDAG->setRoot(SDB->getRoot()); 1203 SDB->clear(); 1204 CodeGenAndEmitDAG(); 1205 } 1206 1207 // Update PHI Nodes 1208 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1209 pi != pe; ++pi) { 1210 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1211 MachineBasicBlock *PHIBB = PHI->getParent(); 1212 assert(PHI->isPHI() && 1213 "This is not a machine PHI node that we are updating!"); 1214 // This is "default" BB. We have two jumps to it. From "header" BB and 1215 // from last "case" BB. 1216 if (PHIBB == SDB->BitTestCases[i].Default) 1217 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1218 .addMBB(SDB->BitTestCases[i].Parent) 1219 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1220 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1221 // One of "cases" BB. 1222 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1223 j != ej; ++j) { 1224 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1225 if (cBB->isSuccessor(PHIBB)) 1226 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1227 } 1228 } 1229 } 1230 SDB->BitTestCases.clear(); 1231 1232 // If the JumpTable record is filled in, then we need to emit a jump table. 1233 // Updating the PHI nodes is tricky in this case, since we need to determine 1234 // whether the PHI is a successor of the range check MBB or the jump table MBB 1235 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1236 // Lower header first, if it wasn't already lowered 1237 if (!SDB->JTCases[i].first.Emitted) { 1238 // Set the current basic block to the mbb we wish to insert the code into 1239 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1240 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1241 // Emit the code 1242 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1243 FuncInfo->MBB); 1244 CurDAG->setRoot(SDB->getRoot()); 1245 SDB->clear(); 1246 CodeGenAndEmitDAG(); 1247 } 1248 1249 // Set the current basic block to the mbb we wish to insert the code into 1250 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1251 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1252 // Emit the code 1253 SDB->visitJumpTable(SDB->JTCases[i].second); 1254 CurDAG->setRoot(SDB->getRoot()); 1255 SDB->clear(); 1256 CodeGenAndEmitDAG(); 1257 1258 // Update PHI Nodes 1259 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1260 pi != pe; ++pi) { 1261 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1262 MachineBasicBlock *PHIBB = PHI->getParent(); 1263 assert(PHI->isPHI() && 1264 "This is not a machine PHI node that we are updating!"); 1265 // "default" BB. We can go there only from header BB. 1266 if (PHIBB == SDB->JTCases[i].second.Default) 1267 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1268 .addMBB(SDB->JTCases[i].first.HeaderBB); 1269 // JT BB. Just iterate over successors here 1270 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1271 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1272 } 1273 } 1274 SDB->JTCases.clear(); 1275 1276 // If the switch block involved a branch to one of the actual successors, we 1277 // need to update PHI nodes in that block. 1278 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1279 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1280 assert(PHI->isPHI() && 1281 "This is not a machine PHI node that we are updating!"); 1282 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1283 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1284 } 1285 1286 // If we generated any switch lowering information, build and codegen any 1287 // additional DAGs necessary. 1288 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1289 // Set the current basic block to the mbb we wish to insert the code into 1290 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1291 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1292 1293 // Determine the unique successors. 1294 SmallVector<MachineBasicBlock *, 2> Succs; 1295 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1296 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1297 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1298 1299 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1300 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1301 CurDAG->setRoot(SDB->getRoot()); 1302 SDB->clear(); 1303 CodeGenAndEmitDAG(); 1304 1305 // Remember the last block, now that any splitting is done, for use in 1306 // populating PHI nodes in successors. 1307 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1308 1309 // Handle any PHI nodes in successors of this chunk, as if we were coming 1310 // from the original BB before switch expansion. Note that PHI nodes can 1311 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1312 // handle them the right number of times. 1313 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1314 FuncInfo->MBB = Succs[i]; 1315 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1316 // FuncInfo->MBB may have been removed from the CFG if a branch was 1317 // constant folded. 1318 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1319 for (MachineBasicBlock::iterator 1320 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1321 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1322 MachineInstrBuilder PHI(*MF, MBBI); 1323 // This value for this PHI node is recorded in PHINodesToUpdate. 1324 for (unsigned pn = 0; ; ++pn) { 1325 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1326 "Didn't find PHI entry!"); 1327 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1328 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1329 break; 1330 } 1331 } 1332 } 1333 } 1334 } 1335 } 1336 SDB->SwitchCases.clear(); 1337} 1338 1339 1340/// Create the scheduler. If a specific scheduler was specified 1341/// via the SchedulerRegistry, use it, otherwise select the 1342/// one preferred by the target. 1343/// 1344ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1345 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1346 1347 if (!Ctor) { 1348 Ctor = ISHeuristic; 1349 RegisterScheduler::setDefault(Ctor); 1350 } 1351 1352 return Ctor(this, OptLevel); 1353} 1354 1355//===----------------------------------------------------------------------===// 1356// Helper functions used by the generated instruction selector. 1357//===----------------------------------------------------------------------===// 1358// Calls to these methods are generated by tblgen. 1359 1360/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1361/// the dag combiner simplified the 255, we still want to match. RHS is the 1362/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1363/// specified in the .td file (e.g. 255). 1364bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1365 int64_t DesiredMaskS) const { 1366 const APInt &ActualMask = RHS->getAPIntValue(); 1367 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1368 1369 // If the actual mask exactly matches, success! 1370 if (ActualMask == DesiredMask) 1371 return true; 1372 1373 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1374 if (ActualMask.intersects(~DesiredMask)) 1375 return false; 1376 1377 // Otherwise, the DAG Combiner may have proven that the value coming in is 1378 // either already zero or is not demanded. Check for known zero input bits. 1379 APInt NeededMask = DesiredMask & ~ActualMask; 1380 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1381 return true; 1382 1383 // TODO: check to see if missing bits are just not demanded. 1384 1385 // Otherwise, this pattern doesn't match. 1386 return false; 1387} 1388 1389/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1390/// the dag combiner simplified the 255, we still want to match. RHS is the 1391/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1392/// specified in the .td file (e.g. 255). 1393bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1394 int64_t DesiredMaskS) const { 1395 const APInt &ActualMask = RHS->getAPIntValue(); 1396 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1397 1398 // If the actual mask exactly matches, success! 1399 if (ActualMask == DesiredMask) 1400 return true; 1401 1402 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1403 if (ActualMask.intersects(~DesiredMask)) 1404 return false; 1405 1406 // Otherwise, the DAG Combiner may have proven that the value coming in is 1407 // either already zero or is not demanded. Check for known zero input bits. 1408 APInt NeededMask = DesiredMask & ~ActualMask; 1409 1410 APInt KnownZero, KnownOne; 1411 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1412 1413 // If all the missing bits in the or are already known to be set, match! 1414 if ((NeededMask & KnownOne) == NeededMask) 1415 return true; 1416 1417 // TODO: check to see if missing bits are just not demanded. 1418 1419 // Otherwise, this pattern doesn't match. 1420 return false; 1421} 1422 1423 1424/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1425/// by tblgen. Others should not call it. 1426void SelectionDAGISel:: 1427SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1428 std::vector<SDValue> InOps; 1429 std::swap(InOps, Ops); 1430 1431 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1432 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1433 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1434 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1435 1436 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1437 if (InOps[e-1].getValueType() == MVT::Glue) 1438 --e; // Don't process a glue operand if it is here. 1439 1440 while (i != e) { 1441 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1442 if (!InlineAsm::isMemKind(Flags)) { 1443 // Just skip over this operand, copying the operands verbatim. 1444 Ops.insert(Ops.end(), InOps.begin()+i, 1445 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1446 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1447 } else { 1448 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1449 "Memory operand with multiple values?"); 1450 // Otherwise, this is a memory operand. Ask the target to select it. 1451 std::vector<SDValue> SelOps; 1452 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1453 report_fatal_error("Could not match memory address. Inline asm" 1454 " failure!"); 1455 1456 // Add this to the output node. 1457 unsigned NewFlags = 1458 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1459 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1460 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1461 i += 2; 1462 } 1463 } 1464 1465 // Add the glue input back if present. 1466 if (e != InOps.size()) 1467 Ops.push_back(InOps.back()); 1468} 1469 1470/// findGlueUse - Return use of MVT::Glue value produced by the specified 1471/// SDNode. 1472/// 1473static SDNode *findGlueUse(SDNode *N) { 1474 unsigned FlagResNo = N->getNumValues()-1; 1475 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1476 SDUse &Use = I.getUse(); 1477 if (Use.getResNo() == FlagResNo) 1478 return Use.getUser(); 1479 } 1480 return NULL; 1481} 1482 1483/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1484/// This function recursively traverses up the operand chain, ignoring 1485/// certain nodes. 1486static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1487 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1488 bool IgnoreChains) { 1489 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1490 // greater than all of its (recursive) operands. If we scan to a point where 1491 // 'use' is smaller than the node we're scanning for, then we know we will 1492 // never find it. 1493 // 1494 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1495 // happen because we scan down to newly selected nodes in the case of glue 1496 // uses. 1497 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1498 return false; 1499 1500 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1501 // won't fail if we scan it again. 1502 if (!Visited.insert(Use)) 1503 return false; 1504 1505 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1506 // Ignore chain uses, they are validated by HandleMergeInputChains. 1507 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1508 continue; 1509 1510 SDNode *N = Use->getOperand(i).getNode(); 1511 if (N == Def) { 1512 if (Use == ImmedUse || Use == Root) 1513 continue; // We are not looking for immediate use. 1514 assert(N != Root); 1515 return true; 1516 } 1517 1518 // Traverse up the operand chain. 1519 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1520 return true; 1521 } 1522 return false; 1523} 1524 1525/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1526/// operand node N of U during instruction selection that starts at Root. 1527bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1528 SDNode *Root) const { 1529 if (OptLevel == CodeGenOpt::None) return false; 1530 return N.hasOneUse(); 1531} 1532 1533/// IsLegalToFold - Returns true if the specific operand node N of 1534/// U can be folded during instruction selection that starts at Root. 1535bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1536 CodeGenOpt::Level OptLevel, 1537 bool IgnoreChains) { 1538 if (OptLevel == CodeGenOpt::None) return false; 1539 1540 // If Root use can somehow reach N through a path that that doesn't contain 1541 // U then folding N would create a cycle. e.g. In the following 1542 // diagram, Root can reach N through X. If N is folded into into Root, then 1543 // X is both a predecessor and a successor of U. 1544 // 1545 // [N*] // 1546 // ^ ^ // 1547 // / \ // 1548 // [U*] [X]? // 1549 // ^ ^ // 1550 // \ / // 1551 // \ / // 1552 // [Root*] // 1553 // 1554 // * indicates nodes to be folded together. 1555 // 1556 // If Root produces glue, then it gets (even more) interesting. Since it 1557 // will be "glued" together with its glue use in the scheduler, we need to 1558 // check if it might reach N. 1559 // 1560 // [N*] // 1561 // ^ ^ // 1562 // / \ // 1563 // [U*] [X]? // 1564 // ^ ^ // 1565 // \ \ // 1566 // \ | // 1567 // [Root*] | // 1568 // ^ | // 1569 // f | // 1570 // | / // 1571 // [Y] / // 1572 // ^ / // 1573 // f / // 1574 // | / // 1575 // [GU] // 1576 // 1577 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1578 // (call it Fold), then X is a predecessor of GU and a successor of 1579 // Fold. But since Fold and GU are glued together, this will create 1580 // a cycle in the scheduling graph. 1581 1582 // If the node has glue, walk down the graph to the "lowest" node in the 1583 // glueged set. 1584 EVT VT = Root->getValueType(Root->getNumValues()-1); 1585 while (VT == MVT::Glue) { 1586 SDNode *GU = findGlueUse(Root); 1587 if (GU == NULL) 1588 break; 1589 Root = GU; 1590 VT = Root->getValueType(Root->getNumValues()-1); 1591 1592 // If our query node has a glue result with a use, we've walked up it. If 1593 // the user (which has already been selected) has a chain or indirectly uses 1594 // the chain, our WalkChainUsers predicate will not consider it. Because of 1595 // this, we cannot ignore chains in this predicate. 1596 IgnoreChains = false; 1597 } 1598 1599 1600 SmallPtrSet<SDNode*, 16> Visited; 1601 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1602} 1603 1604SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1605 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1606 SelectInlineAsmMemoryOperands(Ops); 1607 1608 EVT VTs[] = { MVT::Other, MVT::Glue }; 1609 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1610 VTs, &Ops[0], Ops.size()); 1611 New->setNodeId(-1); 1612 return New.getNode(); 1613} 1614 1615SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1616 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1617} 1618 1619/// GetVBR - decode a vbr encoding whose top bit is set. 1620LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1621GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1622 assert(Val >= 128 && "Not a VBR"); 1623 Val &= 127; // Remove first vbr bit. 1624 1625 unsigned Shift = 7; 1626 uint64_t NextBits; 1627 do { 1628 NextBits = MatcherTable[Idx++]; 1629 Val |= (NextBits&127) << Shift; 1630 Shift += 7; 1631 } while (NextBits & 128); 1632 1633 return Val; 1634} 1635 1636 1637/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1638/// interior glue and chain results to use the new glue and chain results. 1639void SelectionDAGISel:: 1640UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1641 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1642 SDValue InputGlue, 1643 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1644 bool isMorphNodeTo) { 1645 SmallVector<SDNode*, 4> NowDeadNodes; 1646 1647 // Now that all the normal results are replaced, we replace the chain and 1648 // glue results if present. 1649 if (!ChainNodesMatched.empty()) { 1650 assert(InputChain.getNode() != 0 && 1651 "Matched input chains but didn't produce a chain"); 1652 // Loop over all of the nodes we matched that produced a chain result. 1653 // Replace all the chain results with the final chain we ended up with. 1654 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1655 SDNode *ChainNode = ChainNodesMatched[i]; 1656 1657 // If this node was already deleted, don't look at it. 1658 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1659 continue; 1660 1661 // Don't replace the results of the root node if we're doing a 1662 // MorphNodeTo. 1663 if (ChainNode == NodeToMatch && isMorphNodeTo) 1664 continue; 1665 1666 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1667 if (ChainVal.getValueType() == MVT::Glue) 1668 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1669 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1670 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1671 1672 // If the node became dead and we haven't already seen it, delete it. 1673 if (ChainNode->use_empty() && 1674 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1675 NowDeadNodes.push_back(ChainNode); 1676 } 1677 } 1678 1679 // If the result produces glue, update any glue results in the matched 1680 // pattern with the glue result. 1681 if (InputGlue.getNode() != 0) { 1682 // Handle any interior nodes explicitly marked. 1683 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1684 SDNode *FRN = GlueResultNodesMatched[i]; 1685 1686 // If this node was already deleted, don't look at it. 1687 if (FRN->getOpcode() == ISD::DELETED_NODE) 1688 continue; 1689 1690 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1691 "Doesn't have a glue result"); 1692 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1693 InputGlue); 1694 1695 // If the node became dead and we haven't already seen it, delete it. 1696 if (FRN->use_empty() && 1697 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1698 NowDeadNodes.push_back(FRN); 1699 } 1700 } 1701 1702 if (!NowDeadNodes.empty()) 1703 CurDAG->RemoveDeadNodes(NowDeadNodes); 1704 1705 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1706} 1707 1708enum ChainResult { 1709 CR_Simple, 1710 CR_InducesCycle, 1711 CR_LeadsToInteriorNode 1712}; 1713 1714/// WalkChainUsers - Walk down the users of the specified chained node that is 1715/// part of the pattern we're matching, looking at all of the users we find. 1716/// This determines whether something is an interior node, whether we have a 1717/// non-pattern node in between two pattern nodes (which prevent folding because 1718/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1719/// between pattern nodes (in which case the TF becomes part of the pattern). 1720/// 1721/// The walk we do here is guaranteed to be small because we quickly get down to 1722/// already selected nodes "below" us. 1723static ChainResult 1724WalkChainUsers(const SDNode *ChainedNode, 1725 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1726 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1727 ChainResult Result = CR_Simple; 1728 1729 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1730 E = ChainedNode->use_end(); UI != E; ++UI) { 1731 // Make sure the use is of the chain, not some other value we produce. 1732 if (UI.getUse().getValueType() != MVT::Other) continue; 1733 1734 SDNode *User = *UI; 1735 1736 // If we see an already-selected machine node, then we've gone beyond the 1737 // pattern that we're selecting down into the already selected chunk of the 1738 // DAG. 1739 if (User->isMachineOpcode() || 1740 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1741 continue; 1742 1743 unsigned UserOpcode = User->getOpcode(); 1744 if (UserOpcode == ISD::CopyToReg || 1745 UserOpcode == ISD::CopyFromReg || 1746 UserOpcode == ISD::INLINEASM || 1747 UserOpcode == ISD::EH_LABEL || 1748 UserOpcode == ISD::LIFETIME_START || 1749 UserOpcode == ISD::LIFETIME_END) { 1750 // If their node ID got reset to -1 then they've already been selected. 1751 // Treat them like a MachineOpcode. 1752 if (User->getNodeId() == -1) 1753 continue; 1754 } 1755 1756 // If we have a TokenFactor, we handle it specially. 1757 if (User->getOpcode() != ISD::TokenFactor) { 1758 // If the node isn't a token factor and isn't part of our pattern, then it 1759 // must be a random chained node in between two nodes we're selecting. 1760 // This happens when we have something like: 1761 // x = load ptr 1762 // call 1763 // y = x+4 1764 // store y -> ptr 1765 // Because we structurally match the load/store as a read/modify/write, 1766 // but the call is chained between them. We cannot fold in this case 1767 // because it would induce a cycle in the graph. 1768 if (!std::count(ChainedNodesInPattern.begin(), 1769 ChainedNodesInPattern.end(), User)) 1770 return CR_InducesCycle; 1771 1772 // Otherwise we found a node that is part of our pattern. For example in: 1773 // x = load ptr 1774 // y = x+4 1775 // store y -> ptr 1776 // This would happen when we're scanning down from the load and see the 1777 // store as a user. Record that there is a use of ChainedNode that is 1778 // part of the pattern and keep scanning uses. 1779 Result = CR_LeadsToInteriorNode; 1780 InteriorChainedNodes.push_back(User); 1781 continue; 1782 } 1783 1784 // If we found a TokenFactor, there are two cases to consider: first if the 1785 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1786 // uses of the TF are in our pattern) we just want to ignore it. Second, 1787 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1788 // [Load chain] 1789 // ^ 1790 // | 1791 // [Load] 1792 // ^ ^ 1793 // | \ DAG's like cheese 1794 // / \ do you? 1795 // / | 1796 // [TokenFactor] [Op] 1797 // ^ ^ 1798 // | | 1799 // \ / 1800 // \ / 1801 // [Store] 1802 // 1803 // In this case, the TokenFactor becomes part of our match and we rewrite it 1804 // as a new TokenFactor. 1805 // 1806 // To distinguish these two cases, do a recursive walk down the uses. 1807 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1808 case CR_Simple: 1809 // If the uses of the TokenFactor are just already-selected nodes, ignore 1810 // it, it is "below" our pattern. 1811 continue; 1812 case CR_InducesCycle: 1813 // If the uses of the TokenFactor lead to nodes that are not part of our 1814 // pattern that are not selected, folding would turn this into a cycle, 1815 // bail out now. 1816 return CR_InducesCycle; 1817 case CR_LeadsToInteriorNode: 1818 break; // Otherwise, keep processing. 1819 } 1820 1821 // Okay, we know we're in the interesting interior case. The TokenFactor 1822 // is now going to be considered part of the pattern so that we rewrite its 1823 // uses (it may have uses that are not part of the pattern) with the 1824 // ultimate chain result of the generated code. We will also add its chain 1825 // inputs as inputs to the ultimate TokenFactor we create. 1826 Result = CR_LeadsToInteriorNode; 1827 ChainedNodesInPattern.push_back(User); 1828 InteriorChainedNodes.push_back(User); 1829 continue; 1830 } 1831 1832 return Result; 1833} 1834 1835/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1836/// operation for when the pattern matched at least one node with a chains. The 1837/// input vector contains a list of all of the chained nodes that we match. We 1838/// must determine if this is a valid thing to cover (i.e. matching it won't 1839/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1840/// be used as the input node chain for the generated nodes. 1841static SDValue 1842HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1843 SelectionDAG *CurDAG) { 1844 // Walk all of the chained nodes we've matched, recursively scanning down the 1845 // users of the chain result. This adds any TokenFactor nodes that are caught 1846 // in between chained nodes to the chained and interior nodes list. 1847 SmallVector<SDNode*, 3> InteriorChainedNodes; 1848 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1849 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1850 InteriorChainedNodes) == CR_InducesCycle) 1851 return SDValue(); // Would induce a cycle. 1852 } 1853 1854 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1855 // that we are interested in. Form our input TokenFactor node. 1856 SmallVector<SDValue, 3> InputChains; 1857 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1858 // Add the input chain of this node to the InputChains list (which will be 1859 // the operands of the generated TokenFactor) if it's not an interior node. 1860 SDNode *N = ChainNodesMatched[i]; 1861 if (N->getOpcode() != ISD::TokenFactor) { 1862 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1863 continue; 1864 1865 // Otherwise, add the input chain. 1866 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1867 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1868 InputChains.push_back(InChain); 1869 continue; 1870 } 1871 1872 // If we have a token factor, we want to add all inputs of the token factor 1873 // that are not part of the pattern we're matching. 1874 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1875 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1876 N->getOperand(op).getNode())) 1877 InputChains.push_back(N->getOperand(op)); 1878 } 1879 } 1880 1881 SDValue Res; 1882 if (InputChains.size() == 1) 1883 return InputChains[0]; 1884 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1885 MVT::Other, &InputChains[0], InputChains.size()); 1886} 1887 1888/// MorphNode - Handle morphing a node in place for the selector. 1889SDNode *SelectionDAGISel:: 1890MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1891 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1892 // It is possible we're using MorphNodeTo to replace a node with no 1893 // normal results with one that has a normal result (or we could be 1894 // adding a chain) and the input could have glue and chains as well. 1895 // In this case we need to shift the operands down. 1896 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1897 // than the old isel though. 1898 int OldGlueResultNo = -1, OldChainResultNo = -1; 1899 1900 unsigned NTMNumResults = Node->getNumValues(); 1901 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1902 OldGlueResultNo = NTMNumResults-1; 1903 if (NTMNumResults != 1 && 1904 Node->getValueType(NTMNumResults-2) == MVT::Other) 1905 OldChainResultNo = NTMNumResults-2; 1906 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1907 OldChainResultNo = NTMNumResults-1; 1908 1909 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1910 // that this deletes operands of the old node that become dead. 1911 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1912 1913 // MorphNodeTo can operate in two ways: if an existing node with the 1914 // specified operands exists, it can just return it. Otherwise, it 1915 // updates the node in place to have the requested operands. 1916 if (Res == Node) { 1917 // If we updated the node in place, reset the node ID. To the isel, 1918 // this should be just like a newly allocated machine node. 1919 Res->setNodeId(-1); 1920 } 1921 1922 unsigned ResNumResults = Res->getNumValues(); 1923 // Move the glue if needed. 1924 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1925 (unsigned)OldGlueResultNo != ResNumResults-1) 1926 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1927 SDValue(Res, ResNumResults-1)); 1928 1929 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1930 --ResNumResults; 1931 1932 // Move the chain reference if needed. 1933 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1934 (unsigned)OldChainResultNo != ResNumResults-1) 1935 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1936 SDValue(Res, ResNumResults-1)); 1937 1938 // Otherwise, no replacement happened because the node already exists. Replace 1939 // Uses of the old node with the new one. 1940 if (Res != Node) 1941 CurDAG->ReplaceAllUsesWith(Node, Res); 1942 1943 return Res; 1944} 1945 1946/// CheckSame - Implements OP_CheckSame. 1947LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1948CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1949 SDValue N, 1950 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 1951 // Accept if it is exactly the same as a previously recorded node. 1952 unsigned RecNo = MatcherTable[MatcherIndex++]; 1953 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 1954 return N == RecordedNodes[RecNo].first; 1955} 1956 1957/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 1958LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1959CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1960 const SelectionDAGISel &SDISel) { 1961 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 1962} 1963 1964/// CheckNodePredicate - Implements OP_CheckNodePredicate. 1965LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1966CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1967 const SelectionDAGISel &SDISel, SDNode *N) { 1968 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 1969} 1970 1971LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1972CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1973 SDNode *N) { 1974 uint16_t Opc = MatcherTable[MatcherIndex++]; 1975 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 1976 return N->getOpcode() == Opc; 1977} 1978 1979LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1980CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1981 SDValue N, const TargetLowering &TLI) { 1982 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 1983 if (N.getValueType() == VT) return true; 1984 1985 // Handle the case when VT is iPTR. 1986 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 1987} 1988 1989LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 1990CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 1991 SDValue N, const TargetLowering &TLI, 1992 unsigned ChildNo) { 1993 if (ChildNo >= N.getNumOperands()) 1994 return false; // Match fails if out of range child #. 1995 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 1996} 1997 1998 1999LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2000CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2001 SDValue N) { 2002 return cast<CondCodeSDNode>(N)->get() == 2003 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2004} 2005 2006LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2007CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2008 SDValue N, const TargetLowering &TLI) { 2009 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2010 if (cast<VTSDNode>(N)->getVT() == VT) 2011 return true; 2012 2013 // Handle the case when VT is iPTR. 2014 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2015} 2016 2017LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2018CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2019 SDValue N) { 2020 int64_t Val = MatcherTable[MatcherIndex++]; 2021 if (Val & 128) 2022 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2023 2024 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2025 return C != 0 && C->getSExtValue() == Val; 2026} 2027 2028LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2029CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2030 SDValue N, const SelectionDAGISel &SDISel) { 2031 int64_t Val = MatcherTable[MatcherIndex++]; 2032 if (Val & 128) 2033 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2034 2035 if (N->getOpcode() != ISD::AND) return false; 2036 2037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2038 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2039} 2040 2041LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2042CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2043 SDValue N, const SelectionDAGISel &SDISel) { 2044 int64_t Val = MatcherTable[MatcherIndex++]; 2045 if (Val & 128) 2046 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2047 2048 if (N->getOpcode() != ISD::OR) return false; 2049 2050 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2051 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2052} 2053 2054/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2055/// scope, evaluate the current node. If the current predicate is known to 2056/// fail, set Result=true and return anything. If the current predicate is 2057/// known to pass, set Result=false and return the MatcherIndex to continue 2058/// with. If the current predicate is unknown, set Result=false and return the 2059/// MatcherIndex to continue with. 2060static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2061 unsigned Index, SDValue N, 2062 bool &Result, 2063 const SelectionDAGISel &SDISel, 2064 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2065 switch (Table[Index++]) { 2066 default: 2067 Result = false; 2068 return Index-1; // Could not evaluate this predicate. 2069 case SelectionDAGISel::OPC_CheckSame: 2070 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2071 return Index; 2072 case SelectionDAGISel::OPC_CheckPatternPredicate: 2073 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2074 return Index; 2075 case SelectionDAGISel::OPC_CheckPredicate: 2076 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2077 return Index; 2078 case SelectionDAGISel::OPC_CheckOpcode: 2079 Result = !::CheckOpcode(Table, Index, N.getNode()); 2080 return Index; 2081 case SelectionDAGISel::OPC_CheckType: 2082 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2083 return Index; 2084 case SelectionDAGISel::OPC_CheckChild0Type: 2085 case SelectionDAGISel::OPC_CheckChild1Type: 2086 case SelectionDAGISel::OPC_CheckChild2Type: 2087 case SelectionDAGISel::OPC_CheckChild3Type: 2088 case SelectionDAGISel::OPC_CheckChild4Type: 2089 case SelectionDAGISel::OPC_CheckChild5Type: 2090 case SelectionDAGISel::OPC_CheckChild6Type: 2091 case SelectionDAGISel::OPC_CheckChild7Type: 2092 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2093 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2094 return Index; 2095 case SelectionDAGISel::OPC_CheckCondCode: 2096 Result = !::CheckCondCode(Table, Index, N); 2097 return Index; 2098 case SelectionDAGISel::OPC_CheckValueType: 2099 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2100 return Index; 2101 case SelectionDAGISel::OPC_CheckInteger: 2102 Result = !::CheckInteger(Table, Index, N); 2103 return Index; 2104 case SelectionDAGISel::OPC_CheckAndImm: 2105 Result = !::CheckAndImm(Table, Index, N, SDISel); 2106 return Index; 2107 case SelectionDAGISel::OPC_CheckOrImm: 2108 Result = !::CheckOrImm(Table, Index, N, SDISel); 2109 return Index; 2110 } 2111} 2112 2113namespace { 2114 2115struct MatchScope { 2116 /// FailIndex - If this match fails, this is the index to continue with. 2117 unsigned FailIndex; 2118 2119 /// NodeStack - The node stack when the scope was formed. 2120 SmallVector<SDValue, 4> NodeStack; 2121 2122 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2123 unsigned NumRecordedNodes; 2124 2125 /// NumMatchedMemRefs - The number of matched memref entries. 2126 unsigned NumMatchedMemRefs; 2127 2128 /// InputChain/InputGlue - The current chain/glue 2129 SDValue InputChain, InputGlue; 2130 2131 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2132 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2133}; 2134 2135} 2136 2137SDNode *SelectionDAGISel:: 2138SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2139 unsigned TableSize) { 2140 // FIXME: Should these even be selected? Handle these cases in the caller? 2141 switch (NodeToMatch->getOpcode()) { 2142 default: 2143 break; 2144 case ISD::EntryToken: // These nodes remain the same. 2145 case ISD::BasicBlock: 2146 case ISD::Register: 2147 case ISD::RegisterMask: 2148 //case ISD::VALUETYPE: 2149 //case ISD::CONDCODE: 2150 case ISD::HANDLENODE: 2151 case ISD::MDNODE_SDNODE: 2152 case ISD::TargetConstant: 2153 case ISD::TargetConstantFP: 2154 case ISD::TargetConstantPool: 2155 case ISD::TargetFrameIndex: 2156 case ISD::TargetExternalSymbol: 2157 case ISD::TargetBlockAddress: 2158 case ISD::TargetJumpTable: 2159 case ISD::TargetGlobalTLSAddress: 2160 case ISD::TargetGlobalAddress: 2161 case ISD::TokenFactor: 2162 case ISD::CopyFromReg: 2163 case ISD::CopyToReg: 2164 case ISD::EH_LABEL: 2165 case ISD::LIFETIME_START: 2166 case ISD::LIFETIME_END: 2167 NodeToMatch->setNodeId(-1); // Mark selected. 2168 return 0; 2169 case ISD::AssertSext: 2170 case ISD::AssertZext: 2171 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2172 NodeToMatch->getOperand(0)); 2173 return 0; 2174 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2175 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2176 } 2177 2178 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2179 2180 // Set up the node stack with NodeToMatch as the only node on the stack. 2181 SmallVector<SDValue, 8> NodeStack; 2182 SDValue N = SDValue(NodeToMatch, 0); 2183 NodeStack.push_back(N); 2184 2185 // MatchScopes - Scopes used when matching, if a match failure happens, this 2186 // indicates where to continue checking. 2187 SmallVector<MatchScope, 8> MatchScopes; 2188 2189 // RecordedNodes - This is the set of nodes that have been recorded by the 2190 // state machine. The second value is the parent of the node, or null if the 2191 // root is recorded. 2192 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2193 2194 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2195 // pattern. 2196 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2197 2198 // These are the current input chain and glue for use when generating nodes. 2199 // Various Emit operations change these. For example, emitting a copytoreg 2200 // uses and updates these. 2201 SDValue InputChain, InputGlue; 2202 2203 // ChainNodesMatched - If a pattern matches nodes that have input/output 2204 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2205 // which ones they are. The result is captured into this list so that we can 2206 // update the chain results when the pattern is complete. 2207 SmallVector<SDNode*, 3> ChainNodesMatched; 2208 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2209 2210 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2211 NodeToMatch->dump(CurDAG); 2212 dbgs() << '\n'); 2213 2214 // Determine where to start the interpreter. Normally we start at opcode #0, 2215 // but if the state machine starts with an OPC_SwitchOpcode, then we 2216 // accelerate the first lookup (which is guaranteed to be hot) with the 2217 // OpcodeOffset table. 2218 unsigned MatcherIndex = 0; 2219 2220 if (!OpcodeOffset.empty()) { 2221 // Already computed the OpcodeOffset table, just index into it. 2222 if (N.getOpcode() < OpcodeOffset.size()) 2223 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2224 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2225 2226 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2227 // Otherwise, the table isn't computed, but the state machine does start 2228 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2229 // is the first time we're selecting an instruction. 2230 unsigned Idx = 1; 2231 while (1) { 2232 // Get the size of this case. 2233 unsigned CaseSize = MatcherTable[Idx++]; 2234 if (CaseSize & 128) 2235 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2236 if (CaseSize == 0) break; 2237 2238 // Get the opcode, add the index to the table. 2239 uint16_t Opc = MatcherTable[Idx++]; 2240 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2241 if (Opc >= OpcodeOffset.size()) 2242 OpcodeOffset.resize((Opc+1)*2); 2243 OpcodeOffset[Opc] = Idx; 2244 Idx += CaseSize; 2245 } 2246 2247 // Okay, do the lookup for the first opcode. 2248 if (N.getOpcode() < OpcodeOffset.size()) 2249 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2250 } 2251 2252 while (1) { 2253 assert(MatcherIndex < TableSize && "Invalid index"); 2254#ifndef NDEBUG 2255 unsigned CurrentOpcodeIndex = MatcherIndex; 2256#endif 2257 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2258 switch (Opcode) { 2259 case OPC_Scope: { 2260 // Okay, the semantics of this operation are that we should push a scope 2261 // then evaluate the first child. However, pushing a scope only to have 2262 // the first check fail (which then pops it) is inefficient. If we can 2263 // determine immediately that the first check (or first several) will 2264 // immediately fail, don't even bother pushing a scope for them. 2265 unsigned FailIndex; 2266 2267 while (1) { 2268 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2269 if (NumToSkip & 128) 2270 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2271 // Found the end of the scope with no match. 2272 if (NumToSkip == 0) { 2273 FailIndex = 0; 2274 break; 2275 } 2276 2277 FailIndex = MatcherIndex+NumToSkip; 2278 2279 unsigned MatcherIndexOfPredicate = MatcherIndex; 2280 (void)MatcherIndexOfPredicate; // silence warning. 2281 2282 // If we can't evaluate this predicate without pushing a scope (e.g. if 2283 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2284 // push the scope and evaluate the full predicate chain. 2285 bool Result; 2286 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2287 Result, *this, RecordedNodes); 2288 if (!Result) 2289 break; 2290 2291 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2292 << "index " << MatcherIndexOfPredicate 2293 << ", continuing at " << FailIndex << "\n"); 2294 ++NumDAGIselRetries; 2295 2296 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2297 // move to the next case. 2298 MatcherIndex = FailIndex; 2299 } 2300 2301 // If the whole scope failed to match, bail. 2302 if (FailIndex == 0) break; 2303 2304 // Push a MatchScope which indicates where to go if the first child fails 2305 // to match. 2306 MatchScope NewEntry; 2307 NewEntry.FailIndex = FailIndex; 2308 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2309 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2310 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2311 NewEntry.InputChain = InputChain; 2312 NewEntry.InputGlue = InputGlue; 2313 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2314 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2315 MatchScopes.push_back(NewEntry); 2316 continue; 2317 } 2318 case OPC_RecordNode: { 2319 // Remember this node, it may end up being an operand in the pattern. 2320 SDNode *Parent = 0; 2321 if (NodeStack.size() > 1) 2322 Parent = NodeStack[NodeStack.size()-2].getNode(); 2323 RecordedNodes.push_back(std::make_pair(N, Parent)); 2324 continue; 2325 } 2326 2327 case OPC_RecordChild0: case OPC_RecordChild1: 2328 case OPC_RecordChild2: case OPC_RecordChild3: 2329 case OPC_RecordChild4: case OPC_RecordChild5: 2330 case OPC_RecordChild6: case OPC_RecordChild7: { 2331 unsigned ChildNo = Opcode-OPC_RecordChild0; 2332 if (ChildNo >= N.getNumOperands()) 2333 break; // Match fails if out of range child #. 2334 2335 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2336 N.getNode())); 2337 continue; 2338 } 2339 case OPC_RecordMemRef: 2340 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2341 continue; 2342 2343 case OPC_CaptureGlueInput: 2344 // If the current node has an input glue, capture it in InputGlue. 2345 if (N->getNumOperands() != 0 && 2346 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2347 InputGlue = N->getOperand(N->getNumOperands()-1); 2348 continue; 2349 2350 case OPC_MoveChild: { 2351 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2352 if (ChildNo >= N.getNumOperands()) 2353 break; // Match fails if out of range child #. 2354 N = N.getOperand(ChildNo); 2355 NodeStack.push_back(N); 2356 continue; 2357 } 2358 2359 case OPC_MoveParent: 2360 // Pop the current node off the NodeStack. 2361 NodeStack.pop_back(); 2362 assert(!NodeStack.empty() && "Node stack imbalance!"); 2363 N = NodeStack.back(); 2364 continue; 2365 2366 case OPC_CheckSame: 2367 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2368 continue; 2369 case OPC_CheckPatternPredicate: 2370 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2371 continue; 2372 case OPC_CheckPredicate: 2373 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2374 N.getNode())) 2375 break; 2376 continue; 2377 case OPC_CheckComplexPat: { 2378 unsigned CPNum = MatcherTable[MatcherIndex++]; 2379 unsigned RecNo = MatcherTable[MatcherIndex++]; 2380 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2381 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2382 RecordedNodes[RecNo].first, CPNum, 2383 RecordedNodes)) 2384 break; 2385 continue; 2386 } 2387 case OPC_CheckOpcode: 2388 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2389 continue; 2390 2391 case OPC_CheckType: 2392 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2393 continue; 2394 2395 case OPC_SwitchOpcode: { 2396 unsigned CurNodeOpcode = N.getOpcode(); 2397 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2398 unsigned CaseSize; 2399 while (1) { 2400 // Get the size of this case. 2401 CaseSize = MatcherTable[MatcherIndex++]; 2402 if (CaseSize & 128) 2403 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2404 if (CaseSize == 0) break; 2405 2406 uint16_t Opc = MatcherTable[MatcherIndex++]; 2407 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2408 2409 // If the opcode matches, then we will execute this case. 2410 if (CurNodeOpcode == Opc) 2411 break; 2412 2413 // Otherwise, skip over this case. 2414 MatcherIndex += CaseSize; 2415 } 2416 2417 // If no cases matched, bail out. 2418 if (CaseSize == 0) break; 2419 2420 // Otherwise, execute the case we found. 2421 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2422 << " to " << MatcherIndex << "\n"); 2423 continue; 2424 } 2425 2426 case OPC_SwitchType: { 2427 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2428 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2429 unsigned CaseSize; 2430 while (1) { 2431 // Get the size of this case. 2432 CaseSize = MatcherTable[MatcherIndex++]; 2433 if (CaseSize & 128) 2434 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2435 if (CaseSize == 0) break; 2436 2437 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2438 if (CaseVT == MVT::iPTR) 2439 CaseVT = TLI.getPointerTy(); 2440 2441 // If the VT matches, then we will execute this case. 2442 if (CurNodeVT == CaseVT) 2443 break; 2444 2445 // Otherwise, skip over this case. 2446 MatcherIndex += CaseSize; 2447 } 2448 2449 // If no cases matched, bail out. 2450 if (CaseSize == 0) break; 2451 2452 // Otherwise, execute the case we found. 2453 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2454 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2455 continue; 2456 } 2457 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2458 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2459 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2460 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2461 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2462 Opcode-OPC_CheckChild0Type)) 2463 break; 2464 continue; 2465 case OPC_CheckCondCode: 2466 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2467 continue; 2468 case OPC_CheckValueType: 2469 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2470 continue; 2471 case OPC_CheckInteger: 2472 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2473 continue; 2474 case OPC_CheckAndImm: 2475 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2476 continue; 2477 case OPC_CheckOrImm: 2478 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2479 continue; 2480 2481 case OPC_CheckFoldableChainNode: { 2482 assert(NodeStack.size() != 1 && "No parent node"); 2483 // Verify that all intermediate nodes between the root and this one have 2484 // a single use. 2485 bool HasMultipleUses = false; 2486 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2487 if (!NodeStack[i].hasOneUse()) { 2488 HasMultipleUses = true; 2489 break; 2490 } 2491 if (HasMultipleUses) break; 2492 2493 // Check to see that the target thinks this is profitable to fold and that 2494 // we can fold it without inducing cycles in the graph. 2495 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2496 NodeToMatch) || 2497 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2498 NodeToMatch, OptLevel, 2499 true/*We validate our own chains*/)) 2500 break; 2501 2502 continue; 2503 } 2504 case OPC_EmitInteger: { 2505 MVT::SimpleValueType VT = 2506 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2507 int64_t Val = MatcherTable[MatcherIndex++]; 2508 if (Val & 128) 2509 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2510 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2511 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2512 continue; 2513 } 2514 case OPC_EmitRegister: { 2515 MVT::SimpleValueType VT = 2516 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2517 unsigned RegNo = MatcherTable[MatcherIndex++]; 2518 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2519 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2520 continue; 2521 } 2522 case OPC_EmitRegister2: { 2523 // For targets w/ more than 256 register names, the register enum 2524 // values are stored in two bytes in the matcher table (just like 2525 // opcodes). 2526 MVT::SimpleValueType VT = 2527 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2528 unsigned RegNo = MatcherTable[MatcherIndex++]; 2529 RegNo |= MatcherTable[MatcherIndex++] << 8; 2530 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2531 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2532 continue; 2533 } 2534 2535 case OPC_EmitConvertToTarget: { 2536 // Convert from IMM/FPIMM to target version. 2537 unsigned RecNo = MatcherTable[MatcherIndex++]; 2538 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2539 SDValue Imm = RecordedNodes[RecNo].first; 2540 2541 if (Imm->getOpcode() == ISD::Constant) { 2542 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2543 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2544 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2545 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2546 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2547 } 2548 2549 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2550 continue; 2551 } 2552 2553 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2554 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2555 // These are space-optimized forms of OPC_EmitMergeInputChains. 2556 assert(InputChain.getNode() == 0 && 2557 "EmitMergeInputChains should be the first chain producing node"); 2558 assert(ChainNodesMatched.empty() && 2559 "Should only have one EmitMergeInputChains per match"); 2560 2561 // Read all of the chained nodes. 2562 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2563 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2564 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2565 2566 // FIXME: What if other value results of the node have uses not matched 2567 // by this pattern? 2568 if (ChainNodesMatched.back() != NodeToMatch && 2569 !RecordedNodes[RecNo].first.hasOneUse()) { 2570 ChainNodesMatched.clear(); 2571 break; 2572 } 2573 2574 // Merge the input chains if they are not intra-pattern references. 2575 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2576 2577 if (InputChain.getNode() == 0) 2578 break; // Failed to merge. 2579 continue; 2580 } 2581 2582 case OPC_EmitMergeInputChains: { 2583 assert(InputChain.getNode() == 0 && 2584 "EmitMergeInputChains should be the first chain producing node"); 2585 // This node gets a list of nodes we matched in the input that have 2586 // chains. We want to token factor all of the input chains to these nodes 2587 // together. However, if any of the input chains is actually one of the 2588 // nodes matched in this pattern, then we have an intra-match reference. 2589 // Ignore these because the newly token factored chain should not refer to 2590 // the old nodes. 2591 unsigned NumChains = MatcherTable[MatcherIndex++]; 2592 assert(NumChains != 0 && "Can't TF zero chains"); 2593 2594 assert(ChainNodesMatched.empty() && 2595 "Should only have one EmitMergeInputChains per match"); 2596 2597 // Read all of the chained nodes. 2598 for (unsigned i = 0; i != NumChains; ++i) { 2599 unsigned RecNo = MatcherTable[MatcherIndex++]; 2600 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2601 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2602 2603 // FIXME: What if other value results of the node have uses not matched 2604 // by this pattern? 2605 if (ChainNodesMatched.back() != NodeToMatch && 2606 !RecordedNodes[RecNo].first.hasOneUse()) { 2607 ChainNodesMatched.clear(); 2608 break; 2609 } 2610 } 2611 2612 // If the inner loop broke out, the match fails. 2613 if (ChainNodesMatched.empty()) 2614 break; 2615 2616 // Merge the input chains if they are not intra-pattern references. 2617 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2618 2619 if (InputChain.getNode() == 0) 2620 break; // Failed to merge. 2621 2622 continue; 2623 } 2624 2625 case OPC_EmitCopyToReg: { 2626 unsigned RecNo = MatcherTable[MatcherIndex++]; 2627 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2628 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2629 2630 if (InputChain.getNode() == 0) 2631 InputChain = CurDAG->getEntryNode(); 2632 2633 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2634 DestPhysReg, RecordedNodes[RecNo].first, 2635 InputGlue); 2636 2637 InputGlue = InputChain.getValue(1); 2638 continue; 2639 } 2640 2641 case OPC_EmitNodeXForm: { 2642 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2643 unsigned RecNo = MatcherTable[MatcherIndex++]; 2644 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2645 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2646 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2647 continue; 2648 } 2649 2650 case OPC_EmitNode: 2651 case OPC_MorphNodeTo: { 2652 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2653 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2654 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2655 // Get the result VT list. 2656 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2657 SmallVector<EVT, 4> VTs; 2658 for (unsigned i = 0; i != NumVTs; ++i) { 2659 MVT::SimpleValueType VT = 2660 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2661 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2662 VTs.push_back(VT); 2663 } 2664 2665 if (EmitNodeInfo & OPFL_Chain) 2666 VTs.push_back(MVT::Other); 2667 if (EmitNodeInfo & OPFL_GlueOutput) 2668 VTs.push_back(MVT::Glue); 2669 2670 // This is hot code, so optimize the two most common cases of 1 and 2 2671 // results. 2672 SDVTList VTList; 2673 if (VTs.size() == 1) 2674 VTList = CurDAG->getVTList(VTs[0]); 2675 else if (VTs.size() == 2) 2676 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2677 else 2678 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2679 2680 // Get the operand list. 2681 unsigned NumOps = MatcherTable[MatcherIndex++]; 2682 SmallVector<SDValue, 8> Ops; 2683 for (unsigned i = 0; i != NumOps; ++i) { 2684 unsigned RecNo = MatcherTable[MatcherIndex++]; 2685 if (RecNo & 128) 2686 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2687 2688 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2689 Ops.push_back(RecordedNodes[RecNo].first); 2690 } 2691 2692 // If there are variadic operands to add, handle them now. 2693 if (EmitNodeInfo & OPFL_VariadicInfo) { 2694 // Determine the start index to copy from. 2695 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2696 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2697 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2698 "Invalid variadic node"); 2699 // Copy all of the variadic operands, not including a potential glue 2700 // input. 2701 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2702 i != e; ++i) { 2703 SDValue V = NodeToMatch->getOperand(i); 2704 if (V.getValueType() == MVT::Glue) break; 2705 Ops.push_back(V); 2706 } 2707 } 2708 2709 // If this has chain/glue inputs, add them. 2710 if (EmitNodeInfo & OPFL_Chain) 2711 Ops.push_back(InputChain); 2712 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2713 Ops.push_back(InputGlue); 2714 2715 // Create the node. 2716 SDNode *Res = 0; 2717 if (Opcode != OPC_MorphNodeTo) { 2718 // If this is a normal EmitNode command, just create the new node and 2719 // add the results to the RecordedNodes list. 2720 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2721 VTList, Ops); 2722 2723 // Add all the non-glue/non-chain results to the RecordedNodes list. 2724 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2725 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2726 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2727 (SDNode*) 0)); 2728 } 2729 2730 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2731 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2732 EmitNodeInfo); 2733 } else { 2734 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2735 // We will visit the equivalent node later. 2736 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2737 return 0; 2738 } 2739 2740 // If the node had chain/glue results, update our notion of the current 2741 // chain and glue. 2742 if (EmitNodeInfo & OPFL_GlueOutput) { 2743 InputGlue = SDValue(Res, VTs.size()-1); 2744 if (EmitNodeInfo & OPFL_Chain) 2745 InputChain = SDValue(Res, VTs.size()-2); 2746 } else if (EmitNodeInfo & OPFL_Chain) 2747 InputChain = SDValue(Res, VTs.size()-1); 2748 2749 // If the OPFL_MemRefs glue is set on this node, slap all of the 2750 // accumulated memrefs onto it. 2751 // 2752 // FIXME: This is vastly incorrect for patterns with multiple outputs 2753 // instructions that access memory and for ComplexPatterns that match 2754 // loads. 2755 if (EmitNodeInfo & OPFL_MemRefs) { 2756 // Only attach load or store memory operands if the generated 2757 // instruction may load or store. 2758 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2759 bool mayLoad = MCID.mayLoad(); 2760 bool mayStore = MCID.mayStore(); 2761 2762 unsigned NumMemRefs = 0; 2763 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2764 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2765 if ((*I)->isLoad()) { 2766 if (mayLoad) 2767 ++NumMemRefs; 2768 } else if ((*I)->isStore()) { 2769 if (mayStore) 2770 ++NumMemRefs; 2771 } else { 2772 ++NumMemRefs; 2773 } 2774 } 2775 2776 MachineSDNode::mmo_iterator MemRefs = 2777 MF->allocateMemRefsArray(NumMemRefs); 2778 2779 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2780 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2781 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2782 if ((*I)->isLoad()) { 2783 if (mayLoad) 2784 *MemRefsPos++ = *I; 2785 } else if ((*I)->isStore()) { 2786 if (mayStore) 2787 *MemRefsPos++ = *I; 2788 } else { 2789 *MemRefsPos++ = *I; 2790 } 2791 } 2792 2793 cast<MachineSDNode>(Res) 2794 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2795 } 2796 2797 DEBUG(dbgs() << " " 2798 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2799 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 2800 2801 // If this was a MorphNodeTo then we're completely done! 2802 if (Opcode == OPC_MorphNodeTo) { 2803 // Update chain and glue uses. 2804 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2805 InputGlue, GlueResultNodesMatched, true); 2806 return Res; 2807 } 2808 2809 continue; 2810 } 2811 2812 case OPC_MarkGlueResults: { 2813 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2814 2815 // Read and remember all the glue-result nodes. 2816 for (unsigned i = 0; i != NumNodes; ++i) { 2817 unsigned RecNo = MatcherTable[MatcherIndex++]; 2818 if (RecNo & 128) 2819 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2820 2821 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2822 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2823 } 2824 continue; 2825 } 2826 2827 case OPC_CompleteMatch: { 2828 // The match has been completed, and any new nodes (if any) have been 2829 // created. Patch up references to the matched dag to use the newly 2830 // created nodes. 2831 unsigned NumResults = MatcherTable[MatcherIndex++]; 2832 2833 for (unsigned i = 0; i != NumResults; ++i) { 2834 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2835 if (ResSlot & 128) 2836 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2837 2838 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2839 SDValue Res = RecordedNodes[ResSlot].first; 2840 2841 assert(i < NodeToMatch->getNumValues() && 2842 NodeToMatch->getValueType(i) != MVT::Other && 2843 NodeToMatch->getValueType(i) != MVT::Glue && 2844 "Invalid number of results to complete!"); 2845 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2846 NodeToMatch->getValueType(i) == MVT::iPTR || 2847 Res.getValueType() == MVT::iPTR || 2848 NodeToMatch->getValueType(i).getSizeInBits() == 2849 Res.getValueType().getSizeInBits()) && 2850 "invalid replacement"); 2851 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2852 } 2853 2854 // If the root node defines glue, add it to the glue nodes to update list. 2855 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2856 GlueResultNodesMatched.push_back(NodeToMatch); 2857 2858 // Update chain and glue uses. 2859 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2860 InputGlue, GlueResultNodesMatched, false); 2861 2862 assert(NodeToMatch->use_empty() && 2863 "Didn't replace all uses of the node?"); 2864 2865 // FIXME: We just return here, which interacts correctly with SelectRoot 2866 // above. We should fix this to not return an SDNode* anymore. 2867 return 0; 2868 } 2869 } 2870 2871 // If the code reached this point, then the match failed. See if there is 2872 // another child to try in the current 'Scope', otherwise pop it until we 2873 // find a case to check. 2874 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2875 ++NumDAGIselRetries; 2876 while (1) { 2877 if (MatchScopes.empty()) { 2878 CannotYetSelect(NodeToMatch); 2879 return 0; 2880 } 2881 2882 // Restore the interpreter state back to the point where the scope was 2883 // formed. 2884 MatchScope &LastScope = MatchScopes.back(); 2885 RecordedNodes.resize(LastScope.NumRecordedNodes); 2886 NodeStack.clear(); 2887 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2888 N = NodeStack.back(); 2889 2890 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2891 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2892 MatcherIndex = LastScope.FailIndex; 2893 2894 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 2895 2896 InputChain = LastScope.InputChain; 2897 InputGlue = LastScope.InputGlue; 2898 if (!LastScope.HasChainNodesMatched) 2899 ChainNodesMatched.clear(); 2900 if (!LastScope.HasGlueResultNodesMatched) 2901 GlueResultNodesMatched.clear(); 2902 2903 // Check to see what the offset is at the new MatcherIndex. If it is zero 2904 // we have reached the end of this scope, otherwise we have another child 2905 // in the current scope to try. 2906 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2907 if (NumToSkip & 128) 2908 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2909 2910 // If we have another child in this scope to match, update FailIndex and 2911 // try it. 2912 if (NumToSkip != 0) { 2913 LastScope.FailIndex = MatcherIndex+NumToSkip; 2914 break; 2915 } 2916 2917 // End of this scope, pop it and try the next child in the containing 2918 // scope. 2919 MatchScopes.pop_back(); 2920 } 2921 } 2922} 2923 2924 2925 2926void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2927 std::string msg; 2928 raw_string_ostream Msg(msg); 2929 Msg << "Cannot select: "; 2930 2931 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2932 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2933 N->getOpcode() != ISD::INTRINSIC_VOID) { 2934 N->printrFull(Msg, CurDAG); 2935 Msg << "\nIn function: " << MF->getName(); 2936 } else { 2937 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2938 unsigned iid = 2939 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 2940 if (iid < Intrinsic::num_intrinsics) 2941 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 2942 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 2943 Msg << "target intrinsic %" << TII->getName(iid); 2944 else 2945 Msg << "unknown intrinsic #" << iid; 2946 } 2947 report_fatal_error(Msg.str()); 2948} 2949 2950char SelectionDAGISel::ID = 0; 2951