TargetRegisterInfo.h revision 263508
155682Smarkm//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2233294Sstas// 3233294Sstas// The LLVM Compiler Infrastructure 4233294Sstas// 555682Smarkm// This file is distributed under the University of Illinois Open Source 6233294Sstas// License. See LICENSE.TXT for details. 755682Smarkm// 8233294Sstas//===----------------------------------------------------------------------===// 9233294Sstas// 10233294Sstas// This file describes an abstract interface used to get information about a 1155682Smarkm// target machines register file. This information is used for a variety of 12233294Sstas// purposed, especially register allocation. 13233294Sstas// 1455682Smarkm//===----------------------------------------------------------------------===// 15233294Sstas 16233294Sstas#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17233294Sstas#define LLVM_TARGET_TARGETREGISTERINFO_H 1855682Smarkm 19233294Sstas#include "llvm/ADT/ArrayRef.h" 20233294Sstas#include "llvm/CodeGen/MachineBasicBlock.h" 21233294Sstas#include "llvm/CodeGen/ValueTypes.h" 22233294Sstas#include "llvm/IR/CallingConv.h" 23233294Sstas#include "llvm/MC/MCRegisterInfo.h" 24233294Sstas#include <cassert> 25233294Sstas#include <functional> 26233294Sstas 27233294Sstasnamespace llvm { 28233294Sstas 29233294Sstasclass BitVector; 30233294Sstasclass MachineFunction; 31233294Sstasclass RegScavenger; 32233294Sstastemplate<class T> class SmallVectorImpl; 33233294Sstasclass VirtRegMap; 3455682Smarkmclass raw_ostream; 3555682Smarkm 36178825Sdfrclass TargetRegisterClass { 3755682Smarkmpublic: 3855682Smarkm typedef const MCPhysReg* iterator; 3955682Smarkm typedef const MCPhysReg* const_iterator; 40102644Snectar typedef const MVT::SimpleValueType* vt_iterator; 41102644Snectar typedef const TargetRegisterClass* const * sc_iterator; 42102644Snectar 4355682Smarkm // Instance variables filled by tablegen, do not use! 44120945Snectar const MCRegisterClass *MC; 4555682Smarkm const vt_iterator VTs; 46233294Sstas const uint32_t *SubClassMask; 4755682Smarkm const uint16_t *SuperRegIndices; 4855682Smarkm const sc_iterator SuperClasses; 4955682Smarkm ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 5055682Smarkm 5155682Smarkm /// getID() - Return the register class ID number. 5255682Smarkm /// 5355682Smarkm unsigned getID() const { return MC->getID(); } 5455682Smarkm 5555682Smarkm /// getName() - Return the register class name for debugging. 5655682Smarkm /// 5755682Smarkm const char *getName() const { return MC->getName(); } 5855682Smarkm 5955682Smarkm /// begin/end - Return all of the registers in this class. 6055682Smarkm /// 61178825Sdfr iterator begin() const { return MC->begin(); } 62178825Sdfr iterator end() const { return MC->end(); } 63178825Sdfr 64178825Sdfr /// getNumRegs - Return the number of registers in this class. 65178825Sdfr /// 66178825Sdfr unsigned getNumRegs() const { return MC->getNumRegs(); } 67178825Sdfr 68178825Sdfr /// getRegister - Return the specified register in the class. 69178825Sdfr /// 70178825Sdfr unsigned getRegister(unsigned i) const { 7155682Smarkm return MC->getRegister(i); 7255682Smarkm } 7355682Smarkm 74178825Sdfr /// contains - Return true if the specified register is included in this 75178825Sdfr /// register class. This does not include virtual registers. 7655682Smarkm bool contains(unsigned Reg) const { 7755682Smarkm return MC->contains(Reg); 7855682Smarkm } 7955682Smarkm 80233294Sstas /// contains - Return true if both registers are in this class. 81233294Sstas bool contains(unsigned Reg1, unsigned Reg2) const { 82178825Sdfr return MC->contains(Reg1, Reg2); 83178825Sdfr } 8455682Smarkm 8555682Smarkm /// getSize - Return the size of the register in bytes, which is also the size 86178825Sdfr /// of a stack slot allocated to hold a spilled copy of this register. 87178825Sdfr unsigned getSize() const { return MC->getSize(); } 88233294Sstas 89233294Sstas /// getAlignment - Return the minimum required alignment for a register of 90233294Sstas /// this class. 91233294Sstas unsigned getAlignment() const { return MC->getAlignment(); } 92233294Sstas 93178825Sdfr /// getCopyCost - Return the cost of copying a value between two registers in 94178825Sdfr /// this class. A negative number means the register class is very expensive 95178825Sdfr /// to copy e.g. status flag register classes. 96178825Sdfr int getCopyCost() const { return MC->getCopyCost(); } 9755682Smarkm 9855682Smarkm /// isAllocatable - Return true if this register class may be used to create 9955682Smarkm /// virtual registers. 100178825Sdfr bool isAllocatable() const { return MC->isAllocatable(); } 101178825Sdfr 102178825Sdfr /// hasType - return true if this TargetRegisterClass has the ValueType vt. 103178825Sdfr /// 104178825Sdfr bool hasType(EVT vt) const { 105178825Sdfr for(int i = 0; VTs[i] != MVT::Other; ++i) 106178825Sdfr if (EVT(VTs[i]) == vt) 107178825Sdfr return true; 108178825Sdfr return false; 109178825Sdfr } 110178825Sdfr 111178825Sdfr /// vt_begin / vt_end - Loop over all of the value types that can be 112178825Sdfr /// represented by values in this register class. 113178825Sdfr vt_iterator vt_begin() const { 114178825Sdfr return VTs; 115178825Sdfr } 116178825Sdfr 117178825Sdfr vt_iterator vt_end() const { 118178825Sdfr vt_iterator I = VTs; 119178825Sdfr while (*I != MVT::Other) ++I; 120178825Sdfr return I; 121178825Sdfr } 122178825Sdfr 123178825Sdfr /// hasSubClass - return true if the specified TargetRegisterClass 124178825Sdfr /// is a proper sub-class of this TargetRegisterClass. 125178825Sdfr bool hasSubClass(const TargetRegisterClass *RC) const { 126178825Sdfr return RC != this && hasSubClassEq(RC); 127178825Sdfr } 128178825Sdfr 129178825Sdfr /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 130178825Sdfr /// class. 131178825Sdfr bool hasSubClassEq(const TargetRegisterClass *RC) const { 132178825Sdfr unsigned ID = RC->getID(); 133178825Sdfr return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 134178825Sdfr } 135178825Sdfr 136178825Sdfr /// hasSuperClass - return true if the specified TargetRegisterClass is a 137178825Sdfr /// proper super-class of this TargetRegisterClass. 138178825Sdfr bool hasSuperClass(const TargetRegisterClass *RC) const { 139178825Sdfr return RC->hasSubClass(this); 140178825Sdfr } 141178825Sdfr 142178825Sdfr /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 143178825Sdfr /// class. 144178825Sdfr bool hasSuperClassEq(const TargetRegisterClass *RC) const { 145178825Sdfr return RC->hasSubClassEq(this); 146178825Sdfr } 147178825Sdfr 148178825Sdfr /// getSubClassMask - Returns a bit vector of subclasses, including this one. 149178825Sdfr /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 150178825Sdfr /// use it. 151178825Sdfr const uint32_t *getSubClassMask() const { 152178825Sdfr return SubClassMask; 153178825Sdfr } 154178825Sdfr 155178825Sdfr /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices 156178825Sdfr /// that project some super-register class into this register class. The list 157178825Sdfr /// has an entry for each Idx such that: 158178825Sdfr /// 159178825Sdfr /// There exists SuperRC where: 160178825Sdfr /// For all Reg in SuperRC: 161178825Sdfr /// this->contains(Reg:Idx) 162178825Sdfr /// 163178825Sdfr const uint16_t *getSuperRegIndices() const { 164178825Sdfr return SuperRegIndices; 165178825Sdfr } 166178825Sdfr 167178825Sdfr /// getSuperClasses - Returns a NULL terminated list of super-classes. The 168178825Sdfr /// classes are ordered by ID which is also a topological ordering from large 169178825Sdfr /// to small classes. The list does NOT include the current class. 170178825Sdfr sc_iterator getSuperClasses() const { 171178825Sdfr return SuperClasses; 172178825Sdfr } 173178825Sdfr 174178825Sdfr /// isASubClass - return true if this TargetRegisterClass is a subset 175178825Sdfr /// class of at least one other TargetRegisterClass. 176178825Sdfr bool isASubClass() const { 177178825Sdfr return SuperClasses[0] != 0; 178178825Sdfr } 179178825Sdfr 180178825Sdfr /// getRawAllocationOrder - Returns the preferred order for allocating 181178825Sdfr /// registers from this register class in MF. The raw order comes directly 182178825Sdfr /// from the .td file and may include reserved registers that are not 183178825Sdfr /// allocatable. Register allocators should also make sure to allocate 184178825Sdfr /// callee-saved registers only after all the volatiles are used. The 185178825Sdfr /// RegisterClassInfo class provides filtered allocation orders with 186178825Sdfr /// callee-saved registers moved to the end. 187178825Sdfr /// 188178825Sdfr /// The MachineFunction argument can be used to tune the allocatable 189178825Sdfr /// registers based on the characteristics of the function, subtarget, or 190178825Sdfr /// other criteria. 191178825Sdfr /// 192178825Sdfr /// By default, this method returns all registers in the class. 193178825Sdfr /// 194178825Sdfr ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 195178825Sdfr return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 196178825Sdfr } 197233294Sstas}; 198178825Sdfr 199178825Sdfr/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 200178825Sdfr/// registers. These are used by codegen, not by MC. 201178825Sdfrstruct TargetRegisterInfoDesc { 202178825Sdfr unsigned CostPerUse; // Extra cost of instructions using register. 203178825Sdfr bool inAllocatableClass; // Register belongs to an allocatable regclass. 204233294Sstas}; 205233294Sstas 206178825Sdfr/// Each TargetRegisterClass has a per register weight, and weight 207178825Sdfr/// limit which must be less than the limits of its pressure sets. 208178825Sdfrstruct RegClassWeight { 209178825Sdfr unsigned RegWeight; 210178825Sdfr unsigned WeightLimit; 211178825Sdfr}; 212178825Sdfr 213178825Sdfr/// TargetRegisterInfo base class - We assume that the target defines a static 214178825Sdfr/// array of TargetRegisterDesc objects that represent all of the machine 215233294Sstas/// registers that the target has. As such, we simply have to track a pointer 216233294Sstas/// to this array so that we can turn register number into a register 217233294Sstas/// descriptor. 218178825Sdfr/// 219178825Sdfrclass TargetRegisterInfo : public MCRegisterInfo { 220178825Sdfrpublic: 221178825Sdfr typedef const TargetRegisterClass * const * regclass_iterator; 222178825Sdfrprivate: 22355682Smarkm const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 22455682Smarkm const char *const *SubRegIndexNames; // Names of subreg indexes. 225178825Sdfr // Pointer to array of lane masks, one per sub-reg index. 226178825Sdfr const unsigned *SubRegIndexLaneMasks; 22755682Smarkm 22855682Smarkm regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 22955682Smarkm unsigned CoveringLanes; 23055682Smarkm 23155682Smarkmprotected: 23255682Smarkm TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 23355682Smarkm regclass_iterator RegClassBegin, 23455682Smarkm regclass_iterator RegClassEnd, 23555682Smarkm const char *const *SRINames, 23655682Smarkm const unsigned *SRILaneMasks, 237178825Sdfr unsigned CoveringLanes); 23855682Smarkm virtual ~TargetRegisterInfo(); 23955682Smarkmpublic: 240178825Sdfr 24155682Smarkm // Register numbers can represent physical registers, virtual registers, and 24255682Smarkm // sometimes stack slots. The unsigned values are divided into these ranges: 243178825Sdfr // 24455682Smarkm // 0 Not a register, can be used as a sentinel. 24555682Smarkm // [1;2^30) Physical registers assigned by TableGen. 246233294Sstas // [2^30;2^31) Stack slots. (Rarely used.) 247233294Sstas // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 248178825Sdfr // 249178825Sdfr // Further sentinels can be allocated from the small negative integers. 25055682Smarkm // DenseMapInfo<unsigned> uses -1u and -2u. 251178825Sdfr 252178825Sdfr /// isStackSlot - Sometimes it is useful the be able to store a non-negative 253178825Sdfr /// frame index in a variable that normally holds a register. isStackSlot() 254178825Sdfr /// returns true if Reg is in the range used for stack slots. 255178825Sdfr /// 256233294Sstas /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 257233294Sstas /// slots, so if a variable may contains a stack slot, always check 258178825Sdfr /// isStackSlot() first. 259178825Sdfr /// 26055682Smarkm static bool isStackSlot(unsigned Reg) { 26155682Smarkm return int(Reg) >= (1 << 30); 26255682Smarkm } 263178825Sdfr 264178825Sdfr /// stackSlot2Index - Compute the frame index from a register value 265178825Sdfr /// representing a stack slot. 266178825Sdfr static int stackSlot2Index(unsigned Reg) { 267178825Sdfr assert(isStackSlot(Reg) && "Not a stack slot"); 268178825Sdfr return int(Reg - (1u << 30)); 269178825Sdfr } 270178825Sdfr 271178825Sdfr /// index2StackSlot - Convert a non-negative frame index to a stack slot 272178825Sdfr /// register value. 273178825Sdfr static unsigned index2StackSlot(int FI) { 274178825Sdfr assert(FI >= 0 && "Cannot hold a negative frame index."); 275178825Sdfr return FI + (1u << 30); 276178825Sdfr } 277178825Sdfr 278178825Sdfr /// isPhysicalRegister - Return true if the specified register number is in 279178825Sdfr /// the physical register namespace. 280178825Sdfr static bool isPhysicalRegister(unsigned Reg) { 281178825Sdfr assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 282178825Sdfr return int(Reg) > 0; 283178825Sdfr } 284178825Sdfr 285178825Sdfr /// isVirtualRegister - Return true if the specified register number is in 286178825Sdfr /// the virtual register namespace. 287178825Sdfr static bool isVirtualRegister(unsigned Reg) { 288233294Sstas assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 289233294Sstas return int(Reg) < 0; 290178825Sdfr } 291178825Sdfr 292178825Sdfr /// virtReg2Index - Convert a virtual register number to a 0-based index. 293233294Sstas /// The first virtual register in a function will get the index 0. 294233294Sstas static unsigned virtReg2Index(unsigned Reg) { 295178825Sdfr assert(isVirtualRegister(Reg) && "Not a virtual register"); 296178825Sdfr return Reg & ~(1u << 31); 297178825Sdfr } 298178825Sdfr 299178825Sdfr /// index2VirtReg - Convert a 0-based index to a virtual register number. 300178825Sdfr /// This is the inverse operation of VirtReg2IndexFunctor below. 301178825Sdfr static unsigned index2VirtReg(unsigned Index) { 302178825Sdfr return Index | (1u << 31); 303233294Sstas } 304233294Sstas 305178825Sdfr /// getMinimalPhysRegClass - Returns the Register Class of a physical 306178825Sdfr /// register of the given type, picking the most sub register class of 307178825Sdfr /// the right type that contains this physreg. 308178825Sdfr const TargetRegisterClass * 309178825Sdfr getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 310178825Sdfr 311178825Sdfr /// getAllocatableClass - Return the maximal subclass of the given register 312178825Sdfr /// class that is alloctable, or NULL. 313178825Sdfr const TargetRegisterClass * 314178825Sdfr getAllocatableClass(const TargetRegisterClass *RC) const; 315178825Sdfr 316178825Sdfr /// getAllocatableSet - Returns a bitset indexed by register number 317178825Sdfr /// indicating if a register is allocatable or not. If a register class is 318178825Sdfr /// specified, returns the subset for the class. 319178825Sdfr BitVector getAllocatableSet(const MachineFunction &MF, 320178825Sdfr const TargetRegisterClass *RC = NULL) const; 321178825Sdfr 322178825Sdfr /// getCostPerUse - Return the additional cost of using this register instead 323178825Sdfr /// of other registers in its class. 324178825Sdfr unsigned getCostPerUse(unsigned RegNo) const { 325178825Sdfr return InfoDesc[RegNo].CostPerUse; 326178825Sdfr } 327178825Sdfr 328178825Sdfr /// isInAllocatableClass - Return true if the register is in the allocation 329178825Sdfr /// of any register class. 330178825Sdfr bool isInAllocatableClass(unsigned RegNo) const { 331178825Sdfr return InfoDesc[RegNo].inAllocatableClass; 332178825Sdfr } 333178825Sdfr 334178825Sdfr /// getSubRegIndexName - Return the human-readable symbolic target-specific 335178825Sdfr /// name for the specified SubRegIndex. 336233294Sstas const char *getSubRegIndexName(unsigned SubIdx) const { 337233294Sstas assert(SubIdx && SubIdx < getNumSubRegIndices() && 338178825Sdfr "This is not a subregister index"); 339178825Sdfr return SubRegIndexNames[SubIdx-1]; 340178825Sdfr } 341233294Sstas 342233294Sstas /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a 343178825Sdfr /// register that are covered by SubIdx. 344178825Sdfr /// 345178825Sdfr /// Lane masks for sub-register indices are similar to register units for 346178825Sdfr /// physical registers. The individual bits in a lane mask can't be assigned 347178825Sdfr /// any specific meaning. They can be used to check if two sub-register 348178825Sdfr /// indices overlap. 349178825Sdfr /// 350178825Sdfr /// If the target has a register such that: 351233294Sstas /// 352233294Sstas /// getSubReg(Reg, A) overlaps getSubReg(Reg, B) 353178825Sdfr /// 354178825Sdfr /// then: 355178825Sdfr /// 356178825Sdfr /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0 357178825Sdfr /// 358178825Sdfr /// The converse is not necessarily true. If two lane masks have a common 35955682Smarkm /// bit, the corresponding sub-registers may not overlap, but it can be 36055682Smarkm /// assumed that they usually will. 361178825Sdfr unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 362178825Sdfr // SubIdx == 0 is allowed, it has the lane mask ~0u. 36355682Smarkm assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 36455682Smarkm return SubRegIndexLaneMasks[SubIdx]; 36555682Smarkm } 36655682Smarkm 36755682Smarkm /// The lane masks returned by getSubRegIndexLaneMask() above can only be 36855682Smarkm /// used to determine if sub-registers overlap - they can't be used to 36955682Smarkm /// determine if a set of sub-registers completely cover another 370178825Sdfr /// sub-register. 37155682Smarkm /// 37255682Smarkm /// The X86 general purpose registers have two lanes corresponding to the 373178825Sdfr /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have 37455682Smarkm /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the 375178825Sdfr /// sub_32bit sub-register. 37655682Smarkm /// 37755682Smarkm /// On the other hand, the ARM NEON lanes fully cover their registers: The 378233294Sstas /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. 379233294Sstas /// This is related to the CoveredBySubRegs property on register definitions. 380178825Sdfr /// 381178825Sdfr /// This function returns a bit mask of lanes that completely cover their 38255682Smarkm /// sub-registers. More precisely, given: 383178825Sdfr /// 384178825Sdfr /// Covering = getCoveringLanes(); 385178825Sdfr /// MaskA = getSubRegIndexLaneMask(SubA); 386178825Sdfr /// MaskB = getSubRegIndexLaneMask(SubB); 387178825Sdfr /// 388233294Sstas /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by 389233294Sstas /// SubB. 390178825Sdfr unsigned getCoveringLanes() const { return CoveringLanes; } 391178825Sdfr 39255682Smarkm /// regsOverlap - Returns true if the two registers are equal or alias each 39355682Smarkm /// other. The registers may be virtual register. 39455682Smarkm bool regsOverlap(unsigned regA, unsigned regB) const { 39555682Smarkm if (regA == regB) return true; 39655682Smarkm if (isVirtualRegister(regA) || isVirtualRegister(regB)) 39755682Smarkm return false; 39855682Smarkm 39955682Smarkm // Regunits are numerically ordered. Find a common unit. 40055682Smarkm MCRegUnitIterator RUA(regA, this); 40155682Smarkm MCRegUnitIterator RUB(regB, this); 40255682Smarkm do { 40355682Smarkm if (*RUA == *RUB) return true; 40455682Smarkm if (*RUA < *RUB) ++RUA; 40555682Smarkm else ++RUB; 40655682Smarkm } while (RUA.isValid() && RUB.isValid()); 407178825Sdfr return false; 408178825Sdfr } 40955682Smarkm 41055682Smarkm /// hasRegUnit - Returns true if Reg contains RegUnit. 411178825Sdfr bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 41255682Smarkm for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 41355682Smarkm if (*Units == RegUnit) 41455682Smarkm return true; 41555682Smarkm return false; 416233294Sstas } 417233294Sstas 418178825Sdfr /// getCalleeSavedRegs - Return a null-terminated list of all of the 419178825Sdfr /// callee saved registers on this target. The register should be in the 42055682Smarkm /// order of desired callee-save stack frame offset. The first register is 42155682Smarkm /// closest to the incoming stack pointer if stack grows down, and vice versa. 422178825Sdfr /// 423178825Sdfr virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0) 424178825Sdfr const = 0; 425178825Sdfr 426178825Sdfr /// getCallPreservedMask - Return a mask of call-preserved registers for the 427233294Sstas /// given calling convention on the current sub-target. The mask should 428233294Sstas /// include all call-preserved aliases. This is used by the register 429178825Sdfr /// allocator to determine which registers can be live across a call. 430178825Sdfr /// 431178825Sdfr /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 43255682Smarkm /// A set bit indicates that all bits of the corresponding register are 43355682Smarkm /// preserved across the function call. The bit mask is expected to be 434178825Sdfr /// sub-register complete, i.e. if A is preserved, so are all its 435178825Sdfr /// sub-registers. 436178825Sdfr /// 437178825Sdfr /// Bits are numbered from the LSB, so the bit for physical register Reg can 438178825Sdfr /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 439178825Sdfr /// 440178825Sdfr /// A NULL pointer means that no register mask will be used, and call 441178825Sdfr /// instructions should use implicit-def operands to indicate call clobbered 442178825Sdfr /// registers. 443178825Sdfr /// 444178825Sdfr virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 445178825Sdfr // The default mask clobbers everything. All targets should override. 446178825Sdfr return 0; 447178825Sdfr } 448178825Sdfr 449178825Sdfr /// getReservedRegs - Returns a bitset indexed by physical register number 450178825Sdfr /// indicating if a register is a special register that has particular uses 451178825Sdfr /// and should be considered unavailable at all times, e.g. SP, RA. This is 452178825Sdfr /// used by register scavenger to determine what registers are free. 453178825Sdfr virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 454178825Sdfr 455178825Sdfr /// getMatchingSuperReg - Return a super-register of the specified register 456178825Sdfr /// Reg so its sub-register of index SubIdx is Reg. 457178825Sdfr unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 458178825Sdfr const TargetRegisterClass *RC) const { 459178825Sdfr return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 460178825Sdfr } 461178825Sdfr 462178825Sdfr /// getMatchingSuperRegClass - Return a subclass of the specified register 463178825Sdfr /// class A so that each register in it has a sub-register of the 464178825Sdfr /// specified sub-register index which is in the specified register class B. 465233294Sstas /// 466233294Sstas /// TableGen will synthesize missing A sub-classes. 467178825Sdfr virtual const TargetRegisterClass * 468178825Sdfr getMatchingSuperRegClass(const TargetRegisterClass *A, 469178825Sdfr const TargetRegisterClass *B, unsigned Idx) const; 470178825Sdfr 471178825Sdfr /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 472178825Sdfr /// supports the sub-register index Idx. 473178825Sdfr /// If no such sub-class exists, return NULL. 474178825Sdfr /// If all registers in RC already have an Idx sub-register, return RC. 475178825Sdfr /// 476233294Sstas /// TableGen generates a version of this function that is good enough in most 477233294Sstas /// cases. Targets can override if they have constraints that TableGen 478178825Sdfr /// doesn't understand. For example, the x86 sub_8bit sub-register index is 479178825Sdfr /// supported by the full GR32 register class in 64-bit mode, but only by the 480178825Sdfr /// GR32_ABCD regiister class in 32-bit mode. 481178825Sdfr /// 482178825Sdfr /// TableGen will synthesize missing RC sub-classes. 483178825Sdfr virtual const TargetRegisterClass * 484178825Sdfr getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 485178825Sdfr assert(Idx == 0 && "Target has no sub-registers"); 486178825Sdfr return RC; 487178825Sdfr } 488178825Sdfr 489178825Sdfr /// composeSubRegIndices - Return the subregister index you get from composing 490178825Sdfr /// two subregister indices. 491178825Sdfr /// 492178825Sdfr /// The special null sub-register index composes as the identity. 493178825Sdfr /// 494178825Sdfr /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 495178825Sdfr /// returns c. Note that composeSubRegIndices does not tell you about illegal 496178825Sdfr /// compositions. If R does not have a subreg a, or R:a does not have a subreg 497178825Sdfr /// b, composeSubRegIndices doesn't tell you. 498178825Sdfr /// 499178825Sdfr /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 500178825Sdfr /// ssub_0:S0 - ssub_3:S3 subregs. 501178825Sdfr /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 502178825Sdfr /// 503233294Sstas unsigned composeSubRegIndices(unsigned a, unsigned b) const { 504233294Sstas if (!a) return b; 505178825Sdfr if (!b) return a; 506178825Sdfr return composeSubRegIndicesImpl(a, b); 507178825Sdfr } 508178825Sdfr 509178825Sdfrprotected: 510178825Sdfr /// Overridden by TableGen in targets that have sub-registers. 511178825Sdfr virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 512178825Sdfr llvm_unreachable("Target has no sub-registers"); 513178825Sdfr } 514233294Sstas 515233294Sstaspublic: 516178825Sdfr /// getCommonSuperRegClass - Find a common super-register class if it exists. 517178825Sdfr /// 518178825Sdfr /// Find a register class, SuperRC and two sub-register indices, PreA and 519178825Sdfr /// PreB, such that: 520178825Sdfr /// 521178825Sdfr /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 522178825Sdfr /// 523178825Sdfr /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 524178825Sdfr /// 525178825Sdfr /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 526178825Sdfr /// 527178825Sdfr /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 528178825Sdfr /// requirements, and there is no register class with a smaller spill size 529178825Sdfr /// that satisfies the requirements. 530178825Sdfr /// 531178825Sdfr /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 532178825Sdfr /// 533178825Sdfr /// Either of the PreA and PreB sub-register indices may be returned as 0. In 534178825Sdfr /// that case, the returned register class will be a sub-class of the 535178825Sdfr /// corresponding argument register class. 536178825Sdfr /// 537178825Sdfr /// The function returns NULL if no register class can be found. 538178825Sdfr /// 539178825Sdfr const TargetRegisterClass* 540178825Sdfr getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 541178825Sdfr const TargetRegisterClass *RCB, unsigned SubB, 542178825Sdfr unsigned &PreA, unsigned &PreB) const; 543178825Sdfr 544178825Sdfr //===--------------------------------------------------------------------===// 545178825Sdfr // Register Class Information 546178825Sdfr // 547178825Sdfr 548178825Sdfr /// Register class iterators 549178825Sdfr /// 550178825Sdfr regclass_iterator regclass_begin() const { return RegClassBegin; } 551178825Sdfr regclass_iterator regclass_end() const { return RegClassEnd; } 552178825Sdfr 553178825Sdfr unsigned getNumRegClasses() const { 554178825Sdfr return (unsigned)(regclass_end()-regclass_begin()); 555178825Sdfr } 556233294Sstas 557233294Sstas /// getRegClass - Returns the register class associated with the enumeration 558178825Sdfr /// value. See class MCOperandInfo. 559178825Sdfr const TargetRegisterClass *getRegClass(unsigned i) const { 560178825Sdfr assert(i < getNumRegClasses() && "Register Class ID out of range"); 561178825Sdfr return RegClassBegin[i]; 562178825Sdfr } 563178825Sdfr 564178825Sdfr /// getCommonSubClass - find the largest common subclass of A and B. Return 565178825Sdfr /// NULL if there is no common subclass. 566178825Sdfr const TargetRegisterClass * 567233294Sstas getCommonSubClass(const TargetRegisterClass *A, 568233294Sstas const TargetRegisterClass *B) const; 569233294Sstas 570178825Sdfr /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 571178825Sdfr /// values. If a target supports multiple different pointer register classes, 572178825Sdfr /// kind specifies which one is indicated. 573178825Sdfr virtual const TargetRegisterClass * 574178825Sdfr getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 575178825Sdfr llvm_unreachable("Target didn't implement getPointerRegClass!"); 576178825Sdfr } 577178825Sdfr 578178825Sdfr /// getCrossCopyRegClass - Returns a legal register class to copy a register 579178825Sdfr /// in the specified class to or from. If it is possible to copy the register 580178825Sdfr /// directly without using a cross register class copy, return the specified 581178825Sdfr /// RC. Returns NULL if it is not possible to copy between a two registers of 582178825Sdfr /// the specified class. 583178825Sdfr virtual const TargetRegisterClass * 584178825Sdfr getCrossCopyRegClass(const TargetRegisterClass *RC) const { 585178825Sdfr return RC; 586178825Sdfr } 587178825Sdfr 588178825Sdfr /// getLargestLegalSuperClass - Returns the largest super class of RC that is 589178825Sdfr /// legal to use in the current sub-target and has the same spill size. 590178825Sdfr /// The returned register class can be used to create virtual registers which 591178825Sdfr /// means that all its registers can be copied and spilled. 592178825Sdfr virtual const TargetRegisterClass* 593178825Sdfr getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 594178825Sdfr /// The default implementation is very conservative and doesn't allow the 595178825Sdfr /// register allocator to inflate register classes. 596178825Sdfr return RC; 597178825Sdfr } 598178825Sdfr 599178825Sdfr /// getRegPressureLimit - Return the register pressure "high water mark" for 600178825Sdfr /// the specific register class. The scheduler is in high register pressure 601178825Sdfr /// mode (for the specific register class) if it goes over the limit. 602178825Sdfr /// 603178825Sdfr /// Note: this is the old register pressure model that relies on a manually 604178825Sdfr /// specified representative register class per value type. 605178825Sdfr virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 606178825Sdfr MachineFunction &MF) const { 607233294Sstas return 0; 608233294Sstas } 609178825Sdfr 610178825Sdfr /// Get the weight in units of pressure for this register class. 611178825Sdfr virtual const RegClassWeight &getRegClassWeight( 612178825Sdfr const TargetRegisterClass *RC) const = 0; 613178825Sdfr 614178825Sdfr /// Get the weight in units of pressure for this register unit. 615178825Sdfr virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0; 616178825Sdfr 617178825Sdfr /// Get the number of dimensions of register pressure. 618233294Sstas virtual unsigned getNumRegPressureSets() const = 0; 619233294Sstas 620233294Sstas /// Get the name of this register unit pressure set. 621178825Sdfr virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 622178825Sdfr 623178825Sdfr /// Get the register unit pressure limit for this dimension. 624178825Sdfr /// This limit must be adjusted dynamically for reserved registers. 625178825Sdfr virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 626178825Sdfr 627178825Sdfr /// Get the dimensions of register pressure impacted by this register class. 628178825Sdfr /// Returns a -1 terminated array of pressure set IDs. 629178825Sdfr virtual const int *getRegClassPressureSets( 630178825Sdfr const TargetRegisterClass *RC) const = 0; 631178825Sdfr 632178825Sdfr /// Get the dimensions of register pressure impacted by this register unit. 633178825Sdfr /// Returns a -1 terminated array of pressure set IDs. 634178825Sdfr virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0; 635178825Sdfr 636178825Sdfr /// Get a list of 'hint' registers that the register allocator should try 637178825Sdfr /// first when allocating a physical register for the virtual register 638178825Sdfr /// VirtReg. These registers are effectively moved to the front of the 639178825Sdfr /// allocation order. 640178825Sdfr /// 641178825Sdfr /// The Order argument is the allocation order for VirtReg's register class 642178825Sdfr /// as returned from RegisterClassInfo::getOrder(). The hint registers must 643178825Sdfr /// come from Order, and they must not be reserved. 644178825Sdfr /// 645178825Sdfr /// The default implementation of this function can resolve 646178825Sdfr /// target-independent hints provided to MRI::setRegAllocationHint with 647178825Sdfr /// HintType == 0. Targets that override this function should defer to the 648178825Sdfr /// default implementation if they have no reason to change the allocation 649178825Sdfr /// order for VirtReg. There may be target-independent hints. 650178825Sdfr virtual void getRegAllocationHints(unsigned VirtReg, 651178825Sdfr ArrayRef<MCPhysReg> Order, 652178825Sdfr SmallVectorImpl<MCPhysReg> &Hints, 653178825Sdfr const MachineFunction &MF, 654178825Sdfr const VirtRegMap *VRM = 0) const; 655178825Sdfr 656178825Sdfr /// avoidWriteAfterWrite - Return true if the register allocator should avoid 657178825Sdfr /// writing a register from RC in two consecutive instructions. 658178825Sdfr /// This can avoid pipeline stalls on certain architectures. 659178825Sdfr /// It does cause increased register pressure, though. 660178825Sdfr virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 661178825Sdfr return false; 662178825Sdfr } 663178825Sdfr 664178825Sdfr /// UpdateRegAllocHint - A callback to allow target a chance to update 665178825Sdfr /// register allocation hints when a register is "changed" (e.g. coalesced) 666178825Sdfr /// to another register. e.g. On ARM, some virtual registers should target 667178825Sdfr /// register pairs, if one of pair is coalesced to another register, the 668178825Sdfr /// allocation hint of the other half of the pair should be changed to point 669178825Sdfr /// to the new register. 670178825Sdfr virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 671178825Sdfr MachineFunction &MF) const { 672178825Sdfr // Do nothing. 673178825Sdfr } 674178825Sdfr 675178825Sdfr /// requiresRegisterScavenging - returns true if the target requires (and can 676178825Sdfr /// make use of) the register scavenger. 677178825Sdfr virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 678178825Sdfr return false; 679178825Sdfr } 680178825Sdfr 681178825Sdfr /// useFPForScavengingIndex - returns true if the target wants to use 682178825Sdfr /// frame pointer based accesses to spill to the scavenger emergency spill 683178825Sdfr /// slot. 684178825Sdfr virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 685178825Sdfr return true; 686178825Sdfr } 687178825Sdfr 688178825Sdfr /// requiresFrameIndexScavenging - returns true if the target requires post 689178825Sdfr /// PEI scavenging of registers for materializing frame index constants. 690178825Sdfr virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 691178825Sdfr return false; 692178825Sdfr } 693178825Sdfr 694178825Sdfr /// requiresVirtualBaseRegisters - Returns true if the target wants the 695178825Sdfr /// LocalStackAllocation pass to be run and virtual base registers 696178825Sdfr /// used for more efficient stack access. 697178825Sdfr virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 698178825Sdfr return false; 699178825Sdfr } 700178825Sdfr 701178825Sdfr /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 702178825Sdfr /// the stack frame of the given function for the specified register. e.g. On 703178825Sdfr /// x86, if the frame register is required, the first fixed stack object is 704178825Sdfr /// reserved as its spill slot. This tells PEI not to create a new stack frame 705178825Sdfr /// object for the given register. It should be called only after 706178825Sdfr /// processFunctionBeforeCalleeSavedScan(). 707178825Sdfr virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 708178825Sdfr int &FrameIdx) const { 709178825Sdfr return false; 710178825Sdfr } 711178825Sdfr 712178825Sdfr /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 713178825Sdfr /// after register allocation. 714178825Sdfr virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 715178825Sdfr return false; 716178825Sdfr } 717178825Sdfr 718178825Sdfr /// needsStackRealignment - true if storage within the function requires the 719178825Sdfr /// stack pointer to be aligned more than the normal calling convention calls 720178825Sdfr /// for. 721178825Sdfr virtual bool needsStackRealignment(const MachineFunction &MF) const { 722178825Sdfr return false; 723178825Sdfr } 724178825Sdfr 725178825Sdfr /// getFrameIndexInstrOffset - Get the offset from the referenced frame 726178825Sdfr /// index in the instruction, if there is one. 727178825Sdfr virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 728178825Sdfr int Idx) const { 729178825Sdfr return 0; 730178825Sdfr } 731178825Sdfr 732178825Sdfr /// needsFrameBaseReg - Returns true if the instruction's frame index 733178825Sdfr /// reference would be better served by a base register other than FP 734178825Sdfr /// or SP. Used by LocalStackFrameAllocation to determine which frame index 735178825Sdfr /// references it should create new base registers for. 736178825Sdfr virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 737178825Sdfr return false; 738178825Sdfr } 739178825Sdfr 740178825Sdfr /// materializeFrameBaseRegister - Insert defining instruction(s) for 741178825Sdfr /// BaseReg to be a pointer to FrameIdx before insertion point I. 742178825Sdfr virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 743178825Sdfr unsigned BaseReg, int FrameIdx, 744178825Sdfr int64_t Offset) const { 745178825Sdfr llvm_unreachable("materializeFrameBaseRegister does not exist on this " 746178825Sdfr "target"); 747178825Sdfr } 748178825Sdfr 749178825Sdfr /// resolveFrameIndex - Resolve a frame index operand of an instruction 750178825Sdfr /// to reference the indicated base register plus offset instead. 751178825Sdfr virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 752178825Sdfr unsigned BaseReg, int64_t Offset) const { 753178825Sdfr llvm_unreachable("resolveFrameIndex does not exist on this target"); 754178825Sdfr } 755178825Sdfr 756178825Sdfr /// isFrameOffsetLegal - Determine whether a given offset immediate is 757178825Sdfr /// encodable to resolve a frame index. 758178825Sdfr virtual bool isFrameOffsetLegal(const MachineInstr *MI, 759178825Sdfr int64_t Offset) const { 760178825Sdfr llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 761178825Sdfr } 762233294Sstas 763178825Sdfr 764178825Sdfr /// saveScavengerRegister - Spill the register so it can be used by the 765178825Sdfr /// register scavenger. Return true if the register was spilled, false 766178825Sdfr /// otherwise. If this function does not spill the register, the scavenger 767178825Sdfr /// will instead spill it to the emergency spill slot. 768178825Sdfr /// 769178825Sdfr virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 770178825Sdfr MachineBasicBlock::iterator I, 771178825Sdfr MachineBasicBlock::iterator &UseMI, 772178825Sdfr const TargetRegisterClass *RC, 773178825Sdfr unsigned Reg) const { 774178825Sdfr return false; 775178825Sdfr } 776178825Sdfr 777178825Sdfr /// eliminateFrameIndex - This method must be overriden to eliminate abstract 778178825Sdfr /// frame indices from instructions which may use them. The instruction 779178825Sdfr /// referenced by the iterator contains an MO_FrameIndex operand which must be 780178825Sdfr /// eliminated by this method. This method may modify or replace the 781178825Sdfr /// specified instruction, as long as it keeps the iterator pointing at the 782178825Sdfr /// finished product. SPAdj is the SP adjustment due to call frame setup 783178825Sdfr /// instruction. FIOperandNum is the FI operand number. 784178825Sdfr virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 785178825Sdfr int SPAdj, unsigned FIOperandNum, 786178825Sdfr RegScavenger *RS = NULL) const = 0; 787178825Sdfr 788178825Sdfr //===--------------------------------------------------------------------===// 789178825Sdfr /// Debug information queries. 790178825Sdfr 791178825Sdfr /// getFrameRegister - This method should return the register used as a base 792178825Sdfr /// for values allocated in the current stack frame. 793178825Sdfr virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 794178825Sdfr 795178825Sdfr /// getCompactUnwindRegNum - This function maps the register to the number for 796178825Sdfr /// compact unwind encoding. Return -1 if the register isn't valid. 797178825Sdfr virtual int getCompactUnwindRegNum(unsigned, bool) const { 798178825Sdfr return -1; 799178825Sdfr } 800178825Sdfr}; 801178825Sdfr 802178825Sdfr 803178825Sdfr//===----------------------------------------------------------------------===// 804178825Sdfr// SuperRegClassIterator 805178825Sdfr//===----------------------------------------------------------------------===// 806178825Sdfr// 807178825Sdfr// Iterate over the possible super-registers for a given register class. The 808178825Sdfr// iterator will visit a list of pairs (Idx, Mask) corresponding to the 809178825Sdfr// possible classes of super-registers. 810178825Sdfr// 811178825Sdfr// Each bit mask will have at least one set bit, and each set bit in Mask 812178825Sdfr// corresponds to a SuperRC such that: 813178825Sdfr// 814178825Sdfr// For all Reg in SuperRC: Reg:Idx is in RC. 815178825Sdfr// 816178825Sdfr// The iterator can include (O, RC->getSubClassMask()) as the first entry which 817178825Sdfr// also satisfies the above requirement, assuming Reg:0 == Reg. 818178825Sdfr// 819178825Sdfrclass SuperRegClassIterator { 820178825Sdfr const unsigned RCMaskWords; 821178825Sdfr unsigned SubReg; 822178825Sdfr const uint16_t *Idx; 823178825Sdfr const uint32_t *Mask; 824178825Sdfr 825178825Sdfrpublic: 826178825Sdfr /// Create a SuperRegClassIterator that visits all the super-register classes 827178825Sdfr /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 828178825Sdfr SuperRegClassIterator(const TargetRegisterClass *RC, 829178825Sdfr const TargetRegisterInfo *TRI, 830178825Sdfr bool IncludeSelf = false) 831178825Sdfr : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 832178825Sdfr SubReg(0), 833178825Sdfr Idx(RC->getSuperRegIndices()), 834178825Sdfr Mask(RC->getSubClassMask()) { 835178825Sdfr if (!IncludeSelf) 836178825Sdfr ++*this; 837233294Sstas } 838178825Sdfr 839178825Sdfr /// Returns true if this iterator is still pointing at a valid entry. 840178825Sdfr bool isValid() const { return Idx; } 841178825Sdfr 842178825Sdfr /// Returns the current sub-register index. 843178825Sdfr unsigned getSubReg() const { return SubReg; } 844178825Sdfr 845178825Sdfr /// Returns the bit mask if register classes that getSubReg() projects into 846178825Sdfr /// RC. 847178825Sdfr const uint32_t *getMask() const { return Mask; } 848178825Sdfr 849178825Sdfr /// Advance iterator to the next entry. 850178825Sdfr void operator++() { 851178825Sdfr assert(isValid() && "Cannot move iterator past end."); 852178825Sdfr Mask += RCMaskWords; 853178825Sdfr SubReg = *Idx++; 854178825Sdfr if (!SubReg) 855178825Sdfr Idx = 0; 856178825Sdfr } 857178825Sdfr}; 858178825Sdfr 859178825Sdfr// This is useful when building IndexedMaps keyed on virtual registers 860178825Sdfrstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 861178825Sdfr unsigned operator()(unsigned Reg) const { 862178825Sdfr return TargetRegisterInfo::virtReg2Index(Reg); 863178825Sdfr } 864178825Sdfr}; 865178825Sdfr 866178825Sdfr/// PrintReg - Helper class for printing registers on a raw_ostream. 867178825Sdfr/// Prints virtual and physical registers with or without a TRI instance. 868178825Sdfr/// 869178825Sdfr/// The format is: 870178825Sdfr/// %noreg - NoRegister 871178825Sdfr/// %vreg5 - a virtual register. 872178825Sdfr/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 873178825Sdfr/// %EAX - a physical register 874178825Sdfr/// %physreg17 - a physical register when no TRI instance given. 875178825Sdfr/// 876178825Sdfr/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 877178825Sdfr/// 878178825Sdfrclass PrintReg { 879178825Sdfr const TargetRegisterInfo *TRI; 880178825Sdfr unsigned Reg; 881178825Sdfr unsigned SubIdx; 882178825Sdfrpublic: 883178825Sdfr explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, 884178825Sdfr unsigned subidx = 0) 885178825Sdfr : TRI(tri), Reg(reg), SubIdx(subidx) {} 886178825Sdfr void print(raw_ostream&) const; 887178825Sdfr}; 888178825Sdfr 889178825Sdfrstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 890178825Sdfr PR.print(OS); 891178825Sdfr return OS; 892178825Sdfr} 893178825Sdfr 894178825Sdfr/// PrintRegUnit - Helper class for printing register units on a raw_ostream. 895178825Sdfr/// 896178825Sdfr/// Register units are named after their root registers: 897178825Sdfr/// 898178825Sdfr/// AL - Single root. 899178825Sdfr/// FP0~ST7 - Dual roots. 900178825Sdfr/// 901178825Sdfr/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; 902178825Sdfr/// 903178825Sdfrclass PrintRegUnit { 904178825Sdfrprotected: 905178825Sdfr const TargetRegisterInfo *TRI; 906178825Sdfr unsigned Unit; 907178825Sdfrpublic: 908178825Sdfr PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) 909178825Sdfr : TRI(tri), Unit(unit) {} 910178825Sdfr void print(raw_ostream&) const; 911178825Sdfr}; 912178825Sdfr 913178825Sdfrstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) { 914178825Sdfr PR.print(OS); 915178825Sdfr return OS; 916178825Sdfr} 917178825Sdfr 918178825Sdfr/// PrintVRegOrUnit - It is often convenient to track virtual registers and 919178825Sdfr/// physical register units in the same list. 920178825Sdfrclass PrintVRegOrUnit : protected PrintRegUnit { 921178825Sdfrpublic: 922178825Sdfr PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri) 923178825Sdfr : PrintRegUnit(VRegOrUnit, tri) {} 924178825Sdfr void print(raw_ostream&) const; 925178825Sdfr}; 926178825Sdfr 927178825Sdfrstatic inline raw_ostream &operator<<(raw_ostream &OS, 928178825Sdfr const PrintVRegOrUnit &PR) { 929178825Sdfr PR.print(OS); 930178825Sdfr return OS; 931178825Sdfr} 932178825Sdfr 933178825Sdfr} // End llvm namespace 934178825Sdfr 935178825Sdfr#endif 936178825Sdfr