159191Skris/* Target-dependent code for SPARC.
259191Skris
359191Skris   Copyright 2003, 2004 Free Software Foundation, Inc.
459191Skris
5325337Sjkim   This file is part of GDB.
668651Skris
759191Skris   This program is free software; you can redistribute it and/or modify
859191Skris   it under the terms of the GNU General Public License as published by
959191Skris   the Free Software Foundation; either version 2 of the License, or
1059191Skris   (at your option) any later version.
1159191Skris
1259191Skris   This program is distributed in the hope that it will be useful,
1359191Skris   but WITHOUT ANY WARRANTY; without even the implied warranty of
14238405Sjkim   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15238405Sjkim   GNU General Public License for more details.
16290207Sjkim
17290207Sjkim   You should have received a copy of the GNU General Public License
18331638Sjkim   along with this program; if not, write to the Free Software
19290207Sjkim   Foundation, Inc., 59 Temple Place - Suite 330,
20238405Sjkim   Boston, MA 02111-1307, USA.  */
21238405Sjkim
22238405Sjkim#include "defs.h"
23238405Sjkim#include "arch-utils.h"
24238405Sjkim#include "dis-asm.h"
25238405Sjkim#include "floatformat.h"
26238405Sjkim#include "frame.h"
27238405Sjkim#include "frame-base.h"
28238405Sjkim#include "frame-unwind.h"
29238405Sjkim#include "gdbcore.h"
30284283Sjkim#include "gdbtypes.h"
31306195Sjkim#include "inferior.h"
3259191Skris#include "symtab.h"
3359191Skris#include "objfiles.h"
3468651Skris#include "osabi.h"
35290207Sjkim#include "regcache.h"
3659191Skris#include "target.h"
3759191Skris#include "value.h"
3859191Skris
3959191Skris#include "gdb_assert.h"
4059191Skris#include "gdb_string.h"
4159191Skris
4259191Skris#include "sparc-tdep.h"
4359191Skris
4459191Skrisstruct regset;
4559191Skris
4659191Skris/* This file implements the The SPARC 32-bit ABI as defined by the
4759191Skris   section "Low-Level System Information" of the SPARC Compliance
4859191Skris   Definition (SCD) 2.4.1, which is the 32-bit System V psABI for
4959191Skris   SPARC.  The SCD lists changes with respect to the origional 32-bit
5059191Skris   psABI as defined in the "System V ABI, SPARC Processor
5159191Skris   Supplement".
5259191Skris
5359191Skris   Note that if we talk about SunOS, we mean SunOS 4.x, which was
5459191Skris   BSD-based, which is sometimes (retroactively?) referred to as
5559191Skris   Solaris 1.x.  If we talk about Solaris we mean Solaris 2.x and
5659191Skris   above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
5759191Skris   suffering from severe version number inflation).  Solaris 2.x is
5859191Skris   also known as SunOS 5.x, since that's what uname(1) says.  Solaris
5959191Skris   2.x is SVR4-based.  */
6059191Skris
61290207Sjkim/* Please use the sparc32_-prefix for 32-bit specific code, the
62290207Sjkim   sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
63290207Sjkim   code that can handle both.  The 64-bit specific code lives in
64290207Sjkim   sparc64-tdep.c; don't add any here.  */
65290207Sjkim
66290207Sjkim/* The SPARC Floating-Point Quad-Precision format is similar to
67290207Sjkim   big-endian IA-64 Quad-recision format.  */
68290207Sjkim#define floatformat_sparc_quad floatformat_ia64_quad_big
69290207Sjkim
70290207Sjkim/* The stack pointer is offset from the stack frame by a BIAS of 2047
71290207Sjkim   (0x7ff) for 64-bit code.  BIAS is likely to be defined on SPARC
72331638Sjkim   hosts, so undefine it first.  */
73290207Sjkim#undef BIAS
74290207Sjkim#define BIAS 2047
75290207Sjkim
76290207Sjkim/* Macros to extract fields from SPARC instructions.  */
77290207Sjkim#define X_OP(i) (((i) >> 30) & 0x3)
78290207Sjkim#define X_RD(i) (((i) >> 25) & 0x1f)
79290207Sjkim#define X_A(i) (((i) >> 29) & 1)
80290207Sjkim#define X_COND(i) (((i) >> 25) & 0xf)
81290207Sjkim#define X_OP2(i) (((i) >> 22) & 0x7)
82290207Sjkim#define X_IMM22(i) ((i) & 0x3fffff)
83290207Sjkim#define X_OP3(i) (((i) >> 19) & 0x3f)
84290207Sjkim#define X_I(i) (((i) >> 13) & 1)
8559191Skris/* Sign extension macros.  */
8659191Skris#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
8759191Skris#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88246772Sjkim
8959191Skris/* Fetch the instruction at PC.  Instructions are always big-endian
9059191Skris   even if the processor operates in little-endian mode.  */
9159191Skris
92246772Sjkimunsigned long
93246772Sjkimsparc_fetch_instruction (CORE_ADDR pc)
94246772Sjkim{
95246772Sjkim  unsigned char buf[4];
96246772Sjkim  unsigned long insn;
9759191Skris  int i;
9859191Skris
9959191Skris  /* If we can't read the instruction at PC, return zero.  */
100246772Sjkim  if (target_read_memory (pc, buf, sizeof (buf)))
10159191Skris    return 0;
10259191Skris
10359191Skris  insn = 0;
104246772Sjkim  for (i = 0; i < sizeof (buf); i++)
10559191Skris    insn = (insn << 8) | buf[i];
10668651Skris  return insn;
10768651Skris}
108246772Sjkim
109246772Sjkim
110246772Sjkim/* OpenBSD/sparc includes StackGhost, which according to the author's
111246772Sjkim   website http://stackghost.cerias.purdue.edu "... transparently and
112246772Sjkim   automatically protects applications' stack frames; more
11368651Skris   specifically, it guards the return pointers.  The protection
114238405Sjkim   mechanisms require no application source or binary modification and
115238405Sjkim   imposes only a negligible performance penalty."
116246772Sjkim
117246772Sjkim   The same website provides the following description of how
118246772Sjkim   StackGhost works:
119238405Sjkim
120238405Sjkim   "StackGhost interfaces with the kernel trap handler that would
121238405Sjkim   normally write out registers to the stack and the handler that
122238405Sjkim   would read them back in.  By XORing a cookie into the
123238405Sjkim   return-address saved in the user stack when it is actually written
124238405Sjkim   to the stack, and then XOR it out when the return-address is pulled
125238405Sjkim   from the stack, StackGhost can cause attacker corrupted return
126246772Sjkim   pointers to behave in a manner the attacker cannot predict.
127238405Sjkim   StackGhost can also use several unused bits in the return pointer
128238405Sjkim   to detect a smashed return pointer and abort the process."
129238405Sjkim
130246772Sjkim   For GDB this means that whenever we're reading %i7 from a stack
131238405Sjkim   frame's window save area, we'll have to XOR the cookie.
132238405Sjkim
133238405Sjkim   More information on StackGuard can be found on in:
134246772Sjkim
135238405Sjkim   Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
136284283Sjkim   Stack Protection."  2001.  Published in USENIX Security Symposium
137284283Sjkim   '01.  */
138284283Sjkim
139284283Sjkim/* Fetch StackGhost Per-Process XOR cookie.  */
140284283Sjkim
141284283SjkimULONGEST
142284283Sjkimsparc_fetch_wcookie (void)
143284283Sjkim{
144306195Sjkim  struct target_ops *ops = &current_target;
145306195Sjkim  char buf[8];
146306195Sjkim  int len;
147306195Sjkim
148290207Sjkim  len = target_read_partial (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
149290207Sjkim  if (len == -1)
150290207Sjkim    return 0;
151290207Sjkim
152290207Sjkim  /* We should have either an 32-bit or an 64-bit cookie.  */
153238405Sjkim  gdb_assert (len == 4 || len == 8);
154238405Sjkim
155246772Sjkim  return extract_unsigned_integer (buf, len);
156238405Sjkim}
157238405Sjkim
158238405Sjkim
159246772Sjkim/* Return the contents if register REGNUM as an address.  */
160238405Sjkim
161238405Sjkimstatic CORE_ADDR
162238405Sjkimsparc_address_from_register (int regnum)
163238405Sjkim{
164238405Sjkim  ULONGEST addr;
165246772Sjkim
166238405Sjkim  regcache_cooked_read_unsigned (current_regcache, regnum, &addr);
167238405Sjkim  return addr;
168238405Sjkim}
169238405Sjkim
170246772Sjkim
171246772Sjkim/* The functions on this page are intended to be used to classify
172238405Sjkim   function arguments.  */
173238405Sjkim
174238405Sjkim/* Check whether TYPE is "Integral or Pointer".  */
175246772Sjkim
176246772Sjkimstatic int
177238405Sjkimsparc_integral_or_pointer_p (const struct type *type)
178238405Sjkim{
179238405Sjkim  switch (TYPE_CODE (type))
180238405Sjkim    {
181238405Sjkim    case TYPE_CODE_INT:
182238405Sjkim    case TYPE_CODE_BOOL:
183238405Sjkim    case TYPE_CODE_CHAR:
184238405Sjkim    case TYPE_CODE_ENUM:
185238405Sjkim    case TYPE_CODE_RANGE:
186238405Sjkim      {
187205128Ssimon	/* We have byte, half-word, word and extended-word/doubleword
188205128Ssimon           integral types.  The doubleword is an extension to the
189205128Ssimon           origional 32-bit ABI by the SCD 2.4.x.  */
190205128Ssimon	int len = TYPE_LENGTH (type);
191205128Ssimon	return (len == 1 || len == 2 || len == 4 || len == 8);
19259191Skris      }
19359191Skris      return 1;
194246772Sjkim    case TYPE_CODE_PTR:
19559191Skris    case TYPE_CODE_REF:
19659191Skris      {
19759191Skris	/* Allow either 32-bit or 64-bit pointers.  */
19859191Skris	int len = TYPE_LENGTH (type);
19959191Skris	return (len == 4 || len == 8);
200246772Sjkim      }
201246772Sjkim      return 1;
202246772Sjkim    default:
20359191Skris      break;
20459191Skris    }
20559191Skris
20659191Skris  return 0;
20759191Skris}
20859191Skris
20959191Skris/* Check whether TYPE is "Floating".  */
21059191Skris
21159191Skrisstatic int
21259191Skrissparc_floating_p (const struct type *type)
21359191Skris{
21459191Skris  switch (TYPE_CODE (type))
21559191Skris    {
21659191Skris    case TYPE_CODE_FLT:
21759191Skris      {
21859191Skris	int len = TYPE_LENGTH (type);
21959191Skris	return (len == 4 || len == 8 || len == 16);
22059191Skris      }
22159191Skris    default:
22268651Skris      break;
22368651Skris    }
22468651Skris
22568651Skris  return 0;
22668651Skris}
22768651Skris
22868651Skris/* Check whether TYPE is "Structure or Union".  */
22968651Skris
23068651Skrisstatic int
23168651Skrissparc_structure_or_union_p (const struct type *type)
23268651Skris{
23368651Skris  switch (TYPE_CODE (type))
23468651Skris    {
23568651Skris    case TYPE_CODE_STRUCT:
23668651Skris    case TYPE_CODE_UNION:
23759191Skris      return 1;
23859191Skris    default:
23959191Skris      break;
24059191Skris    }
24159191Skris
24259191Skris  return 0;
24359191Skris}
24459191Skris
24559191Skris/* Register information.  */
24659191Skris
24759191Skrisstatic const char *sparc32_register_names[] =
24859191Skris{
24959191Skris  "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
25059191Skris  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
25159191Skris  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
25259191Skris  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
25359191Skris
25459191Skris  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
25559191Skris  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
25659191Skris  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
25759191Skris  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
25859191Skris
25959191Skris  "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
26059191Skris};
26159191Skris
26259191Skris/* Total number of registers.  */
26359191Skris#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
26459191Skris
26559191Skris/* We provide the aliases %d0..%d30 for the floating registers as
26659191Skris   "psuedo" registers.  */
26759191Skris
26859191Skrisstatic const char *sparc32_pseudo_register_names[] =
26959191Skris{
27059191Skris  "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
27159191Skris  "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
27259191Skris};
27359191Skris
27459191Skris/* Total number of pseudo registers.  */
27559191Skris#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
27659191Skris
27759191Skris/* Return the name of register REGNUM.  */
27859191Skris
27959191Skrisstatic const char *
28059191Skrissparc32_register_name (int regnum)
28159191Skris{
28259191Skris  if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
28359191Skris    return sparc32_register_names[regnum];
28459191Skris
28559191Skris  if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
28659191Skris    return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
28759191Skris
28859191Skris  return NULL;
28959191Skris}
29059191Skris
291205128Ssimon/* Return the GDB type object for the "standard" data type of data in
292205128Ssimon   register REGNUM. */
29359191Skris
294194206Ssimonstatic struct type *
29559191Skrissparc32_register_type (struct gdbarch *gdbarch, int regnum)
296238405Sjkim{
29759191Skris  if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
29859191Skris    return builtin_type_float;
29959191Skris
30059191Skris  if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
30159191Skris    return builtin_type_double;
30259191Skris
30359191Skris  if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
30459191Skris    return builtin_type_void_data_ptr;
30559191Skris
30659191Skris  if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
30759191Skris    return builtin_type_void_func_ptr;
30859191Skris
30959191Skris  return builtin_type_int32;
31059191Skris}
31159191Skris
31259191Skrisstatic void
31359191Skrissparc32_pseudo_register_read (struct gdbarch *gdbarch,
31459191Skris			      struct regcache *regcache,
31559191Skris			      int regnum, void *buf)
31659191Skris{
31759191Skris  gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
31859191Skris
319238405Sjkim  regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
32059191Skris  regcache_raw_read (regcache, regnum, buf);
32159191Skris  regcache_raw_read (regcache, regnum + 1, ((char *)buf) + 4);
32259191Skris}
32359191Skris
32459191Skrisstatic void
32589837Skrissparc32_pseudo_register_write (struct gdbarch *gdbarch,
32659191Skris			       struct regcache *regcache,
32789837Skris			       int regnum, const void *buf)
32859191Skris{
32989837Skris  gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
33059191Skris
331238405Sjkim  regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
33259191Skris  regcache_raw_write (regcache, regnum, buf);
33359191Skris  regcache_raw_write (regcache, regnum + 1, ((const char *)buf) + 4);
33459191Skris}
335238405Sjkim
33659191Skris
33759191Skrisstatic CORE_ADDR
33859191Skrissparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
33959191Skris			 CORE_ADDR funcaddr, int using_gcc,
34059191Skris			 struct value **args, int nargs,
34159191Skris			 struct type *value_type,
34259191Skris			 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
34359191Skris{
34459191Skris  *bp_addr = sp - 4;
34559191Skris  *real_pc = funcaddr;
34659191Skris
347238405Sjkim  if (using_struct_return (value_type, using_gcc))
34859191Skris    {
34959191Skris      char buf[4];
35059191Skris
351238405Sjkim      /* This is an UNIMP instruction.  */
35259191Skris      store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
35359191Skris      write_memory (sp - 8, buf, 4);
35459191Skris      return sp - 8;
35559191Skris    }
35659191Skris
35759191Skris  return sp - 4;
35859191Skris}
35959191Skris
36059191Skrisstatic CORE_ADDR
36159191Skrissparc32_store_arguments (struct regcache *regcache, int nargs,
36259191Skris			 struct value **args, CORE_ADDR sp,
36359191Skris			 int struct_return, CORE_ADDR struct_addr)
36459191Skris{
36559191Skris  /* Number of words in the "parameter array".  */
36659191Skris  int num_elements = 0;
36759191Skris  int element = 0;
36859191Skris  int i;
369205128Ssimon
370205128Ssimon  for (i = 0; i < nargs; i++)
37159191Skris    {
37259191Skris      struct type *type = VALUE_TYPE (args[i]);
37359191Skris      int len = TYPE_LENGTH (type);
37459191Skris
37559191Skris      if (sparc_structure_or_union_p (type)
37659191Skris	  || (sparc_floating_p (type) && len == 16))
37759191Skris	{
37859191Skris	  /* Structure, Union and Quad-Precision Arguments.  */
37959191Skris	  sp -= len;
38059191Skris
38159191Skris	  /* Use doubleword alignment for these values.  That's always
38259191Skris             correct, and wasting a few bytes shouldn't be a problem.  */
383238405Sjkim	  sp &= ~0x7;
38459191Skris
38559191Skris	  write_memory (sp, VALUE_CONTENTS (args[i]), len);
38659191Skris	  args[i] = value_from_pointer (lookup_pointer_type (type), sp);
38759191Skris	  num_elements++;
38859191Skris	}
38959191Skris      else if (sparc_floating_p (type))
39059191Skris	{
39159191Skris	  /* Floating arguments.  */
39259191Skris	  gdb_assert (len == 4 || len == 8);
39359191Skris	  num_elements += (len / 4);
39459191Skris	}
39559191Skris      else
39659191Skris	{
39759191Skris	  /* Integral and pointer arguments.  */
39859191Skris	  gdb_assert (sparc_integral_or_pointer_p (type));
39959191Skris
40059191Skris	  if (len < 4)
40159191Skris	    args[i] = value_cast (builtin_type_int32, args[i]);
40259191Skris	  num_elements += ((len + 3) / 4);
40359191Skris	}
40459191Skris    }
40559191Skris
40668651Skris  /* Always allocate at least six words.  */
40768651Skris  sp -= max (6, num_elements) * 4;
40868651Skris
40968651Skris  /* The psABI says that "Software convention requires space for the
41068651Skris     struct/union return value pointer, even if the word is unused."  */
41168651Skris  sp -= 4;
41268651Skris
41368651Skris  /* The psABI says that "Although software convention and the
41468651Skris     operating system require every stack frame to be doubleword
41568651Skris     aligned."  */
41668651Skris  sp &= ~0x7;
41768651Skris
41868651Skris  for (i = 0; i < nargs; i++)
41968651Skris    {
42068651Skris      char *valbuf = VALUE_CONTENTS (args[i]);
42168651Skris      struct type *type = VALUE_TYPE (args[i]);
42268651Skris      int len = TYPE_LENGTH (type);
42368651Skris
42468651Skris      gdb_assert (len == 4 || len == 8);
42568651Skris
42668651Skris      if (element < 6)
42768651Skris	{
42868651Skris	  int regnum = SPARC_O0_REGNUM + element;
42959191Skris
43059191Skris	  regcache_cooked_write (regcache, regnum, valbuf);
43159191Skris	  if (len > 4 && element < 5)
43259191Skris	    regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
43359191Skris	}
43459191Skris
43568651Skris      /* Always store the argument in memory.  */
43668651Skris      write_memory (sp + 4 + element * 4, valbuf, len);
437267256Sjkim      element += len / 4;
43868651Skris    }
43968651Skris
44068651Skris  gdb_assert (element == num_elements);
44168651Skris
44268651Skris  if (struct_return)
44368651Skris    {
44468651Skris      char buf[4];
44568651Skris
446205128Ssimon      store_unsigned_integer (buf, 4, struct_addr);
447205128Ssimon      write_memory (sp, buf, 4);
448205128Ssimon    }
449205128Ssimon
45059191Skris  return sp;
45159191Skris}
45259191Skris
45359191Skrisstatic CORE_ADDR
454284283Sjkimsparc32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
455284283Sjkim			 struct regcache *regcache, CORE_ADDR bp_addr,
456290207Sjkim			 int nargs, struct value **args, CORE_ADDR sp,
457284283Sjkim			 int struct_return, CORE_ADDR struct_addr)
45859191Skris{
459  CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
460
461  /* Set return address.  */
462  regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
463
464  /* Set up function arguments.  */
465  sp = sparc32_store_arguments (regcache, nargs, args, sp,
466				struct_return, struct_addr);
467
468  /* Allocate the 16-word window save area.  */
469  sp -= 16 * 4;
470
471  /* Stack should be doubleword aligned at this point.  */
472  gdb_assert (sp % 8 == 0);
473
474  /* Finally, update the stack pointer.  */
475  regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
476
477  return sp;
478}
479
480
481/* Use the program counter to determine the contents and size of a
482   breakpoint instruction.  Return a pointer to a string of bytes that
483   encode a breakpoint instruction, store the length of the string in
484   *LEN and optionally adjust *PC to point to the correct memory
485   location for inserting the breakpoint.  */
486
487static const unsigned char *
488sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
489{
490  static unsigned char break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
491
492  *len = sizeof (break_insn);
493  return break_insn;
494}
495
496
497/* Allocate and initialize a frame cache.  */
498
499static struct sparc_frame_cache *
500sparc_alloc_frame_cache (void)
501{
502  struct sparc_frame_cache *cache;
503  int i;
504
505  cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
506
507  /* Base address.  */
508  cache->base = 0;
509  cache->pc = 0;
510
511  /* Frameless until proven otherwise.  */
512  cache->frameless_p = 1;
513
514  cache->struct_return_p = 0;
515
516  return cache;
517}
518
519CORE_ADDR
520sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
521			struct sparc_frame_cache *cache)
522{
523  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
524  unsigned long insn;
525  int offset = 0;
526  int dest = -1;
527
528  if (current_pc <= pc)
529    return current_pc;
530
531  /* We have to handle to "Procedure Linkage Table" (PLT) special.  On
532     SPARC the linker usually defines a symbol (typically
533     _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
534     This symbol makes us end up here with PC pointing at the start of
535     the PLT and CURRENT_PC probably pointing at a PLT entry.  If we
536     would do our normal prologue analysis, we would probably conclude
537     that we've got a frame when in reality we don't, since the
538     dynamic linker patches up the first PLT with some code that
539     starts with a SAVE instruction.  Patch up PC such that it points
540     at the start of our PLT entry.  */
541  if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
542    pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
543
544  insn = sparc_fetch_instruction (pc);
545
546  /* Recognize a SETHI insn and record its destination.  */
547  if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
548    {
549      dest = X_RD (insn);
550      offset += 4;
551
552      insn = sparc_fetch_instruction (pc + 4);
553    }
554
555  /* Allow for an arithmetic operation on DEST or %g1.  */
556  if (X_OP (insn) == 2 && X_I (insn)
557      && (X_RD (insn) == 1 || X_RD (insn) == dest))
558    {
559      offset += 4;
560
561      insn = sparc_fetch_instruction (pc + 8);
562    }
563
564  /* Check for the SAVE instruction that sets up the frame.  */
565  if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
566    {
567      cache->frameless_p = 0;
568      return pc + offset + 4;
569    }
570
571  return pc;
572}
573
574static CORE_ADDR
575sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
576{
577  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
578  return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
579}
580
581/* Return PC of first real instruction of the function starting at
582   START_PC.  */
583
584static CORE_ADDR
585sparc32_skip_prologue (CORE_ADDR start_pc)
586{
587  struct symtab_and_line sal;
588  CORE_ADDR func_start, func_end;
589  struct sparc_frame_cache cache;
590
591  /* This is the preferred method, find the end of the prologue by
592     using the debugging information.  */
593  if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
594    {
595      sal = find_pc_line (func_start, 0);
596
597      if (sal.end < func_end
598	  && start_pc <= sal.end)
599	return sal.end;
600    }
601
602  return sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache);
603}
604
605/* Normal frames.  */
606
607struct sparc_frame_cache *
608sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
609{
610  struct sparc_frame_cache *cache;
611
612  if (*this_cache)
613    return *this_cache;
614
615  cache = sparc_alloc_frame_cache ();
616  *this_cache = cache;
617
618  cache->pc = frame_func_unwind (next_frame);
619  if (cache->pc != 0)
620    {
621      CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame);
622      sparc_analyze_prologue (cache->pc, addr_in_block, cache);
623    }
624
625  if (cache->frameless_p)
626    {
627      /* This function is frameless, so %fp (%i6) holds the frame
628         pointer for our calling frame.  Use %sp (%o6) as this frame's
629         base address.  */
630      cache->base =
631	frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
632    }
633  else
634    {
635      /* For normal frames, %fp (%i6) holds the frame pointer, the
636         base address for the current stack frame.  */
637      cache->base =
638	frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
639    }
640
641  return cache;
642}
643
644struct sparc_frame_cache *
645sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
646{
647  struct sparc_frame_cache *cache;
648  struct symbol *sym;
649
650  if (*this_cache)
651    return *this_cache;
652
653  cache = sparc_frame_cache (next_frame, this_cache);
654
655  sym = find_pc_function (cache->pc);
656  if (sym)
657    {
658      struct type *type = check_typedef (SYMBOL_TYPE (sym));
659      enum type_code code = TYPE_CODE (type);
660
661      if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
662	{
663	  type = check_typedef (TYPE_TARGET_TYPE (type));
664	  if (sparc_structure_or_union_p (type)
665	      || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
666	    cache->struct_return_p = 1;
667	}
668    }
669
670  return cache;
671}
672
673static void
674sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
675		       struct frame_id *this_id)
676{
677  struct sparc_frame_cache *cache =
678    sparc32_frame_cache (next_frame, this_cache);
679
680  /* This marks the outermost frame.  */
681  if (cache->base == 0)
682    return;
683
684  (*this_id) = frame_id_build (cache->base, cache->pc);
685}
686
687static void
688sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
689			     int regnum, int *optimizedp,
690			     enum lval_type *lvalp, CORE_ADDR *addrp,
691			     int *realnump, void *valuep)
692{
693  struct sparc_frame_cache *cache =
694    sparc32_frame_cache (next_frame, this_cache);
695
696  if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
697    {
698      *optimizedp = 0;
699      *lvalp = not_lval;
700      *addrp = 0;
701      *realnump = -1;
702      if (valuep)
703	{
704	  CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
705
706	  /* If this functions has a Structure, Union or
707             Quad-Precision return value, we have to skip the UNIMP
708             instruction that encodes the size of the structure.  */
709	  if (cache->struct_return_p)
710	    pc += 4;
711
712	  regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
713	  pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
714	  store_unsigned_integer (valuep, 4, pc);
715	}
716      return;
717    }
718
719  /* Handle StackGhost.  */
720  {
721    ULONGEST wcookie = sparc_fetch_wcookie ();
722
723    if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
724      {
725	*optimizedp = 0;
726	*lvalp = not_lval;
727	*addrp = 0;
728	*realnump = -1;
729	if (valuep)
730	  {
731	    CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
732	    ULONGEST i7;
733
734	    /* Read the value in from memory.  */
735	    i7 = get_frame_memory_unsigned (next_frame, addr, 4);
736	    store_unsigned_integer (valuep, 4, i7 ^ wcookie);
737	  }
738	return;
739      }
740  }
741
742  /* The previous frame's `local' and `in' registers have been saved
743     in the register save area.  */
744  if (!cache->frameless_p
745      && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
746    {
747      *optimizedp = 0;
748      *lvalp = lval_memory;
749      *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
750      *realnump = -1;
751      if (valuep)
752	{
753	  struct gdbarch *gdbarch = get_frame_arch (next_frame);
754
755	  /* Read the value in from memory.  */
756	  read_memory (*addrp, valuep, register_size (gdbarch, regnum));
757	}
758      return;
759    }
760
761  /* The previous frame's `out' registers are accessable as the
762     current frame's `in' registers.  */
763  if (!cache->frameless_p
764      && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
765    regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
766
767  frame_register_unwind (next_frame, regnum,
768			 optimizedp, lvalp, addrp, realnump, valuep);
769}
770
771static const struct frame_unwind sparc32_frame_unwind =
772{
773  NORMAL_FRAME,
774  sparc32_frame_this_id,
775  sparc32_frame_prev_register
776};
777
778static const struct frame_unwind *
779sparc32_frame_sniffer (struct frame_info *next_frame)
780{
781  return &sparc32_frame_unwind;
782}
783
784
785static CORE_ADDR
786sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
787{
788  struct sparc_frame_cache *cache =
789    sparc32_frame_cache (next_frame, this_cache);
790
791  return cache->base;
792}
793
794static const struct frame_base sparc32_frame_base =
795{
796  &sparc32_frame_unwind,
797  sparc32_frame_base_address,
798  sparc32_frame_base_address,
799  sparc32_frame_base_address
800};
801
802static struct frame_id
803sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
804{
805  CORE_ADDR sp;
806
807  sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
808  return frame_id_build (sp, frame_pc_unwind (next_frame));
809}
810
811
812/* Extract from an array REGBUF containing the (raw) register state, a
813   function return value of TYPE, and copy that into VALBUF.  */
814
815static void
816sparc32_extract_return_value (struct type *type, struct regcache *regcache,
817			      void *valbuf)
818{
819  int len = TYPE_LENGTH (type);
820  char buf[8];
821
822  gdb_assert (!sparc_structure_or_union_p (type));
823  gdb_assert (!(sparc_floating_p (type) && len == 16));
824
825  if (sparc_floating_p (type))
826    {
827      /* Floating return values.  */
828      regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
829      if (len > 4)
830	regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
831      memcpy (valbuf, buf, len);
832    }
833  else
834    {
835      /* Integral and pointer return values.  */
836      gdb_assert (sparc_integral_or_pointer_p (type));
837
838      regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
839      if (len > 4)
840	{
841	  regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
842	  gdb_assert (len == 8);
843	  memcpy (valbuf, buf, 8);
844	}
845      else
846	{
847	  /* Just stripping off any unused bytes should preserve the
848	     signed-ness just fine.  */
849	  memcpy (valbuf, buf + 4 - len, len);
850	}
851    }
852}
853
854/* Write into the appropriate registers a function return value stored
855   in VALBUF of type TYPE.  */
856
857static void
858sparc32_store_return_value (struct type *type, struct regcache *regcache,
859			    const void *valbuf)
860{
861  int len = TYPE_LENGTH (type);
862  char buf[8];
863
864  gdb_assert (!sparc_structure_or_union_p (type));
865  gdb_assert (!(sparc_floating_p (type) && len == 16));
866
867  if (sparc_floating_p (type))
868    {
869      /* Floating return values.  */
870      memcpy (buf, valbuf, len);
871      regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
872      if (len > 4)
873	regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
874    }
875  else
876    {
877      /* Integral and pointer return values.  */
878      gdb_assert (sparc_integral_or_pointer_p (type));
879
880      if (len > 4)
881	{
882	  gdb_assert (len == 8);
883	  memcpy (buf, valbuf, 8);
884	  regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
885	}
886      else
887	{
888	  /* ??? Do we need to do any sign-extension here?  */
889	  memcpy (buf + 4 - len, valbuf, len);
890	}
891      regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
892    }
893}
894
895static enum return_value_convention
896sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
897		      struct regcache *regcache, void *readbuf,
898		      const void *writebuf)
899{
900  if (sparc_structure_or_union_p (type)
901      || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
902    return RETURN_VALUE_STRUCT_CONVENTION;
903
904  if (readbuf)
905    sparc32_extract_return_value (type, regcache, readbuf);
906  if (writebuf)
907    sparc32_store_return_value (type, regcache, writebuf);
908
909  return RETURN_VALUE_REGISTER_CONVENTION;
910}
911
912#if 0
913/* NOTE: cagney/2004-01-17: For the moment disable this method.  The
914   architecture and CORE-gdb will need new code (and a replacement for
915   DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS) before this can be made to
916   work robustly.  Here is a possible function signature: */
917/* NOTE: cagney/2004-01-17: So far only the 32-bit SPARC ABI has been
918   identifed as having a way to robustly recover the address of a
919   struct-convention return-value (after the function has returned).
920   For all other ABIs so far examined, the calling convention makes no
921   guarenteed that the register containing the return-value will be
922   preserved and hence that the return-value's address can be
923   recovered.  */
924/* Extract from REGCACHE, which contains the (raw) register state, the
925   address in which a function should return its structure value, as a
926   CORE_ADDR.  */
927
928static CORE_ADDR
929sparc32_extract_struct_value_address (struct regcache *regcache)
930{
931  ULONGEST sp;
932
933  regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
934  return read_memory_unsigned_integer (sp + 64, 4);
935}
936#endif
937
938static int
939sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
940{
941  return (sparc_structure_or_union_p (type)
942	  || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
943}
944
945
946/* The SPARC Architecture doesn't have hardware single-step support,
947   and most operating systems don't implement it either, so we provide
948   software single-step mechanism.  */
949
950static CORE_ADDR
951sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
952{
953  unsigned long insn = sparc_fetch_instruction (pc);
954  int conditional_p = X_COND (insn) & 0x7;
955  int branch_p = 0;
956  long offset = 0;			/* Must be signed for sign-extend.  */
957
958  if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
959    {
960      /* Branch on Integer Register with Prediction (BPr).  */
961      branch_p = 1;
962      conditional_p = 1;
963    }
964  else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
965    {
966      /* Branch on Floating-Point Condition Codes (FBfcc).  */
967      branch_p = 1;
968      offset = 4 * X_DISP22 (insn);
969    }
970  else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
971    {
972      /* Branch on Floating-Point Condition Codes with Prediction
973         (FBPfcc).  */
974      branch_p = 1;
975      offset = 4 * X_DISP19 (insn);
976    }
977  else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
978    {
979      /* Branch on Integer Condition Codes (Bicc).  */
980      branch_p = 1;
981      offset = 4 * X_DISP22 (insn);
982    }
983  else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
984    {
985      /* Branch on Integer Condition Codes with Prediction (BPcc).  */
986      branch_p = 1;
987      offset = 4 * X_DISP19 (insn);
988    }
989
990  /* FIXME: Handle DONE and RETRY instructions.  */
991
992  /* FIXME: Handle the Trap instruction.  */
993
994  if (branch_p)
995    {
996      if (conditional_p)
997	{
998	  /* For conditional branches, return nPC + 4 iff the annul
999	     bit is 1.  */
1000	  return (X_A (insn) ? *npc + 4 : 0);
1001	}
1002      else
1003	{
1004	  /* For unconditional branches, return the target if its
1005	     specified condition is "always" and return nPC + 4 if the
1006	     condition is "never".  If the annul bit is 1, set *NPC to
1007	     zero.  */
1008	  if (X_COND (insn) == 0x0)
1009	    pc = *npc, offset = 4;
1010	  if (X_A (insn))
1011	    *npc = 0;
1012
1013	  gdb_assert (offset != 0);
1014	  return pc + offset;
1015	}
1016    }
1017
1018  return 0;
1019}
1020
1021void
1022sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1023{
1024  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1025  static CORE_ADDR npc, nnpc;
1026  static char npc_save[4], nnpc_save[4];
1027
1028  if (insert_breakpoints_p)
1029    {
1030      CORE_ADDR pc;
1031
1032      pc = sparc_address_from_register (tdep->pc_regnum);
1033      npc = sparc_address_from_register (tdep->npc_regnum);
1034
1035      /* Analyze the instruction at PC.  */
1036      nnpc = sparc_analyze_control_transfer (pc, &npc);
1037      if (npc != 0)
1038	target_insert_breakpoint (npc, npc_save);
1039      if (nnpc != 0)
1040	target_insert_breakpoint (nnpc, nnpc_save);
1041
1042      /* Assert that we have set at least one breakpoint, and that
1043         they're not set at the same spot.  */
1044      gdb_assert (npc != 0 || nnpc != 0);
1045      gdb_assert (nnpc != npc);
1046    }
1047  else
1048    {
1049      if (npc != 0)
1050	target_remove_breakpoint (npc, npc_save);
1051      if (nnpc != 0)
1052	target_remove_breakpoint (nnpc, nnpc_save);
1053    }
1054}
1055
1056static void
1057sparc_write_pc (CORE_ADDR pc, ptid_t ptid)
1058{
1059  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1060
1061  write_register_pid (tdep->pc_regnum, pc, ptid);
1062  write_register_pid (tdep->npc_regnum, pc + 4, ptid);
1063}
1064
1065/* Unglobalize NAME.  */
1066
1067char *
1068sparc_stabs_unglobalize_name (char *name)
1069{
1070  /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1071     SunPRO) convert file static variables into global values, a
1072     process known as globalization.  In order to do this, the
1073     compiler will create a unique prefix and prepend it to each file
1074     static variable.  For static variables within a function, this
1075     globalization prefix is followed by the function name (nested
1076     static variables within a function are supposed to generate a
1077     warning message, and are left alone).  The procedure is
1078     documented in the Stabs Interface Manual, which is distrubuted
1079     with the compilers, although version 4.0 of the manual seems to
1080     be incorrect in some places, at least for SPARC.  The
1081     globalization prefix is encoded into an N_OPT stab, with the form
1082     "G=<prefix>".  The globalization prefix always seems to start
1083     with a dollar sign '$'; a dot '.' is used as a seperator.  So we
1084     simply strip everything up until the last dot.  */
1085
1086  if (name[0] == '$')
1087    {
1088      char *p = strrchr (name, '.');
1089      if (p)
1090	return p + 1;
1091    }
1092
1093  return name;
1094}
1095
1096
1097/* Return the appropriate register set for the core section identified
1098   by SECT_NAME and SECT_SIZE.  */
1099
1100const struct regset *
1101sparc_regset_from_core_section (struct gdbarch *gdbarch,
1102				const char *sect_name, size_t sect_size)
1103{
1104  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1105
1106  if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1107    return tdep->gregset;
1108
1109  if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1110    return tdep->fpregset;
1111
1112  return NULL;
1113}
1114
1115
1116static struct gdbarch *
1117sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1118{
1119  struct gdbarch_tdep *tdep;
1120  struct gdbarch *gdbarch;
1121
1122  /* If there is already a candidate, use it.  */
1123  arches = gdbarch_list_lookup_by_info (arches, &info);
1124  if (arches != NULL)
1125    return arches->gdbarch;
1126
1127  /* Allocate space for the new architecture.  */
1128  tdep = XMALLOC (struct gdbarch_tdep);
1129  gdbarch = gdbarch_alloc (&info, tdep);
1130
1131  tdep->pc_regnum = SPARC32_PC_REGNUM;
1132  tdep->npc_regnum = SPARC32_NPC_REGNUM;
1133  tdep->gregset = NULL;
1134  tdep->sizeof_gregset = 0;
1135  tdep->fpregset = NULL;
1136  tdep->sizeof_fpregset = 0;
1137  tdep->plt_entry_size = 0;
1138
1139  set_gdbarch_long_double_bit (gdbarch, 128);
1140  set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad);
1141
1142  set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1143  set_gdbarch_register_name (gdbarch, sparc32_register_name);
1144  set_gdbarch_register_type (gdbarch, sparc32_register_type);
1145  set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1146  set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1147  set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1148
1149  /* Register numbers of various important registers.  */
1150  set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1151  set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1152  set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1153
1154  /* Call dummy code.  */
1155  set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1156  set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1157  set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1158
1159  set_gdbarch_return_value (gdbarch, sparc32_return_value);
1160  set_gdbarch_stabs_argument_has_addr
1161    (gdbarch, sparc32_stabs_argument_has_addr);
1162
1163  set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1164
1165  /* Stack grows downward.  */
1166  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1167
1168  set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1169
1170  set_gdbarch_frame_args_skip (gdbarch, 8);
1171
1172  set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1173
1174  set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1175  set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1176
1177  set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1178
1179  set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1180
1181  frame_base_set_default (gdbarch, &sparc32_frame_base);
1182
1183  /* Hook in ABI-specific overrides, if they have been registered.  */
1184  gdbarch_init_osabi (info, gdbarch);
1185
1186  frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1187
1188  /* If we have register sets, enable the generic core file support.  */
1189  if (tdep->gregset)
1190    set_gdbarch_regset_from_core_section (gdbarch,
1191					  sparc_regset_from_core_section);
1192
1193  return gdbarch;
1194}
1195
1196/* Helper functions for dealing with register windows.  */
1197
1198void
1199sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1200{
1201  int offset = 0;
1202  char buf[8];
1203  int i;
1204
1205  if (sp & 1)
1206    {
1207      /* Registers are 64-bit.  */
1208      sp += BIAS;
1209
1210      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1211	{
1212	  if (regnum == i || regnum == -1)
1213	    {
1214	      target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1215	      regcache_raw_supply (regcache, i, buf);
1216	    }
1217	}
1218    }
1219  else
1220    {
1221      /* Registers are 32-bit.  Toss any sign-extension of the stack
1222	 pointer.  */
1223      sp &= 0xffffffffUL;
1224
1225      /* Clear out the top half of the temporary buffer, and put the
1226	 register value in the bottom half if we're in 64-bit mode.  */
1227      if (gdbarch_ptr_bit (current_gdbarch) == 64)
1228	{
1229	  memset (buf, 0, 4);
1230	  offset = 4;
1231	}
1232
1233      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1234	{
1235	  if (regnum == i || regnum == -1)
1236	    {
1237	      target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1238				  buf + offset, 4);
1239
1240	      /* Handle StackGhost.  */
1241	      if (i == SPARC_I7_REGNUM)
1242		{
1243		  ULONGEST wcookie = sparc_fetch_wcookie ();
1244		  ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1245
1246		  store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1247		}
1248
1249	      regcache_raw_supply (regcache, i, buf);
1250	    }
1251	}
1252    }
1253}
1254
1255void
1256sparc_collect_rwindow (const struct regcache *regcache,
1257		       CORE_ADDR sp, int regnum)
1258{
1259  int offset = 0;
1260  char buf[8];
1261  int i;
1262
1263  if (sp & 1)
1264    {
1265      /* Registers are 64-bit.  */
1266      sp += BIAS;
1267
1268      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1269	{
1270	  if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1271	    {
1272	      regcache_raw_collect (regcache, i, buf);
1273	      target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1274	    }
1275	}
1276    }
1277  else
1278    {
1279      /* Registers are 32-bit.  Toss any sign-extension of the stack
1280	 pointer.  */
1281      sp &= 0xffffffffUL;
1282
1283      /* Only use the bottom half if we're in 64-bit mode.  */
1284      if (gdbarch_ptr_bit (current_gdbarch) == 64)
1285	offset = 4;
1286
1287      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1288	{
1289	  if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1290	    {
1291	      regcache_raw_collect (regcache, i, buf);
1292
1293	      /* Handle StackGhost.  */
1294	      if (i == SPARC_I7_REGNUM)
1295		{
1296		  ULONGEST wcookie = sparc_fetch_wcookie ();
1297		  ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1298
1299		  store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1300		}
1301
1302	      target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1303				   buf + offset, 4);
1304	    }
1305	}
1306    }
1307}
1308
1309/* Helper functions for dealing with register sets.  */
1310
1311void
1312sparc32_supply_gregset (const struct sparc_gregset *gregset,
1313			struct regcache *regcache,
1314			int regnum, const void *gregs)
1315{
1316  const char *regs = gregs;
1317  int i;
1318
1319  if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1320    regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1321			 regs + gregset->r_psr_offset);
1322
1323  if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1324    regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1325			 regs + gregset->r_pc_offset);
1326
1327  if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1328    regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1329			 regs + gregset->r_npc_offset);
1330
1331  if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1332    regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1333			 regs + gregset->r_y_offset);
1334
1335  if (regnum == SPARC_G0_REGNUM || regnum == -1)
1336    regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1337
1338  if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1339    {
1340      int offset = gregset->r_g1_offset;
1341
1342      for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1343	{
1344	  if (regnum == i || regnum == -1)
1345	    regcache_raw_supply (regcache, i, regs + offset);
1346	  offset += 4;
1347	}
1348    }
1349
1350  if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1351    {
1352      /* Not all of the register set variants include Locals and
1353         Inputs.  For those that don't, we read them off the stack.  */
1354      if (gregset->r_l0_offset == -1)
1355	{
1356	  ULONGEST sp;
1357
1358	  regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1359	  sparc_supply_rwindow (regcache, sp, regnum);
1360	}
1361      else
1362	{
1363	  int offset = gregset->r_l0_offset;
1364
1365	  for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1366	    {
1367	      if (regnum == i || regnum == -1)
1368		regcache_raw_supply (regcache, i, regs + offset);
1369	      offset += 4;
1370	    }
1371	}
1372    }
1373}
1374
1375void
1376sparc32_collect_gregset (const struct sparc_gregset *gregset,
1377			 const struct regcache *regcache,
1378			 int regnum, void *gregs)
1379{
1380  char *regs = gregs;
1381  int i;
1382
1383  if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1384    regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1385			  regs + gregset->r_psr_offset);
1386
1387  if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1388    regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1389			  regs + gregset->r_pc_offset);
1390
1391  if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1392    regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1393			  regs + gregset->r_npc_offset);
1394
1395  if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1396    regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1397			  regs + gregset->r_y_offset);
1398
1399  if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1400    {
1401      int offset = gregset->r_g1_offset;
1402
1403      /* %g0 is always zero.  */
1404      for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1405	{
1406	  if (regnum == i || regnum == -1)
1407	    regcache_raw_collect (regcache, i, regs + offset);
1408	  offset += 4;
1409	}
1410    }
1411
1412  if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1413    {
1414      /* Not all of the register set variants include Locals and
1415         Inputs.  For those that don't, we read them off the stack.  */
1416      if (gregset->r_l0_offset != -1)
1417	{
1418	  int offset = gregset->r_l0_offset;
1419
1420	  for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1421	    {
1422	      if (regnum == i || regnum == -1)
1423		regcache_raw_collect (regcache, i, regs + offset);
1424	      offset += 4;
1425	    }
1426	}
1427    }
1428}
1429
1430void
1431sparc32_supply_fpregset (struct regcache *regcache,
1432			 int regnum, const void *fpregs)
1433{
1434  const char *regs = fpregs;
1435  int i;
1436
1437  for (i = 0; i < 32; i++)
1438    {
1439      if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1440	regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1441    }
1442
1443  if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1444    regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1445}
1446
1447void
1448sparc32_collect_fpregset (const struct regcache *regcache,
1449			  int regnum, void *fpregs)
1450{
1451  char *regs = fpregs;
1452  int i;
1453
1454  for (i = 0; i < 32; i++)
1455    {
1456      if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1457	regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1458    }
1459
1460  if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1461    regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1462}
1463
1464
1465/* SunOS 4.  */
1466
1467/* From <machine/reg.h>.  */
1468const struct sparc_gregset sparc32_sunos4_gregset =
1469{
1470  0 * 4,			/* %psr */
1471  1 * 4,			/* %pc */
1472  2 * 4,			/* %npc */
1473  3 * 4,			/* %y */
1474  -1,				/* %wim */
1475  -1,				/* %tbr */
1476  4 * 4,			/* %g1 */
1477  -1				/* %l0 */
1478};
1479
1480
1481/* Provide a prototype to silence -Wmissing-prototypes.  */
1482void _initialize_sparc_tdep (void);
1483
1484void
1485_initialize_sparc_tdep (void)
1486{
1487  register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1488}
1489