1130803Smarcel/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. 2130803Smarcel 3130803Smarcel Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 4130803Smarcel 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software 5130803Smarcel Foundation, Inc. 6130803Smarcel 7130803Smarcel Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU 8130803Smarcel and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. 9130803Smarcel 10130803Smarcel This file is part of GDB. 11130803Smarcel 12130803Smarcel This program is free software; you can redistribute it and/or modify 13130803Smarcel it under the terms of the GNU General Public License as published by 14130803Smarcel the Free Software Foundation; either version 2 of the License, or 15130803Smarcel (at your option) any later version. 16130803Smarcel 17130803Smarcel This program is distributed in the hope that it will be useful, 18130803Smarcel but WITHOUT ANY WARRANTY; without even the implied warranty of 19130803Smarcel MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20130803Smarcel GNU General Public License for more details. 21130803Smarcel 22130803Smarcel You should have received a copy of the GNU General Public License 23130803Smarcel along with this program; if not, write to the Free Software 24130803Smarcel Foundation, Inc., 59 Temple Place - Suite 330, 25130803Smarcel Boston, MA 02111-1307, USA. */ 26130803Smarcel 27130803Smarcel#include "defs.h" 28130803Smarcel#include "gdb_string.h" 29130803Smarcel#include "gdb_assert.h" 30130803Smarcel#include "frame.h" 31130803Smarcel#include "inferior.h" 32130803Smarcel#include "symtab.h" 33130803Smarcel#include "value.h" 34130803Smarcel#include "gdbcmd.h" 35130803Smarcel#include "language.h" 36130803Smarcel#include "gdbcore.h" 37130803Smarcel#include "symfile.h" 38130803Smarcel#include "objfiles.h" 39130803Smarcel#include "gdbtypes.h" 40130803Smarcel#include "target.h" 41130803Smarcel#include "arch-utils.h" 42130803Smarcel#include "regcache.h" 43130803Smarcel#include "osabi.h" 44130803Smarcel#include "mips-tdep.h" 45130803Smarcel#include "block.h" 46130803Smarcel#include "reggroups.h" 47130803Smarcel#include "opcode/mips.h" 48130803Smarcel#include "elf/mips.h" 49130803Smarcel#include "elf-bfd.h" 50130803Smarcel#include "symcat.h" 51130803Smarcel#include "sim-regno.h" 52130803Smarcel#include "dis-asm.h" 53130803Smarcel#include "frame-unwind.h" 54130803Smarcel#include "frame-base.h" 55130803Smarcel#include "trad-frame.h" 56130803Smarcel 57130803Smarcelstatic const struct objfile_data *mips_pdr_data; 58130803Smarcel 59130803Smarcelstatic void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off); 60130803Smarcelstatic struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); 61130803Smarcel 62130803Smarcel/* A useful bit in the CP0 status register (PS_REGNUM). */ 63130803Smarcel/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ 64130803Smarcel#define ST0_FR (1 << 26) 65130803Smarcel 66130803Smarcel/* The sizes of floating point registers. */ 67130803Smarcel 68130803Smarcelenum 69130803Smarcel{ 70130803Smarcel MIPS_FPU_SINGLE_REGSIZE = 4, 71130803Smarcel MIPS_FPU_DOUBLE_REGSIZE = 8 72130803Smarcel}; 73130803Smarcel 74130803Smarcel 75130803Smarcelstatic const char *mips_abi_string; 76130803Smarcel 77130803Smarcelstatic const char *mips_abi_strings[] = { 78130803Smarcel "auto", 79130803Smarcel "n32", 80130803Smarcel "o32", 81130803Smarcel "n64", 82130803Smarcel "o64", 83130803Smarcel "eabi32", 84130803Smarcel "eabi64", 85130803Smarcel NULL 86130803Smarcel}; 87130803Smarcel 88130803Smarcelstruct frame_extra_info 89130803Smarcel{ 90130803Smarcel mips_extra_func_info_t proc_desc; 91130803Smarcel int num_args; 92130803Smarcel}; 93130803Smarcel 94130803Smarcel/* Various MIPS ISA options (related to stack analysis) can be 95130803Smarcel overridden dynamically. Establish an enum/array for managing 96130803Smarcel them. */ 97130803Smarcel 98130803Smarcelstatic const char size_auto[] = "auto"; 99130803Smarcelstatic const char size_32[] = "32"; 100130803Smarcelstatic const char size_64[] = "64"; 101130803Smarcel 102130803Smarcelstatic const char *size_enums[] = { 103130803Smarcel size_auto, 104130803Smarcel size_32, 105130803Smarcel size_64, 106130803Smarcel 0 107130803Smarcel}; 108130803Smarcel 109130803Smarcel/* Some MIPS boards don't support floating point while others only 110130803Smarcel support single-precision floating-point operations. See also 111130803Smarcel FP_REGISTER_DOUBLE. */ 112130803Smarcel 113130803Smarcelenum mips_fpu_type 114130803Smarcel{ 115130803Smarcel MIPS_FPU_DOUBLE, /* Full double precision floating point. */ 116130803Smarcel MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ 117130803Smarcel MIPS_FPU_NONE /* No floating point. */ 118130803Smarcel}; 119130803Smarcel 120130803Smarcel#ifndef MIPS_DEFAULT_FPU_TYPE 121130803Smarcel#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE 122130803Smarcel#endif 123130803Smarcelstatic int mips_fpu_type_auto = 1; 124130803Smarcelstatic enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; 125130803Smarcel 126130803Smarcelstatic int mips_debug = 0; 127130803Smarcel 128130803Smarcel/* MIPS specific per-architecture information */ 129130803Smarcelstruct gdbarch_tdep 130130803Smarcel{ 131130803Smarcel /* from the elf header */ 132130803Smarcel int elf_flags; 133130803Smarcel 134130803Smarcel /* mips options */ 135130803Smarcel enum mips_abi mips_abi; 136130803Smarcel enum mips_abi found_abi; 137130803Smarcel enum mips_fpu_type mips_fpu_type; 138130803Smarcel int mips_last_arg_regnum; 139130803Smarcel int mips_last_fp_arg_regnum; 140130803Smarcel int mips_default_saved_regsize; 141130803Smarcel int mips_fp_register_double; 142130803Smarcel int mips_default_stack_argsize; 143130803Smarcel int default_mask_address_p; 144130803Smarcel /* Is the target using 64-bit raw integer registers but only 145130803Smarcel storing a left-aligned 32-bit value in each? */ 146130803Smarcel int mips64_transfers_32bit_regs_p; 147130803Smarcel /* Indexes for various registers. IRIX and embedded have 148130803Smarcel different values. This contains the "public" fields. Don't 149130803Smarcel add any that do not need to be public. */ 150130803Smarcel const struct mips_regnum *regnum; 151130803Smarcel /* Register names table for the current register set. */ 152130803Smarcel const char **mips_processor_reg_names; 153130803Smarcel}; 154130803Smarcel 155130803Smarcelconst struct mips_regnum * 156130803Smarcelmips_regnum (struct gdbarch *gdbarch) 157130803Smarcel{ 158130803Smarcel return gdbarch_tdep (gdbarch)->regnum; 159130803Smarcel} 160130803Smarcel 161130803Smarcelstatic int 162130803Smarcelmips_fpa0_regnum (struct gdbarch *gdbarch) 163130803Smarcel{ 164130803Smarcel return mips_regnum (gdbarch)->fp0 + 12; 165130803Smarcel} 166130803Smarcel 167130803Smarcel#define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ 168130803Smarcel || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) 169130803Smarcel 170130803Smarcel#define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) 171130803Smarcel 172130803Smarcel#define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) 173130803Smarcel 174130803Smarcel#define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) 175130803Smarcel 176130803Smarcel/* MIPS16 function addresses are odd (bit 0 is set). Here are some 177130803Smarcel functions to test, set, or clear bit 0 of addresses. */ 178130803Smarcel 179130803Smarcelstatic CORE_ADDR 180130803Smarcelis_mips16_addr (CORE_ADDR addr) 181130803Smarcel{ 182130803Smarcel return ((addr) & 1); 183130803Smarcel} 184130803Smarcel 185130803Smarcelstatic CORE_ADDR 186130803Smarcelmake_mips16_addr (CORE_ADDR addr) 187130803Smarcel{ 188130803Smarcel return ((addr) | 1); 189130803Smarcel} 190130803Smarcel 191130803Smarcelstatic CORE_ADDR 192130803Smarcelunmake_mips16_addr (CORE_ADDR addr) 193130803Smarcel{ 194130803Smarcel return ((addr) & ~1); 195130803Smarcel} 196130803Smarcel 197130803Smarcel/* Return the contents of register REGNUM as a signed integer. */ 198130803Smarcel 199130803Smarcelstatic LONGEST 200130803Smarcelread_signed_register (int regnum) 201130803Smarcel{ 202130803Smarcel void *buf = alloca (register_size (current_gdbarch, regnum)); 203130803Smarcel deprecated_read_register_gen (regnum, buf); 204130803Smarcel return (extract_signed_integer 205130803Smarcel (buf, register_size (current_gdbarch, regnum))); 206130803Smarcel} 207130803Smarcel 208130803Smarcelstatic LONGEST 209130803Smarcelread_signed_register_pid (int regnum, ptid_t ptid) 210130803Smarcel{ 211130803Smarcel ptid_t save_ptid; 212130803Smarcel LONGEST retval; 213130803Smarcel 214130803Smarcel if (ptid_equal (ptid, inferior_ptid)) 215130803Smarcel return read_signed_register (regnum); 216130803Smarcel 217130803Smarcel save_ptid = inferior_ptid; 218130803Smarcel 219130803Smarcel inferior_ptid = ptid; 220130803Smarcel 221130803Smarcel retval = read_signed_register (regnum); 222130803Smarcel 223130803Smarcel inferior_ptid = save_ptid; 224130803Smarcel 225130803Smarcel return retval; 226130803Smarcel} 227130803Smarcel 228130803Smarcel/* Return the MIPS ABI associated with GDBARCH. */ 229130803Smarcelenum mips_abi 230130803Smarcelmips_abi (struct gdbarch *gdbarch) 231130803Smarcel{ 232130803Smarcel return gdbarch_tdep (gdbarch)->mips_abi; 233130803Smarcel} 234130803Smarcel 235130803Smarcelint 236130803Smarcelmips_regsize (struct gdbarch *gdbarch) 237130803Smarcel{ 238130803Smarcel return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word 239130803Smarcel / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); 240130803Smarcel} 241130803Smarcel 242130803Smarcel/* Return the currently configured (or set) saved register size. */ 243130803Smarcel 244130803Smarcelstatic const char *mips_saved_regsize_string = size_auto; 245130803Smarcel 246130803Smarcelstatic unsigned int 247130803Smarcelmips_saved_regsize (struct gdbarch_tdep *tdep) 248130803Smarcel{ 249130803Smarcel if (mips_saved_regsize_string == size_auto) 250130803Smarcel return tdep->mips_default_saved_regsize; 251130803Smarcel else if (mips_saved_regsize_string == size_64) 252130803Smarcel return 8; 253130803Smarcel else /* if (mips_saved_regsize_string == size_32) */ 254130803Smarcel return 4; 255130803Smarcel} 256130803Smarcel 257130803Smarcel/* Functions for setting and testing a bit in a minimal symbol that 258130803Smarcel marks it as 16-bit function. The MSB of the minimal symbol's 259130803Smarcel "info" field is used for this purpose. 260130803Smarcel 261130803Smarcel ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", 262130803Smarcel i.e. refers to a 16-bit function, and sets a "special" bit in a 263130803Smarcel minimal symbol to mark it as a 16-bit function 264130803Smarcel 265130803Smarcel MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ 266130803Smarcel 267130803Smarcelstatic void 268130803Smarcelmips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) 269130803Smarcel{ 270130803Smarcel if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) 271130803Smarcel { 272130803Smarcel MSYMBOL_INFO (msym) = (char *) 273130803Smarcel (((long) MSYMBOL_INFO (msym)) | 0x80000000); 274130803Smarcel SYMBOL_VALUE_ADDRESS (msym) |= 1; 275130803Smarcel } 276130803Smarcel} 277130803Smarcel 278130803Smarcelstatic int 279130803Smarcelmsymbol_is_special (struct minimal_symbol *msym) 280130803Smarcel{ 281130803Smarcel return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); 282130803Smarcel} 283130803Smarcel 284130803Smarcel/* XFER a value from the big/little/left end of the register. 285130803Smarcel Depending on the size of the value it might occupy the entire 286130803Smarcel register or just part of it. Make an allowance for this, aligning 287130803Smarcel things accordingly. */ 288130803Smarcel 289130803Smarcelstatic void 290130803Smarcelmips_xfer_register (struct regcache *regcache, int reg_num, int length, 291130803Smarcel enum bfd_endian endian, bfd_byte * in, 292130803Smarcel const bfd_byte * out, int buf_offset) 293130803Smarcel{ 294130803Smarcel int reg_offset = 0; 295130803Smarcel gdb_assert (reg_num >= NUM_REGS); 296130803Smarcel /* Need to transfer the left or right part of the register, based on 297130803Smarcel the targets byte order. */ 298130803Smarcel switch (endian) 299130803Smarcel { 300130803Smarcel case BFD_ENDIAN_BIG: 301130803Smarcel reg_offset = register_size (current_gdbarch, reg_num) - length; 302130803Smarcel break; 303130803Smarcel case BFD_ENDIAN_LITTLE: 304130803Smarcel reg_offset = 0; 305130803Smarcel break; 306130803Smarcel case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ 307130803Smarcel reg_offset = 0; 308130803Smarcel break; 309130803Smarcel default: 310130803Smarcel internal_error (__FILE__, __LINE__, "bad switch"); 311130803Smarcel } 312130803Smarcel if (mips_debug) 313130803Smarcel fprintf_unfiltered (gdb_stderr, 314130803Smarcel "xfer $%d, reg offset %d, buf offset %d, length %d, ", 315130803Smarcel reg_num, reg_offset, buf_offset, length); 316130803Smarcel if (mips_debug && out != NULL) 317130803Smarcel { 318130803Smarcel int i; 319130803Smarcel fprintf_unfiltered (gdb_stdlog, "out "); 320130803Smarcel for (i = 0; i < length; i++) 321130803Smarcel fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); 322130803Smarcel } 323130803Smarcel if (in != NULL) 324130803Smarcel regcache_cooked_read_part (regcache, reg_num, reg_offset, length, 325130803Smarcel in + buf_offset); 326130803Smarcel if (out != NULL) 327130803Smarcel regcache_cooked_write_part (regcache, reg_num, reg_offset, length, 328130803Smarcel out + buf_offset); 329130803Smarcel if (mips_debug && in != NULL) 330130803Smarcel { 331130803Smarcel int i; 332130803Smarcel fprintf_unfiltered (gdb_stdlog, "in "); 333130803Smarcel for (i = 0; i < length; i++) 334130803Smarcel fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); 335130803Smarcel } 336130803Smarcel if (mips_debug) 337130803Smarcel fprintf_unfiltered (gdb_stdlog, "\n"); 338130803Smarcel} 339130803Smarcel 340130803Smarcel/* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU 341130803Smarcel compatiblity mode. A return value of 1 means that we have 342130803Smarcel physical 64-bit registers, but should treat them as 32-bit registers. */ 343130803Smarcel 344130803Smarcelstatic int 345130803Smarcelmips2_fp_compat (void) 346130803Smarcel{ 347130803Smarcel /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not 348130803Smarcel meaningful. */ 349130803Smarcel if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 350130803Smarcel 4) 351130803Smarcel return 0; 352130803Smarcel 353130803Smarcel#if 0 354130803Smarcel /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, 355130803Smarcel in all the places we deal with FP registers. PR gdb/413. */ 356130803Smarcel /* Otherwise check the FR bit in the status register - it controls 357130803Smarcel the FP compatiblity mode. If it is clear we are in compatibility 358130803Smarcel mode. */ 359130803Smarcel if ((read_register (PS_REGNUM) & ST0_FR) == 0) 360130803Smarcel return 1; 361130803Smarcel#endif 362130803Smarcel 363130803Smarcel return 0; 364130803Smarcel} 365130803Smarcel 366130803Smarcel/* Indicate that the ABI makes use of double-precision registers 367130803Smarcel provided by the FPU (rather than combining pairs of registers to 368130803Smarcel form double-precision values). See also MIPS_FPU_TYPE. */ 369130803Smarcel#define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) 370130803Smarcel 371130803Smarcel/* The amount of space reserved on the stack for registers. This is 372130803Smarcel different to MIPS_SAVED_REGSIZE as it determines the alignment of 373130803Smarcel data allocated after the registers have run out. */ 374130803Smarcel 375130803Smarcelstatic const char *mips_stack_argsize_string = size_auto; 376130803Smarcel 377130803Smarcelstatic unsigned int 378130803Smarcelmips_stack_argsize (struct gdbarch_tdep *tdep) 379130803Smarcel{ 380130803Smarcel if (mips_stack_argsize_string == size_auto) 381130803Smarcel return tdep->mips_default_stack_argsize; 382130803Smarcel else if (mips_stack_argsize_string == size_64) 383130803Smarcel return 8; 384130803Smarcel else /* if (mips_stack_argsize_string == size_32) */ 385130803Smarcel return 4; 386130803Smarcel} 387130803Smarcel 388130803Smarcel#define VM_MIN_ADDRESS (CORE_ADDR)0x400000 389130803Smarcel 390130803Smarcelstatic mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, 391130803Smarcel struct frame_info *, int); 392130803Smarcel 393130803Smarcelstatic CORE_ADDR heuristic_proc_start (CORE_ADDR); 394130803Smarcel 395130803Smarcelstatic CORE_ADDR read_next_frame_reg (struct frame_info *, int); 396130803Smarcel 397130803Smarcelstatic void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); 398130803Smarcel 399130803Smarcelstatic mips_extra_func_info_t find_proc_desc (CORE_ADDR pc, 400130803Smarcel struct frame_info *next_frame, 401130803Smarcel int cur_frame); 402130803Smarcel 403130803Smarcelstatic CORE_ADDR after_prologue (CORE_ADDR pc, 404130803Smarcel mips_extra_func_info_t proc_desc); 405130803Smarcel 406130803Smarcelstatic struct type *mips_float_register_type (void); 407130803Smarcelstatic struct type *mips_double_register_type (void); 408130803Smarcel 409130803Smarcel/* The list of available "set mips " and "show mips " commands */ 410130803Smarcel 411130803Smarcelstatic struct cmd_list_element *setmipscmdlist = NULL; 412130803Smarcelstatic struct cmd_list_element *showmipscmdlist = NULL; 413130803Smarcel 414130803Smarcel/* Integer registers 0 thru 31 are handled explicitly by 415130803Smarcel mips_register_name(). Processor specific registers 32 and above 416130803Smarcel are listed in the followign tables. */ 417130803Smarcel 418130803Smarcelenum 419130803Smarcel{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; 420130803Smarcel 421130803Smarcel/* Generic MIPS. */ 422130803Smarcel 423130803Smarcelstatic const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 424130803Smarcel "sr", "lo", "hi", "bad", "cause", "pc", 425130803Smarcel "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 426130803Smarcel "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 427130803Smarcel "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 428130803Smarcel "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 429130803Smarcel "fsr", "fir", "" /*"fp" */ , "", 430130803Smarcel "", "", "", "", "", "", "", "", 431130803Smarcel "", "", "", "", "", "", "", "", 432130803Smarcel}; 433130803Smarcel 434130803Smarcel/* Names of IDT R3041 registers. */ 435130803Smarcel 436130803Smarcelstatic const char *mips_r3041_reg_names[] = { 437130803Smarcel "sr", "lo", "hi", "bad", "cause", "pc", 438130803Smarcel "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 439130803Smarcel "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 440130803Smarcel "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 441130803Smarcel "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 442130803Smarcel "fsr", "fir", "", /*"fp" */ "", 443130803Smarcel "", "", "bus", "ccfg", "", "", "", "", 444130803Smarcel "", "", "port", "cmp", "", "", "epc", "prid", 445130803Smarcel}; 446130803Smarcel 447130803Smarcel/* Names of tx39 registers. */ 448130803Smarcel 449130803Smarcelstatic const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 450130803Smarcel "sr", "lo", "hi", "bad", "cause", "pc", 451130803Smarcel "", "", "", "", "", "", "", "", 452130803Smarcel "", "", "", "", "", "", "", "", 453130803Smarcel "", "", "", "", "", "", "", "", 454130803Smarcel "", "", "", "", "", "", "", "", 455130803Smarcel "", "", "", "", 456130803Smarcel "", "", "", "", "", "", "", "", 457130803Smarcel "", "", "config", "cache", "debug", "depc", "epc", "" 458130803Smarcel}; 459130803Smarcel 460130803Smarcel/* Names of IRIX registers. */ 461130803Smarcelstatic const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 462130803Smarcel "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 463130803Smarcel "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 464130803Smarcel "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 465130803Smarcel "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 466130803Smarcel "pc", "cause", "bad", "hi", "lo", "fsr", "fir" 467130803Smarcel}; 468130803Smarcel 469130803Smarcel 470130803Smarcel/* Return the name of the register corresponding to REGNO. */ 471130803Smarcelstatic const char * 472130803Smarcelmips_register_name (int regno) 473130803Smarcel{ 474130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 475130803Smarcel /* GPR names for all ABIs other than n32/n64. */ 476130803Smarcel static char *mips_gpr_names[] = { 477130803Smarcel "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 478130803Smarcel "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 479130803Smarcel "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 480130803Smarcel "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 481130803Smarcel }; 482130803Smarcel 483130803Smarcel /* GPR names for n32 and n64 ABIs. */ 484130803Smarcel static char *mips_n32_n64_gpr_names[] = { 485130803Smarcel "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 486130803Smarcel "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 487130803Smarcel "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 488130803Smarcel "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 489130803Smarcel }; 490130803Smarcel 491130803Smarcel enum mips_abi abi = mips_abi (current_gdbarch); 492130803Smarcel 493130803Smarcel /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then 494130803Smarcel don't make the raw register names visible. */ 495130803Smarcel int rawnum = regno % NUM_REGS; 496130803Smarcel if (regno < NUM_REGS) 497130803Smarcel return ""; 498130803Smarcel 499130803Smarcel /* The MIPS integer registers are always mapped from 0 to 31. The 500130803Smarcel names of the registers (which reflects the conventions regarding 501130803Smarcel register use) vary depending on the ABI. */ 502130803Smarcel if (0 <= rawnum && rawnum < 32) 503130803Smarcel { 504130803Smarcel if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) 505130803Smarcel return mips_n32_n64_gpr_names[rawnum]; 506130803Smarcel else 507130803Smarcel return mips_gpr_names[rawnum]; 508130803Smarcel } 509130803Smarcel else if (32 <= rawnum && rawnum < NUM_REGS) 510130803Smarcel { 511130803Smarcel gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); 512130803Smarcel return tdep->mips_processor_reg_names[rawnum - 32]; 513130803Smarcel } 514130803Smarcel else 515130803Smarcel internal_error (__FILE__, __LINE__, 516130803Smarcel "mips_register_name: bad register number %d", rawnum); 517130803Smarcel} 518130803Smarcel 519130803Smarcel/* Return the groups that a MIPS register can be categorised into. */ 520130803Smarcel 521130803Smarcelstatic int 522130803Smarcelmips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 523130803Smarcel struct reggroup *reggroup) 524130803Smarcel{ 525130803Smarcel int vector_p; 526130803Smarcel int float_p; 527130803Smarcel int raw_p; 528130803Smarcel int rawnum = regnum % NUM_REGS; 529130803Smarcel int pseudo = regnum / NUM_REGS; 530130803Smarcel if (reggroup == all_reggroup) 531130803Smarcel return pseudo; 532130803Smarcel vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); 533130803Smarcel float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; 534130803Smarcel /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs 535130803Smarcel (gdbarch), as not all architectures are multi-arch. */ 536130803Smarcel raw_p = rawnum < NUM_REGS; 537130803Smarcel if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') 538130803Smarcel return 0; 539130803Smarcel if (reggroup == float_reggroup) 540130803Smarcel return float_p && pseudo; 541130803Smarcel if (reggroup == vector_reggroup) 542130803Smarcel return vector_p && pseudo; 543130803Smarcel if (reggroup == general_reggroup) 544130803Smarcel return (!vector_p && !float_p) && pseudo; 545130803Smarcel /* Save the pseudo registers. Need to make certain that any code 546130803Smarcel extracting register values from a saved register cache also uses 547130803Smarcel pseudo registers. */ 548130803Smarcel if (reggroup == save_reggroup) 549130803Smarcel return raw_p && pseudo; 550130803Smarcel /* Restore the same pseudo register. */ 551130803Smarcel if (reggroup == restore_reggroup) 552130803Smarcel return raw_p && pseudo; 553130803Smarcel return 0; 554130803Smarcel} 555130803Smarcel 556130803Smarcel/* Map the symbol table registers which live in the range [1 * 557130803Smarcel NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw 558130803Smarcel registers. Take care of alignment and size problems. */ 559130803Smarcel 560130803Smarcelstatic void 561130803Smarcelmips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 562130803Smarcel int cookednum, void *buf) 563130803Smarcel{ 564130803Smarcel int rawnum = cookednum % NUM_REGS; 565130803Smarcel gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); 566130803Smarcel if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 567130803Smarcel regcache_raw_read (regcache, rawnum, buf); 568130803Smarcel else if (register_size (gdbarch, rawnum) > 569130803Smarcel register_size (gdbarch, cookednum)) 570130803Smarcel { 571130803Smarcel if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p 572130803Smarcel || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) 573130803Smarcel regcache_raw_read_part (regcache, rawnum, 0, 4, buf); 574130803Smarcel else 575130803Smarcel regcache_raw_read_part (regcache, rawnum, 4, 4, buf); 576130803Smarcel } 577130803Smarcel else 578130803Smarcel internal_error (__FILE__, __LINE__, "bad register size"); 579130803Smarcel} 580130803Smarcel 581130803Smarcelstatic void 582130803Smarcelmips_pseudo_register_write (struct gdbarch *gdbarch, 583130803Smarcel struct regcache *regcache, int cookednum, 584130803Smarcel const void *buf) 585130803Smarcel{ 586130803Smarcel int rawnum = cookednum % NUM_REGS; 587130803Smarcel gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); 588130803Smarcel if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 589130803Smarcel regcache_raw_write (regcache, rawnum, buf); 590130803Smarcel else if (register_size (gdbarch, rawnum) > 591130803Smarcel register_size (gdbarch, cookednum)) 592130803Smarcel { 593130803Smarcel if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p 594130803Smarcel || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) 595130803Smarcel regcache_raw_write_part (regcache, rawnum, 0, 4, buf); 596130803Smarcel else 597130803Smarcel regcache_raw_write_part (regcache, rawnum, 4, 4, buf); 598130803Smarcel } 599130803Smarcel else 600130803Smarcel internal_error (__FILE__, __LINE__, "bad register size"); 601130803Smarcel} 602130803Smarcel 603130803Smarcel/* Table to translate MIPS16 register field to actual register number. */ 604130803Smarcelstatic int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 605130803Smarcel 606130803Smarcel/* Heuristic_proc_start may hunt through the text section for a long 607130803Smarcel time across a 2400 baud serial line. Allows the user to limit this 608130803Smarcel search. */ 609130803Smarcel 610130803Smarcelstatic unsigned int heuristic_fence_post = 0; 611130803Smarcel 612130803Smarcel#define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ 613130803Smarcel#define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ 614130803Smarcel#define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) 615130803Smarcel#define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) 616130803Smarcel#define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) 617130803Smarcel#define PROC_REG_MASK(proc) ((proc)->pdr.regmask) 618130803Smarcel#define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) 619130803Smarcel#define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) 620130803Smarcel#define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) 621130803Smarcel#define PROC_PC_REG(proc) ((proc)->pdr.pcreg) 622130803Smarcel/* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, 623130803Smarcel this will corrupt pdr.iline. Fortunately we don't use it. */ 624130803Smarcel#define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) 625130803Smarcel#define _PROC_MAGIC_ 0x0F0F0F0F 626130803Smarcel#define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) 627130803Smarcel#define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) 628130803Smarcel 629130803Smarcelstruct linked_proc_info 630130803Smarcel{ 631130803Smarcel struct mips_extra_func_info info; 632130803Smarcel struct linked_proc_info *next; 633130803Smarcel} 634130803Smarcel *linked_proc_desc_table = NULL; 635130803Smarcel 636130803Smarcel/* Number of bytes of storage in the actual machine representation for 637130803Smarcel register N. NOTE: This defines the pseudo register type so need to 638130803Smarcel rebuild the architecture vector. */ 639130803Smarcel 640130803Smarcelstatic int mips64_transfers_32bit_regs_p = 0; 641130803Smarcel 642130803Smarcelstatic void 643130803Smarcelset_mips64_transfers_32bit_regs (char *args, int from_tty, 644130803Smarcel struct cmd_list_element *c) 645130803Smarcel{ 646130803Smarcel struct gdbarch_info info; 647130803Smarcel gdbarch_info_init (&info); 648130803Smarcel /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 649130803Smarcel instead of relying on globals. Doing that would let generic code 650130803Smarcel handle the search for this specific architecture. */ 651130803Smarcel if (!gdbarch_update_p (info)) 652130803Smarcel { 653130803Smarcel mips64_transfers_32bit_regs_p = 0; 654130803Smarcel error ("32-bit compatibility mode not supported"); 655130803Smarcel } 656130803Smarcel} 657130803Smarcel 658130803Smarcel/* Convert to/from a register and the corresponding memory value. */ 659130803Smarcel 660130803Smarcelstatic int 661130803Smarcelmips_convert_register_p (int regnum, struct type *type) 662130803Smarcel{ 663130803Smarcel return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 664130803Smarcel && register_size (current_gdbarch, regnum) == 4 665130803Smarcel && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 666130803Smarcel && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 667130803Smarcel && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); 668130803Smarcel} 669130803Smarcel 670130803Smarcelstatic void 671130803Smarcelmips_register_to_value (struct frame_info *frame, int regnum, 672130803Smarcel struct type *type, void *to) 673130803Smarcel{ 674130803Smarcel get_frame_register (frame, regnum + 0, (char *) to + 4); 675130803Smarcel get_frame_register (frame, regnum + 1, (char *) to + 0); 676130803Smarcel} 677130803Smarcel 678130803Smarcelstatic void 679130803Smarcelmips_value_to_register (struct frame_info *frame, int regnum, 680130803Smarcel struct type *type, const void *from) 681130803Smarcel{ 682130803Smarcel put_frame_register (frame, regnum + 0, (const char *) from + 4); 683130803Smarcel put_frame_register (frame, regnum + 1, (const char *) from + 0); 684130803Smarcel} 685130803Smarcel 686130803Smarcel/* Return the GDB type object for the "standard" data type of data in 687130803Smarcel register REG. */ 688130803Smarcel 689130803Smarcelstatic struct type * 690130803Smarcelmips_register_type (struct gdbarch *gdbarch, int regnum) 691130803Smarcel{ 692130803Smarcel gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); 693130803Smarcel if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 694130803Smarcel && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) 695130803Smarcel { 696130803Smarcel /* The floating-point registers raw, or cooked, always match 697130803Smarcel mips_regsize(), and also map 1:1, byte for byte. */ 698130803Smarcel switch (gdbarch_byte_order (gdbarch)) 699130803Smarcel { 700130803Smarcel case BFD_ENDIAN_BIG: 701130803Smarcel if (mips_regsize (gdbarch) == 4) 702130803Smarcel return builtin_type_ieee_single_big; 703130803Smarcel else 704130803Smarcel return builtin_type_ieee_double_big; 705130803Smarcel case BFD_ENDIAN_LITTLE: 706130803Smarcel if (mips_regsize (gdbarch) == 4) 707130803Smarcel return builtin_type_ieee_single_little; 708130803Smarcel else 709130803Smarcel return builtin_type_ieee_double_little; 710130803Smarcel case BFD_ENDIAN_UNKNOWN: 711130803Smarcel default: 712130803Smarcel internal_error (__FILE__, __LINE__, "bad switch"); 713130803Smarcel } 714130803Smarcel } 715130803Smarcel else if (regnum >= 716130803Smarcel (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status) 717130803Smarcel && regnum <= NUM_REGS + LAST_EMBED_REGNUM) 718130803Smarcel /* The pseudo/cooked view of the embedded registers is always 719130803Smarcel 32-bit. The raw view is handled below. */ 720130803Smarcel return builtin_type_int32; 721130803Smarcel else if (regnum >= NUM_REGS && mips_regsize (gdbarch) 722130803Smarcel && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 723130803Smarcel /* The target, while using a 64-bit register buffer, is only 724130803Smarcel transfering 32-bits of each integer register. Reflect this in 725130803Smarcel the cooked/pseudo register value. */ 726130803Smarcel return builtin_type_int32; 727130803Smarcel else if (mips_regsize (gdbarch) == 8) 728130803Smarcel /* 64-bit ISA. */ 729130803Smarcel return builtin_type_int64; 730130803Smarcel else 731130803Smarcel /* 32-bit ISA. */ 732130803Smarcel return builtin_type_int32; 733130803Smarcel} 734130803Smarcel 735130803Smarcel/* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ 736130803Smarcel 737130803Smarcelstatic CORE_ADDR 738130803Smarcelmips_read_sp (void) 739130803Smarcel{ 740130803Smarcel return read_signed_register (SP_REGNUM); 741130803Smarcel} 742130803Smarcel 743130803Smarcel/* Should the upper word of 64-bit addresses be zeroed? */ 744130803Smarcelenum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; 745130803Smarcel 746130803Smarcelstatic int 747130803Smarcelmips_mask_address_p (struct gdbarch_tdep *tdep) 748130803Smarcel{ 749130803Smarcel switch (mask_address_var) 750130803Smarcel { 751130803Smarcel case AUTO_BOOLEAN_TRUE: 752130803Smarcel return 1; 753130803Smarcel case AUTO_BOOLEAN_FALSE: 754130803Smarcel return 0; 755130803Smarcel break; 756130803Smarcel case AUTO_BOOLEAN_AUTO: 757130803Smarcel return tdep->default_mask_address_p; 758130803Smarcel default: 759130803Smarcel internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); 760130803Smarcel return -1; 761130803Smarcel } 762130803Smarcel} 763130803Smarcel 764130803Smarcelstatic void 765130803Smarcelshow_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) 766130803Smarcel{ 767130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 768130803Smarcel switch (mask_address_var) 769130803Smarcel { 770130803Smarcel case AUTO_BOOLEAN_TRUE: 771130803Smarcel printf_filtered ("The 32 bit mips address mask is enabled\n"); 772130803Smarcel break; 773130803Smarcel case AUTO_BOOLEAN_FALSE: 774130803Smarcel printf_filtered ("The 32 bit mips address mask is disabled\n"); 775130803Smarcel break; 776130803Smarcel case AUTO_BOOLEAN_AUTO: 777130803Smarcel printf_filtered 778130803Smarcel ("The 32 bit address mask is set automatically. Currently %s\n", 779130803Smarcel mips_mask_address_p (tdep) ? "enabled" : "disabled"); 780130803Smarcel break; 781130803Smarcel default: 782130803Smarcel internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); 783130803Smarcel break; 784130803Smarcel } 785130803Smarcel} 786130803Smarcel 787130803Smarcel/* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ 788130803Smarcel 789130803Smarcelstatic int 790130803Smarcelpc_is_mips16 (bfd_vma memaddr) 791130803Smarcel{ 792130803Smarcel struct minimal_symbol *sym; 793130803Smarcel 794130803Smarcel /* If bit 0 of the address is set, assume this is a MIPS16 address. */ 795130803Smarcel if (is_mips16_addr (memaddr)) 796130803Smarcel return 1; 797130803Smarcel 798130803Smarcel /* A flag indicating that this is a MIPS16 function is stored by elfread.c in 799130803Smarcel the high bit of the info field. Use this to decide if the function is 800130803Smarcel MIPS16 or normal MIPS. */ 801130803Smarcel sym = lookup_minimal_symbol_by_pc (memaddr); 802130803Smarcel if (sym) 803130803Smarcel return msymbol_is_special (sym); 804130803Smarcel else 805130803Smarcel return 0; 806130803Smarcel} 807130803Smarcel 808130803Smarcel/* MIPS believes that the PC has a sign extended value. Perhaphs the 809130803Smarcel all registers should be sign extended for simplicity? */ 810130803Smarcel 811130803Smarcelstatic CORE_ADDR 812130803Smarcelmips_read_pc (ptid_t ptid) 813130803Smarcel{ 814130803Smarcel return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); 815130803Smarcel} 816130803Smarcel 817130803Smarcelstatic CORE_ADDR 818130803Smarcelmips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 819130803Smarcel{ 820130803Smarcel return frame_unwind_register_signed (next_frame, 821130803Smarcel NUM_REGS + mips_regnum (gdbarch)->pc); 822130803Smarcel} 823130803Smarcel 824130803Smarcel/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 825130803Smarcel dummy frame. The frame ID's base needs to match the TOS value 826130803Smarcel saved by save_dummy_frame_tos(), and the PC match the dummy frame's 827130803Smarcel breakpoint. */ 828130803Smarcel 829130803Smarcelstatic struct frame_id 830130803Smarcelmips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 831130803Smarcel{ 832130803Smarcel return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + SP_REGNUM), 833130803Smarcel frame_pc_unwind (next_frame)); 834130803Smarcel} 835130803Smarcel 836130803Smarcelstatic void 837130803Smarcelmips_write_pc (CORE_ADDR pc, ptid_t ptid) 838130803Smarcel{ 839130803Smarcel write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); 840130803Smarcel} 841130803Smarcel 842130803Smarcel/* This returns the PC of the first inst after the prologue. If we can't 843130803Smarcel find the prologue, then return 0. */ 844130803Smarcel 845130803Smarcelstatic CORE_ADDR 846130803Smarcelafter_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc) 847130803Smarcel{ 848130803Smarcel struct symtab_and_line sal; 849130803Smarcel CORE_ADDR func_addr, func_end; 850130803Smarcel 851130803Smarcel /* Pass cur_frame == 0 to find_proc_desc. We should not attempt 852130803Smarcel to read the stack pointer from the current machine state, because 853130803Smarcel the current machine state has nothing to do with the information 854130803Smarcel we need from the proc_desc; and the process may or may not exist 855130803Smarcel right now. */ 856130803Smarcel if (!proc_desc) 857130803Smarcel proc_desc = find_proc_desc (pc, NULL, 0); 858130803Smarcel 859130803Smarcel if (proc_desc) 860130803Smarcel { 861130803Smarcel /* If function is frameless, then we need to do it the hard way. I 862130803Smarcel strongly suspect that frameless always means prologueless... */ 863130803Smarcel if (PROC_FRAME_REG (proc_desc) == SP_REGNUM 864130803Smarcel && PROC_FRAME_OFFSET (proc_desc) == 0) 865130803Smarcel return 0; 866130803Smarcel } 867130803Smarcel 868130803Smarcel if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 869130803Smarcel return 0; /* Unknown */ 870130803Smarcel 871130803Smarcel sal = find_pc_line (func_addr, 0); 872130803Smarcel 873130803Smarcel if (sal.end < func_end) 874130803Smarcel return sal.end; 875130803Smarcel 876130803Smarcel /* The line after the prologue is after the end of the function. In this 877130803Smarcel case, tell the caller to find the prologue the hard way. */ 878130803Smarcel 879130803Smarcel return 0; 880130803Smarcel} 881130803Smarcel 882130803Smarcel/* Decode a MIPS32 instruction that saves a register in the stack, and 883130803Smarcel set the appropriate bit in the general register mask or float register mask 884130803Smarcel to indicate which register is saved. This is a helper function 885130803Smarcel for mips_find_saved_regs. */ 886130803Smarcel 887130803Smarcelstatic void 888130803Smarcelmips32_decode_reg_save (t_inst inst, unsigned long *gen_mask, 889130803Smarcel unsigned long *float_mask) 890130803Smarcel{ 891130803Smarcel int reg; 892130803Smarcel 893130803Smarcel if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ 894130803Smarcel || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ 895130803Smarcel || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ 896130803Smarcel { 897130803Smarcel /* It might be possible to use the instruction to 898130803Smarcel find the offset, rather than the code below which 899130803Smarcel is based on things being in a certain order in the 900130803Smarcel frame, but figuring out what the instruction's offset 901130803Smarcel is relative to might be a little tricky. */ 902130803Smarcel reg = (inst & 0x001f0000) >> 16; 903130803Smarcel *gen_mask |= (1 << reg); 904130803Smarcel } 905130803Smarcel else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ 906130803Smarcel || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ 907130803Smarcel || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ 908130803Smarcel 909130803Smarcel { 910130803Smarcel reg = ((inst & 0x001f0000) >> 16); 911130803Smarcel *float_mask |= (1 << reg); 912130803Smarcel } 913130803Smarcel} 914130803Smarcel 915130803Smarcel/* Decode a MIPS16 instruction that saves a register in the stack, and 916130803Smarcel set the appropriate bit in the general register or float register mask 917130803Smarcel to indicate which register is saved. This is a helper function 918130803Smarcel for mips_find_saved_regs. */ 919130803Smarcel 920130803Smarcelstatic void 921130803Smarcelmips16_decode_reg_save (t_inst inst, unsigned long *gen_mask) 922130803Smarcel{ 923130803Smarcel if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ 924130803Smarcel { 925130803Smarcel int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; 926130803Smarcel *gen_mask |= (1 << reg); 927130803Smarcel } 928130803Smarcel else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ 929130803Smarcel { 930130803Smarcel int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; 931130803Smarcel *gen_mask |= (1 << reg); 932130803Smarcel } 933130803Smarcel else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ 934130803Smarcel || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ 935130803Smarcel *gen_mask |= (1 << RA_REGNUM); 936130803Smarcel} 937130803Smarcel 938130803Smarcel 939130803Smarcel/* Fetch and return instruction from the specified location. If the PC 940130803Smarcel is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ 941130803Smarcel 942130803Smarcelstatic t_inst 943130803Smarcelmips_fetch_instruction (CORE_ADDR addr) 944130803Smarcel{ 945130803Smarcel char buf[MIPS_INSTLEN]; 946130803Smarcel int instlen; 947130803Smarcel int status; 948130803Smarcel 949130803Smarcel if (pc_is_mips16 (addr)) 950130803Smarcel { 951130803Smarcel instlen = MIPS16_INSTLEN; 952130803Smarcel addr = unmake_mips16_addr (addr); 953130803Smarcel } 954130803Smarcel else 955130803Smarcel instlen = MIPS_INSTLEN; 956130803Smarcel status = read_memory_nobpt (addr, buf, instlen); 957130803Smarcel if (status) 958130803Smarcel memory_error (status, addr); 959130803Smarcel return extract_unsigned_integer (buf, instlen); 960130803Smarcel} 961130803Smarcel 962130803Smarcelstatic ULONGEST 963130803Smarcelmips16_fetch_instruction (CORE_ADDR addr) 964130803Smarcel{ 965130803Smarcel char buf[MIPS_INSTLEN]; 966130803Smarcel int instlen; 967130803Smarcel int status; 968130803Smarcel 969130803Smarcel instlen = MIPS16_INSTLEN; 970130803Smarcel addr = unmake_mips16_addr (addr); 971130803Smarcel status = read_memory_nobpt (addr, buf, instlen); 972130803Smarcel if (status) 973130803Smarcel memory_error (status, addr); 974130803Smarcel return extract_unsigned_integer (buf, instlen); 975130803Smarcel} 976130803Smarcel 977130803Smarcelstatic ULONGEST 978130803Smarcelmips32_fetch_instruction (CORE_ADDR addr) 979130803Smarcel{ 980130803Smarcel char buf[MIPS_INSTLEN]; 981130803Smarcel int instlen; 982130803Smarcel int status; 983130803Smarcel instlen = MIPS_INSTLEN; 984130803Smarcel status = read_memory_nobpt (addr, buf, instlen); 985130803Smarcel if (status) 986130803Smarcel memory_error (status, addr); 987130803Smarcel return extract_unsigned_integer (buf, instlen); 988130803Smarcel} 989130803Smarcel 990130803Smarcel 991130803Smarcel/* These the fields of 32 bit mips instructions */ 992130803Smarcel#define mips32_op(x) (x >> 26) 993130803Smarcel#define itype_op(x) (x >> 26) 994130803Smarcel#define itype_rs(x) ((x >> 21) & 0x1f) 995130803Smarcel#define itype_rt(x) ((x >> 16) & 0x1f) 996130803Smarcel#define itype_immediate(x) (x & 0xffff) 997130803Smarcel 998130803Smarcel#define jtype_op(x) (x >> 26) 999130803Smarcel#define jtype_target(x) (x & 0x03ffffff) 1000130803Smarcel 1001130803Smarcel#define rtype_op(x) (x >> 26) 1002130803Smarcel#define rtype_rs(x) ((x >> 21) & 0x1f) 1003130803Smarcel#define rtype_rt(x) ((x >> 16) & 0x1f) 1004130803Smarcel#define rtype_rd(x) ((x >> 11) & 0x1f) 1005130803Smarcel#define rtype_shamt(x) ((x >> 6) & 0x1f) 1006130803Smarcel#define rtype_funct(x) (x & 0x3f) 1007130803Smarcel 1008130803Smarcelstatic CORE_ADDR 1009130803Smarcelmips32_relative_offset (unsigned long inst) 1010130803Smarcel{ 1011130803Smarcel long x; 1012130803Smarcel x = itype_immediate (inst); 1013130803Smarcel if (x & 0x8000) /* sign bit set */ 1014130803Smarcel { 1015130803Smarcel x |= 0xffff0000; /* sign extension */ 1016130803Smarcel } 1017130803Smarcel x = x << 2; 1018130803Smarcel return x; 1019130803Smarcel} 1020130803Smarcel 1021130803Smarcel/* Determine whate to set a single step breakpoint while considering 1022130803Smarcel branch prediction */ 1023130803Smarcelstatic CORE_ADDR 1024130803Smarcelmips32_next_pc (CORE_ADDR pc) 1025130803Smarcel{ 1026130803Smarcel unsigned long inst; 1027130803Smarcel int op; 1028130803Smarcel inst = mips_fetch_instruction (pc); 1029130803Smarcel if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ 1030130803Smarcel { 1031130803Smarcel if (itype_op (inst) >> 2 == 5) 1032130803Smarcel /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 1033130803Smarcel { 1034130803Smarcel op = (itype_op (inst) & 0x03); 1035130803Smarcel switch (op) 1036130803Smarcel { 1037130803Smarcel case 0: /* BEQL */ 1038130803Smarcel goto equal_branch; 1039130803Smarcel case 1: /* BNEL */ 1040130803Smarcel goto neq_branch; 1041130803Smarcel case 2: /* BLEZL */ 1042130803Smarcel goto less_branch; 1043130803Smarcel case 3: /* BGTZ */ 1044130803Smarcel goto greater_branch; 1045130803Smarcel default: 1046130803Smarcel pc += 4; 1047130803Smarcel } 1048130803Smarcel } 1049130803Smarcel else if (itype_op (inst) == 17 && itype_rs (inst) == 8) 1050130803Smarcel /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 1051130803Smarcel { 1052130803Smarcel int tf = itype_rt (inst) & 0x01; 1053130803Smarcel int cnum = itype_rt (inst) >> 2; 1054130803Smarcel int fcrcs = 1055130803Smarcel read_signed_register (mips_regnum (current_gdbarch)-> 1056130803Smarcel fp_control_status); 1057130803Smarcel int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); 1058130803Smarcel 1059130803Smarcel if (((cond >> cnum) & 0x01) == tf) 1060130803Smarcel pc += mips32_relative_offset (inst) + 4; 1061130803Smarcel else 1062130803Smarcel pc += 8; 1063130803Smarcel } 1064130803Smarcel else 1065130803Smarcel pc += 4; /* Not a branch, next instruction is easy */ 1066130803Smarcel } 1067130803Smarcel else 1068130803Smarcel { /* This gets way messy */ 1069130803Smarcel 1070130803Smarcel /* Further subdivide into SPECIAL, REGIMM and other */ 1071130803Smarcel switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ 1072130803Smarcel { 1073130803Smarcel case 0: /* SPECIAL */ 1074130803Smarcel op = rtype_funct (inst); 1075130803Smarcel switch (op) 1076130803Smarcel { 1077130803Smarcel case 8: /* JR */ 1078130803Smarcel case 9: /* JALR */ 1079130803Smarcel /* Set PC to that address */ 1080130803Smarcel pc = read_signed_register (rtype_rs (inst)); 1081130803Smarcel break; 1082130803Smarcel default: 1083130803Smarcel pc += 4; 1084130803Smarcel } 1085130803Smarcel 1086130803Smarcel break; /* end SPECIAL */ 1087130803Smarcel case 1: /* REGIMM */ 1088130803Smarcel { 1089130803Smarcel op = itype_rt (inst); /* branch condition */ 1090130803Smarcel switch (op) 1091130803Smarcel { 1092130803Smarcel case 0: /* BLTZ */ 1093130803Smarcel case 2: /* BLTZL */ 1094130803Smarcel case 16: /* BLTZAL */ 1095130803Smarcel case 18: /* BLTZALL */ 1096130803Smarcel less_branch: 1097130803Smarcel if (read_signed_register (itype_rs (inst)) < 0) 1098130803Smarcel pc += mips32_relative_offset (inst) + 4; 1099130803Smarcel else 1100130803Smarcel pc += 8; /* after the delay slot */ 1101130803Smarcel break; 1102130803Smarcel case 1: /* BGEZ */ 1103130803Smarcel case 3: /* BGEZL */ 1104130803Smarcel case 17: /* BGEZAL */ 1105130803Smarcel case 19: /* BGEZALL */ 1106130803Smarcel if (read_signed_register (itype_rs (inst)) >= 0) 1107130803Smarcel pc += mips32_relative_offset (inst) + 4; 1108130803Smarcel else 1109130803Smarcel pc += 8; /* after the delay slot */ 1110130803Smarcel break; 1111130803Smarcel /* All of the other instructions in the REGIMM category */ 1112130803Smarcel default: 1113130803Smarcel pc += 4; 1114130803Smarcel } 1115130803Smarcel } 1116130803Smarcel break; /* end REGIMM */ 1117130803Smarcel case 2: /* J */ 1118130803Smarcel case 3: /* JAL */ 1119130803Smarcel { 1120130803Smarcel unsigned long reg; 1121130803Smarcel reg = jtype_target (inst) << 2; 1122130803Smarcel /* Upper four bits get never changed... */ 1123130803Smarcel pc = reg + ((pc + 4) & 0xf0000000); 1124130803Smarcel } 1125130803Smarcel break; 1126130803Smarcel /* FIXME case JALX : */ 1127130803Smarcel { 1128130803Smarcel unsigned long reg; 1129130803Smarcel reg = jtype_target (inst) << 2; 1130130803Smarcel pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ 1131130803Smarcel /* Add 1 to indicate 16 bit mode - Invert ISA mode */ 1132130803Smarcel } 1133130803Smarcel break; /* The new PC will be alternate mode */ 1134130803Smarcel case 4: /* BEQ, BEQL */ 1135130803Smarcel equal_branch: 1136130803Smarcel if (read_signed_register (itype_rs (inst)) == 1137130803Smarcel read_signed_register (itype_rt (inst))) 1138130803Smarcel pc += mips32_relative_offset (inst) + 4; 1139130803Smarcel else 1140130803Smarcel pc += 8; 1141130803Smarcel break; 1142130803Smarcel case 5: /* BNE, BNEL */ 1143130803Smarcel neq_branch: 1144130803Smarcel if (read_signed_register (itype_rs (inst)) != 1145130803Smarcel read_signed_register (itype_rt (inst))) 1146130803Smarcel pc += mips32_relative_offset (inst) + 4; 1147130803Smarcel else 1148130803Smarcel pc += 8; 1149130803Smarcel break; 1150130803Smarcel case 6: /* BLEZ, BLEZL */ 1151130803Smarcel if (read_signed_register (itype_rs (inst) <= 0)) 1152130803Smarcel pc += mips32_relative_offset (inst) + 4; 1153130803Smarcel else 1154130803Smarcel pc += 8; 1155130803Smarcel break; 1156130803Smarcel case 7: 1157130803Smarcel default: 1158130803Smarcel greater_branch: /* BGTZ, BGTZL */ 1159130803Smarcel if (read_signed_register (itype_rs (inst) > 0)) 1160130803Smarcel pc += mips32_relative_offset (inst) + 4; 1161130803Smarcel else 1162130803Smarcel pc += 8; 1163130803Smarcel break; 1164130803Smarcel } /* switch */ 1165130803Smarcel } /* else */ 1166130803Smarcel return pc; 1167130803Smarcel} /* mips32_next_pc */ 1168130803Smarcel 1169130803Smarcel/* Decoding the next place to set a breakpoint is irregular for the 1170130803Smarcel mips 16 variant, but fortunately, there fewer instructions. We have to cope 1171130803Smarcel ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. 1172130803Smarcel We dont want to set a single step instruction on the extend instruction 1173130803Smarcel either. 1174130803Smarcel */ 1175130803Smarcel 1176130803Smarcel/* Lots of mips16 instruction formats */ 1177130803Smarcel/* Predicting jumps requires itype,ritype,i8type 1178130803Smarcel and their extensions extItype,extritype,extI8type 1179130803Smarcel */ 1180130803Smarcelenum mips16_inst_fmts 1181130803Smarcel{ 1182130803Smarcel itype, /* 0 immediate 5,10 */ 1183130803Smarcel ritype, /* 1 5,3,8 */ 1184130803Smarcel rrtype, /* 2 5,3,3,5 */ 1185130803Smarcel rritype, /* 3 5,3,3,5 */ 1186130803Smarcel rrrtype, /* 4 5,3,3,3,2 */ 1187130803Smarcel rriatype, /* 5 5,3,3,1,4 */ 1188130803Smarcel shifttype, /* 6 5,3,3,3,2 */ 1189130803Smarcel i8type, /* 7 5,3,8 */ 1190130803Smarcel i8movtype, /* 8 5,3,3,5 */ 1191130803Smarcel i8mov32rtype, /* 9 5,3,5,3 */ 1192130803Smarcel i64type, /* 10 5,3,8 */ 1193130803Smarcel ri64type, /* 11 5,3,3,5 */ 1194130803Smarcel jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ 1195130803Smarcel exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ 1196130803Smarcel extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ 1197130803Smarcel extRRItype, /* 15 5,5,5,5,3,3,5 */ 1198130803Smarcel extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ 1199130803Smarcel EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ 1200130803Smarcel extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ 1201130803Smarcel extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ 1202130803Smarcel extRi64type, /* 20 5,6,5,5,3,3,5 */ 1203130803Smarcel extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ 1204130803Smarcel}; 1205130803Smarcel/* I am heaping all the fields of the formats into one structure and 1206130803Smarcel then, only the fields which are involved in instruction extension */ 1207130803Smarcelstruct upk_mips16 1208130803Smarcel{ 1209130803Smarcel CORE_ADDR offset; 1210130803Smarcel unsigned int regx; /* Function in i8 type */ 1211130803Smarcel unsigned int regy; 1212130803Smarcel}; 1213130803Smarcel 1214130803Smarcel 1215130803Smarcel/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format 1216130803Smarcel for the bits which make up the immediatate extension. */ 1217130803Smarcel 1218130803Smarcelstatic CORE_ADDR 1219130803Smarcelextended_offset (unsigned int extension) 1220130803Smarcel{ 1221130803Smarcel CORE_ADDR value; 1222130803Smarcel value = (extension >> 21) & 0x3f; /* * extract 15:11 */ 1223130803Smarcel value = value << 6; 1224130803Smarcel value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ 1225130803Smarcel value = value << 5; 1226130803Smarcel value |= extension & 0x01f; /* extract 4:0 */ 1227130803Smarcel return value; 1228130803Smarcel} 1229130803Smarcel 1230130803Smarcel/* Only call this function if you know that this is an extendable 1231130803Smarcel instruction, It wont malfunction, but why make excess remote memory references? 1232130803Smarcel If the immediate operands get sign extended or somthing, do it after 1233130803Smarcel the extension is performed. 1234130803Smarcel */ 1235130803Smarcel/* FIXME: Every one of these cases needs to worry about sign extension 1236130803Smarcel when the offset is to be used in relative addressing */ 1237130803Smarcel 1238130803Smarcel 1239130803Smarcelstatic unsigned int 1240130803Smarcelfetch_mips_16 (CORE_ADDR pc) 1241130803Smarcel{ 1242130803Smarcel char buf[8]; 1243130803Smarcel pc &= 0xfffffffe; /* clear the low order bit */ 1244130803Smarcel target_read_memory (pc, buf, 2); 1245130803Smarcel return extract_unsigned_integer (buf, 2); 1246130803Smarcel} 1247130803Smarcel 1248130803Smarcelstatic void 1249130803Smarcelunpack_mips16 (CORE_ADDR pc, 1250130803Smarcel unsigned int extension, 1251130803Smarcel unsigned int inst, 1252130803Smarcel enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) 1253130803Smarcel{ 1254130803Smarcel CORE_ADDR offset; 1255130803Smarcel int regx; 1256130803Smarcel int regy; 1257130803Smarcel switch (insn_format) 1258130803Smarcel { 1259130803Smarcel case itype: 1260130803Smarcel { 1261130803Smarcel CORE_ADDR value; 1262130803Smarcel if (extension) 1263130803Smarcel { 1264130803Smarcel value = extended_offset (extension); 1265130803Smarcel value = value << 11; /* rom for the original value */ 1266130803Smarcel value |= inst & 0x7ff; /* eleven bits from instruction */ 1267130803Smarcel } 1268130803Smarcel else 1269130803Smarcel { 1270130803Smarcel value = inst & 0x7ff; 1271130803Smarcel /* FIXME : Consider sign extension */ 1272130803Smarcel } 1273130803Smarcel offset = value; 1274130803Smarcel regx = -1; 1275130803Smarcel regy = -1; 1276130803Smarcel } 1277130803Smarcel break; 1278130803Smarcel case ritype: 1279130803Smarcel case i8type: 1280130803Smarcel { /* A register identifier and an offset */ 1281130803Smarcel /* Most of the fields are the same as I type but the 1282130803Smarcel immediate value is of a different length */ 1283130803Smarcel CORE_ADDR value; 1284130803Smarcel if (extension) 1285130803Smarcel { 1286130803Smarcel value = extended_offset (extension); 1287130803Smarcel value = value << 8; /* from the original instruction */ 1288130803Smarcel value |= inst & 0xff; /* eleven bits from instruction */ 1289130803Smarcel regx = (extension >> 8) & 0x07; /* or i8 funct */ 1290130803Smarcel if (value & 0x4000) /* test the sign bit , bit 26 */ 1291130803Smarcel { 1292130803Smarcel value &= ~0x3fff; /* remove the sign bit */ 1293130803Smarcel value = -value; 1294130803Smarcel } 1295130803Smarcel } 1296130803Smarcel else 1297130803Smarcel { 1298130803Smarcel value = inst & 0xff; /* 8 bits */ 1299130803Smarcel regx = (inst >> 8) & 0x07; /* or i8 funct */ 1300130803Smarcel /* FIXME: Do sign extension , this format needs it */ 1301130803Smarcel if (value & 0x80) /* THIS CONFUSES ME */ 1302130803Smarcel { 1303130803Smarcel value &= 0xef; /* remove the sign bit */ 1304130803Smarcel value = -value; 1305130803Smarcel } 1306130803Smarcel } 1307130803Smarcel offset = value; 1308130803Smarcel regy = -1; 1309130803Smarcel break; 1310130803Smarcel } 1311130803Smarcel case jalxtype: 1312130803Smarcel { 1313130803Smarcel unsigned long value; 1314130803Smarcel unsigned int nexthalf; 1315130803Smarcel value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); 1316130803Smarcel value = value << 16; 1317130803Smarcel nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ 1318130803Smarcel value |= nexthalf; 1319130803Smarcel offset = value; 1320130803Smarcel regx = -1; 1321130803Smarcel regy = -1; 1322130803Smarcel break; 1323130803Smarcel } 1324130803Smarcel default: 1325130803Smarcel internal_error (__FILE__, __LINE__, "bad switch"); 1326130803Smarcel } 1327130803Smarcel upk->offset = offset; 1328130803Smarcel upk->regx = regx; 1329130803Smarcel upk->regy = regy; 1330130803Smarcel} 1331130803Smarcel 1332130803Smarcel 1333130803Smarcelstatic CORE_ADDR 1334130803Smarceladd_offset_16 (CORE_ADDR pc, int offset) 1335130803Smarcel{ 1336130803Smarcel return ((offset << 2) | ((pc + 2) & (0xf0000000))); 1337130803Smarcel} 1338130803Smarcel 1339130803Smarcelstatic CORE_ADDR 1340130803Smarcelextended_mips16_next_pc (CORE_ADDR pc, 1341130803Smarcel unsigned int extension, unsigned int insn) 1342130803Smarcel{ 1343130803Smarcel int op = (insn >> 11); 1344130803Smarcel switch (op) 1345130803Smarcel { 1346130803Smarcel case 2: /* Branch */ 1347130803Smarcel { 1348130803Smarcel CORE_ADDR offset; 1349130803Smarcel struct upk_mips16 upk; 1350130803Smarcel unpack_mips16 (pc, extension, insn, itype, &upk); 1351130803Smarcel offset = upk.offset; 1352130803Smarcel if (offset & 0x800) 1353130803Smarcel { 1354130803Smarcel offset &= 0xeff; 1355130803Smarcel offset = -offset; 1356130803Smarcel } 1357130803Smarcel pc += (offset << 1) + 2; 1358130803Smarcel break; 1359130803Smarcel } 1360130803Smarcel case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ 1361130803Smarcel { 1362130803Smarcel struct upk_mips16 upk; 1363130803Smarcel unpack_mips16 (pc, extension, insn, jalxtype, &upk); 1364130803Smarcel pc = add_offset_16 (pc, upk.offset); 1365130803Smarcel if ((insn >> 10) & 0x01) /* Exchange mode */ 1366130803Smarcel pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ 1367130803Smarcel else 1368130803Smarcel pc |= 0x01; 1369130803Smarcel break; 1370130803Smarcel } 1371130803Smarcel case 4: /* beqz */ 1372130803Smarcel { 1373130803Smarcel struct upk_mips16 upk; 1374130803Smarcel int reg; 1375130803Smarcel unpack_mips16 (pc, extension, insn, ritype, &upk); 1376130803Smarcel reg = read_signed_register (upk.regx); 1377130803Smarcel if (reg == 0) 1378130803Smarcel pc += (upk.offset << 1) + 2; 1379130803Smarcel else 1380130803Smarcel pc += 2; 1381130803Smarcel break; 1382130803Smarcel } 1383130803Smarcel case 5: /* bnez */ 1384130803Smarcel { 1385130803Smarcel struct upk_mips16 upk; 1386130803Smarcel int reg; 1387130803Smarcel unpack_mips16 (pc, extension, insn, ritype, &upk); 1388130803Smarcel reg = read_signed_register (upk.regx); 1389130803Smarcel if (reg != 0) 1390130803Smarcel pc += (upk.offset << 1) + 2; 1391130803Smarcel else 1392130803Smarcel pc += 2; 1393130803Smarcel break; 1394130803Smarcel } 1395130803Smarcel case 12: /* I8 Formats btez btnez */ 1396130803Smarcel { 1397130803Smarcel struct upk_mips16 upk; 1398130803Smarcel int reg; 1399130803Smarcel unpack_mips16 (pc, extension, insn, i8type, &upk); 1400130803Smarcel /* upk.regx contains the opcode */ 1401130803Smarcel reg = read_signed_register (24); /* Test register is 24 */ 1402130803Smarcel if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ 1403130803Smarcel || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ 1404130803Smarcel /* pc = add_offset_16(pc,upk.offset) ; */ 1405130803Smarcel pc += (upk.offset << 1) + 2; 1406130803Smarcel else 1407130803Smarcel pc += 2; 1408130803Smarcel break; 1409130803Smarcel } 1410130803Smarcel case 29: /* RR Formats JR, JALR, JALR-RA */ 1411130803Smarcel { 1412130803Smarcel struct upk_mips16 upk; 1413130803Smarcel /* upk.fmt = rrtype; */ 1414130803Smarcel op = insn & 0x1f; 1415130803Smarcel if (op == 0) 1416130803Smarcel { 1417130803Smarcel int reg; 1418130803Smarcel upk.regx = (insn >> 8) & 0x07; 1419130803Smarcel upk.regy = (insn >> 5) & 0x07; 1420130803Smarcel switch (upk.regy) 1421130803Smarcel { 1422130803Smarcel case 0: 1423130803Smarcel reg = upk.regx; 1424130803Smarcel break; 1425130803Smarcel case 1: 1426130803Smarcel reg = 31; 1427130803Smarcel break; /* Function return instruction */ 1428130803Smarcel case 2: 1429130803Smarcel reg = upk.regx; 1430130803Smarcel break; 1431130803Smarcel default: 1432130803Smarcel reg = 31; 1433130803Smarcel break; /* BOGUS Guess */ 1434130803Smarcel } 1435130803Smarcel pc = read_signed_register (reg); 1436130803Smarcel } 1437130803Smarcel else 1438130803Smarcel pc += 2; 1439130803Smarcel break; 1440130803Smarcel } 1441130803Smarcel case 30: 1442130803Smarcel /* This is an instruction extension. Fetch the real instruction 1443130803Smarcel (which follows the extension) and decode things based on 1444130803Smarcel that. */ 1445130803Smarcel { 1446130803Smarcel pc += 2; 1447130803Smarcel pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); 1448130803Smarcel break; 1449130803Smarcel } 1450130803Smarcel default: 1451130803Smarcel { 1452130803Smarcel pc += 2; 1453130803Smarcel break; 1454130803Smarcel } 1455130803Smarcel } 1456130803Smarcel return pc; 1457130803Smarcel} 1458130803Smarcel 1459130803Smarcelstatic CORE_ADDR 1460130803Smarcelmips16_next_pc (CORE_ADDR pc) 1461130803Smarcel{ 1462130803Smarcel unsigned int insn = fetch_mips_16 (pc); 1463130803Smarcel return extended_mips16_next_pc (pc, 0, insn); 1464130803Smarcel} 1465130803Smarcel 1466130803Smarcel/* The mips_next_pc function supports single_step when the remote 1467130803Smarcel target monitor or stub is not developed enough to do a single_step. 1468130803Smarcel It works by decoding the current instruction and predicting where a 1469130803Smarcel branch will go. This isnt hard because all the data is available. 1470130803Smarcel The MIPS32 and MIPS16 variants are quite different */ 1471130803SmarcelCORE_ADDR 1472130803Smarcelmips_next_pc (CORE_ADDR pc) 1473130803Smarcel{ 1474130803Smarcel if (pc & 0x01) 1475130803Smarcel return mips16_next_pc (pc); 1476130803Smarcel else 1477130803Smarcel return mips32_next_pc (pc); 1478130803Smarcel} 1479130803Smarcel 1480130803Smarcelstruct mips_frame_cache 1481130803Smarcel{ 1482130803Smarcel CORE_ADDR base; 1483130803Smarcel struct trad_frame_saved_reg *saved_regs; 1484130803Smarcel}; 1485130803Smarcel 1486130803Smarcel 1487130803Smarcelstatic struct mips_frame_cache * 1488130803Smarcelmips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) 1489130803Smarcel{ 1490130803Smarcel mips_extra_func_info_t proc_desc; 1491130803Smarcel struct mips_frame_cache *cache; 1492130803Smarcel struct gdbarch *gdbarch = get_frame_arch (next_frame); 1493130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1494130803Smarcel /* r0 bit means kernel trap */ 1495130803Smarcel int kernel_trap; 1496130803Smarcel /* What registers have been saved? Bitmasks. */ 1497130803Smarcel unsigned long gen_mask, float_mask; 1498214947Sgonzo long reg_offset; 1499130803Smarcel 1500130803Smarcel if ((*this_cache) != NULL) 1501130803Smarcel return (*this_cache); 1502130803Smarcel cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 1503130803Smarcel (*this_cache) = cache; 1504130803Smarcel cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); 1505130803Smarcel 1506130803Smarcel /* Get the mdebug proc descriptor. */ 1507130803Smarcel proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1); 1508130803Smarcel if (proc_desc == NULL) 1509130803Smarcel /* I'm not sure how/whether this can happen. Normally when we 1510130803Smarcel can't find a proc_desc, we "synthesize" one using 1511130803Smarcel heuristic_proc_desc and set the saved_regs right away. */ 1512130803Smarcel return cache; 1513130803Smarcel 1514130803Smarcel /* Extract the frame's base. */ 1515130803Smarcel cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) 1516130803Smarcel + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); 1517214947Sgonzo /* Save registers offset from scratching by following find_proc_desc call */ 1518214947Sgonzo reg_offset = PROC_REG_OFFSET (proc_desc); 1519130803Smarcel 1520130803Smarcel kernel_trap = PROC_REG_MASK (proc_desc) & 1; 1521130803Smarcel gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); 1522130803Smarcel float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); 1523130803Smarcel 1524130803Smarcel /* In any frame other than the innermost or a frame interrupted by a 1525130803Smarcel signal, we assume that all registers have been saved. This 1526130803Smarcel assumes that all register saves in a function happen before the 1527130803Smarcel first function call. */ 1528130803Smarcel if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) 1529130803Smarcel /* Not sure exactly what kernel_trap means, but if it means the 1530130803Smarcel kernel saves the registers without a prologue doing it, we 1531130803Smarcel better not examine the prologue to see whether registers 1532130803Smarcel have been saved yet. */ 1533130803Smarcel && !kernel_trap) 1534130803Smarcel { 1535130803Smarcel /* We need to figure out whether the registers that the 1536130803Smarcel proc_desc claims are saved have been saved yet. */ 1537130803Smarcel 1538130803Smarcel CORE_ADDR addr; 1539130803Smarcel 1540130803Smarcel /* Bitmasks; set if we have found a save for the register. */ 1541130803Smarcel unsigned long gen_save_found = 0; 1542130803Smarcel unsigned long float_save_found = 0; 1543130803Smarcel int mips16; 1544130803Smarcel 1545130803Smarcel /* If the address is odd, assume this is MIPS16 code. */ 1546130803Smarcel addr = PROC_LOW_ADDR (proc_desc); 1547130803Smarcel mips16 = pc_is_mips16 (addr); 1548130803Smarcel 1549130803Smarcel /* Scan through this function's instructions preceding the 1550130803Smarcel current PC, and look for those that save registers. */ 1551130803Smarcel while (addr < frame_pc_unwind (next_frame)) 1552130803Smarcel { 1553130803Smarcel if (mips16) 1554130803Smarcel { 1555130803Smarcel mips16_decode_reg_save (mips16_fetch_instruction (addr), 1556130803Smarcel &gen_save_found); 1557130803Smarcel addr += MIPS16_INSTLEN; 1558130803Smarcel } 1559130803Smarcel else 1560130803Smarcel { 1561130803Smarcel mips32_decode_reg_save (mips32_fetch_instruction (addr), 1562130803Smarcel &gen_save_found, &float_save_found); 1563130803Smarcel addr += MIPS_INSTLEN; 1564130803Smarcel } 1565130803Smarcel } 1566130803Smarcel gen_mask = gen_save_found; 1567130803Smarcel float_mask = float_save_found; 1568130803Smarcel } 1569130803Smarcel 1570130803Smarcel /* Fill in the offsets for the registers which gen_mask says were 1571130803Smarcel saved. */ 1572130803Smarcel { 1573214947Sgonzo CORE_ADDR reg_position = (cache->base + reg_offset); 1574130803Smarcel int ireg; 1575130803Smarcel for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) 1576130803Smarcel if (gen_mask & 0x80000000) 1577130803Smarcel { 1578130803Smarcel cache->saved_regs[NUM_REGS + ireg].addr = reg_position; 1579130803Smarcel reg_position -= mips_saved_regsize (tdep); 1580130803Smarcel } 1581130803Smarcel } 1582130803Smarcel 1583130803Smarcel /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse 1584130803Smarcel order of that normally used by gcc. Therefore, we have to fetch 1585130803Smarcel the first instruction of the function, and if it's an entry 1586130803Smarcel instruction that saves $s0 or $s1, correct their saved addresses. */ 1587130803Smarcel if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) 1588130803Smarcel { 1589130803Smarcel ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); 1590130803Smarcel if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) 1591130803Smarcel /* entry */ 1592130803Smarcel { 1593130803Smarcel int reg; 1594130803Smarcel int sreg_count = (inst >> 6) & 3; 1595130803Smarcel 1596130803Smarcel /* Check if the ra register was pushed on the stack. */ 1597130803Smarcel CORE_ADDR reg_position = (cache->base 1598130803Smarcel + PROC_REG_OFFSET (proc_desc)); 1599130803Smarcel if (inst & 0x20) 1600130803Smarcel reg_position -= mips_saved_regsize (tdep); 1601130803Smarcel 1602130803Smarcel /* Check if the s0 and s1 registers were pushed on the 1603130803Smarcel stack. */ 1604130803Smarcel /* NOTE: cagney/2004-02-08: Huh? This is doing no such 1605130803Smarcel check. */ 1606130803Smarcel for (reg = 16; reg < sreg_count + 16; reg++) 1607130803Smarcel { 1608130803Smarcel cache->saved_regs[NUM_REGS + reg].addr = reg_position; 1609130803Smarcel reg_position -= mips_saved_regsize (tdep); 1610130803Smarcel } 1611130803Smarcel } 1612130803Smarcel } 1613130803Smarcel 1614130803Smarcel /* Fill in the offsets for the registers which float_mask says were 1615130803Smarcel saved. */ 1616130803Smarcel { 1617130803Smarcel CORE_ADDR reg_position = (cache->base 1618130803Smarcel + PROC_FREG_OFFSET (proc_desc)); 1619130803Smarcel int ireg; 1620130803Smarcel /* Fill in the offsets for the float registers which float_mask 1621130803Smarcel says were saved. */ 1622130803Smarcel for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) 1623130803Smarcel if (float_mask & 0x80000000) 1624130803Smarcel { 1625130803Smarcel if (mips_saved_regsize (tdep) == 4 1626130803Smarcel && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1627130803Smarcel { 1628130803Smarcel /* On a big endian 32 bit ABI, floating point registers 1629130803Smarcel are paired to form doubles such that the most 1630130803Smarcel significant part is in $f[N+1] and the least 1631130803Smarcel significant in $f[N] vis: $f[N+1] ||| $f[N]. The 1632130803Smarcel registers are also spilled as a pair and stored as a 1633130803Smarcel double. 1634130803Smarcel 1635130803Smarcel When little-endian the least significant part is 1636130803Smarcel stored first leading to the memory order $f[N] and 1637130803Smarcel then $f[N+1]. 1638130803Smarcel 1639130803Smarcel Unfortunately, when big-endian the most significant 1640130803Smarcel part of the double is stored first, and the least 1641130803Smarcel significant is stored second. This leads to the 1642130803Smarcel registers being ordered in memory as firt $f[N+1] and 1643130803Smarcel then $f[N]. 1644130803Smarcel 1645130803Smarcel For the big-endian case make certain that the 1646130803Smarcel addresses point at the correct (swapped) locations 1647130803Smarcel $f[N] and $f[N+1] pair (keep in mind that 1648130803Smarcel reg_position is decremented each time through the 1649130803Smarcel loop). */ 1650130803Smarcel if ((ireg & 1)) 1651130803Smarcel cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] 1652130803Smarcel .addr = reg_position - mips_saved_regsize (tdep); 1653130803Smarcel else 1654130803Smarcel cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] 1655130803Smarcel .addr = reg_position + mips_saved_regsize (tdep); 1656130803Smarcel } 1657130803Smarcel else 1658130803Smarcel cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] 1659130803Smarcel .addr = reg_position; 1660130803Smarcel reg_position -= mips_saved_regsize (tdep); 1661130803Smarcel } 1662130803Smarcel 1663130803Smarcel cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] 1664130803Smarcel = cache->saved_regs[NUM_REGS + RA_REGNUM]; 1665130803Smarcel } 1666130803Smarcel 1667130803Smarcel /* SP_REGNUM, contains the value and not the address. */ 1668130803Smarcel trad_frame_set_value (cache->saved_regs, NUM_REGS + SP_REGNUM, cache->base); 1669130803Smarcel 1670130803Smarcel return (*this_cache); 1671130803Smarcel} 1672130803Smarcel 1673130803Smarcelstatic void 1674130803Smarcelmips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, 1675130803Smarcel struct frame_id *this_id) 1676130803Smarcel{ 1677130803Smarcel struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, 1678130803Smarcel this_cache); 1679130803Smarcel (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); 1680130803Smarcel} 1681130803Smarcel 1682130803Smarcelstatic void 1683130803Smarcelmips_mdebug_frame_prev_register (struct frame_info *next_frame, 1684130803Smarcel void **this_cache, 1685130803Smarcel int regnum, int *optimizedp, 1686130803Smarcel enum lval_type *lvalp, CORE_ADDR *addrp, 1687130803Smarcel int *realnump, void *valuep) 1688130803Smarcel{ 1689130803Smarcel struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, 1690130803Smarcel this_cache); 1691130803Smarcel trad_frame_prev_register (next_frame, info->saved_regs, regnum, 1692130803Smarcel optimizedp, lvalp, addrp, realnump, valuep); 1693130803Smarcel} 1694130803Smarcel 1695130803Smarcelstatic const struct frame_unwind mips_mdebug_frame_unwind = 1696130803Smarcel{ 1697130803Smarcel NORMAL_FRAME, 1698130803Smarcel mips_mdebug_frame_this_id, 1699130803Smarcel mips_mdebug_frame_prev_register 1700130803Smarcel}; 1701130803Smarcel 1702130803Smarcelstatic const struct frame_unwind * 1703130803Smarcelmips_mdebug_frame_sniffer (struct frame_info *next_frame) 1704130803Smarcel{ 1705130803Smarcel return &mips_mdebug_frame_unwind; 1706130803Smarcel} 1707130803Smarcel 1708130803Smarcelstatic CORE_ADDR 1709130803Smarcelmips_mdebug_frame_base_address (struct frame_info *next_frame, 1710130803Smarcel void **this_cache) 1711130803Smarcel{ 1712130803Smarcel struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, 1713130803Smarcel this_cache); 1714130803Smarcel return info->base; 1715130803Smarcel} 1716130803Smarcel 1717130803Smarcelstatic const struct frame_base mips_mdebug_frame_base = { 1718130803Smarcel &mips_mdebug_frame_unwind, 1719130803Smarcel mips_mdebug_frame_base_address, 1720130803Smarcel mips_mdebug_frame_base_address, 1721130803Smarcel mips_mdebug_frame_base_address 1722130803Smarcel}; 1723130803Smarcel 1724130803Smarcelstatic const struct frame_base * 1725130803Smarcelmips_mdebug_frame_base_sniffer (struct frame_info *next_frame) 1726130803Smarcel{ 1727130803Smarcel return &mips_mdebug_frame_base; 1728130803Smarcel} 1729130803Smarcel 1730130803Smarcelstatic CORE_ADDR 1731130803Smarcelread_next_frame_reg (struct frame_info *fi, int regno) 1732130803Smarcel{ 1733130803Smarcel /* Always a pseudo. */ 1734130803Smarcel gdb_assert (regno >= NUM_REGS); 1735130803Smarcel if (fi == NULL) 1736130803Smarcel { 1737130803Smarcel LONGEST val; 1738130803Smarcel regcache_cooked_read_signed (current_regcache, regno, &val); 1739130803Smarcel return val; 1740130803Smarcel } 1741130803Smarcel else if ((regno % NUM_REGS) == SP_REGNUM) 1742130803Smarcel /* The SP_REGNUM is special, its value is stored in saved_regs. 1743130803Smarcel In fact, it is so special that it can even only be fetched 1744130803Smarcel using a raw register number! Once this code as been converted 1745130803Smarcel to frame-unwind the problem goes away. */ 1746130803Smarcel return frame_unwind_register_signed (fi, regno % NUM_REGS); 1747130803Smarcel else 1748130803Smarcel return frame_unwind_register_signed (fi, regno); 1749130803Smarcel 1750130803Smarcel} 1751130803Smarcel 1752130803Smarcel/* mips_addr_bits_remove - remove useless address bits */ 1753130803Smarcel 1754130803Smarcelstatic CORE_ADDR 1755130803Smarcelmips_addr_bits_remove (CORE_ADDR addr) 1756130803Smarcel{ 1757130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1758130803Smarcel if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) 1759130803Smarcel /* This hack is a work-around for existing boards using PMON, the 1760130803Smarcel simulator, and any other 64-bit targets that doesn't have true 1761130803Smarcel 64-bit addressing. On these targets, the upper 32 bits of 1762130803Smarcel addresses are ignored by the hardware. Thus, the PC or SP are 1763130803Smarcel likely to have been sign extended to all 1s by instruction 1764130803Smarcel sequences that load 32-bit addresses. For example, a typical 1765130803Smarcel piece of code that loads an address is this: 1766130803Smarcel 1767130803Smarcel lui $r2, <upper 16 bits> 1768130803Smarcel ori $r2, <lower 16 bits> 1769130803Smarcel 1770130803Smarcel But the lui sign-extends the value such that the upper 32 bits 1771130803Smarcel may be all 1s. The workaround is simply to mask off these 1772130803Smarcel bits. In the future, gcc may be changed to support true 64-bit 1773130803Smarcel addressing, and this masking will have to be disabled. */ 1774130803Smarcel return addr &= 0xffffffffUL; 1775130803Smarcel else 1776130803Smarcel return addr; 1777130803Smarcel} 1778130803Smarcel 1779130803Smarcel/* mips_software_single_step() is called just before we want to resume 1780130803Smarcel the inferior, if we want to single-step it but there is no hardware 1781130803Smarcel or kernel single-step support (MIPS on GNU/Linux for example). We find 1782130803Smarcel the target of the coming instruction and breakpoint it. 1783130803Smarcel 1784130803Smarcel single_step is also called just after the inferior stops. If we had 1785130803Smarcel set up a simulated single-step, we undo our damage. */ 1786130803Smarcel 1787130803Smarcelvoid 1788130803Smarcelmips_software_single_step (enum target_signal sig, int insert_breakpoints_p) 1789130803Smarcel{ 1790130803Smarcel static CORE_ADDR next_pc; 1791130803Smarcel typedef char binsn_quantum[BREAKPOINT_MAX]; 1792130803Smarcel static binsn_quantum break_mem; 1793130803Smarcel CORE_ADDR pc; 1794130803Smarcel 1795130803Smarcel if (insert_breakpoints_p) 1796130803Smarcel { 1797130803Smarcel pc = read_register (mips_regnum (current_gdbarch)->pc); 1798130803Smarcel next_pc = mips_next_pc (pc); 1799130803Smarcel 1800130803Smarcel target_insert_breakpoint (next_pc, break_mem); 1801130803Smarcel } 1802130803Smarcel else 1803130803Smarcel target_remove_breakpoint (next_pc, break_mem); 1804130803Smarcel} 1805130803Smarcel 1806130803Smarcelstatic struct mips_extra_func_info temp_proc_desc; 1807130803Smarcel 1808130803Smarcel/* This hack will go away once the get_prev_frame() code has been 1809130803Smarcel modified to set the frame's type first. That is BEFORE init extra 1810130803Smarcel frame info et.al. is called. This is because it will become 1811130803Smarcel possible to skip the init extra info call for sigtramp and dummy 1812130803Smarcel frames. */ 1813130803Smarcelstatic CORE_ADDR *temp_saved_regs; 1814130803Smarcel 1815130803Smarcel/* Set a register's saved stack address in temp_saved_regs. If an 1816130803Smarcel address has already been set for this register, do nothing; this 1817130803Smarcel way we will only recognize the first save of a given register in a 1818130803Smarcel function prologue. 1819130803Smarcel 1820130803Smarcel For simplicity, save the address in both [0 .. NUM_REGS) and 1821130803Smarcel [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range 1822130803Smarcel is used as it is only second range (the ABI instead of ISA 1823130803Smarcel registers) that comes into play when finding saved registers in a 1824130803Smarcel frame. */ 1825130803Smarcel 1826130803Smarcelstatic void 1827130803Smarcelset_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset) 1828130803Smarcel{ 1829130803Smarcel if (saved_regs[regno] == 0) 1830130803Smarcel { 1831130803Smarcel saved_regs[regno + 0 * NUM_REGS] = offset; 1832130803Smarcel saved_regs[regno + 1 * NUM_REGS] = offset; 1833130803Smarcel } 1834130803Smarcel} 1835130803Smarcel 1836130803Smarcel 1837130803Smarcel/* Test whether the PC points to the return instruction at the 1838130803Smarcel end of a function. */ 1839130803Smarcel 1840130803Smarcelstatic int 1841130803Smarcelmips_about_to_return (CORE_ADDR pc) 1842130803Smarcel{ 1843130803Smarcel if (pc_is_mips16 (pc)) 1844130803Smarcel /* This mips16 case isn't necessarily reliable. Sometimes the compiler 1845130803Smarcel generates a "jr $ra"; other times it generates code to load 1846130803Smarcel the return address from the stack to an accessible register (such 1847130803Smarcel as $a3), then a "jr" using that register. This second case 1848130803Smarcel is almost impossible to distinguish from an indirect jump 1849130803Smarcel used for switch statements, so we don't even try. */ 1850130803Smarcel return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ 1851130803Smarcel else 1852130803Smarcel return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ 1853130803Smarcel} 1854130803Smarcel 1855130803Smarcel 1856130803Smarcel/* This fencepost looks highly suspicious to me. Removing it also 1857130803Smarcel seems suspicious as it could affect remote debugging across serial 1858130803Smarcel lines. */ 1859130803Smarcel 1860130803Smarcelstatic CORE_ADDR 1861130803Smarcelheuristic_proc_start (CORE_ADDR pc) 1862130803Smarcel{ 1863130803Smarcel CORE_ADDR start_pc; 1864130803Smarcel CORE_ADDR fence; 1865130803Smarcel int instlen; 1866130803Smarcel int seen_adjsp = 0; 1867130803Smarcel 1868130803Smarcel pc = ADDR_BITS_REMOVE (pc); 1869130803Smarcel start_pc = pc; 1870130803Smarcel fence = start_pc - heuristic_fence_post; 1871130803Smarcel if (start_pc == 0) 1872130803Smarcel return 0; 1873130803Smarcel 1874130803Smarcel if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) 1875130803Smarcel fence = VM_MIN_ADDRESS; 1876130803Smarcel 1877130803Smarcel instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; 1878130803Smarcel 1879130803Smarcel /* search back for previous return */ 1880130803Smarcel for (start_pc -= instlen;; start_pc -= instlen) 1881130803Smarcel if (start_pc < fence) 1882130803Smarcel { 1883130803Smarcel /* It's not clear to me why we reach this point when 1884130803Smarcel stop_soon, but with this test, at least we 1885130803Smarcel don't print out warnings for every child forked (eg, on 1886130803Smarcel decstation). 22apr93 rich@cygnus.com. */ 1887130803Smarcel if (stop_soon == NO_STOP_QUIETLY) 1888130803Smarcel { 1889130803Smarcel static int blurb_printed = 0; 1890130803Smarcel 1891130803Smarcel warning 1892130803Smarcel ("Warning: GDB can't find the start of the function at 0x%s.", 1893130803Smarcel paddr_nz (pc)); 1894130803Smarcel 1895130803Smarcel if (!blurb_printed) 1896130803Smarcel { 1897130803Smarcel /* This actually happens frequently in embedded 1898130803Smarcel development, when you first connect to a board 1899130803Smarcel and your stack pointer and pc are nowhere in 1900130803Smarcel particular. This message needs to give people 1901130803Smarcel in that situation enough information to 1902130803Smarcel determine that it's no big deal. */ 1903130803Smarcel printf_filtered ("\n\ 1904130803Smarcel GDB is unable to find the start of the function at 0x%s\n\ 1905130803Smarceland thus can't determine the size of that function's stack frame.\n\ 1906130803SmarcelThis means that GDB may be unable to access that stack frame, or\n\ 1907130803Smarcelthe frames below it.\n\ 1908130803Smarcel This problem is most likely caused by an invalid program counter or\n\ 1909130803Smarcelstack pointer.\n\ 1910130803Smarcel However, if you think GDB should simply search farther back\n\ 1911130803Smarcelfrom 0x%s for code which looks like the beginning of a\n\ 1912130803Smarcelfunction, you can increase the range of the search using the `set\n\ 1913130803Smarcelheuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); 1914130803Smarcel blurb_printed = 1; 1915130803Smarcel } 1916130803Smarcel } 1917130803Smarcel 1918130803Smarcel return 0; 1919130803Smarcel } 1920130803Smarcel else if (pc_is_mips16 (start_pc)) 1921130803Smarcel { 1922130803Smarcel unsigned short inst; 1923130803Smarcel 1924130803Smarcel /* On MIPS16, any one of the following is likely to be the 1925130803Smarcel start of a function: 1926130803Smarcel entry 1927130803Smarcel addiu sp,-n 1928130803Smarcel daddiu sp,-n 1929130803Smarcel extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ 1930130803Smarcel inst = mips_fetch_instruction (start_pc); 1931130803Smarcel if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ 1932130803Smarcel || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ 1933130803Smarcel || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ 1934130803Smarcel || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ 1935130803Smarcel break; 1936130803Smarcel else if ((inst & 0xff00) == 0x6300 /* addiu sp */ 1937130803Smarcel || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 1938130803Smarcel seen_adjsp = 1; 1939130803Smarcel else 1940130803Smarcel seen_adjsp = 0; 1941130803Smarcel } 1942130803Smarcel else if (mips_about_to_return (start_pc)) 1943130803Smarcel { 1944130803Smarcel start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ 1945130803Smarcel break; 1946130803Smarcel } 1947130803Smarcel 1948130803Smarcel return start_pc; 1949130803Smarcel} 1950130803Smarcel 1951130803Smarcel/* Fetch the immediate value from a MIPS16 instruction. 1952130803Smarcel If the previous instruction was an EXTEND, use it to extend 1953130803Smarcel the upper bits of the immediate value. This is a helper function 1954130803Smarcel for mips16_heuristic_proc_desc. */ 1955130803Smarcel 1956130803Smarcelstatic int 1957130803Smarcelmips16_get_imm (unsigned short prev_inst, /* previous instruction */ 1958130803Smarcel unsigned short inst, /* current instruction */ 1959130803Smarcel int nbits, /* number of bits in imm field */ 1960130803Smarcel int scale, /* scale factor to be applied to imm */ 1961130803Smarcel int is_signed) /* is the imm field signed? */ 1962130803Smarcel{ 1963130803Smarcel int offset; 1964130803Smarcel 1965130803Smarcel if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ 1966130803Smarcel { 1967130803Smarcel offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); 1968130803Smarcel if (offset & 0x8000) /* check for negative extend */ 1969130803Smarcel offset = 0 - (0x10000 - (offset & 0xffff)); 1970130803Smarcel return offset | (inst & 0x1f); 1971130803Smarcel } 1972130803Smarcel else 1973130803Smarcel { 1974130803Smarcel int max_imm = 1 << nbits; 1975130803Smarcel int mask = max_imm - 1; 1976130803Smarcel int sign_bit = max_imm >> 1; 1977130803Smarcel 1978130803Smarcel offset = inst & mask; 1979130803Smarcel if (is_signed && (offset & sign_bit)) 1980130803Smarcel offset = 0 - (max_imm - offset); 1981130803Smarcel return offset * scale; 1982130803Smarcel } 1983130803Smarcel} 1984130803Smarcel 1985130803Smarcel 1986130803Smarcel/* Fill in values in temp_proc_desc based on the MIPS16 instruction 1987130803Smarcel stream from start_pc to limit_pc. */ 1988130803Smarcel 1989130803Smarcelstatic void 1990130803Smarcelmips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, 1991130803Smarcel struct frame_info *next_frame, CORE_ADDR sp) 1992130803Smarcel{ 1993130803Smarcel CORE_ADDR cur_pc; 1994130803Smarcel CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ 1995130803Smarcel unsigned short prev_inst = 0; /* saved copy of previous instruction */ 1996130803Smarcel unsigned inst = 0; /* current instruction */ 1997130803Smarcel unsigned entry_inst = 0; /* the entry instruction */ 1998130803Smarcel int reg, offset; 1999130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2000130803Smarcel 2001130803Smarcel PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ 2002130803Smarcel PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ 2003130803Smarcel 2004130803Smarcel for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) 2005130803Smarcel { 2006130803Smarcel /* Save the previous instruction. If it's an EXTEND, we'll extract 2007130803Smarcel the immediate offset extension from it in mips16_get_imm. */ 2008130803Smarcel prev_inst = inst; 2009130803Smarcel 2010130803Smarcel /* Fetch and decode the instruction. */ 2011130803Smarcel inst = (unsigned short) mips_fetch_instruction (cur_pc); 2012130803Smarcel if ((inst & 0xff00) == 0x6300 /* addiu sp */ 2013130803Smarcel || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 2014130803Smarcel { 2015130803Smarcel offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); 2016130803Smarcel if (offset < 0) /* negative stack adjustment? */ 2017130803Smarcel PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; 2018130803Smarcel else 2019130803Smarcel /* Exit loop if a positive stack adjustment is found, which 2020130803Smarcel usually means that the stack cleanup code in the function 2021130803Smarcel epilogue is reached. */ 2022130803Smarcel break; 2023130803Smarcel } 2024130803Smarcel else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ 2025130803Smarcel { 2026130803Smarcel offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2027130803Smarcel reg = mips16_to_32_reg[(inst & 0x700) >> 8]; 2028130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); 2029130803Smarcel set_reg_offset (temp_saved_regs, reg, sp + offset); 2030130803Smarcel } 2031130803Smarcel else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ 2032130803Smarcel { 2033130803Smarcel offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2034130803Smarcel reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; 2035130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); 2036130803Smarcel set_reg_offset (temp_saved_regs, reg, sp + offset); 2037130803Smarcel } 2038130803Smarcel else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ 2039130803Smarcel { 2040130803Smarcel offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2041130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); 2042130803Smarcel set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); 2043130803Smarcel } 2044130803Smarcel else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ 2045130803Smarcel { 2046130803Smarcel offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); 2047130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); 2048130803Smarcel set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); 2049130803Smarcel } 2050130803Smarcel else if (inst == 0x673d) /* move $s1, $sp */ 2051130803Smarcel { 2052130803Smarcel frame_addr = sp; 2053130803Smarcel PROC_FRAME_REG (&temp_proc_desc) = 17; 2054130803Smarcel } 2055130803Smarcel else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ 2056130803Smarcel { 2057130803Smarcel offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2058130803Smarcel frame_addr = sp + offset; 2059130803Smarcel PROC_FRAME_REG (&temp_proc_desc) = 17; 2060130803Smarcel PROC_FRAME_ADJUST (&temp_proc_desc) = offset; 2061130803Smarcel } 2062130803Smarcel else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ 2063130803Smarcel { 2064130803Smarcel offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); 2065130803Smarcel reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; 2066130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2067130803Smarcel set_reg_offset (temp_saved_regs, reg, frame_addr + offset); 2068130803Smarcel } 2069130803Smarcel else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ 2070130803Smarcel { 2071130803Smarcel offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2072130803Smarcel reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; 2073130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2074130803Smarcel set_reg_offset (temp_saved_regs, reg, frame_addr + offset); 2075130803Smarcel } 2076130803Smarcel else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ 2077130803Smarcel entry_inst = inst; /* save for later processing */ 2078130803Smarcel else if ((inst & 0xf800) == 0x1800) /* jal(x) */ 2079130803Smarcel cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ 2080130803Smarcel } 2081130803Smarcel 2082130803Smarcel /* The entry instruction is typically the first instruction in a function, 2083130803Smarcel and it stores registers at offsets relative to the value of the old SP 2084130803Smarcel (before the prologue). But the value of the sp parameter to this 2085130803Smarcel function is the new SP (after the prologue has been executed). So we 2086130803Smarcel can't calculate those offsets until we've seen the entire prologue, 2087130803Smarcel and can calculate what the old SP must have been. */ 2088130803Smarcel if (entry_inst != 0) 2089130803Smarcel { 2090130803Smarcel int areg_count = (entry_inst >> 8) & 7; 2091130803Smarcel int sreg_count = (entry_inst >> 6) & 3; 2092130803Smarcel 2093130803Smarcel /* The entry instruction always subtracts 32 from the SP. */ 2094130803Smarcel PROC_FRAME_OFFSET (&temp_proc_desc) += 32; 2095130803Smarcel 2096130803Smarcel /* Now we can calculate what the SP must have been at the 2097130803Smarcel start of the function prologue. */ 2098130803Smarcel sp += PROC_FRAME_OFFSET (&temp_proc_desc); 2099130803Smarcel 2100130803Smarcel /* Check if a0-a3 were saved in the caller's argument save area. */ 2101130803Smarcel for (reg = 4, offset = 0; reg < areg_count + 4; reg++) 2102130803Smarcel { 2103130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2104130803Smarcel set_reg_offset (temp_saved_regs, reg, sp + offset); 2105130803Smarcel offset += mips_saved_regsize (tdep); 2106130803Smarcel } 2107130803Smarcel 2108130803Smarcel /* Check if the ra register was pushed on the stack. */ 2109130803Smarcel offset = -4; 2110130803Smarcel if (entry_inst & 0x20) 2111130803Smarcel { 2112130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; 2113130803Smarcel set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset); 2114130803Smarcel offset -= mips_saved_regsize (tdep); 2115130803Smarcel } 2116130803Smarcel 2117130803Smarcel /* Check if the s0 and s1 registers were pushed on the stack. */ 2118130803Smarcel for (reg = 16; reg < sreg_count + 16; reg++) 2119130803Smarcel { 2120130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2121130803Smarcel set_reg_offset (temp_saved_regs, reg, sp + offset); 2122130803Smarcel offset -= mips_saved_regsize (tdep); 2123130803Smarcel } 2124130803Smarcel } 2125130803Smarcel} 2126130803Smarcel 2127130803Smarcelstatic void 2128130803Smarcelmips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, 2129130803Smarcel struct frame_info *next_frame, CORE_ADDR sp) 2130130803Smarcel{ 2131130803Smarcel CORE_ADDR cur_pc; 2132130803Smarcel CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ 2133130803Smarcelrestart: 2134130803Smarcel temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); 2135130803Smarcel memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); 2136130803Smarcel PROC_FRAME_OFFSET (&temp_proc_desc) = 0; 2137130803Smarcel PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ 2138130803Smarcel for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) 2139130803Smarcel { 2140130803Smarcel unsigned long inst, high_word, low_word; 2141130803Smarcel int reg; 2142130803Smarcel 2143130803Smarcel /* Fetch the instruction. */ 2144130803Smarcel inst = (unsigned long) mips_fetch_instruction (cur_pc); 2145130803Smarcel 2146130803Smarcel /* Save some code by pre-extracting some useful fields. */ 2147130803Smarcel high_word = (inst >> 16) & 0xffff; 2148130803Smarcel low_word = inst & 0xffff; 2149130803Smarcel reg = high_word & 0x1f; 2150130803Smarcel 2151130803Smarcel if (high_word == 0x27bd /* addiu $sp,$sp,-i */ 2152130803Smarcel || high_word == 0x23bd /* addi $sp,$sp,-i */ 2153130803Smarcel || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ 2154130803Smarcel { 2155130803Smarcel if (low_word & 0x8000) /* negative stack adjustment? */ 2156130803Smarcel PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; 2157130803Smarcel else 2158130803Smarcel /* Exit loop if a positive stack adjustment is found, which 2159130803Smarcel usually means that the stack cleanup code in the function 2160130803Smarcel epilogue is reached. */ 2161130803Smarcel break; 2162130803Smarcel } 2163130803Smarcel else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ 2164130803Smarcel { 2165130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2166130803Smarcel set_reg_offset (temp_saved_regs, reg, sp + low_word); 2167214947Sgonzo /* Do we have registers offset yet? */ 2168214947Sgonzo if (!PROC_REG_OFFSET (&temp_proc_desc)) 2169214947Sgonzo PROC_REG_OFFSET (&temp_proc_desc) = low_word - PROC_FRAME_OFFSET (&temp_proc_desc); 2170130803Smarcel } 2171130803Smarcel else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ 2172130803Smarcel { 2173130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2174130803Smarcel set_reg_offset (temp_saved_regs, reg, 2175214947Sgonzo sp + low_word); 2176214947Sgonzo /* Do we have registers offset yet? */ 2177214947Sgonzo if (!PROC_REG_OFFSET (&temp_proc_desc)) 2178214947Sgonzo PROC_REG_OFFSET (&temp_proc_desc) = low_word - PROC_FRAME_OFFSET (&temp_proc_desc); 2179130803Smarcel } 2180130803Smarcel else if (high_word == 0x27be) /* addiu $30,$sp,size */ 2181130803Smarcel { 2182130803Smarcel /* Old gcc frame, r30 is virtual frame pointer. */ 2183130803Smarcel if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) 2184130803Smarcel frame_addr = sp + low_word; 2185130803Smarcel else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) 2186130803Smarcel { 2187130803Smarcel unsigned alloca_adjust; 2188130803Smarcel PROC_FRAME_REG (&temp_proc_desc) = 30; 2189130803Smarcel frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); 2190130803Smarcel alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); 2191130803Smarcel if (alloca_adjust > 0) 2192130803Smarcel { 2193130803Smarcel /* FP > SP + frame_size. This may be because 2194130803Smarcel * of an alloca or somethings similar. 2195130803Smarcel * Fix sp to "pre-alloca" value, and try again. 2196130803Smarcel */ 2197130803Smarcel sp += alloca_adjust; 2198130803Smarcel goto restart; 2199130803Smarcel } 2200130803Smarcel } 2201130803Smarcel } 2202130803Smarcel /* move $30,$sp. With different versions of gas this will be either 2203130803Smarcel `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. 2204130803Smarcel Accept any one of these. */ 2205130803Smarcel else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) 2206130803Smarcel { 2207130803Smarcel /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ 2208130803Smarcel if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) 2209130803Smarcel { 2210130803Smarcel unsigned alloca_adjust; 2211130803Smarcel PROC_FRAME_REG (&temp_proc_desc) = 30; 2212130803Smarcel frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); 2213130803Smarcel alloca_adjust = (unsigned) (frame_addr - sp); 2214130803Smarcel if (alloca_adjust > 0) 2215130803Smarcel { 2216130803Smarcel /* FP > SP + frame_size. This may be because 2217130803Smarcel * of an alloca or somethings similar. 2218130803Smarcel * Fix sp to "pre-alloca" value, and try again. 2219130803Smarcel */ 2220130803Smarcel sp += alloca_adjust; 2221130803Smarcel goto restart; 2222130803Smarcel } 2223130803Smarcel } 2224130803Smarcel } 2225130803Smarcel else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ 2226130803Smarcel { 2227130803Smarcel PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; 2228130803Smarcel set_reg_offset (temp_saved_regs, reg, frame_addr + low_word); 2229130803Smarcel } 2230130803Smarcel } 2231130803Smarcel} 2232130803Smarcel 2233130803Smarcelstatic mips_extra_func_info_t 2234130803Smarcelheuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, 2235130803Smarcel struct frame_info *next_frame, int cur_frame) 2236130803Smarcel{ 2237130803Smarcel CORE_ADDR sp; 2238130803Smarcel 2239130803Smarcel if (cur_frame) 2240130803Smarcel sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM); 2241130803Smarcel else 2242130803Smarcel sp = 0; 2243130803Smarcel 2244130803Smarcel if (start_pc == 0) 2245130803Smarcel return NULL; 2246130803Smarcel memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); 2247130803Smarcel temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); 2248130803Smarcel memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); 2249130803Smarcel PROC_LOW_ADDR (&temp_proc_desc) = start_pc; 2250130803Smarcel PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; 2251130803Smarcel PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; 2252130803Smarcel 2253130803Smarcel if (start_pc + 200 < limit_pc) 2254130803Smarcel limit_pc = start_pc + 200; 2255130803Smarcel if (pc_is_mips16 (start_pc)) 2256130803Smarcel mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); 2257130803Smarcel else 2258130803Smarcel mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); 2259130803Smarcel return &temp_proc_desc; 2260130803Smarcel} 2261130803Smarcel 2262130803Smarcelstruct mips_objfile_private 2263130803Smarcel{ 2264130803Smarcel bfd_size_type size; 2265130803Smarcel char *contents; 2266130803Smarcel}; 2267130803Smarcel 2268130803Smarcel/* Global used to communicate between non_heuristic_proc_desc and 2269130803Smarcel compare_pdr_entries within qsort (). */ 2270130803Smarcelstatic bfd *the_bfd; 2271130803Smarcel 2272130803Smarcelstatic int 2273130803Smarcelcompare_pdr_entries (const void *a, const void *b) 2274130803Smarcel{ 2275130803Smarcel CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); 2276130803Smarcel CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); 2277130803Smarcel 2278130803Smarcel if (lhs < rhs) 2279130803Smarcel return -1; 2280130803Smarcel else if (lhs == rhs) 2281130803Smarcel return 0; 2282130803Smarcel else 2283130803Smarcel return 1; 2284130803Smarcel} 2285130803Smarcel 2286130803Smarcelstatic mips_extra_func_info_t 2287130803Smarcelnon_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) 2288130803Smarcel{ 2289130803Smarcel CORE_ADDR startaddr; 2290130803Smarcel mips_extra_func_info_t proc_desc; 2291130803Smarcel struct block *b = block_for_pc (pc); 2292130803Smarcel struct symbol *sym; 2293130803Smarcel struct obj_section *sec; 2294130803Smarcel struct mips_objfile_private *priv; 2295130803Smarcel 2296130803Smarcel if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) 2297130803Smarcel return NULL; 2298130803Smarcel 2299130803Smarcel find_pc_partial_function (pc, NULL, &startaddr, NULL); 2300130803Smarcel if (addrptr) 2301130803Smarcel *addrptr = startaddr; 2302130803Smarcel 2303130803Smarcel priv = NULL; 2304130803Smarcel 2305130803Smarcel sec = find_pc_section (pc); 2306130803Smarcel if (sec != NULL) 2307130803Smarcel { 2308130803Smarcel priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); 2309130803Smarcel 2310130803Smarcel /* Search the ".pdr" section generated by GAS. This includes most of 2311130803Smarcel the information normally found in ECOFF PDRs. */ 2312130803Smarcel 2313130803Smarcel the_bfd = sec->objfile->obfd; 2314130803Smarcel if (priv == NULL 2315130803Smarcel && (the_bfd->format == bfd_object 2316130803Smarcel && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour 2317130803Smarcel && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) 2318130803Smarcel { 2319130803Smarcel /* Right now GAS only outputs the address as a four-byte sequence. 2320130803Smarcel This means that we should not bother with this method on 64-bit 2321130803Smarcel targets (until that is fixed). */ 2322130803Smarcel 2323130803Smarcel priv = obstack_alloc (&sec->objfile->objfile_obstack, 2324130803Smarcel sizeof (struct mips_objfile_private)); 2325130803Smarcel priv->size = 0; 2326130803Smarcel set_objfile_data (sec->objfile, mips_pdr_data, priv); 2327130803Smarcel } 2328130803Smarcel else if (priv == NULL) 2329130803Smarcel { 2330130803Smarcel asection *bfdsec; 2331130803Smarcel 2332130803Smarcel priv = obstack_alloc (&sec->objfile->objfile_obstack, 2333130803Smarcel sizeof (struct mips_objfile_private)); 2334130803Smarcel 2335130803Smarcel bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); 2336130803Smarcel if (bfdsec != NULL) 2337130803Smarcel { 2338130803Smarcel priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); 2339130803Smarcel priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, 2340130803Smarcel priv->size); 2341130803Smarcel bfd_get_section_contents (sec->objfile->obfd, bfdsec, 2342130803Smarcel priv->contents, 0, priv->size); 2343130803Smarcel 2344130803Smarcel /* In general, the .pdr section is sorted. However, in the 2345130803Smarcel presence of multiple code sections (and other corner cases) 2346130803Smarcel it can become unsorted. Sort it so that we can use a faster 2347130803Smarcel binary search. */ 2348130803Smarcel qsort (priv->contents, priv->size / 32, 32, 2349130803Smarcel compare_pdr_entries); 2350130803Smarcel } 2351130803Smarcel else 2352130803Smarcel priv->size = 0; 2353130803Smarcel 2354130803Smarcel set_objfile_data (sec->objfile, mips_pdr_data, priv); 2355130803Smarcel } 2356130803Smarcel the_bfd = NULL; 2357130803Smarcel 2358130803Smarcel if (priv->size != 0) 2359130803Smarcel { 2360130803Smarcel int low, mid, high; 2361130803Smarcel char *ptr; 2362130803Smarcel 2363130803Smarcel low = 0; 2364130803Smarcel high = priv->size / 32; 2365130803Smarcel 2366130803Smarcel do 2367130803Smarcel { 2368130803Smarcel CORE_ADDR pdr_pc; 2369130803Smarcel 2370130803Smarcel mid = (low + high) / 2; 2371130803Smarcel 2372130803Smarcel ptr = priv->contents + mid * 32; 2373130803Smarcel pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); 2374130803Smarcel pdr_pc += ANOFFSET (sec->objfile->section_offsets, 2375130803Smarcel SECT_OFF_TEXT (sec->objfile)); 2376130803Smarcel if (pdr_pc == startaddr) 2377130803Smarcel break; 2378130803Smarcel if (pdr_pc > startaddr) 2379130803Smarcel high = mid; 2380130803Smarcel else 2381130803Smarcel low = mid + 1; 2382130803Smarcel } 2383130803Smarcel while (low != high); 2384130803Smarcel 2385130803Smarcel if (low != high) 2386130803Smarcel { 2387130803Smarcel struct symbol *sym = find_pc_function (pc); 2388130803Smarcel 2389130803Smarcel /* Fill in what we need of the proc_desc. */ 2390130803Smarcel proc_desc = (mips_extra_func_info_t) 2391130803Smarcel obstack_alloc (&sec->objfile->objfile_obstack, 2392130803Smarcel sizeof (struct mips_extra_func_info)); 2393130803Smarcel PROC_LOW_ADDR (proc_desc) = startaddr; 2394130803Smarcel 2395130803Smarcel /* Only used for dummy frames. */ 2396130803Smarcel PROC_HIGH_ADDR (proc_desc) = 0; 2397130803Smarcel 2398130803Smarcel PROC_FRAME_OFFSET (proc_desc) 2399130803Smarcel = bfd_get_32 (sec->objfile->obfd, ptr + 20); 2400130803Smarcel PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, 2401130803Smarcel ptr + 24); 2402130803Smarcel PROC_FRAME_ADJUST (proc_desc) = 0; 2403130803Smarcel PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, 2404130803Smarcel ptr + 4); 2405130803Smarcel PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, 2406130803Smarcel ptr + 12); 2407130803Smarcel PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, 2408130803Smarcel ptr + 8); 2409130803Smarcel PROC_FREG_OFFSET (proc_desc) 2410130803Smarcel = bfd_get_32 (sec->objfile->obfd, ptr + 16); 2411130803Smarcel PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, 2412130803Smarcel ptr + 28); 2413130803Smarcel proc_desc->pdr.isym = (long) sym; 2414130803Smarcel 2415130803Smarcel return proc_desc; 2416130803Smarcel } 2417130803Smarcel } 2418130803Smarcel } 2419130803Smarcel 2420130803Smarcel if (b == NULL) 2421130803Smarcel return NULL; 2422130803Smarcel 2423130803Smarcel if (startaddr > BLOCK_START (b)) 2424130803Smarcel { 2425130803Smarcel /* This is the "pathological" case referred to in a comment in 2426130803Smarcel print_frame_info. It might be better to move this check into 2427130803Smarcel symbol reading. */ 2428130803Smarcel return NULL; 2429130803Smarcel } 2430130803Smarcel 2431130803Smarcel sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); 2432130803Smarcel 2433130803Smarcel /* If we never found a PDR for this function in symbol reading, then 2434130803Smarcel examine prologues to find the information. */ 2435130803Smarcel if (sym) 2436130803Smarcel { 2437130803Smarcel proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); 2438130803Smarcel if (PROC_FRAME_REG (proc_desc) == -1) 2439130803Smarcel return NULL; 2440130803Smarcel else 2441130803Smarcel return proc_desc; 2442130803Smarcel } 2443130803Smarcel else 2444130803Smarcel return NULL; 2445130803Smarcel} 2446130803Smarcel 2447130803Smarcel 2448130803Smarcelstatic mips_extra_func_info_t 2449130803Smarcelfind_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame) 2450130803Smarcel{ 2451130803Smarcel mips_extra_func_info_t proc_desc; 2452130803Smarcel CORE_ADDR startaddr = 0; 2453130803Smarcel 2454130803Smarcel proc_desc = non_heuristic_proc_desc (pc, &startaddr); 2455130803Smarcel 2456130803Smarcel if (proc_desc) 2457130803Smarcel { 2458130803Smarcel /* IF this is the topmost frame AND 2459130803Smarcel * (this proc does not have debugging information OR 2460130803Smarcel * the PC is in the procedure prologue) 2461130803Smarcel * THEN create a "heuristic" proc_desc (by analyzing 2462130803Smarcel * the actual code) to replace the "official" proc_desc. 2463130803Smarcel */ 2464130803Smarcel if (next_frame == NULL) 2465130803Smarcel { 2466130803Smarcel struct symtab_and_line val; 2467130803Smarcel struct symbol *proc_symbol = 2468130803Smarcel PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); 2469130803Smarcel 2470130803Smarcel if (proc_symbol) 2471130803Smarcel { 2472130803Smarcel val = find_pc_line (BLOCK_START 2473130803Smarcel (SYMBOL_BLOCK_VALUE (proc_symbol)), 0); 2474130803Smarcel val.pc = val.end ? val.end : pc; 2475130803Smarcel } 2476130803Smarcel if (!proc_symbol || pc < val.pc) 2477130803Smarcel { 2478130803Smarcel mips_extra_func_info_t found_heuristic = 2479130803Smarcel heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), 2480130803Smarcel pc, next_frame, cur_frame); 2481130803Smarcel if (found_heuristic) 2482130803Smarcel proc_desc = found_heuristic; 2483130803Smarcel } 2484130803Smarcel } 2485130803Smarcel } 2486130803Smarcel else 2487130803Smarcel { 2488130803Smarcel /* Is linked_proc_desc_table really necessary? It only seems to be used 2489130803Smarcel by procedure call dummys. However, the procedures being called ought 2490130803Smarcel to have their own proc_descs, and even if they don't, 2491130803Smarcel heuristic_proc_desc knows how to create them! */ 2492130803Smarcel 2493130803Smarcel struct linked_proc_info *link; 2494130803Smarcel 2495130803Smarcel for (link = linked_proc_desc_table; link; link = link->next) 2496130803Smarcel if (PROC_LOW_ADDR (&link->info) <= pc 2497130803Smarcel && PROC_HIGH_ADDR (&link->info) > pc) 2498130803Smarcel return &link->info; 2499130803Smarcel 2500130803Smarcel if (startaddr == 0) 2501130803Smarcel startaddr = heuristic_proc_start (pc); 2502130803Smarcel 2503130803Smarcel proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame); 2504130803Smarcel } 2505130803Smarcel return proc_desc; 2506130803Smarcel} 2507130803Smarcel 2508130803Smarcel/* MIPS stack frames are almost impenetrable. When execution stops, 2509130803Smarcel we basically have to look at symbol information for the function 2510130803Smarcel that we stopped in, which tells us *which* register (if any) is 2511130803Smarcel the base of the frame pointer, and what offset from that register 2512130803Smarcel the frame itself is at. 2513130803Smarcel 2514130803Smarcel This presents a problem when trying to examine a stack in memory 2515130803Smarcel (that isn't executing at the moment), using the "frame" command. We 2516130803Smarcel don't have a PC, nor do we have any registers except SP. 2517130803Smarcel 2518130803Smarcel This routine takes two arguments, SP and PC, and tries to make the 2519130803Smarcel cached frames look as if these two arguments defined a frame on the 2520130803Smarcel cache. This allows the rest of info frame to extract the important 2521130803Smarcel arguments without difficulty. */ 2522130803Smarcel 2523130803Smarcelstruct frame_info * 2524130803Smarcelsetup_arbitrary_frame (int argc, CORE_ADDR *argv) 2525130803Smarcel{ 2526130803Smarcel if (argc != 2) 2527130803Smarcel error ("MIPS frame specifications require two arguments: sp and pc"); 2528130803Smarcel 2529130803Smarcel return create_new_frame (argv[0], argv[1]); 2530130803Smarcel} 2531130803Smarcel 2532130803Smarcel/* According to the current ABI, should the type be passed in a 2533130803Smarcel floating-point register (assuming that there is space)? When there 2534130803Smarcel is no FPU, FP are not even considered as possibile candidates for 2535130803Smarcel FP registers and, consequently this returns false - forces FP 2536130803Smarcel arguments into integer registers. */ 2537130803Smarcel 2538130803Smarcelstatic int 2539130803Smarcelfp_register_arg_p (enum type_code typecode, struct type *arg_type) 2540130803Smarcel{ 2541130803Smarcel return ((typecode == TYPE_CODE_FLT 2542130803Smarcel || (MIPS_EABI 2543130803Smarcel && (typecode == TYPE_CODE_STRUCT 2544130803Smarcel || typecode == TYPE_CODE_UNION) 2545130803Smarcel && TYPE_NFIELDS (arg_type) == 1 2546130803Smarcel && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) 2547130803Smarcel && MIPS_FPU_TYPE != MIPS_FPU_NONE); 2548130803Smarcel} 2549130803Smarcel 2550130803Smarcel/* On o32, argument passing in GPRs depends on the alignment of the type being 2551130803Smarcel passed. Return 1 if this type must be aligned to a doubleword boundary. */ 2552130803Smarcel 2553130803Smarcelstatic int 2554130803Smarcelmips_type_needs_double_align (struct type *type) 2555130803Smarcel{ 2556130803Smarcel enum type_code typecode = TYPE_CODE (type); 2557130803Smarcel 2558130803Smarcel if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) 2559130803Smarcel return 1; 2560130803Smarcel else if (typecode == TYPE_CODE_STRUCT) 2561130803Smarcel { 2562130803Smarcel if (TYPE_NFIELDS (type) < 1) 2563130803Smarcel return 0; 2564130803Smarcel return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); 2565130803Smarcel } 2566130803Smarcel else if (typecode == TYPE_CODE_UNION) 2567130803Smarcel { 2568130803Smarcel int i, n; 2569130803Smarcel 2570130803Smarcel n = TYPE_NFIELDS (type); 2571130803Smarcel for (i = 0; i < n; i++) 2572130803Smarcel if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) 2573130803Smarcel return 1; 2574130803Smarcel return 0; 2575130803Smarcel } 2576130803Smarcel return 0; 2577130803Smarcel} 2578130803Smarcel 2579130803Smarcel/* Adjust the address downward (direction of stack growth) so that it 2580130803Smarcel is correctly aligned for a new stack frame. */ 2581130803Smarcelstatic CORE_ADDR 2582130803Smarcelmips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 2583130803Smarcel{ 2584130803Smarcel return align_down (addr, 16); 2585130803Smarcel} 2586130803Smarcel 2587130803Smarcel/* Determine how a return value is stored within the MIPS register 2588130803Smarcel file, given the return type `valtype'. */ 2589130803Smarcel 2590130803Smarcelstruct return_value_word 2591130803Smarcel{ 2592130803Smarcel int len; 2593130803Smarcel int reg; 2594130803Smarcel int reg_offset; 2595130803Smarcel int buf_offset; 2596130803Smarcel}; 2597130803Smarcel 2598130803Smarcelstatic void 2599130803Smarcelreturn_value_location (struct type *valtype, 2600130803Smarcel struct return_value_word *hi, 2601130803Smarcel struct return_value_word *lo) 2602130803Smarcel{ 2603130803Smarcel int len = TYPE_LENGTH (valtype); 2604130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2605130803Smarcel 2606130803Smarcel if (TYPE_CODE (valtype) == TYPE_CODE_FLT 2607130803Smarcel && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) 2608130803Smarcel || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) 2609130803Smarcel { 2610130803Smarcel if (!FP_REGISTER_DOUBLE && len == 8) 2611130803Smarcel { 2612130803Smarcel /* We need to break a 64bit float in two 32 bit halves and 2613130803Smarcel spread them across a floating-point register pair. */ 2614130803Smarcel lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; 2615130803Smarcel hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4; 2616130803Smarcel lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 2617130803Smarcel && register_size (current_gdbarch, 2618130803Smarcel mips_regnum (current_gdbarch)-> 2619130803Smarcel fp0) == 8) ? 4 : 0); 2620130803Smarcel hi->reg_offset = lo->reg_offset; 2621130803Smarcel lo->reg = mips_regnum (current_gdbarch)->fp0 + 0; 2622130803Smarcel hi->reg = mips_regnum (current_gdbarch)->fp0 + 1; 2623130803Smarcel lo->len = 4; 2624130803Smarcel hi->len = 4; 2625130803Smarcel } 2626130803Smarcel else 2627130803Smarcel { 2628130803Smarcel /* The floating point value fits in a single floating-point 2629130803Smarcel register. */ 2630130803Smarcel lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 2631130803Smarcel && register_size (current_gdbarch, 2632130803Smarcel mips_regnum (current_gdbarch)-> 2633130803Smarcel fp0) == 8 2634130803Smarcel && len == 4) ? 4 : 0); 2635130803Smarcel lo->reg = mips_regnum (current_gdbarch)->fp0; 2636130803Smarcel lo->len = len; 2637130803Smarcel lo->buf_offset = 0; 2638130803Smarcel hi->len = 0; 2639130803Smarcel hi->reg_offset = 0; 2640130803Smarcel hi->buf_offset = 0; 2641130803Smarcel hi->reg = 0; 2642130803Smarcel } 2643130803Smarcel } 2644130803Smarcel else 2645130803Smarcel { 2646130803Smarcel /* Locate a result possibly spread across two registers. */ 2647130803Smarcel int regnum = 2; 2648130803Smarcel lo->reg = regnum + 0; 2649130803Smarcel hi->reg = regnum + 1; 2650130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 2651130803Smarcel && len < mips_saved_regsize (tdep)) 2652130803Smarcel { 2653130803Smarcel /* "un-left-justify" the value in the low register */ 2654130803Smarcel lo->reg_offset = mips_saved_regsize (tdep) - len; 2655130803Smarcel lo->len = len; 2656130803Smarcel hi->reg_offset = 0; 2657130803Smarcel hi->len = 0; 2658130803Smarcel } 2659130803Smarcel else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_saved_regsize (tdep) /* odd-size structs */ 2660130803Smarcel && len < mips_saved_regsize (tdep) * 2 2661130803Smarcel && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || 2662130803Smarcel TYPE_CODE (valtype) == TYPE_CODE_UNION)) 2663130803Smarcel { 2664130803Smarcel /* "un-left-justify" the value spread across two registers. */ 2665130803Smarcel lo->reg_offset = 2 * mips_saved_regsize (tdep) - len; 2666130803Smarcel lo->len = mips_saved_regsize (tdep) - lo->reg_offset; 2667130803Smarcel hi->reg_offset = 0; 2668130803Smarcel hi->len = len - lo->len; 2669130803Smarcel } 2670130803Smarcel else 2671130803Smarcel { 2672130803Smarcel /* Only perform a partial copy of the second register. */ 2673130803Smarcel lo->reg_offset = 0; 2674130803Smarcel hi->reg_offset = 0; 2675130803Smarcel if (len > mips_saved_regsize (tdep)) 2676130803Smarcel { 2677130803Smarcel lo->len = mips_saved_regsize (tdep); 2678130803Smarcel hi->len = len - mips_saved_regsize (tdep); 2679130803Smarcel } 2680130803Smarcel else 2681130803Smarcel { 2682130803Smarcel lo->len = len; 2683130803Smarcel hi->len = 0; 2684130803Smarcel } 2685130803Smarcel } 2686130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 2687130803Smarcel && register_size (current_gdbarch, regnum) == 8 2688130803Smarcel && mips_saved_regsize (tdep) == 4) 2689130803Smarcel { 2690130803Smarcel /* Account for the fact that only the least-signficant part 2691130803Smarcel of the register is being used */ 2692130803Smarcel lo->reg_offset += 4; 2693130803Smarcel hi->reg_offset += 4; 2694130803Smarcel } 2695130803Smarcel lo->buf_offset = 0; 2696130803Smarcel hi->buf_offset = lo->len; 2697130803Smarcel } 2698130803Smarcel} 2699130803Smarcel 2700130803Smarcel/* Should call_function allocate stack space for a struct return? */ 2701130803Smarcel 2702130803Smarcelstatic int 2703130803Smarcelmips_eabi_use_struct_convention (int gcc_p, struct type *type) 2704130803Smarcel{ 2705130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2706130803Smarcel return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)); 2707130803Smarcel} 2708130803Smarcel 2709130803Smarcel/* Should call_function pass struct by reference? 2710130803Smarcel For each architecture, structs are passed either by 2711130803Smarcel value or by reference, depending on their size. */ 2712130803Smarcel 2713130803Smarcelstatic int 2714130803Smarcelmips_eabi_reg_struct_has_addr (int gcc_p, struct type *type) 2715130803Smarcel{ 2716130803Smarcel enum type_code typecode = TYPE_CODE (check_typedef (type)); 2717130803Smarcel int len = TYPE_LENGTH (check_typedef (type)); 2718130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2719130803Smarcel 2720130803Smarcel if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) 2721130803Smarcel return (len > mips_saved_regsize (tdep)); 2722130803Smarcel 2723130803Smarcel return 0; 2724130803Smarcel} 2725130803Smarcel 2726130803Smarcelstatic CORE_ADDR 2727130803Smarcelmips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 2728130803Smarcel struct regcache *regcache, CORE_ADDR bp_addr, 2729130803Smarcel int nargs, struct value **args, CORE_ADDR sp, 2730130803Smarcel int struct_return, CORE_ADDR struct_addr) 2731130803Smarcel{ 2732130803Smarcel int argreg; 2733130803Smarcel int float_argreg; 2734130803Smarcel int argnum; 2735130803Smarcel int len = 0; 2736130803Smarcel int stack_offset = 0; 2737130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2738130803Smarcel 2739130803Smarcel /* For shared libraries, "t9" needs to point at the function 2740130803Smarcel address. */ 2741130803Smarcel regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); 2742130803Smarcel 2743130803Smarcel /* Set the return address register to point to the entry point of 2744130803Smarcel the program, where a breakpoint lies in wait. */ 2745130803Smarcel regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); 2746130803Smarcel 2747130803Smarcel /* First ensure that the stack and structure return address (if any) 2748130803Smarcel are properly aligned. The stack has to be at least 64-bit 2749130803Smarcel aligned even on 32-bit machines, because doubles must be 64-bit 2750130803Smarcel aligned. For n32 and n64, stack frames need to be 128-bit 2751130803Smarcel aligned, so we round to this widest known alignment. */ 2752130803Smarcel 2753130803Smarcel sp = align_down (sp, 16); 2754130803Smarcel struct_addr = align_down (struct_addr, 16); 2755130803Smarcel 2756130803Smarcel /* Now make space on the stack for the args. We allocate more 2757130803Smarcel than necessary for EABI, because the first few arguments are 2758130803Smarcel passed in registers, but that's OK. */ 2759130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 2760130803Smarcel len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 2761130803Smarcel mips_stack_argsize (tdep)); 2762130803Smarcel sp -= align_up (len, 16); 2763130803Smarcel 2764130803Smarcel if (mips_debug) 2765130803Smarcel fprintf_unfiltered (gdb_stdlog, 2766130803Smarcel "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", 2767130803Smarcel paddr_nz (sp), (long) align_up (len, 16)); 2768130803Smarcel 2769130803Smarcel /* Initialize the integer and float register pointers. */ 2770130803Smarcel argreg = A0_REGNUM; 2771130803Smarcel float_argreg = mips_fpa0_regnum (current_gdbarch); 2772130803Smarcel 2773130803Smarcel /* The struct_return pointer occupies the first parameter-passing reg. */ 2774130803Smarcel if (struct_return) 2775130803Smarcel { 2776130803Smarcel if (mips_debug) 2777130803Smarcel fprintf_unfiltered (gdb_stdlog, 2778130803Smarcel "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", 2779130803Smarcel argreg, paddr_nz (struct_addr)); 2780130803Smarcel write_register (argreg++, struct_addr); 2781130803Smarcel } 2782130803Smarcel 2783130803Smarcel /* Now load as many as possible of the first arguments into 2784130803Smarcel registers, and push the rest onto the stack. Loop thru args 2785130803Smarcel from first to last. */ 2786130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 2787130803Smarcel { 2788130803Smarcel char *val; 2789130803Smarcel char valbuf[MAX_REGISTER_SIZE]; 2790130803Smarcel struct value *arg = args[argnum]; 2791130803Smarcel struct type *arg_type = check_typedef (VALUE_TYPE (arg)); 2792130803Smarcel int len = TYPE_LENGTH (arg_type); 2793130803Smarcel enum type_code typecode = TYPE_CODE (arg_type); 2794130803Smarcel 2795130803Smarcel if (mips_debug) 2796130803Smarcel fprintf_unfiltered (gdb_stdlog, 2797130803Smarcel "mips_eabi_push_dummy_call: %d len=%d type=%d", 2798130803Smarcel argnum + 1, len, (int) typecode); 2799130803Smarcel 2800130803Smarcel /* The EABI passes structures that do not fit in a register by 2801130803Smarcel reference. */ 2802130803Smarcel if (len > mips_saved_regsize (tdep) 2803130803Smarcel && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) 2804130803Smarcel { 2805130803Smarcel store_unsigned_integer (valbuf, mips_saved_regsize (tdep), 2806130803Smarcel VALUE_ADDRESS (arg)); 2807130803Smarcel typecode = TYPE_CODE_PTR; 2808130803Smarcel len = mips_saved_regsize (tdep); 2809130803Smarcel val = valbuf; 2810130803Smarcel if (mips_debug) 2811130803Smarcel fprintf_unfiltered (gdb_stdlog, " push"); 2812130803Smarcel } 2813130803Smarcel else 2814130803Smarcel val = (char *) VALUE_CONTENTS (arg); 2815130803Smarcel 2816130803Smarcel /* 32-bit ABIs always start floating point arguments in an 2817130803Smarcel even-numbered floating point register. Round the FP register 2818130803Smarcel up before the check to see if there are any FP registers 2819130803Smarcel left. Non MIPS_EABI targets also pass the FP in the integer 2820130803Smarcel registers so also round up normal registers. */ 2821130803Smarcel if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) 2822130803Smarcel { 2823130803Smarcel if ((float_argreg & 1)) 2824130803Smarcel float_argreg++; 2825130803Smarcel } 2826130803Smarcel 2827130803Smarcel /* Floating point arguments passed in registers have to be 2828130803Smarcel treated specially. On 32-bit architectures, doubles 2829130803Smarcel are passed in register pairs; the even register gets 2830130803Smarcel the low word, and the odd register gets the high word. 2831130803Smarcel On non-EABI processors, the first two floating point arguments are 2832130803Smarcel also copied to general registers, because MIPS16 functions 2833130803Smarcel don't use float registers for arguments. This duplication of 2834130803Smarcel arguments in general registers can't hurt non-MIPS16 functions 2835130803Smarcel because those registers are normally skipped. */ 2836130803Smarcel /* MIPS_EABI squeezes a struct that contains a single floating 2837130803Smarcel point value into an FP register instead of pushing it onto the 2838130803Smarcel stack. */ 2839130803Smarcel if (fp_register_arg_p (typecode, arg_type) 2840130803Smarcel && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) 2841130803Smarcel { 2842130803Smarcel if (!FP_REGISTER_DOUBLE && len == 8) 2843130803Smarcel { 2844130803Smarcel int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; 2845130803Smarcel unsigned long regval; 2846130803Smarcel 2847130803Smarcel /* Write the low word of the double to the even register(s). */ 2848130803Smarcel regval = extract_unsigned_integer (val + low_offset, 4); 2849130803Smarcel if (mips_debug) 2850130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 2851130803Smarcel float_argreg, phex (regval, 4)); 2852130803Smarcel write_register (float_argreg++, regval); 2853130803Smarcel 2854130803Smarcel /* Write the high word of the double to the odd register(s). */ 2855130803Smarcel regval = extract_unsigned_integer (val + 4 - low_offset, 4); 2856130803Smarcel if (mips_debug) 2857130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 2858130803Smarcel float_argreg, phex (regval, 4)); 2859130803Smarcel write_register (float_argreg++, regval); 2860130803Smarcel } 2861130803Smarcel else 2862130803Smarcel { 2863130803Smarcel /* This is a floating point value that fits entirely 2864130803Smarcel in a single register. */ 2865130803Smarcel /* On 32 bit ABI's the float_argreg is further adjusted 2866130803Smarcel above to ensure that it is even register aligned. */ 2867130803Smarcel LONGEST regval = extract_unsigned_integer (val, len); 2868130803Smarcel if (mips_debug) 2869130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 2870130803Smarcel float_argreg, phex (regval, len)); 2871130803Smarcel write_register (float_argreg++, regval); 2872130803Smarcel } 2873130803Smarcel } 2874130803Smarcel else 2875130803Smarcel { 2876130803Smarcel /* Copy the argument to general registers or the stack in 2877130803Smarcel register-sized pieces. Large arguments are split between 2878130803Smarcel registers and stack. */ 2879130803Smarcel /* Note: structs whose size is not a multiple of 2880130803Smarcel mips_regsize() are treated specially: Irix cc passes them 2881130803Smarcel in registers where gcc sometimes puts them on the stack. 2882130803Smarcel For maximum compatibility, we will put them in both 2883130803Smarcel places. */ 2884130803Smarcel int odd_sized_struct = ((len > mips_saved_regsize (tdep)) 2885130803Smarcel && (len % mips_saved_regsize (tdep) != 0)); 2886130803Smarcel 2887130803Smarcel /* Note: Floating-point values that didn't fit into an FP 2888130803Smarcel register are only written to memory. */ 2889130803Smarcel while (len > 0) 2890130803Smarcel { 2891130803Smarcel /* Remember if the argument was written to the stack. */ 2892130803Smarcel int stack_used_p = 0; 2893130803Smarcel int partial_len = (len < mips_saved_regsize (tdep) 2894130803Smarcel ? len : mips_saved_regsize (tdep)); 2895130803Smarcel 2896130803Smarcel if (mips_debug) 2897130803Smarcel fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 2898130803Smarcel partial_len); 2899130803Smarcel 2900130803Smarcel /* Write this portion of the argument to the stack. */ 2901130803Smarcel if (argreg > MIPS_LAST_ARG_REGNUM 2902130803Smarcel || odd_sized_struct 2903130803Smarcel || fp_register_arg_p (typecode, arg_type)) 2904130803Smarcel { 2905130803Smarcel /* Should shorter than int integer values be 2906130803Smarcel promoted to int before being stored? */ 2907130803Smarcel int longword_offset = 0; 2908130803Smarcel CORE_ADDR addr; 2909130803Smarcel stack_used_p = 1; 2910130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 2911130803Smarcel { 2912130803Smarcel if (mips_stack_argsize (tdep) == 8 2913130803Smarcel && (typecode == TYPE_CODE_INT 2914130803Smarcel || typecode == TYPE_CODE_PTR 2915130803Smarcel || typecode == TYPE_CODE_FLT) && len <= 4) 2916130803Smarcel longword_offset = mips_stack_argsize (tdep) - len; 2917130803Smarcel else if ((typecode == TYPE_CODE_STRUCT 2918130803Smarcel || typecode == TYPE_CODE_UNION) 2919130803Smarcel && (TYPE_LENGTH (arg_type) 2920130803Smarcel < mips_stack_argsize (tdep))) 2921130803Smarcel longword_offset = mips_stack_argsize (tdep) - len; 2922130803Smarcel } 2923130803Smarcel 2924130803Smarcel if (mips_debug) 2925130803Smarcel { 2926130803Smarcel fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", 2927130803Smarcel paddr_nz (stack_offset)); 2928130803Smarcel fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", 2929130803Smarcel paddr_nz (longword_offset)); 2930130803Smarcel } 2931130803Smarcel 2932130803Smarcel addr = sp + stack_offset + longword_offset; 2933130803Smarcel 2934130803Smarcel if (mips_debug) 2935130803Smarcel { 2936130803Smarcel int i; 2937130803Smarcel fprintf_unfiltered (gdb_stdlog, " @0x%s ", 2938130803Smarcel paddr_nz (addr)); 2939130803Smarcel for (i = 0; i < partial_len; i++) 2940130803Smarcel { 2941130803Smarcel fprintf_unfiltered (gdb_stdlog, "%02x", 2942130803Smarcel val[i] & 0xff); 2943130803Smarcel } 2944130803Smarcel } 2945130803Smarcel write_memory (addr, val, partial_len); 2946130803Smarcel } 2947130803Smarcel 2948130803Smarcel /* Note!!! This is NOT an else clause. Odd sized 2949130803Smarcel structs may go thru BOTH paths. Floating point 2950130803Smarcel arguments will not. */ 2951130803Smarcel /* Write this portion of the argument to a general 2952130803Smarcel purpose register. */ 2953130803Smarcel if (argreg <= MIPS_LAST_ARG_REGNUM 2954130803Smarcel && !fp_register_arg_p (typecode, arg_type)) 2955130803Smarcel { 2956130803Smarcel LONGEST regval = 2957130803Smarcel extract_unsigned_integer (val, partial_len); 2958130803Smarcel 2959130803Smarcel if (mips_debug) 2960130803Smarcel fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 2961130803Smarcel argreg, 2962130803Smarcel phex (regval, 2963130803Smarcel mips_saved_regsize (tdep))); 2964130803Smarcel write_register (argreg, regval); 2965130803Smarcel argreg++; 2966130803Smarcel } 2967130803Smarcel 2968130803Smarcel len -= partial_len; 2969130803Smarcel val += partial_len; 2970130803Smarcel 2971130803Smarcel /* Compute the the offset into the stack at which we 2972130803Smarcel will copy the next parameter. 2973130803Smarcel 2974130803Smarcel In the new EABI (and the NABI32), the stack_offset 2975130803Smarcel only needs to be adjusted when it has been used. */ 2976130803Smarcel 2977130803Smarcel if (stack_used_p) 2978130803Smarcel stack_offset += align_up (partial_len, 2979130803Smarcel mips_stack_argsize (tdep)); 2980130803Smarcel } 2981130803Smarcel } 2982130803Smarcel if (mips_debug) 2983130803Smarcel fprintf_unfiltered (gdb_stdlog, "\n"); 2984130803Smarcel } 2985130803Smarcel 2986130803Smarcel regcache_cooked_write_signed (regcache, SP_REGNUM, sp); 2987130803Smarcel 2988130803Smarcel /* Return adjusted stack pointer. */ 2989130803Smarcel return sp; 2990130803Smarcel} 2991130803Smarcel 2992130803Smarcel/* Given a return value in `regbuf' with a type `valtype', extract and 2993130803Smarcel copy its value into `valbuf'. */ 2994130803Smarcel 2995130803Smarcelstatic void 2996130803Smarcelmips_eabi_extract_return_value (struct type *valtype, 2997130803Smarcel char regbuf[], char *valbuf) 2998130803Smarcel{ 2999130803Smarcel struct return_value_word lo; 3000130803Smarcel struct return_value_word hi; 3001130803Smarcel return_value_location (valtype, &hi, &lo); 3002130803Smarcel 3003130803Smarcel memcpy (valbuf + lo.buf_offset, 3004130803Smarcel regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + 3005130803Smarcel lo.reg_offset, lo.len); 3006130803Smarcel 3007130803Smarcel if (hi.len > 0) 3008130803Smarcel memcpy (valbuf + hi.buf_offset, 3009130803Smarcel regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + 3010130803Smarcel hi.reg_offset, hi.len); 3011130803Smarcel} 3012130803Smarcel 3013130803Smarcel/* Given a return value in `valbuf' with a type `valtype', write it's 3014130803Smarcel value into the appropriate register. */ 3015130803Smarcel 3016130803Smarcelstatic void 3017130803Smarcelmips_eabi_store_return_value (struct type *valtype, char *valbuf) 3018130803Smarcel{ 3019130803Smarcel char raw_buffer[MAX_REGISTER_SIZE]; 3020130803Smarcel struct return_value_word lo; 3021130803Smarcel struct return_value_word hi; 3022130803Smarcel return_value_location (valtype, &hi, &lo); 3023130803Smarcel 3024130803Smarcel memset (raw_buffer, 0, sizeof (raw_buffer)); 3025130803Smarcel memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); 3026130803Smarcel deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), 3027130803Smarcel raw_buffer, register_size (current_gdbarch, 3028130803Smarcel lo.reg)); 3029130803Smarcel 3030130803Smarcel if (hi.len > 0) 3031130803Smarcel { 3032130803Smarcel memset (raw_buffer, 0, sizeof (raw_buffer)); 3033130803Smarcel memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); 3034130803Smarcel deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), 3035130803Smarcel raw_buffer, 3036130803Smarcel register_size (current_gdbarch, 3037130803Smarcel hi.reg)); 3038130803Smarcel } 3039130803Smarcel} 3040130803Smarcel 3041130803Smarcel/* N32/N64 ABI stuff. */ 3042130803Smarcel 3043130803Smarcelstatic CORE_ADDR 3044130803Smarcelmips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 3045130803Smarcel struct regcache *regcache, CORE_ADDR bp_addr, 3046130803Smarcel int nargs, struct value **args, CORE_ADDR sp, 3047130803Smarcel int struct_return, CORE_ADDR struct_addr) 3048130803Smarcel{ 3049130803Smarcel int argreg; 3050130803Smarcel int float_argreg; 3051130803Smarcel int argnum; 3052130803Smarcel int len = 0; 3053130803Smarcel int stack_offset = 0; 3054130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3055130803Smarcel 3056130803Smarcel /* For shared libraries, "t9" needs to point at the function 3057130803Smarcel address. */ 3058130803Smarcel regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); 3059130803Smarcel 3060130803Smarcel /* Set the return address register to point to the entry point of 3061130803Smarcel the program, where a breakpoint lies in wait. */ 3062130803Smarcel regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); 3063130803Smarcel 3064130803Smarcel /* First ensure that the stack and structure return address (if any) 3065130803Smarcel are properly aligned. The stack has to be at least 64-bit 3066130803Smarcel aligned even on 32-bit machines, because doubles must be 64-bit 3067130803Smarcel aligned. For n32 and n64, stack frames need to be 128-bit 3068130803Smarcel aligned, so we round to this widest known alignment. */ 3069130803Smarcel 3070130803Smarcel sp = align_down (sp, 16); 3071130803Smarcel struct_addr = align_down (struct_addr, 16); 3072130803Smarcel 3073130803Smarcel /* Now make space on the stack for the args. */ 3074130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 3075130803Smarcel len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 3076130803Smarcel mips_stack_argsize (tdep)); 3077130803Smarcel sp -= align_up (len, 16); 3078130803Smarcel 3079130803Smarcel if (mips_debug) 3080130803Smarcel fprintf_unfiltered (gdb_stdlog, 3081130803Smarcel "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", 3082130803Smarcel paddr_nz (sp), (long) align_up (len, 16)); 3083130803Smarcel 3084130803Smarcel /* Initialize the integer and float register pointers. */ 3085130803Smarcel argreg = A0_REGNUM; 3086130803Smarcel float_argreg = mips_fpa0_regnum (current_gdbarch); 3087130803Smarcel 3088130803Smarcel /* The struct_return pointer occupies the first parameter-passing reg. */ 3089130803Smarcel if (struct_return) 3090130803Smarcel { 3091130803Smarcel if (mips_debug) 3092130803Smarcel fprintf_unfiltered (gdb_stdlog, 3093130803Smarcel "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", 3094130803Smarcel argreg, paddr_nz (struct_addr)); 3095130803Smarcel write_register (argreg++, struct_addr); 3096130803Smarcel } 3097130803Smarcel 3098130803Smarcel /* Now load as many as possible of the first arguments into 3099130803Smarcel registers, and push the rest onto the stack. Loop thru args 3100130803Smarcel from first to last. */ 3101130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 3102130803Smarcel { 3103130803Smarcel char *val; 3104130803Smarcel struct value *arg = args[argnum]; 3105130803Smarcel struct type *arg_type = check_typedef (VALUE_TYPE (arg)); 3106130803Smarcel int len = TYPE_LENGTH (arg_type); 3107130803Smarcel enum type_code typecode = TYPE_CODE (arg_type); 3108130803Smarcel 3109130803Smarcel if (mips_debug) 3110130803Smarcel fprintf_unfiltered (gdb_stdlog, 3111130803Smarcel "mips_n32n64_push_dummy_call: %d len=%d type=%d", 3112130803Smarcel argnum + 1, len, (int) typecode); 3113130803Smarcel 3114130803Smarcel val = (char *) VALUE_CONTENTS (arg); 3115130803Smarcel 3116130803Smarcel if (fp_register_arg_p (typecode, arg_type) 3117130803Smarcel && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) 3118130803Smarcel { 3119130803Smarcel /* This is a floating point value that fits entirely 3120130803Smarcel in a single register. */ 3121130803Smarcel /* On 32 bit ABI's the float_argreg is further adjusted 3122130803Smarcel above to ensure that it is even register aligned. */ 3123130803Smarcel LONGEST regval = extract_unsigned_integer (val, len); 3124130803Smarcel if (mips_debug) 3125130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3126130803Smarcel float_argreg, phex (regval, len)); 3127130803Smarcel write_register (float_argreg++, regval); 3128130803Smarcel 3129130803Smarcel if (mips_debug) 3130130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3131130803Smarcel argreg, phex (regval, len)); 3132130803Smarcel write_register (argreg, regval); 3133130803Smarcel argreg += 1; 3134130803Smarcel } 3135130803Smarcel else 3136130803Smarcel { 3137130803Smarcel /* Copy the argument to general registers or the stack in 3138130803Smarcel register-sized pieces. Large arguments are split between 3139130803Smarcel registers and stack. */ 3140130803Smarcel /* Note: structs whose size is not a multiple of 3141130803Smarcel mips_regsize() are treated specially: Irix cc passes them 3142130803Smarcel in registers where gcc sometimes puts them on the stack. 3143130803Smarcel For maximum compatibility, we will put them in both 3144130803Smarcel places. */ 3145130803Smarcel int odd_sized_struct = ((len > mips_saved_regsize (tdep)) 3146130803Smarcel && (len % mips_saved_regsize (tdep) != 0)); 3147130803Smarcel /* Note: Floating-point values that didn't fit into an FP 3148130803Smarcel register are only written to memory. */ 3149130803Smarcel while (len > 0) 3150130803Smarcel { 3151130803Smarcel /* Rememer if the argument was written to the stack. */ 3152130803Smarcel int stack_used_p = 0; 3153130803Smarcel int partial_len = (len < mips_saved_regsize (tdep) 3154130803Smarcel ? len : mips_saved_regsize (tdep)); 3155130803Smarcel 3156130803Smarcel if (mips_debug) 3157130803Smarcel fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 3158130803Smarcel partial_len); 3159130803Smarcel 3160130803Smarcel /* Write this portion of the argument to the stack. */ 3161130803Smarcel if (argreg > MIPS_LAST_ARG_REGNUM 3162130803Smarcel || odd_sized_struct 3163130803Smarcel || fp_register_arg_p (typecode, arg_type)) 3164130803Smarcel { 3165130803Smarcel /* Should shorter than int integer values be 3166130803Smarcel promoted to int before being stored? */ 3167130803Smarcel int longword_offset = 0; 3168130803Smarcel CORE_ADDR addr; 3169130803Smarcel stack_used_p = 1; 3170130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 3171130803Smarcel { 3172130803Smarcel if (mips_stack_argsize (tdep) == 8 3173130803Smarcel && (typecode == TYPE_CODE_INT 3174130803Smarcel || typecode == TYPE_CODE_PTR 3175130803Smarcel || typecode == TYPE_CODE_FLT) && len <= 4) 3176130803Smarcel longword_offset = mips_stack_argsize (tdep) - len; 3177130803Smarcel } 3178130803Smarcel 3179130803Smarcel if (mips_debug) 3180130803Smarcel { 3181130803Smarcel fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", 3182130803Smarcel paddr_nz (stack_offset)); 3183130803Smarcel fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", 3184130803Smarcel paddr_nz (longword_offset)); 3185130803Smarcel } 3186130803Smarcel 3187130803Smarcel addr = sp + stack_offset + longword_offset; 3188130803Smarcel 3189130803Smarcel if (mips_debug) 3190130803Smarcel { 3191130803Smarcel int i; 3192130803Smarcel fprintf_unfiltered (gdb_stdlog, " @0x%s ", 3193130803Smarcel paddr_nz (addr)); 3194130803Smarcel for (i = 0; i < partial_len; i++) 3195130803Smarcel { 3196130803Smarcel fprintf_unfiltered (gdb_stdlog, "%02x", 3197130803Smarcel val[i] & 0xff); 3198130803Smarcel } 3199130803Smarcel } 3200130803Smarcel write_memory (addr, val, partial_len); 3201130803Smarcel } 3202130803Smarcel 3203130803Smarcel /* Note!!! This is NOT an else clause. Odd sized 3204130803Smarcel structs may go thru BOTH paths. Floating point 3205130803Smarcel arguments will not. */ 3206130803Smarcel /* Write this portion of the argument to a general 3207130803Smarcel purpose register. */ 3208130803Smarcel if (argreg <= MIPS_LAST_ARG_REGNUM 3209130803Smarcel && !fp_register_arg_p (typecode, arg_type)) 3210130803Smarcel { 3211130803Smarcel LONGEST regval = 3212130803Smarcel extract_unsigned_integer (val, partial_len); 3213130803Smarcel 3214130803Smarcel /* A non-floating-point argument being passed in a 3215130803Smarcel general register. If a struct or union, and if 3216130803Smarcel the remaining length is smaller than the register 3217130803Smarcel size, we have to adjust the register value on 3218130803Smarcel big endian targets. 3219130803Smarcel 3220130803Smarcel It does not seem to be necessary to do the 3221130803Smarcel same for integral types. 3222130803Smarcel 3223130803Smarcel cagney/2001-07-23: gdb/179: Also, GCC, when 3224130803Smarcel outputting LE O32 with sizeof (struct) < 3225130803Smarcel mips_saved_regsize(), generates a left shift as 3226130803Smarcel part of storing the argument in a register a 3227130803Smarcel register (the left shift isn't generated when 3228130803Smarcel sizeof (struct) >= mips_saved_regsize()). Since 3229130803Smarcel it is quite possible that this is GCC 3230130803Smarcel contradicting the LE/O32 ABI, GDB has not been 3231130803Smarcel adjusted to accommodate this. Either someone 3232130803Smarcel needs to demonstrate that the LE/O32 ABI 3233130803Smarcel specifies such a left shift OR this new ABI gets 3234130803Smarcel identified as such and GDB gets tweaked 3235130803Smarcel accordingly. */ 3236130803Smarcel 3237130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 3238130803Smarcel && partial_len < mips_saved_regsize (tdep) 3239130803Smarcel && (typecode == TYPE_CODE_STRUCT || 3240130803Smarcel typecode == TYPE_CODE_UNION)) 3241130803Smarcel regval <<= ((mips_saved_regsize (tdep) - partial_len) * 3242130803Smarcel TARGET_CHAR_BIT); 3243130803Smarcel 3244130803Smarcel if (mips_debug) 3245130803Smarcel fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 3246130803Smarcel argreg, 3247130803Smarcel phex (regval, 3248130803Smarcel mips_saved_regsize (tdep))); 3249130803Smarcel write_register (argreg, regval); 3250130803Smarcel argreg++; 3251130803Smarcel } 3252130803Smarcel 3253130803Smarcel len -= partial_len; 3254130803Smarcel val += partial_len; 3255130803Smarcel 3256130803Smarcel /* Compute the the offset into the stack at which we 3257130803Smarcel will copy the next parameter. 3258130803Smarcel 3259130803Smarcel In N32 (N64?), the stack_offset only needs to be 3260130803Smarcel adjusted when it has been used. */ 3261130803Smarcel 3262130803Smarcel if (stack_used_p) 3263130803Smarcel stack_offset += align_up (partial_len, 3264130803Smarcel mips_stack_argsize (tdep)); 3265130803Smarcel } 3266130803Smarcel } 3267130803Smarcel if (mips_debug) 3268130803Smarcel fprintf_unfiltered (gdb_stdlog, "\n"); 3269130803Smarcel } 3270130803Smarcel 3271130803Smarcel regcache_cooked_write_signed (regcache, SP_REGNUM, sp); 3272130803Smarcel 3273130803Smarcel /* Return adjusted stack pointer. */ 3274130803Smarcel return sp; 3275130803Smarcel} 3276130803Smarcel 3277130803Smarcelstatic enum return_value_convention 3278130803Smarcelmips_n32n64_return_value (struct gdbarch *gdbarch, 3279130803Smarcel struct type *type, struct regcache *regcache, 3280130803Smarcel void *readbuf, const void *writebuf) 3281130803Smarcel{ 3282130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 3283130803Smarcel if (TYPE_CODE (type) == TYPE_CODE_STRUCT 3284130803Smarcel || TYPE_CODE (type) == TYPE_CODE_UNION 3285130803Smarcel || TYPE_CODE (type) == TYPE_CODE_ARRAY 3286130803Smarcel || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep)) 3287130803Smarcel return RETURN_VALUE_STRUCT_CONVENTION; 3288130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_FLT 3289130803Smarcel && tdep->mips_fpu_type != MIPS_FPU_NONE) 3290130803Smarcel { 3291130803Smarcel /* A floating-point value belongs in the least significant part 3292130803Smarcel of FP0. */ 3293130803Smarcel if (mips_debug) 3294130803Smarcel fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 3295130803Smarcel mips_xfer_register (regcache, 3296130803Smarcel NUM_REGS + mips_regnum (current_gdbarch)->fp0, 3297130803Smarcel TYPE_LENGTH (type), 3298130803Smarcel TARGET_BYTE_ORDER, readbuf, writebuf, 0); 3299130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3300130803Smarcel } 3301130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 3302130803Smarcel && TYPE_NFIELDS (type) <= 2 3303130803Smarcel && TYPE_NFIELDS (type) >= 1 3304130803Smarcel && ((TYPE_NFIELDS (type) == 1 3305130803Smarcel && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) 3306130803Smarcel == TYPE_CODE_FLT)) 3307130803Smarcel || (TYPE_NFIELDS (type) == 2 3308130803Smarcel && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) 3309130803Smarcel == TYPE_CODE_FLT) 3310130803Smarcel && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) 3311130803Smarcel == TYPE_CODE_FLT))) 3312130803Smarcel && tdep->mips_fpu_type != MIPS_FPU_NONE) 3313130803Smarcel { 3314130803Smarcel /* A struct that contains one or two floats. Each value is part 3315130803Smarcel in the least significant part of their floating point 3316130803Smarcel register.. */ 3317130803Smarcel int regnum; 3318130803Smarcel int field; 3319130803Smarcel for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; 3320130803Smarcel field < TYPE_NFIELDS (type); field++, regnum += 2) 3321130803Smarcel { 3322130803Smarcel int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) 3323130803Smarcel / TARGET_CHAR_BIT); 3324130803Smarcel if (mips_debug) 3325130803Smarcel fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", 3326130803Smarcel offset); 3327130803Smarcel mips_xfer_register (regcache, NUM_REGS + regnum, 3328130803Smarcel TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), 3329130803Smarcel TARGET_BYTE_ORDER, readbuf, writebuf, offset); 3330130803Smarcel } 3331130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3332130803Smarcel } 3333130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 3334130803Smarcel || TYPE_CODE (type) == TYPE_CODE_UNION) 3335130803Smarcel { 3336130803Smarcel /* A structure or union. Extract the left justified value, 3337130803Smarcel regardless of the byte order. I.e. DO NOT USE 3338130803Smarcel mips_xfer_lower. */ 3339130803Smarcel int offset; 3340130803Smarcel int regnum; 3341130803Smarcel for (offset = 0, regnum = V0_REGNUM; 3342130803Smarcel offset < TYPE_LENGTH (type); 3343130803Smarcel offset += register_size (current_gdbarch, regnum), regnum++) 3344130803Smarcel { 3345130803Smarcel int xfer = register_size (current_gdbarch, regnum); 3346130803Smarcel if (offset + xfer > TYPE_LENGTH (type)) 3347130803Smarcel xfer = TYPE_LENGTH (type) - offset; 3348130803Smarcel if (mips_debug) 3349130803Smarcel fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", 3350130803Smarcel offset, xfer, regnum); 3351130803Smarcel mips_xfer_register (regcache, NUM_REGS + regnum, xfer, 3352130803Smarcel BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); 3353130803Smarcel } 3354130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3355130803Smarcel } 3356130803Smarcel else 3357130803Smarcel { 3358130803Smarcel /* A scalar extract each part but least-significant-byte 3359130803Smarcel justified. */ 3360130803Smarcel int offset; 3361130803Smarcel int regnum; 3362130803Smarcel for (offset = 0, regnum = V0_REGNUM; 3363130803Smarcel offset < TYPE_LENGTH (type); 3364130803Smarcel offset += register_size (current_gdbarch, regnum), regnum++) 3365130803Smarcel { 3366130803Smarcel int xfer = register_size (current_gdbarch, regnum); 3367130803Smarcel if (offset + xfer > TYPE_LENGTH (type)) 3368130803Smarcel xfer = TYPE_LENGTH (type) - offset; 3369130803Smarcel if (mips_debug) 3370130803Smarcel fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 3371130803Smarcel offset, xfer, regnum); 3372130803Smarcel mips_xfer_register (regcache, NUM_REGS + regnum, xfer, 3373130803Smarcel TARGET_BYTE_ORDER, readbuf, writebuf, offset); 3374130803Smarcel } 3375130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3376130803Smarcel } 3377130803Smarcel} 3378130803Smarcel 3379130803Smarcel/* O32 ABI stuff. */ 3380130803Smarcel 3381130803Smarcelstatic CORE_ADDR 3382130803Smarcelmips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 3383130803Smarcel struct regcache *regcache, CORE_ADDR bp_addr, 3384130803Smarcel int nargs, struct value **args, CORE_ADDR sp, 3385130803Smarcel int struct_return, CORE_ADDR struct_addr) 3386130803Smarcel{ 3387130803Smarcel int argreg; 3388130803Smarcel int float_argreg; 3389130803Smarcel int argnum; 3390130803Smarcel int len = 0; 3391130803Smarcel int stack_offset = 0; 3392130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3393130803Smarcel 3394130803Smarcel /* For shared libraries, "t9" needs to point at the function 3395130803Smarcel address. */ 3396130803Smarcel regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); 3397130803Smarcel 3398130803Smarcel /* Set the return address register to point to the entry point of 3399130803Smarcel the program, where a breakpoint lies in wait. */ 3400130803Smarcel regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); 3401130803Smarcel 3402130803Smarcel /* First ensure that the stack and structure return address (if any) 3403130803Smarcel are properly aligned. The stack has to be at least 64-bit 3404130803Smarcel aligned even on 32-bit machines, because doubles must be 64-bit 3405130803Smarcel aligned. For n32 and n64, stack frames need to be 128-bit 3406130803Smarcel aligned, so we round to this widest known alignment. */ 3407130803Smarcel 3408130803Smarcel sp = align_down (sp, 16); 3409130803Smarcel struct_addr = align_down (struct_addr, 16); 3410130803Smarcel 3411130803Smarcel /* Now make space on the stack for the args. */ 3412130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 3413130803Smarcel len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 3414130803Smarcel mips_stack_argsize (tdep)); 3415130803Smarcel sp -= align_up (len, 16); 3416130803Smarcel 3417130803Smarcel if (mips_debug) 3418130803Smarcel fprintf_unfiltered (gdb_stdlog, 3419130803Smarcel "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", 3420130803Smarcel paddr_nz (sp), (long) align_up (len, 16)); 3421130803Smarcel 3422130803Smarcel /* Initialize the integer and float register pointers. */ 3423130803Smarcel argreg = A0_REGNUM; 3424130803Smarcel float_argreg = mips_fpa0_regnum (current_gdbarch); 3425130803Smarcel 3426130803Smarcel /* The struct_return pointer occupies the first parameter-passing reg. */ 3427130803Smarcel if (struct_return) 3428130803Smarcel { 3429130803Smarcel if (mips_debug) 3430130803Smarcel fprintf_unfiltered (gdb_stdlog, 3431130803Smarcel "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", 3432130803Smarcel argreg, paddr_nz (struct_addr)); 3433130803Smarcel write_register (argreg++, struct_addr); 3434130803Smarcel stack_offset += mips_stack_argsize (tdep); 3435130803Smarcel } 3436130803Smarcel 3437130803Smarcel /* Now load as many as possible of the first arguments into 3438130803Smarcel registers, and push the rest onto the stack. Loop thru args 3439130803Smarcel from first to last. */ 3440130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 3441130803Smarcel { 3442130803Smarcel char *val; 3443130803Smarcel struct value *arg = args[argnum]; 3444130803Smarcel struct type *arg_type = check_typedef (VALUE_TYPE (arg)); 3445130803Smarcel int len = TYPE_LENGTH (arg_type); 3446130803Smarcel enum type_code typecode = TYPE_CODE (arg_type); 3447130803Smarcel 3448130803Smarcel if (mips_debug) 3449130803Smarcel fprintf_unfiltered (gdb_stdlog, 3450130803Smarcel "mips_o32_push_dummy_call: %d len=%d type=%d", 3451130803Smarcel argnum + 1, len, (int) typecode); 3452130803Smarcel 3453130803Smarcel val = (char *) VALUE_CONTENTS (arg); 3454130803Smarcel 3455130803Smarcel /* 32-bit ABIs always start floating point arguments in an 3456130803Smarcel even-numbered floating point register. Round the FP register 3457130803Smarcel up before the check to see if there are any FP registers 3458130803Smarcel left. O32/O64 targets also pass the FP in the integer 3459130803Smarcel registers so also round up normal registers. */ 3460130803Smarcel if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) 3461130803Smarcel { 3462130803Smarcel if ((float_argreg & 1)) 3463130803Smarcel float_argreg++; 3464130803Smarcel } 3465130803Smarcel 3466130803Smarcel /* Floating point arguments passed in registers have to be 3467130803Smarcel treated specially. On 32-bit architectures, doubles 3468130803Smarcel are passed in register pairs; the even register gets 3469130803Smarcel the low word, and the odd register gets the high word. 3470130803Smarcel On O32/O64, the first two floating point arguments are 3471130803Smarcel also copied to general registers, because MIPS16 functions 3472130803Smarcel don't use float registers for arguments. This duplication of 3473130803Smarcel arguments in general registers can't hurt non-MIPS16 functions 3474130803Smarcel because those registers are normally skipped. */ 3475130803Smarcel 3476130803Smarcel if (fp_register_arg_p (typecode, arg_type) 3477130803Smarcel && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) 3478130803Smarcel { 3479130803Smarcel if (!FP_REGISTER_DOUBLE && len == 8) 3480130803Smarcel { 3481130803Smarcel int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; 3482130803Smarcel unsigned long regval; 3483130803Smarcel 3484130803Smarcel /* Write the low word of the double to the even register(s). */ 3485130803Smarcel regval = extract_unsigned_integer (val + low_offset, 4); 3486130803Smarcel if (mips_debug) 3487130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3488130803Smarcel float_argreg, phex (regval, 4)); 3489130803Smarcel write_register (float_argreg++, regval); 3490130803Smarcel if (mips_debug) 3491130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3492130803Smarcel argreg, phex (regval, 4)); 3493130803Smarcel write_register (argreg++, regval); 3494130803Smarcel 3495130803Smarcel /* Write the high word of the double to the odd register(s). */ 3496130803Smarcel regval = extract_unsigned_integer (val + 4 - low_offset, 4); 3497130803Smarcel if (mips_debug) 3498130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3499130803Smarcel float_argreg, phex (regval, 4)); 3500130803Smarcel write_register (float_argreg++, regval); 3501130803Smarcel 3502130803Smarcel if (mips_debug) 3503130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3504130803Smarcel argreg, phex (regval, 4)); 3505130803Smarcel write_register (argreg++, regval); 3506130803Smarcel } 3507130803Smarcel else 3508130803Smarcel { 3509130803Smarcel /* This is a floating point value that fits entirely 3510130803Smarcel in a single register. */ 3511130803Smarcel /* On 32 bit ABI's the float_argreg is further adjusted 3512130803Smarcel above to ensure that it is even register aligned. */ 3513130803Smarcel LONGEST regval = extract_unsigned_integer (val, len); 3514130803Smarcel if (mips_debug) 3515130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3516130803Smarcel float_argreg, phex (regval, len)); 3517130803Smarcel write_register (float_argreg++, regval); 3518130803Smarcel /* CAGNEY: 32 bit MIPS ABI's always reserve two FP 3519130803Smarcel registers for each argument. The below is (my 3520130803Smarcel guess) to ensure that the corresponding integer 3521130803Smarcel register has reserved the same space. */ 3522130803Smarcel if (mips_debug) 3523130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3524130803Smarcel argreg, phex (regval, len)); 3525130803Smarcel write_register (argreg, regval); 3526130803Smarcel argreg += FP_REGISTER_DOUBLE ? 1 : 2; 3527130803Smarcel } 3528130803Smarcel /* Reserve space for the FP register. */ 3529130803Smarcel stack_offset += align_up (len, mips_stack_argsize (tdep)); 3530130803Smarcel } 3531130803Smarcel else 3532130803Smarcel { 3533130803Smarcel /* Copy the argument to general registers or the stack in 3534130803Smarcel register-sized pieces. Large arguments are split between 3535130803Smarcel registers and stack. */ 3536130803Smarcel /* Note: structs whose size is not a multiple of 3537130803Smarcel mips_regsize() are treated specially: Irix cc passes them 3538130803Smarcel in registers where gcc sometimes puts them on the stack. 3539130803Smarcel For maximum compatibility, we will put them in both 3540130803Smarcel places. */ 3541130803Smarcel int odd_sized_struct = ((len > mips_saved_regsize (tdep)) 3542130803Smarcel && (len % mips_saved_regsize (tdep) != 0)); 3543130803Smarcel /* Structures should be aligned to eight bytes (even arg registers) 3544130803Smarcel on MIPS_ABI_O32, if their first member has double precision. */ 3545130803Smarcel if (mips_saved_regsize (tdep) < 8 3546130803Smarcel && mips_type_needs_double_align (arg_type)) 3547130803Smarcel { 3548130803Smarcel if ((argreg & 1)) 3549130803Smarcel argreg++; 3550130803Smarcel } 3551130803Smarcel /* Note: Floating-point values that didn't fit into an FP 3552130803Smarcel register are only written to memory. */ 3553130803Smarcel while (len > 0) 3554130803Smarcel { 3555130803Smarcel /* Remember if the argument was written to the stack. */ 3556130803Smarcel int stack_used_p = 0; 3557130803Smarcel int partial_len = (len < mips_saved_regsize (tdep) 3558130803Smarcel ? len : mips_saved_regsize (tdep)); 3559130803Smarcel 3560130803Smarcel if (mips_debug) 3561130803Smarcel fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 3562130803Smarcel partial_len); 3563130803Smarcel 3564130803Smarcel /* Write this portion of the argument to the stack. */ 3565130803Smarcel if (argreg > MIPS_LAST_ARG_REGNUM 3566130803Smarcel || odd_sized_struct 3567130803Smarcel || fp_register_arg_p (typecode, arg_type)) 3568130803Smarcel { 3569130803Smarcel /* Should shorter than int integer values be 3570130803Smarcel promoted to int before being stored? */ 3571130803Smarcel int longword_offset = 0; 3572130803Smarcel CORE_ADDR addr; 3573130803Smarcel stack_used_p = 1; 3574130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 3575130803Smarcel { 3576130803Smarcel if (mips_stack_argsize (tdep) == 8 3577130803Smarcel && (typecode == TYPE_CODE_INT 3578130803Smarcel || typecode == TYPE_CODE_PTR 3579130803Smarcel || typecode == TYPE_CODE_FLT) && len <= 4) 3580130803Smarcel longword_offset = mips_stack_argsize (tdep) - len; 3581130803Smarcel } 3582130803Smarcel 3583130803Smarcel if (mips_debug) 3584130803Smarcel { 3585130803Smarcel fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", 3586130803Smarcel paddr_nz (stack_offset)); 3587130803Smarcel fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", 3588130803Smarcel paddr_nz (longword_offset)); 3589130803Smarcel } 3590130803Smarcel 3591130803Smarcel addr = sp + stack_offset + longword_offset; 3592130803Smarcel 3593130803Smarcel if (mips_debug) 3594130803Smarcel { 3595130803Smarcel int i; 3596130803Smarcel fprintf_unfiltered (gdb_stdlog, " @0x%s ", 3597130803Smarcel paddr_nz (addr)); 3598130803Smarcel for (i = 0; i < partial_len; i++) 3599130803Smarcel { 3600130803Smarcel fprintf_unfiltered (gdb_stdlog, "%02x", 3601130803Smarcel val[i] & 0xff); 3602130803Smarcel } 3603130803Smarcel } 3604130803Smarcel write_memory (addr, val, partial_len); 3605130803Smarcel } 3606130803Smarcel 3607130803Smarcel /* Note!!! This is NOT an else clause. Odd sized 3608130803Smarcel structs may go thru BOTH paths. Floating point 3609130803Smarcel arguments will not. */ 3610130803Smarcel /* Write this portion of the argument to a general 3611130803Smarcel purpose register. */ 3612130803Smarcel if (argreg <= MIPS_LAST_ARG_REGNUM 3613130803Smarcel && !fp_register_arg_p (typecode, arg_type)) 3614130803Smarcel { 3615130803Smarcel LONGEST regval = extract_signed_integer (val, partial_len); 3616130803Smarcel /* Value may need to be sign extended, because 3617130803Smarcel mips_regsize() != mips_saved_regsize(). */ 3618130803Smarcel 3619130803Smarcel /* A non-floating-point argument being passed in a 3620130803Smarcel general register. If a struct or union, and if 3621130803Smarcel the remaining length is smaller than the register 3622130803Smarcel size, we have to adjust the register value on 3623130803Smarcel big endian targets. 3624130803Smarcel 3625130803Smarcel It does not seem to be necessary to do the 3626130803Smarcel same for integral types. 3627130803Smarcel 3628130803Smarcel Also don't do this adjustment on O64 binaries. 3629130803Smarcel 3630130803Smarcel cagney/2001-07-23: gdb/179: Also, GCC, when 3631130803Smarcel outputting LE O32 with sizeof (struct) < 3632130803Smarcel mips_saved_regsize(), generates a left shift as 3633130803Smarcel part of storing the argument in a register a 3634130803Smarcel register (the left shift isn't generated when 3635130803Smarcel sizeof (struct) >= mips_saved_regsize()). Since 3636130803Smarcel it is quite possible that this is GCC 3637130803Smarcel contradicting the LE/O32 ABI, GDB has not been 3638130803Smarcel adjusted to accommodate this. Either someone 3639130803Smarcel needs to demonstrate that the LE/O32 ABI 3640130803Smarcel specifies such a left shift OR this new ABI gets 3641130803Smarcel identified as such and GDB gets tweaked 3642130803Smarcel accordingly. */ 3643130803Smarcel 3644130803Smarcel if (mips_saved_regsize (tdep) < 8 3645130803Smarcel && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 3646130803Smarcel && partial_len < mips_saved_regsize (tdep) 3647130803Smarcel && (typecode == TYPE_CODE_STRUCT || 3648130803Smarcel typecode == TYPE_CODE_UNION)) 3649130803Smarcel regval <<= ((mips_saved_regsize (tdep) - partial_len) * 3650130803Smarcel TARGET_CHAR_BIT); 3651130803Smarcel 3652130803Smarcel if (mips_debug) 3653130803Smarcel fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 3654130803Smarcel argreg, 3655130803Smarcel phex (regval, 3656130803Smarcel mips_saved_regsize (tdep))); 3657130803Smarcel write_register (argreg, regval); 3658130803Smarcel argreg++; 3659130803Smarcel 3660130803Smarcel /* Prevent subsequent floating point arguments from 3661130803Smarcel being passed in floating point registers. */ 3662130803Smarcel float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; 3663130803Smarcel } 3664130803Smarcel 3665130803Smarcel len -= partial_len; 3666130803Smarcel val += partial_len; 3667130803Smarcel 3668130803Smarcel /* Compute the the offset into the stack at which we 3669130803Smarcel will copy the next parameter. 3670130803Smarcel 3671130803Smarcel In older ABIs, the caller reserved space for 3672130803Smarcel registers that contained arguments. This was loosely 3673130803Smarcel refered to as their "home". Consequently, space is 3674130803Smarcel always allocated. */ 3675130803Smarcel 3676130803Smarcel stack_offset += align_up (partial_len, 3677130803Smarcel mips_stack_argsize (tdep)); 3678130803Smarcel } 3679130803Smarcel } 3680130803Smarcel if (mips_debug) 3681130803Smarcel fprintf_unfiltered (gdb_stdlog, "\n"); 3682130803Smarcel } 3683130803Smarcel 3684130803Smarcel regcache_cooked_write_signed (regcache, SP_REGNUM, sp); 3685130803Smarcel 3686130803Smarcel /* Return adjusted stack pointer. */ 3687130803Smarcel return sp; 3688130803Smarcel} 3689130803Smarcel 3690130803Smarcelstatic enum return_value_convention 3691130803Smarcelmips_o32_return_value (struct gdbarch *gdbarch, struct type *type, 3692130803Smarcel struct regcache *regcache, 3693130803Smarcel void *readbuf, const void *writebuf) 3694130803Smarcel{ 3695130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 3696130803Smarcel 3697130803Smarcel if (TYPE_CODE (type) == TYPE_CODE_STRUCT 3698130803Smarcel || TYPE_CODE (type) == TYPE_CODE_UNION 3699130803Smarcel || TYPE_CODE (type) == TYPE_CODE_ARRAY) 3700130803Smarcel return RETURN_VALUE_STRUCT_CONVENTION; 3701130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_FLT 3702130803Smarcel && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) 3703130803Smarcel { 3704130803Smarcel /* A single-precision floating-point value. It fits in the 3705130803Smarcel least significant part of FP0. */ 3706130803Smarcel if (mips_debug) 3707130803Smarcel fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 3708130803Smarcel mips_xfer_register (regcache, 3709130803Smarcel NUM_REGS + mips_regnum (current_gdbarch)->fp0, 3710130803Smarcel TYPE_LENGTH (type), 3711130803Smarcel TARGET_BYTE_ORDER, readbuf, writebuf, 0); 3712130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3713130803Smarcel } 3714130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_FLT 3715130803Smarcel && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) 3716130803Smarcel { 3717130803Smarcel /* A double-precision floating-point value. The most 3718130803Smarcel significant part goes in FP1, and the least significant in 3719130803Smarcel FP0. */ 3720130803Smarcel if (mips_debug) 3721130803Smarcel fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); 3722130803Smarcel switch (TARGET_BYTE_ORDER) 3723130803Smarcel { 3724130803Smarcel case BFD_ENDIAN_LITTLE: 3725130803Smarcel mips_xfer_register (regcache, 3726130803Smarcel NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 3727130803Smarcel 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); 3728130803Smarcel mips_xfer_register (regcache, 3729130803Smarcel NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 3730130803Smarcel 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); 3731130803Smarcel break; 3732130803Smarcel case BFD_ENDIAN_BIG: 3733130803Smarcel mips_xfer_register (regcache, 3734130803Smarcel NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 3735130803Smarcel 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); 3736130803Smarcel mips_xfer_register (regcache, 3737130803Smarcel NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 3738130803Smarcel 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); 3739130803Smarcel break; 3740130803Smarcel default: 3741130803Smarcel internal_error (__FILE__, __LINE__, "bad switch"); 3742130803Smarcel } 3743130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3744130803Smarcel } 3745130803Smarcel#if 0 3746130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 3747130803Smarcel && TYPE_NFIELDS (type) <= 2 3748130803Smarcel && TYPE_NFIELDS (type) >= 1 3749130803Smarcel && ((TYPE_NFIELDS (type) == 1 3750130803Smarcel && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) 3751130803Smarcel == TYPE_CODE_FLT)) 3752130803Smarcel || (TYPE_NFIELDS (type) == 2 3753130803Smarcel && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) 3754130803Smarcel == TYPE_CODE_FLT) 3755130803Smarcel && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) 3756130803Smarcel == TYPE_CODE_FLT))) 3757130803Smarcel && tdep->mips_fpu_type != MIPS_FPU_NONE) 3758130803Smarcel { 3759130803Smarcel /* A struct that contains one or two floats. Each value is part 3760130803Smarcel in the least significant part of their floating point 3761130803Smarcel register.. */ 3762130803Smarcel bfd_byte reg[MAX_REGISTER_SIZE]; 3763130803Smarcel int regnum; 3764130803Smarcel int field; 3765130803Smarcel for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; 3766130803Smarcel field < TYPE_NFIELDS (type); field++, regnum += 2) 3767130803Smarcel { 3768130803Smarcel int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) 3769130803Smarcel / TARGET_CHAR_BIT); 3770130803Smarcel if (mips_debug) 3771130803Smarcel fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", 3772130803Smarcel offset); 3773130803Smarcel mips_xfer_register (regcache, NUM_REGS + regnum, 3774130803Smarcel TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), 3775130803Smarcel TARGET_BYTE_ORDER, readbuf, writebuf, offset); 3776130803Smarcel } 3777130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3778130803Smarcel } 3779130803Smarcel#endif 3780130803Smarcel#if 0 3781130803Smarcel else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 3782130803Smarcel || TYPE_CODE (type) == TYPE_CODE_UNION) 3783130803Smarcel { 3784130803Smarcel /* A structure or union. Extract the left justified value, 3785130803Smarcel regardless of the byte order. I.e. DO NOT USE 3786130803Smarcel mips_xfer_lower. */ 3787130803Smarcel int offset; 3788130803Smarcel int regnum; 3789130803Smarcel for (offset = 0, regnum = V0_REGNUM; 3790130803Smarcel offset < TYPE_LENGTH (type); 3791130803Smarcel offset += register_size (current_gdbarch, regnum), regnum++) 3792130803Smarcel { 3793130803Smarcel int xfer = register_size (current_gdbarch, regnum); 3794130803Smarcel if (offset + xfer > TYPE_LENGTH (type)) 3795130803Smarcel xfer = TYPE_LENGTH (type) - offset; 3796130803Smarcel if (mips_debug) 3797130803Smarcel fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", 3798130803Smarcel offset, xfer, regnum); 3799130803Smarcel mips_xfer_register (regcache, NUM_REGS + regnum, xfer, 3800130803Smarcel BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); 3801130803Smarcel } 3802130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3803130803Smarcel } 3804130803Smarcel#endif 3805130803Smarcel else 3806130803Smarcel { 3807130803Smarcel /* A scalar extract each part but least-significant-byte 3808130803Smarcel justified. o32 thinks registers are 4 byte, regardless of 3809130803Smarcel the ISA. mips_stack_argsize controls this. */ 3810130803Smarcel int offset; 3811130803Smarcel int regnum; 3812130803Smarcel for (offset = 0, regnum = V0_REGNUM; 3813130803Smarcel offset < TYPE_LENGTH (type); 3814130803Smarcel offset += mips_stack_argsize (tdep), regnum++) 3815130803Smarcel { 3816130803Smarcel int xfer = mips_stack_argsize (tdep); 3817130803Smarcel if (offset + xfer > TYPE_LENGTH (type)) 3818130803Smarcel xfer = TYPE_LENGTH (type) - offset; 3819130803Smarcel if (mips_debug) 3820130803Smarcel fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 3821130803Smarcel offset, xfer, regnum); 3822130803Smarcel mips_xfer_register (regcache, NUM_REGS + regnum, xfer, 3823130803Smarcel TARGET_BYTE_ORDER, readbuf, writebuf, offset); 3824130803Smarcel } 3825130803Smarcel return RETURN_VALUE_REGISTER_CONVENTION; 3826130803Smarcel } 3827130803Smarcel} 3828130803Smarcel 3829130803Smarcel/* O64 ABI. This is a hacked up kind of 64-bit version of the o32 3830130803Smarcel ABI. */ 3831130803Smarcel 3832130803Smarcelstatic CORE_ADDR 3833130803Smarcelmips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 3834130803Smarcel struct regcache *regcache, CORE_ADDR bp_addr, 3835130803Smarcel int nargs, 3836130803Smarcel struct value **args, CORE_ADDR sp, 3837130803Smarcel int struct_return, CORE_ADDR struct_addr) 3838130803Smarcel{ 3839130803Smarcel int argreg; 3840130803Smarcel int float_argreg; 3841130803Smarcel int argnum; 3842130803Smarcel int len = 0; 3843130803Smarcel int stack_offset = 0; 3844130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3845130803Smarcel 3846130803Smarcel /* For shared libraries, "t9" needs to point at the function 3847130803Smarcel address. */ 3848130803Smarcel regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr); 3849130803Smarcel 3850130803Smarcel /* Set the return address register to point to the entry point of 3851130803Smarcel the program, where a breakpoint lies in wait. */ 3852130803Smarcel regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr); 3853130803Smarcel 3854130803Smarcel /* First ensure that the stack and structure return address (if any) 3855130803Smarcel are properly aligned. The stack has to be at least 64-bit 3856130803Smarcel aligned even on 32-bit machines, because doubles must be 64-bit 3857130803Smarcel aligned. For n32 and n64, stack frames need to be 128-bit 3858130803Smarcel aligned, so we round to this widest known alignment. */ 3859130803Smarcel 3860130803Smarcel sp = align_down (sp, 16); 3861130803Smarcel struct_addr = align_down (struct_addr, 16); 3862130803Smarcel 3863130803Smarcel /* Now make space on the stack for the args. */ 3864130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 3865130803Smarcel len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 3866130803Smarcel mips_stack_argsize (tdep)); 3867130803Smarcel sp -= align_up (len, 16); 3868130803Smarcel 3869130803Smarcel if (mips_debug) 3870130803Smarcel fprintf_unfiltered (gdb_stdlog, 3871130803Smarcel "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", 3872130803Smarcel paddr_nz (sp), (long) align_up (len, 16)); 3873130803Smarcel 3874130803Smarcel /* Initialize the integer and float register pointers. */ 3875130803Smarcel argreg = A0_REGNUM; 3876130803Smarcel float_argreg = mips_fpa0_regnum (current_gdbarch); 3877130803Smarcel 3878130803Smarcel /* The struct_return pointer occupies the first parameter-passing reg. */ 3879130803Smarcel if (struct_return) 3880130803Smarcel { 3881130803Smarcel if (mips_debug) 3882130803Smarcel fprintf_unfiltered (gdb_stdlog, 3883130803Smarcel "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", 3884130803Smarcel argreg, paddr_nz (struct_addr)); 3885130803Smarcel write_register (argreg++, struct_addr); 3886130803Smarcel stack_offset += mips_stack_argsize (tdep); 3887130803Smarcel } 3888130803Smarcel 3889130803Smarcel /* Now load as many as possible of the first arguments into 3890130803Smarcel registers, and push the rest onto the stack. Loop thru args 3891130803Smarcel from first to last. */ 3892130803Smarcel for (argnum = 0; argnum < nargs; argnum++) 3893130803Smarcel { 3894130803Smarcel char *val; 3895130803Smarcel struct value *arg = args[argnum]; 3896130803Smarcel struct type *arg_type = check_typedef (VALUE_TYPE (arg)); 3897130803Smarcel int len = TYPE_LENGTH (arg_type); 3898130803Smarcel enum type_code typecode = TYPE_CODE (arg_type); 3899130803Smarcel 3900130803Smarcel if (mips_debug) 3901130803Smarcel fprintf_unfiltered (gdb_stdlog, 3902130803Smarcel "mips_o64_push_dummy_call: %d len=%d type=%d", 3903130803Smarcel argnum + 1, len, (int) typecode); 3904130803Smarcel 3905130803Smarcel val = (char *) VALUE_CONTENTS (arg); 3906130803Smarcel 3907130803Smarcel /* 32-bit ABIs always start floating point arguments in an 3908130803Smarcel even-numbered floating point register. Round the FP register 3909130803Smarcel up before the check to see if there are any FP registers 3910130803Smarcel left. O32/O64 targets also pass the FP in the integer 3911130803Smarcel registers so also round up normal registers. */ 3912130803Smarcel if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type)) 3913130803Smarcel { 3914130803Smarcel if ((float_argreg & 1)) 3915130803Smarcel float_argreg++; 3916130803Smarcel } 3917130803Smarcel 3918130803Smarcel /* Floating point arguments passed in registers have to be 3919130803Smarcel treated specially. On 32-bit architectures, doubles 3920130803Smarcel are passed in register pairs; the even register gets 3921130803Smarcel the low word, and the odd register gets the high word. 3922130803Smarcel On O32/O64, the first two floating point arguments are 3923130803Smarcel also copied to general registers, because MIPS16 functions 3924130803Smarcel don't use float registers for arguments. This duplication of 3925130803Smarcel arguments in general registers can't hurt non-MIPS16 functions 3926130803Smarcel because those registers are normally skipped. */ 3927130803Smarcel 3928130803Smarcel if (fp_register_arg_p (typecode, arg_type) 3929130803Smarcel && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) 3930130803Smarcel { 3931130803Smarcel if (!FP_REGISTER_DOUBLE && len == 8) 3932130803Smarcel { 3933130803Smarcel int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; 3934130803Smarcel unsigned long regval; 3935130803Smarcel 3936130803Smarcel /* Write the low word of the double to the even register(s). */ 3937130803Smarcel regval = extract_unsigned_integer (val + low_offset, 4); 3938130803Smarcel if (mips_debug) 3939130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3940130803Smarcel float_argreg, phex (regval, 4)); 3941130803Smarcel write_register (float_argreg++, regval); 3942130803Smarcel if (mips_debug) 3943130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3944130803Smarcel argreg, phex (regval, 4)); 3945130803Smarcel write_register (argreg++, regval); 3946130803Smarcel 3947130803Smarcel /* Write the high word of the double to the odd register(s). */ 3948130803Smarcel regval = extract_unsigned_integer (val + 4 - low_offset, 4); 3949130803Smarcel if (mips_debug) 3950130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3951130803Smarcel float_argreg, phex (regval, 4)); 3952130803Smarcel write_register (float_argreg++, regval); 3953130803Smarcel 3954130803Smarcel if (mips_debug) 3955130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3956130803Smarcel argreg, phex (regval, 4)); 3957130803Smarcel write_register (argreg++, regval); 3958130803Smarcel } 3959130803Smarcel else 3960130803Smarcel { 3961130803Smarcel /* This is a floating point value that fits entirely 3962130803Smarcel in a single register. */ 3963130803Smarcel /* On 32 bit ABI's the float_argreg is further adjusted 3964130803Smarcel above to ensure that it is even register aligned. */ 3965130803Smarcel LONGEST regval = extract_unsigned_integer (val, len); 3966130803Smarcel if (mips_debug) 3967130803Smarcel fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 3968130803Smarcel float_argreg, phex (regval, len)); 3969130803Smarcel write_register (float_argreg++, regval); 3970130803Smarcel /* CAGNEY: 32 bit MIPS ABI's always reserve two FP 3971130803Smarcel registers for each argument. The below is (my 3972130803Smarcel guess) to ensure that the corresponding integer 3973130803Smarcel register has reserved the same space. */ 3974130803Smarcel if (mips_debug) 3975130803Smarcel fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 3976130803Smarcel argreg, phex (regval, len)); 3977130803Smarcel write_register (argreg, regval); 3978130803Smarcel argreg += FP_REGISTER_DOUBLE ? 1 : 2; 3979130803Smarcel } 3980130803Smarcel /* Reserve space for the FP register. */ 3981130803Smarcel stack_offset += align_up (len, mips_stack_argsize (tdep)); 3982130803Smarcel } 3983130803Smarcel else 3984130803Smarcel { 3985130803Smarcel /* Copy the argument to general registers or the stack in 3986130803Smarcel register-sized pieces. Large arguments are split between 3987130803Smarcel registers and stack. */ 3988130803Smarcel /* Note: structs whose size is not a multiple of 3989130803Smarcel mips_regsize() are treated specially: Irix cc passes them 3990130803Smarcel in registers where gcc sometimes puts them on the stack. 3991130803Smarcel For maximum compatibility, we will put them in both 3992130803Smarcel places. */ 3993130803Smarcel int odd_sized_struct = ((len > mips_saved_regsize (tdep)) 3994130803Smarcel && (len % mips_saved_regsize (tdep) != 0)); 3995130803Smarcel /* Structures should be aligned to eight bytes (even arg registers) 3996130803Smarcel on MIPS_ABI_O32, if their first member has double precision. */ 3997130803Smarcel if (mips_saved_regsize (tdep) < 8 3998130803Smarcel && mips_type_needs_double_align (arg_type)) 3999130803Smarcel { 4000130803Smarcel if ((argreg & 1)) 4001130803Smarcel argreg++; 4002130803Smarcel } 4003130803Smarcel /* Note: Floating-point values that didn't fit into an FP 4004130803Smarcel register are only written to memory. */ 4005130803Smarcel while (len > 0) 4006130803Smarcel { 4007130803Smarcel /* Remember if the argument was written to the stack. */ 4008130803Smarcel int stack_used_p = 0; 4009130803Smarcel int partial_len = (len < mips_saved_regsize (tdep) 4010130803Smarcel ? len : mips_saved_regsize (tdep)); 4011130803Smarcel 4012130803Smarcel if (mips_debug) 4013130803Smarcel fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 4014130803Smarcel partial_len); 4015130803Smarcel 4016130803Smarcel /* Write this portion of the argument to the stack. */ 4017130803Smarcel if (argreg > MIPS_LAST_ARG_REGNUM 4018130803Smarcel || odd_sized_struct 4019130803Smarcel || fp_register_arg_p (typecode, arg_type)) 4020130803Smarcel { 4021130803Smarcel /* Should shorter than int integer values be 4022130803Smarcel promoted to int before being stored? */ 4023130803Smarcel int longword_offset = 0; 4024130803Smarcel CORE_ADDR addr; 4025130803Smarcel stack_used_p = 1; 4026130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4027130803Smarcel { 4028130803Smarcel if (mips_stack_argsize (tdep) == 8 4029130803Smarcel && (typecode == TYPE_CODE_INT 4030130803Smarcel || typecode == TYPE_CODE_PTR 4031130803Smarcel || typecode == TYPE_CODE_FLT) && len <= 4) 4032130803Smarcel longword_offset = mips_stack_argsize (tdep) - len; 4033130803Smarcel } 4034130803Smarcel 4035130803Smarcel if (mips_debug) 4036130803Smarcel { 4037130803Smarcel fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", 4038130803Smarcel paddr_nz (stack_offset)); 4039130803Smarcel fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", 4040130803Smarcel paddr_nz (longword_offset)); 4041130803Smarcel } 4042130803Smarcel 4043130803Smarcel addr = sp + stack_offset + longword_offset; 4044130803Smarcel 4045130803Smarcel if (mips_debug) 4046130803Smarcel { 4047130803Smarcel int i; 4048130803Smarcel fprintf_unfiltered (gdb_stdlog, " @0x%s ", 4049130803Smarcel paddr_nz (addr)); 4050130803Smarcel for (i = 0; i < partial_len; i++) 4051130803Smarcel { 4052130803Smarcel fprintf_unfiltered (gdb_stdlog, "%02x", 4053130803Smarcel val[i] & 0xff); 4054130803Smarcel } 4055130803Smarcel } 4056130803Smarcel write_memory (addr, val, partial_len); 4057130803Smarcel } 4058130803Smarcel 4059130803Smarcel /* Note!!! This is NOT an else clause. Odd sized 4060130803Smarcel structs may go thru BOTH paths. Floating point 4061130803Smarcel arguments will not. */ 4062130803Smarcel /* Write this portion of the argument to a general 4063130803Smarcel purpose register. */ 4064130803Smarcel if (argreg <= MIPS_LAST_ARG_REGNUM 4065130803Smarcel && !fp_register_arg_p (typecode, arg_type)) 4066130803Smarcel { 4067130803Smarcel LONGEST regval = extract_signed_integer (val, partial_len); 4068130803Smarcel /* Value may need to be sign extended, because 4069130803Smarcel mips_regsize() != mips_saved_regsize(). */ 4070130803Smarcel 4071130803Smarcel /* A non-floating-point argument being passed in a 4072130803Smarcel general register. If a struct or union, and if 4073130803Smarcel the remaining length is smaller than the register 4074130803Smarcel size, we have to adjust the register value on 4075130803Smarcel big endian targets. 4076130803Smarcel 4077130803Smarcel It does not seem to be necessary to do the 4078130803Smarcel same for integral types. 4079130803Smarcel 4080130803Smarcel Also don't do this adjustment on O64 binaries. 4081130803Smarcel 4082130803Smarcel cagney/2001-07-23: gdb/179: Also, GCC, when 4083130803Smarcel outputting LE O32 with sizeof (struct) < 4084130803Smarcel mips_saved_regsize(), generates a left shift as 4085130803Smarcel part of storing the argument in a register a 4086130803Smarcel register (the left shift isn't generated when 4087130803Smarcel sizeof (struct) >= mips_saved_regsize()). Since 4088130803Smarcel it is quite possible that this is GCC 4089130803Smarcel contradicting the LE/O32 ABI, GDB has not been 4090130803Smarcel adjusted to accommodate this. Either someone 4091130803Smarcel needs to demonstrate that the LE/O32 ABI 4092130803Smarcel specifies such a left shift OR this new ABI gets 4093130803Smarcel identified as such and GDB gets tweaked 4094130803Smarcel accordingly. */ 4095130803Smarcel 4096130803Smarcel if (mips_saved_regsize (tdep) < 8 4097130803Smarcel && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 4098130803Smarcel && partial_len < mips_saved_regsize (tdep) 4099130803Smarcel && (typecode == TYPE_CODE_STRUCT || 4100130803Smarcel typecode == TYPE_CODE_UNION)) 4101130803Smarcel regval <<= ((mips_saved_regsize (tdep) - partial_len) * 4102130803Smarcel TARGET_CHAR_BIT); 4103130803Smarcel 4104130803Smarcel if (mips_debug) 4105130803Smarcel fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 4106130803Smarcel argreg, 4107130803Smarcel phex (regval, 4108130803Smarcel mips_saved_regsize (tdep))); 4109130803Smarcel write_register (argreg, regval); 4110130803Smarcel argreg++; 4111130803Smarcel 4112130803Smarcel /* Prevent subsequent floating point arguments from 4113130803Smarcel being passed in floating point registers. */ 4114130803Smarcel float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; 4115130803Smarcel } 4116130803Smarcel 4117130803Smarcel len -= partial_len; 4118130803Smarcel val += partial_len; 4119130803Smarcel 4120130803Smarcel /* Compute the the offset into the stack at which we 4121130803Smarcel will copy the next parameter. 4122130803Smarcel 4123130803Smarcel In older ABIs, the caller reserved space for 4124130803Smarcel registers that contained arguments. This was loosely 4125130803Smarcel refered to as their "home". Consequently, space is 4126130803Smarcel always allocated. */ 4127130803Smarcel 4128130803Smarcel stack_offset += align_up (partial_len, 4129130803Smarcel mips_stack_argsize (tdep)); 4130130803Smarcel } 4131130803Smarcel } 4132130803Smarcel if (mips_debug) 4133130803Smarcel fprintf_unfiltered (gdb_stdlog, "\n"); 4134130803Smarcel } 4135130803Smarcel 4136130803Smarcel regcache_cooked_write_signed (regcache, SP_REGNUM, sp); 4137130803Smarcel 4138130803Smarcel /* Return adjusted stack pointer. */ 4139130803Smarcel return sp; 4140130803Smarcel} 4141130803Smarcel 4142130803Smarcelstatic void 4143130803Smarcelmips_o64_extract_return_value (struct type *valtype, 4144130803Smarcel char regbuf[], char *valbuf) 4145130803Smarcel{ 4146130803Smarcel struct return_value_word lo; 4147130803Smarcel struct return_value_word hi; 4148130803Smarcel return_value_location (valtype, &hi, &lo); 4149130803Smarcel 4150130803Smarcel memcpy (valbuf + lo.buf_offset, 4151130803Smarcel regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + 4152130803Smarcel lo.reg_offset, lo.len); 4153130803Smarcel 4154130803Smarcel if (hi.len > 0) 4155130803Smarcel memcpy (valbuf + hi.buf_offset, 4156130803Smarcel regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + 4157130803Smarcel hi.reg_offset, hi.len); 4158130803Smarcel} 4159130803Smarcel 4160130803Smarcelstatic void 4161130803Smarcelmips_o64_store_return_value (struct type *valtype, char *valbuf) 4162130803Smarcel{ 4163130803Smarcel char raw_buffer[MAX_REGISTER_SIZE]; 4164130803Smarcel struct return_value_word lo; 4165130803Smarcel struct return_value_word hi; 4166130803Smarcel return_value_location (valtype, &hi, &lo); 4167130803Smarcel 4168130803Smarcel memset (raw_buffer, 0, sizeof (raw_buffer)); 4169130803Smarcel memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); 4170130803Smarcel deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), 4171130803Smarcel raw_buffer, register_size (current_gdbarch, 4172130803Smarcel lo.reg)); 4173130803Smarcel 4174130803Smarcel if (hi.len > 0) 4175130803Smarcel { 4176130803Smarcel memset (raw_buffer, 0, sizeof (raw_buffer)); 4177130803Smarcel memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); 4178130803Smarcel deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), 4179130803Smarcel raw_buffer, 4180130803Smarcel register_size (current_gdbarch, 4181130803Smarcel hi.reg)); 4182130803Smarcel } 4183130803Smarcel} 4184130803Smarcel 4185130803Smarcel/* Floating point register management. 4186130803Smarcel 4187130803Smarcel Background: MIPS1 & 2 fp registers are 32 bits wide. To support 4188130803Smarcel 64bit operations, these early MIPS cpus treat fp register pairs 4189130803Smarcel (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp 4190130803Smarcel registers and offer a compatibility mode that emulates the MIPS2 fp 4191130803Smarcel model. When operating in MIPS2 fp compat mode, later cpu's split 4192130803Smarcel double precision floats into two 32-bit chunks and store them in 4193130803Smarcel consecutive fp regs. To display 64-bit floats stored in this 4194130803Smarcel fashion, we have to combine 32 bits from f0 and 32 bits from f1. 4195130803Smarcel Throw in user-configurable endianness and you have a real mess. 4196130803Smarcel 4197130803Smarcel The way this works is: 4198130803Smarcel - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit 4199130803Smarcel double-precision value will be split across two logical registers. 4200130803Smarcel The lower-numbered logical register will hold the low-order bits, 4201130803Smarcel regardless of the processor's endianness. 4202130803Smarcel - If we are on a 64-bit processor, and we are looking for a 4203130803Smarcel single-precision value, it will be in the low ordered bits 4204130803Smarcel of a 64-bit GPR (after mfc1, for example) or a 64-bit register 4205130803Smarcel save slot in memory. 4206130803Smarcel - If we are in 64-bit mode, everything is straightforward. 4207130803Smarcel 4208130803Smarcel Note that this code only deals with "live" registers at the top of the 4209130803Smarcel stack. We will attempt to deal with saved registers later, when 4210130803Smarcel the raw/cooked register interface is in place. (We need a general 4211130803Smarcel interface that can deal with dynamic saved register sizes -- fp 4212130803Smarcel regs could be 32 bits wide in one frame and 64 on the frame above 4213130803Smarcel and below). */ 4214130803Smarcel 4215130803Smarcelstatic struct type * 4216130803Smarcelmips_float_register_type (void) 4217130803Smarcel{ 4218130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4219130803Smarcel return builtin_type_ieee_single_big; 4220130803Smarcel else 4221130803Smarcel return builtin_type_ieee_single_little; 4222130803Smarcel} 4223130803Smarcel 4224130803Smarcelstatic struct type * 4225130803Smarcelmips_double_register_type (void) 4226130803Smarcel{ 4227130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4228130803Smarcel return builtin_type_ieee_double_big; 4229130803Smarcel else 4230130803Smarcel return builtin_type_ieee_double_little; 4231130803Smarcel} 4232130803Smarcel 4233130803Smarcel/* Copy a 32-bit single-precision value from the current frame 4234130803Smarcel into rare_buffer. */ 4235130803Smarcel 4236130803Smarcelstatic void 4237130803Smarcelmips_read_fp_register_single (struct frame_info *frame, int regno, 4238130803Smarcel char *rare_buffer) 4239130803Smarcel{ 4240130803Smarcel int raw_size = register_size (current_gdbarch, regno); 4241130803Smarcel char *raw_buffer = alloca (raw_size); 4242130803Smarcel 4243130803Smarcel if (!frame_register_read (frame, regno, raw_buffer)) 4244130803Smarcel error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); 4245130803Smarcel if (raw_size == 8) 4246130803Smarcel { 4247130803Smarcel /* We have a 64-bit value for this register. Find the low-order 4248130803Smarcel 32 bits. */ 4249130803Smarcel int offset; 4250130803Smarcel 4251130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4252130803Smarcel offset = 4; 4253130803Smarcel else 4254130803Smarcel offset = 0; 4255130803Smarcel 4256130803Smarcel memcpy (rare_buffer, raw_buffer + offset, 4); 4257130803Smarcel } 4258130803Smarcel else 4259130803Smarcel { 4260130803Smarcel memcpy (rare_buffer, raw_buffer, 4); 4261130803Smarcel } 4262130803Smarcel} 4263130803Smarcel 4264130803Smarcel/* Copy a 64-bit double-precision value from the current frame into 4265130803Smarcel rare_buffer. This may include getting half of it from the next 4266130803Smarcel register. */ 4267130803Smarcel 4268130803Smarcelstatic void 4269130803Smarcelmips_read_fp_register_double (struct frame_info *frame, int regno, 4270130803Smarcel char *rare_buffer) 4271130803Smarcel{ 4272130803Smarcel int raw_size = register_size (current_gdbarch, regno); 4273130803Smarcel 4274130803Smarcel if (raw_size == 8 && !mips2_fp_compat ()) 4275130803Smarcel { 4276130803Smarcel /* We have a 64-bit value for this register, and we should use 4277130803Smarcel all 64 bits. */ 4278130803Smarcel if (!frame_register_read (frame, regno, rare_buffer)) 4279130803Smarcel error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); 4280130803Smarcel } 4281130803Smarcel else 4282130803Smarcel { 4283130803Smarcel if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) 4284130803Smarcel internal_error (__FILE__, __LINE__, 4285130803Smarcel "mips_read_fp_register_double: bad access to " 4286130803Smarcel "odd-numbered FP register"); 4287130803Smarcel 4288130803Smarcel /* mips_read_fp_register_single will find the correct 32 bits from 4289130803Smarcel each register. */ 4290130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4291130803Smarcel { 4292130803Smarcel mips_read_fp_register_single (frame, regno, rare_buffer + 4); 4293130803Smarcel mips_read_fp_register_single (frame, regno + 1, rare_buffer); 4294130803Smarcel } 4295130803Smarcel else 4296130803Smarcel { 4297130803Smarcel mips_read_fp_register_single (frame, regno, rare_buffer); 4298130803Smarcel mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); 4299130803Smarcel } 4300130803Smarcel } 4301130803Smarcel} 4302130803Smarcel 4303130803Smarcelstatic void 4304130803Smarcelmips_print_fp_register (struct ui_file *file, struct frame_info *frame, 4305130803Smarcel int regnum) 4306130803Smarcel{ /* do values for FP (float) regs */ 4307130803Smarcel char *raw_buffer; 4308130803Smarcel double doub, flt1; /* doubles extracted from raw hex data */ 4309130803Smarcel int inv1, inv2; 4310130803Smarcel 4311130803Smarcel raw_buffer = 4312130803Smarcel (char *) alloca (2 * 4313130803Smarcel register_size (current_gdbarch, 4314130803Smarcel mips_regnum (current_gdbarch)->fp0)); 4315130803Smarcel 4316130803Smarcel fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); 4317130803Smarcel fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), 4318130803Smarcel ""); 4319130803Smarcel 4320130803Smarcel if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) 4321130803Smarcel { 4322130803Smarcel /* 4-byte registers: Print hex and floating. Also print even 4323130803Smarcel numbered registers as doubles. */ 4324130803Smarcel mips_read_fp_register_single (frame, regnum, raw_buffer); 4325130803Smarcel flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); 4326130803Smarcel 4327130803Smarcel print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', 4328130803Smarcel file); 4329130803Smarcel 4330130803Smarcel fprintf_filtered (file, " flt: "); 4331130803Smarcel if (inv1) 4332130803Smarcel fprintf_filtered (file, " <invalid float> "); 4333130803Smarcel else 4334130803Smarcel fprintf_filtered (file, "%-17.9g", flt1); 4335130803Smarcel 4336130803Smarcel if (regnum % 2 == 0) 4337130803Smarcel { 4338130803Smarcel mips_read_fp_register_double (frame, regnum, raw_buffer); 4339130803Smarcel doub = unpack_double (mips_double_register_type (), raw_buffer, 4340130803Smarcel &inv2); 4341130803Smarcel 4342130803Smarcel fprintf_filtered (file, " dbl: "); 4343130803Smarcel if (inv2) 4344130803Smarcel fprintf_filtered (file, "<invalid double>"); 4345130803Smarcel else 4346130803Smarcel fprintf_filtered (file, "%-24.17g", doub); 4347130803Smarcel } 4348130803Smarcel } 4349130803Smarcel else 4350130803Smarcel { 4351130803Smarcel /* Eight byte registers: print each one as hex, float and double. */ 4352130803Smarcel mips_read_fp_register_single (frame, regnum, raw_buffer); 4353130803Smarcel flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); 4354130803Smarcel 4355130803Smarcel mips_read_fp_register_double (frame, regnum, raw_buffer); 4356130803Smarcel doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); 4357130803Smarcel 4358130803Smarcel 4359130803Smarcel print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', 4360130803Smarcel file); 4361130803Smarcel 4362130803Smarcel fprintf_filtered (file, " flt: "); 4363130803Smarcel if (inv1) 4364130803Smarcel fprintf_filtered (file, "<invalid float>"); 4365130803Smarcel else 4366130803Smarcel fprintf_filtered (file, "%-17.9g", flt1); 4367130803Smarcel 4368130803Smarcel fprintf_filtered (file, " dbl: "); 4369130803Smarcel if (inv2) 4370130803Smarcel fprintf_filtered (file, "<invalid double>"); 4371130803Smarcel else 4372130803Smarcel fprintf_filtered (file, "%-24.17g", doub); 4373130803Smarcel } 4374130803Smarcel} 4375130803Smarcel 4376130803Smarcelstatic void 4377130803Smarcelmips_print_register (struct ui_file *file, struct frame_info *frame, 4378130803Smarcel int regnum, int all) 4379130803Smarcel{ 4380130803Smarcel struct gdbarch *gdbarch = get_frame_arch (frame); 4381130803Smarcel char raw_buffer[MAX_REGISTER_SIZE]; 4382130803Smarcel int offset; 4383130803Smarcel 4384130803Smarcel if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) 4385130803Smarcel { 4386130803Smarcel mips_print_fp_register (file, frame, regnum); 4387130803Smarcel return; 4388130803Smarcel } 4389130803Smarcel 4390130803Smarcel /* Get the data in raw format. */ 4391130803Smarcel if (!frame_register_read (frame, regnum, raw_buffer)) 4392130803Smarcel { 4393130803Smarcel fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); 4394130803Smarcel return; 4395130803Smarcel } 4396130803Smarcel 4397130803Smarcel fputs_filtered (REGISTER_NAME (regnum), file); 4398130803Smarcel 4399130803Smarcel /* The problem with printing numeric register names (r26, etc.) is that 4400130803Smarcel the user can't use them on input. Probably the best solution is to 4401130803Smarcel fix it so that either the numeric or the funky (a2, etc.) names 4402130803Smarcel are accepted on input. */ 4403130803Smarcel if (regnum < MIPS_NUMREGS) 4404130803Smarcel fprintf_filtered (file, "(r%d): ", regnum); 4405130803Smarcel else 4406130803Smarcel fprintf_filtered (file, ": "); 4407130803Smarcel 4408130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4409130803Smarcel offset = 4410130803Smarcel register_size (current_gdbarch, 4411130803Smarcel regnum) - register_size (current_gdbarch, regnum); 4412130803Smarcel else 4413130803Smarcel offset = 0; 4414130803Smarcel 4415130803Smarcel print_scalar_formatted (raw_buffer + offset, 4416130803Smarcel gdbarch_register_type (gdbarch, regnum), 'x', 0, 4417130803Smarcel file); 4418130803Smarcel} 4419130803Smarcel 4420130803Smarcel/* Replacement for generic do_registers_info. 4421130803Smarcel Print regs in pretty columns. */ 4422130803Smarcel 4423130803Smarcelstatic int 4424130803Smarcelprint_fp_register_row (struct ui_file *file, struct frame_info *frame, 4425130803Smarcel int regnum) 4426130803Smarcel{ 4427130803Smarcel fprintf_filtered (file, " "); 4428130803Smarcel mips_print_fp_register (file, frame, regnum); 4429130803Smarcel fprintf_filtered (file, "\n"); 4430130803Smarcel return regnum + 1; 4431130803Smarcel} 4432130803Smarcel 4433130803Smarcel 4434130803Smarcel/* Print a row's worth of GP (int) registers, with name labels above */ 4435130803Smarcel 4436130803Smarcelstatic int 4437130803Smarcelprint_gp_register_row (struct ui_file *file, struct frame_info *frame, 4438130803Smarcel int start_regnum) 4439130803Smarcel{ 4440130803Smarcel struct gdbarch *gdbarch = get_frame_arch (frame); 4441130803Smarcel /* do values for GP (int) regs */ 4442130803Smarcel char raw_buffer[MAX_REGISTER_SIZE]; 4443130803Smarcel int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ 4444130803Smarcel int col, byte; 4445130803Smarcel int regnum; 4446130803Smarcel 4447130803Smarcel /* For GP registers, we print a separate row of names above the vals */ 4448130803Smarcel fprintf_filtered (file, " "); 4449130803Smarcel for (col = 0, regnum = start_regnum; 4450130803Smarcel col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) 4451130803Smarcel { 4452130803Smarcel if (*REGISTER_NAME (regnum) == '\0') 4453130803Smarcel continue; /* unused register */ 4454130803Smarcel if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == 4455130803Smarcel TYPE_CODE_FLT) 4456130803Smarcel break; /* end the row: reached FP register */ 4457130803Smarcel fprintf_filtered (file, 4458130803Smarcel mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", 4459130803Smarcel REGISTER_NAME (regnum)); 4460130803Smarcel col++; 4461130803Smarcel } 4462130803Smarcel /* print the R0 to R31 names */ 4463130803Smarcel if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) 4464130803Smarcel fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); 4465130803Smarcel else 4466130803Smarcel fprintf_filtered (file, "\n "); 4467130803Smarcel 4468130803Smarcel /* now print the values in hex, 4 or 8 to the row */ 4469130803Smarcel for (col = 0, regnum = start_regnum; 4470130803Smarcel col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) 4471130803Smarcel { 4472130803Smarcel if (*REGISTER_NAME (regnum) == '\0') 4473130803Smarcel continue; /* unused register */ 4474130803Smarcel if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == 4475130803Smarcel TYPE_CODE_FLT) 4476130803Smarcel break; /* end row: reached FP register */ 4477130803Smarcel /* OK: get the data in raw format. */ 4478130803Smarcel if (!frame_register_read (frame, regnum, raw_buffer)) 4479130803Smarcel error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); 4480130803Smarcel /* pad small registers */ 4481130803Smarcel for (byte = 0; 4482130803Smarcel byte < (mips_regsize (current_gdbarch) 4483130803Smarcel - register_size (current_gdbarch, regnum)); byte++) 4484130803Smarcel printf_filtered (" "); 4485130803Smarcel /* Now print the register value in hex, endian order. */ 4486130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4487130803Smarcel for (byte = 4488130803Smarcel register_size (current_gdbarch, 4489130803Smarcel regnum) - register_size (current_gdbarch, regnum); 4490130803Smarcel byte < register_size (current_gdbarch, regnum); byte++) 4491130803Smarcel fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); 4492130803Smarcel else 4493130803Smarcel for (byte = register_size (current_gdbarch, regnum) - 1; 4494130803Smarcel byte >= 0; byte--) 4495130803Smarcel fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); 4496130803Smarcel fprintf_filtered (file, " "); 4497130803Smarcel col++; 4498130803Smarcel } 4499130803Smarcel if (col > 0) /* ie. if we actually printed anything... */ 4500130803Smarcel fprintf_filtered (file, "\n"); 4501130803Smarcel 4502130803Smarcel return regnum; 4503130803Smarcel} 4504130803Smarcel 4505130803Smarcel/* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ 4506130803Smarcel 4507130803Smarcelstatic void 4508130803Smarcelmips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 4509130803Smarcel struct frame_info *frame, int regnum, int all) 4510130803Smarcel{ 4511130803Smarcel if (regnum != -1) /* do one specified register */ 4512130803Smarcel { 4513130803Smarcel gdb_assert (regnum >= NUM_REGS); 4514130803Smarcel if (*(REGISTER_NAME (regnum)) == '\0') 4515130803Smarcel error ("Not a valid register for the current processor type"); 4516130803Smarcel 4517130803Smarcel mips_print_register (file, frame, regnum, 0); 4518130803Smarcel fprintf_filtered (file, "\n"); 4519130803Smarcel } 4520130803Smarcel else 4521130803Smarcel /* do all (or most) registers */ 4522130803Smarcel { 4523130803Smarcel regnum = NUM_REGS; 4524130803Smarcel while (regnum < NUM_REGS + NUM_PSEUDO_REGS) 4525130803Smarcel { 4526130803Smarcel if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == 4527130803Smarcel TYPE_CODE_FLT) 4528130803Smarcel { 4529130803Smarcel if (all) /* true for "INFO ALL-REGISTERS" command */ 4530130803Smarcel regnum = print_fp_register_row (file, frame, regnum); 4531130803Smarcel else 4532130803Smarcel regnum += MIPS_NUMREGS; /* skip floating point regs */ 4533130803Smarcel } 4534130803Smarcel else 4535130803Smarcel regnum = print_gp_register_row (file, frame, regnum); 4536130803Smarcel } 4537130803Smarcel } 4538130803Smarcel} 4539130803Smarcel 4540130803Smarcel/* Is this a branch with a delay slot? */ 4541130803Smarcel 4542130803Smarcelstatic int is_delayed (unsigned long); 4543130803Smarcel 4544130803Smarcelstatic int 4545130803Smarcelis_delayed (unsigned long insn) 4546130803Smarcel{ 4547130803Smarcel int i; 4548130803Smarcel for (i = 0; i < NUMOPCODES; ++i) 4549130803Smarcel if (mips_opcodes[i].pinfo != INSN_MACRO 4550130803Smarcel && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) 4551130803Smarcel break; 4552130803Smarcel return (i < NUMOPCODES 4553130803Smarcel && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY 4554130803Smarcel | INSN_COND_BRANCH_DELAY 4555130803Smarcel | INSN_COND_BRANCH_LIKELY))); 4556130803Smarcel} 4557130803Smarcel 4558130803Smarcelint 4559130803Smarcelmips_step_skips_delay (CORE_ADDR pc) 4560130803Smarcel{ 4561130803Smarcel char buf[MIPS_INSTLEN]; 4562130803Smarcel 4563130803Smarcel /* There is no branch delay slot on MIPS16. */ 4564130803Smarcel if (pc_is_mips16 (pc)) 4565130803Smarcel return 0; 4566130803Smarcel 4567130803Smarcel if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) 4568130803Smarcel /* If error reading memory, guess that it is not a delayed branch. */ 4569130803Smarcel return 0; 4570130803Smarcel return is_delayed ((unsigned long) 4571130803Smarcel extract_unsigned_integer (buf, MIPS_INSTLEN)); 4572130803Smarcel} 4573130803Smarcel 4574130803Smarcel/* Skip the PC past function prologue instructions (32-bit version). 4575130803Smarcel This is a helper function for mips_skip_prologue. */ 4576130803Smarcel 4577130803Smarcelstatic CORE_ADDR 4578130803Smarcelmips32_skip_prologue (CORE_ADDR pc) 4579130803Smarcel{ 4580130803Smarcel t_inst inst; 4581130803Smarcel CORE_ADDR end_pc; 4582130803Smarcel int seen_sp_adjust = 0; 4583130803Smarcel int load_immediate_bytes = 0; 4584130803Smarcel 4585130803Smarcel /* Find an upper bound on the prologue. */ 4586130803Smarcel end_pc = skip_prologue_using_sal (pc); 4587130803Smarcel if (end_pc == 0) 4588130803Smarcel end_pc = pc + 100; /* Magic. */ 4589130803Smarcel 4590130803Smarcel /* Skip the typical prologue instructions. These are the stack adjustment 4591130803Smarcel instruction and the instructions that save registers on the stack 4592130803Smarcel or in the gcc frame. */ 4593130803Smarcel for (; pc < end_pc; pc += MIPS_INSTLEN) 4594130803Smarcel { 4595130803Smarcel unsigned long high_word; 4596130803Smarcel 4597130803Smarcel inst = mips_fetch_instruction (pc); 4598130803Smarcel high_word = (inst >> 16) & 0xffff; 4599130803Smarcel 4600130803Smarcel if (high_word == 0x27bd /* addiu $sp,$sp,offset */ 4601130803Smarcel || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ 4602130803Smarcel seen_sp_adjust = 1; 4603130803Smarcel else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ 4604130803Smarcel inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ 4605130803Smarcel seen_sp_adjust = 1; 4606130803Smarcel else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ 4607130803Smarcel || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ 4608130803Smarcel && (inst & 0x001F0000)) /* reg != $zero */ 4609130803Smarcel continue; 4610130803Smarcel 4611130803Smarcel else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ 4612130803Smarcel continue; 4613130803Smarcel else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) 4614130803Smarcel /* sx reg,n($s8) */ 4615130803Smarcel continue; /* reg != $zero */ 4616130803Smarcel 4617130803Smarcel /* move $s8,$sp. With different versions of gas this will be either 4618130803Smarcel `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. 4619130803Smarcel Accept any one of these. */ 4620130803Smarcel else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) 4621130803Smarcel continue; 4622130803Smarcel 4623130803Smarcel else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ 4624130803Smarcel continue; 4625130803Smarcel else if (high_word == 0x3c1c) /* lui $gp,n */ 4626130803Smarcel continue; 4627130803Smarcel else if (high_word == 0x279c) /* addiu $gp,$gp,n */ 4628130803Smarcel continue; 4629130803Smarcel else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ 4630130803Smarcel || inst == 0x033ce021) /* addu $gp,$t9,$gp */ 4631130803Smarcel continue; 4632130803Smarcel /* The following instructions load $at or $t0 with an immediate 4633130803Smarcel value in preparation for a stack adjustment via 4634130803Smarcel subu $sp,$sp,[$at,$t0]. These instructions could also initialize 4635130803Smarcel a local variable, so we accept them only before a stack adjustment 4636130803Smarcel instruction was seen. */ 4637130803Smarcel else if (!seen_sp_adjust) 4638130803Smarcel { 4639130803Smarcel if (high_word == 0x3c01 || /* lui $at,n */ 4640130803Smarcel high_word == 0x3c08) /* lui $t0,n */ 4641130803Smarcel { 4642130803Smarcel load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ 4643130803Smarcel continue; 4644130803Smarcel } 4645130803Smarcel else if (high_word == 0x3421 || /* ori $at,$at,n */ 4646130803Smarcel high_word == 0x3508 || /* ori $t0,$t0,n */ 4647130803Smarcel high_word == 0x3401 || /* ori $at,$zero,n */ 4648130803Smarcel high_word == 0x3408) /* ori $t0,$zero,n */ 4649130803Smarcel { 4650130803Smarcel load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ 4651130803Smarcel continue; 4652130803Smarcel } 4653130803Smarcel else 4654130803Smarcel break; 4655130803Smarcel } 4656130803Smarcel else 4657130803Smarcel break; 4658130803Smarcel } 4659130803Smarcel 4660130803Smarcel /* In a frameless function, we might have incorrectly 4661130803Smarcel skipped some load immediate instructions. Undo the skipping 4662130803Smarcel if the load immediate was not followed by a stack adjustment. */ 4663130803Smarcel if (load_immediate_bytes && !seen_sp_adjust) 4664130803Smarcel pc -= load_immediate_bytes; 4665130803Smarcel return pc; 4666130803Smarcel} 4667130803Smarcel 4668130803Smarcel/* Skip the PC past function prologue instructions (16-bit version). 4669130803Smarcel This is a helper function for mips_skip_prologue. */ 4670130803Smarcel 4671130803Smarcelstatic CORE_ADDR 4672130803Smarcelmips16_skip_prologue (CORE_ADDR pc) 4673130803Smarcel{ 4674130803Smarcel CORE_ADDR end_pc; 4675130803Smarcel int extend_bytes = 0; 4676130803Smarcel int prev_extend_bytes; 4677130803Smarcel 4678130803Smarcel /* Table of instructions likely to be found in a function prologue. */ 4679130803Smarcel static struct 4680130803Smarcel { 4681130803Smarcel unsigned short inst; 4682130803Smarcel unsigned short mask; 4683130803Smarcel } 4684130803Smarcel table[] = 4685130803Smarcel { 4686130803Smarcel { 4687130803Smarcel 0x6300, 0xff00} 4688130803Smarcel , /* addiu $sp,offset */ 4689130803Smarcel { 4690130803Smarcel 0xfb00, 0xff00} 4691130803Smarcel , /* daddiu $sp,offset */ 4692130803Smarcel { 4693130803Smarcel 0xd000, 0xf800} 4694130803Smarcel , /* sw reg,n($sp) */ 4695130803Smarcel { 4696130803Smarcel 0xf900, 0xff00} 4697130803Smarcel , /* sd reg,n($sp) */ 4698130803Smarcel { 4699130803Smarcel 0x6200, 0xff00} 4700130803Smarcel , /* sw $ra,n($sp) */ 4701130803Smarcel { 4702130803Smarcel 0xfa00, 0xff00} 4703130803Smarcel , /* sd $ra,n($sp) */ 4704130803Smarcel { 4705130803Smarcel 0x673d, 0xffff} 4706130803Smarcel , /* move $s1,sp */ 4707130803Smarcel { 4708130803Smarcel 0xd980, 0xff80} 4709130803Smarcel , /* sw $a0-$a3,n($s1) */ 4710130803Smarcel { 4711130803Smarcel 0x6704, 0xff1c} 4712130803Smarcel , /* move reg,$a0-$a3 */ 4713130803Smarcel { 4714130803Smarcel 0xe809, 0xf81f} 4715130803Smarcel , /* entry pseudo-op */ 4716130803Smarcel { 4717130803Smarcel 0x0100, 0xff00} 4718130803Smarcel , /* addiu $s1,$sp,n */ 4719130803Smarcel { 4720130803Smarcel 0, 0} /* end of table marker */ 4721130803Smarcel }; 4722130803Smarcel 4723130803Smarcel /* Find an upper bound on the prologue. */ 4724130803Smarcel end_pc = skip_prologue_using_sal (pc); 4725130803Smarcel if (end_pc == 0) 4726130803Smarcel end_pc = pc + 100; /* Magic. */ 4727130803Smarcel 4728130803Smarcel /* Skip the typical prologue instructions. These are the stack adjustment 4729130803Smarcel instruction and the instructions that save registers on the stack 4730130803Smarcel or in the gcc frame. */ 4731130803Smarcel for (; pc < end_pc; pc += MIPS16_INSTLEN) 4732130803Smarcel { 4733130803Smarcel unsigned short inst; 4734130803Smarcel int i; 4735130803Smarcel 4736130803Smarcel inst = mips_fetch_instruction (pc); 4737130803Smarcel 4738130803Smarcel /* Normally we ignore an extend instruction. However, if it is 4739130803Smarcel not followed by a valid prologue instruction, we must adjust 4740130803Smarcel the pc back over the extend so that it won't be considered 4741130803Smarcel part of the prologue. */ 4742130803Smarcel if ((inst & 0xf800) == 0xf000) /* extend */ 4743130803Smarcel { 4744130803Smarcel extend_bytes = MIPS16_INSTLEN; 4745130803Smarcel continue; 4746130803Smarcel } 4747130803Smarcel prev_extend_bytes = extend_bytes; 4748130803Smarcel extend_bytes = 0; 4749130803Smarcel 4750130803Smarcel /* Check for other valid prologue instructions besides extend. */ 4751130803Smarcel for (i = 0; table[i].mask != 0; i++) 4752130803Smarcel if ((inst & table[i].mask) == table[i].inst) /* found, get out */ 4753130803Smarcel break; 4754130803Smarcel if (table[i].mask != 0) /* it was in table? */ 4755130803Smarcel continue; /* ignore it */ 4756130803Smarcel else 4757130803Smarcel /* non-prologue */ 4758130803Smarcel { 4759130803Smarcel /* Return the current pc, adjusted backwards by 2 if 4760130803Smarcel the previous instruction was an extend. */ 4761130803Smarcel return pc - prev_extend_bytes; 4762130803Smarcel } 4763130803Smarcel } 4764130803Smarcel return pc; 4765130803Smarcel} 4766130803Smarcel 4767130803Smarcel/* To skip prologues, I use this predicate. Returns either PC itself 4768130803Smarcel if the code at PC does not look like a function prologue; otherwise 4769130803Smarcel returns an address that (if we're lucky) follows the prologue. If 4770130803Smarcel LENIENT, then we must skip everything which is involved in setting 4771130803Smarcel up the frame (it's OK to skip more, just so long as we don't skip 4772130803Smarcel anything which might clobber the registers which are being saved. 4773130803Smarcel We must skip more in the case where part of the prologue is in the 4774130803Smarcel delay slot of a non-prologue instruction). */ 4775130803Smarcel 4776130803Smarcelstatic CORE_ADDR 4777130803Smarcelmips_skip_prologue (CORE_ADDR pc) 4778130803Smarcel{ 4779130803Smarcel /* See if we can determine the end of the prologue via the symbol table. 4780130803Smarcel If so, then return either PC, or the PC after the prologue, whichever 4781130803Smarcel is greater. */ 4782130803Smarcel 4783130803Smarcel CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); 4784130803Smarcel 4785130803Smarcel if (post_prologue_pc != 0) 4786130803Smarcel return max (pc, post_prologue_pc); 4787130803Smarcel 4788130803Smarcel /* Can't determine prologue from the symbol table, need to examine 4789130803Smarcel instructions. */ 4790130803Smarcel 4791130803Smarcel if (pc_is_mips16 (pc)) 4792130803Smarcel return mips16_skip_prologue (pc); 4793130803Smarcel else 4794130803Smarcel return mips32_skip_prologue (pc); 4795130803Smarcel} 4796130803Smarcel 4797130803Smarcel/* Exported procedure: Is PC in the signal trampoline code */ 4798130803Smarcel 4799130803Smarcelstatic int 4800130803Smarcelmips_pc_in_sigtramp (CORE_ADDR pc, char *ignore) 4801130803Smarcel{ 4802130803Smarcel if (sigtramp_address == 0) 4803130803Smarcel fixup_sigtramp (); 4804130803Smarcel return (pc >= sigtramp_address && pc < sigtramp_end); 4805130803Smarcel} 4806130803Smarcel 4807130803Smarcel/* Root of all "set mips "/"show mips " commands. This will eventually be 4808130803Smarcel used for all MIPS-specific commands. */ 4809130803Smarcel 4810130803Smarcelstatic void 4811130803Smarcelshow_mips_command (char *args, int from_tty) 4812130803Smarcel{ 4813130803Smarcel help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); 4814130803Smarcel} 4815130803Smarcel 4816130803Smarcelstatic void 4817130803Smarcelset_mips_command (char *args, int from_tty) 4818130803Smarcel{ 4819130803Smarcel printf_unfiltered 4820130803Smarcel ("\"set mips\" must be followed by an appropriate subcommand.\n"); 4821130803Smarcel help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); 4822130803Smarcel} 4823130803Smarcel 4824130803Smarcel/* Commands to show/set the MIPS FPU type. */ 4825130803Smarcel 4826130803Smarcelstatic void 4827130803Smarcelshow_mipsfpu_command (char *args, int from_tty) 4828130803Smarcel{ 4829130803Smarcel char *fpu; 4830130803Smarcel switch (MIPS_FPU_TYPE) 4831130803Smarcel { 4832130803Smarcel case MIPS_FPU_SINGLE: 4833130803Smarcel fpu = "single-precision"; 4834130803Smarcel break; 4835130803Smarcel case MIPS_FPU_DOUBLE: 4836130803Smarcel fpu = "double-precision"; 4837130803Smarcel break; 4838130803Smarcel case MIPS_FPU_NONE: 4839130803Smarcel fpu = "absent (none)"; 4840130803Smarcel break; 4841130803Smarcel default: 4842130803Smarcel internal_error (__FILE__, __LINE__, "bad switch"); 4843130803Smarcel } 4844130803Smarcel if (mips_fpu_type_auto) 4845130803Smarcel printf_unfiltered 4846130803Smarcel ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", 4847130803Smarcel fpu); 4848130803Smarcel else 4849130803Smarcel printf_unfiltered 4850130803Smarcel ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); 4851130803Smarcel} 4852130803Smarcel 4853130803Smarcel 4854130803Smarcelstatic void 4855130803Smarcelset_mipsfpu_command (char *args, int from_tty) 4856130803Smarcel{ 4857130803Smarcel printf_unfiltered 4858130803Smarcel ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); 4859130803Smarcel show_mipsfpu_command (args, from_tty); 4860130803Smarcel} 4861130803Smarcel 4862130803Smarcelstatic void 4863130803Smarcelset_mipsfpu_single_command (char *args, int from_tty) 4864130803Smarcel{ 4865130803Smarcel struct gdbarch_info info; 4866130803Smarcel gdbarch_info_init (&info); 4867130803Smarcel mips_fpu_type = MIPS_FPU_SINGLE; 4868130803Smarcel mips_fpu_type_auto = 0; 4869130803Smarcel /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 4870130803Smarcel instead of relying on globals. Doing that would let generic code 4871130803Smarcel handle the search for this specific architecture. */ 4872130803Smarcel if (!gdbarch_update_p (info)) 4873130803Smarcel internal_error (__FILE__, __LINE__, "set mipsfpu failed"); 4874130803Smarcel} 4875130803Smarcel 4876130803Smarcelstatic void 4877130803Smarcelset_mipsfpu_double_command (char *args, int from_tty) 4878130803Smarcel{ 4879130803Smarcel struct gdbarch_info info; 4880130803Smarcel gdbarch_info_init (&info); 4881130803Smarcel mips_fpu_type = MIPS_FPU_DOUBLE; 4882130803Smarcel mips_fpu_type_auto = 0; 4883130803Smarcel /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 4884130803Smarcel instead of relying on globals. Doing that would let generic code 4885130803Smarcel handle the search for this specific architecture. */ 4886130803Smarcel if (!gdbarch_update_p (info)) 4887130803Smarcel internal_error (__FILE__, __LINE__, "set mipsfpu failed"); 4888130803Smarcel} 4889130803Smarcel 4890130803Smarcelstatic void 4891130803Smarcelset_mipsfpu_none_command (char *args, int from_tty) 4892130803Smarcel{ 4893130803Smarcel struct gdbarch_info info; 4894130803Smarcel gdbarch_info_init (&info); 4895130803Smarcel mips_fpu_type = MIPS_FPU_NONE; 4896130803Smarcel mips_fpu_type_auto = 0; 4897130803Smarcel /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 4898130803Smarcel instead of relying on globals. Doing that would let generic code 4899130803Smarcel handle the search for this specific architecture. */ 4900130803Smarcel if (!gdbarch_update_p (info)) 4901130803Smarcel internal_error (__FILE__, __LINE__, "set mipsfpu failed"); 4902130803Smarcel} 4903130803Smarcel 4904130803Smarcelstatic void 4905130803Smarcelset_mipsfpu_auto_command (char *args, int from_tty) 4906130803Smarcel{ 4907130803Smarcel mips_fpu_type_auto = 1; 4908130803Smarcel} 4909130803Smarcel 4910130803Smarcel/* Attempt to identify the particular processor model by reading the 4911130803Smarcel processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that 4912130803Smarcel the relevant processor still exists (it dates back to '94) and 4913130803Smarcel secondly this is not the way to do this. The processor type should 4914130803Smarcel be set by forcing an architecture change. */ 4915130803Smarcel 4916130803Smarcelvoid 4917130803Smarceldeprecated_mips_set_processor_regs_hack (void) 4918130803Smarcel{ 4919130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 4920130803Smarcel CORE_ADDR prid; 4921130803Smarcel 4922130803Smarcel prid = read_register (PRID_REGNUM); 4923130803Smarcel 4924130803Smarcel if ((prid & ~0xf) == 0x700) 4925130803Smarcel tdep->mips_processor_reg_names = mips_r3041_reg_names; 4926130803Smarcel} 4927130803Smarcel 4928130803Smarcel/* Just like reinit_frame_cache, but with the right arguments to be 4929130803Smarcel callable as an sfunc. */ 4930130803Smarcel 4931130803Smarcelstatic void 4932130803Smarcelreinit_frame_cache_sfunc (char *args, int from_tty, 4933130803Smarcel struct cmd_list_element *c) 4934130803Smarcel{ 4935130803Smarcel reinit_frame_cache (); 4936130803Smarcel} 4937130803Smarcel 4938130803Smarcelstatic int 4939130803Smarcelgdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) 4940130803Smarcel{ 4941130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 4942130803Smarcel mips_extra_func_info_t proc_desc; 4943130803Smarcel 4944130803Smarcel /* Search for the function containing this address. Set the low bit 4945130803Smarcel of the address when searching, in case we were given an even address 4946130803Smarcel that is the start of a 16-bit function. If we didn't do this, 4947130803Smarcel the search would fail because the symbol table says the function 4948130803Smarcel starts at an odd address, i.e. 1 byte past the given address. */ 4949130803Smarcel memaddr = ADDR_BITS_REMOVE (memaddr); 4950130803Smarcel proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); 4951130803Smarcel 4952130803Smarcel /* Make an attempt to determine if this is a 16-bit function. If 4953130803Smarcel the procedure descriptor exists and the address therein is odd, 4954130803Smarcel it's definitely a 16-bit function. Otherwise, we have to just 4955130803Smarcel guess that if the address passed in is odd, it's 16-bits. */ 4956130803Smarcel /* FIXME: cagney/2003-06-26: Is this even necessary? The 4957130803Smarcel disassembler needs to be able to locally determine the ISA, and 4958130803Smarcel not rely on GDB. Otherwize the stand-alone 'objdump -d' will not 4959130803Smarcel work. */ 4960130803Smarcel if (proc_desc) 4961130803Smarcel { 4962130803Smarcel if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) 4963130803Smarcel info->mach = bfd_mach_mips16; 4964130803Smarcel } 4965130803Smarcel else 4966130803Smarcel { 4967130803Smarcel if (pc_is_mips16 (memaddr)) 4968130803Smarcel info->mach = bfd_mach_mips16; 4969130803Smarcel } 4970130803Smarcel 4971130803Smarcel /* Round down the instruction address to the appropriate boundary. */ 4972130803Smarcel memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); 4973130803Smarcel 4974130803Smarcel /* Set the disassembler options. */ 4975130803Smarcel if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) 4976130803Smarcel { 4977130803Smarcel /* Set up the disassembler info, so that we get the right 4978130803Smarcel register names from libopcodes. */ 4979130803Smarcel if (tdep->mips_abi == MIPS_ABI_N32) 4980130803Smarcel info->disassembler_options = "gpr-names=n32"; 4981130803Smarcel else 4982130803Smarcel info->disassembler_options = "gpr-names=64"; 4983130803Smarcel info->flavour = bfd_target_elf_flavour; 4984130803Smarcel } 4985130803Smarcel else 4986130803Smarcel /* This string is not recognized explicitly by the disassembler, 4987130803Smarcel but it tells the disassembler to not try to guess the ABI from 4988130803Smarcel the bfd elf headers, such that, if the user overrides the ABI 4989130803Smarcel of a program linked as NewABI, the disassembly will follow the 4990130803Smarcel register naming conventions specified by the user. */ 4991130803Smarcel info->disassembler_options = "gpr-names=32"; 4992130803Smarcel 4993130803Smarcel /* Call the appropriate disassembler based on the target endian-ness. */ 4994130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 4995130803Smarcel return print_insn_big_mips (memaddr, info); 4996130803Smarcel else 4997130803Smarcel return print_insn_little_mips (memaddr, info); 4998130803Smarcel} 4999130803Smarcel 5000130803Smarcel/* This function implements the BREAKPOINT_FROM_PC macro. It uses the program 5001130803Smarcel counter value to determine whether a 16- or 32-bit breakpoint should be 5002130803Smarcel used. It returns a pointer to a string of bytes that encode a breakpoint 5003130803Smarcel instruction, stores the length of the string to *lenptr, and adjusts pc 5004130803Smarcel (if necessary) to point to the actual memory location where the 5005130803Smarcel breakpoint should be inserted. */ 5006130803Smarcel 5007130803Smarcelstatic const unsigned char * 5008130803Smarcelmips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 5009130803Smarcel{ 5010130803Smarcel if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 5011130803Smarcel { 5012130803Smarcel if (pc_is_mips16 (*pcptr)) 5013130803Smarcel { 5014130803Smarcel static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; 5015130803Smarcel *pcptr = unmake_mips16_addr (*pcptr); 5016130803Smarcel *lenptr = sizeof (mips16_big_breakpoint); 5017130803Smarcel return mips16_big_breakpoint; 5018130803Smarcel } 5019130803Smarcel else 5020130803Smarcel { 5021130803Smarcel /* The IDT board uses an unusual breakpoint value, and 5022130803Smarcel sometimes gets confused when it sees the usual MIPS 5023130803Smarcel breakpoint instruction. */ 5024130803Smarcel static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; 5025130803Smarcel static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; 5026130803Smarcel static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; 5027130803Smarcel 5028130803Smarcel *lenptr = sizeof (big_breakpoint); 5029130803Smarcel 5030130803Smarcel if (strcmp (target_shortname, "mips") == 0) 5031130803Smarcel return idt_big_breakpoint; 5032130803Smarcel else if (strcmp (target_shortname, "ddb") == 0 5033130803Smarcel || strcmp (target_shortname, "pmon") == 0 5034130803Smarcel || strcmp (target_shortname, "lsi") == 0) 5035130803Smarcel return pmon_big_breakpoint; 5036130803Smarcel else 5037130803Smarcel return big_breakpoint; 5038130803Smarcel } 5039130803Smarcel } 5040130803Smarcel else 5041130803Smarcel { 5042130803Smarcel if (pc_is_mips16 (*pcptr)) 5043130803Smarcel { 5044130803Smarcel static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; 5045130803Smarcel *pcptr = unmake_mips16_addr (*pcptr); 5046130803Smarcel *lenptr = sizeof (mips16_little_breakpoint); 5047130803Smarcel return mips16_little_breakpoint; 5048130803Smarcel } 5049130803Smarcel else 5050130803Smarcel { 5051130803Smarcel static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; 5052130803Smarcel static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; 5053130803Smarcel static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; 5054130803Smarcel 5055130803Smarcel *lenptr = sizeof (little_breakpoint); 5056130803Smarcel 5057130803Smarcel if (strcmp (target_shortname, "mips") == 0) 5058130803Smarcel return idt_little_breakpoint; 5059130803Smarcel else if (strcmp (target_shortname, "ddb") == 0 5060130803Smarcel || strcmp (target_shortname, "pmon") == 0 5061130803Smarcel || strcmp (target_shortname, "lsi") == 0) 5062130803Smarcel return pmon_little_breakpoint; 5063130803Smarcel else 5064130803Smarcel return little_breakpoint; 5065130803Smarcel } 5066130803Smarcel } 5067130803Smarcel} 5068130803Smarcel 5069130803Smarcel/* If PC is in a mips16 call or return stub, return the address of the target 5070130803Smarcel PC, which is either the callee or the caller. There are several 5071130803Smarcel cases which must be handled: 5072130803Smarcel 5073130803Smarcel * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the 5074130803Smarcel target PC is in $31 ($ra). 5075130803Smarcel * If the PC is in __mips16_call_stub_{1..10}, this is a call stub 5076130803Smarcel and the target PC is in $2. 5077130803Smarcel * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. 5078130803Smarcel before the jal instruction, this is effectively a call stub 5079130803Smarcel and the the target PC is in $2. Otherwise this is effectively 5080130803Smarcel a return stub and the target PC is in $18. 5081130803Smarcel 5082130803Smarcel See the source code for the stubs in gcc/config/mips/mips16.S for 5083130803Smarcel gory details. 5084130803Smarcel 5085130803Smarcel This function implements the SKIP_TRAMPOLINE_CODE macro. 5086130803Smarcel */ 5087130803Smarcel 5088130803Smarcelstatic CORE_ADDR 5089130803Smarcelmips_skip_stub (CORE_ADDR pc) 5090130803Smarcel{ 5091130803Smarcel char *name; 5092130803Smarcel CORE_ADDR start_addr; 5093130803Smarcel 5094130803Smarcel /* Find the starting address and name of the function containing the PC. */ 5095130803Smarcel if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 5096130803Smarcel return 0; 5097130803Smarcel 5098130803Smarcel /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the 5099130803Smarcel target PC is in $31 ($ra). */ 5100130803Smarcel if (strcmp (name, "__mips16_ret_sf") == 0 5101130803Smarcel || strcmp (name, "__mips16_ret_df") == 0) 5102130803Smarcel return read_signed_register (RA_REGNUM); 5103130803Smarcel 5104130803Smarcel if (strncmp (name, "__mips16_call_stub_", 19) == 0) 5105130803Smarcel { 5106130803Smarcel /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub 5107130803Smarcel and the target PC is in $2. */ 5108130803Smarcel if (name[19] >= '0' && name[19] <= '9') 5109130803Smarcel return read_signed_register (2); 5110130803Smarcel 5111130803Smarcel /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. 5112130803Smarcel before the jal instruction, this is effectively a call stub 5113130803Smarcel and the the target PC is in $2. Otherwise this is effectively 5114130803Smarcel a return stub and the target PC is in $18. */ 5115130803Smarcel else if (name[19] == 's' || name[19] == 'd') 5116130803Smarcel { 5117130803Smarcel if (pc == start_addr) 5118130803Smarcel { 5119130803Smarcel /* Check if the target of the stub is a compiler-generated 5120130803Smarcel stub. Such a stub for a function bar might have a name 5121130803Smarcel like __fn_stub_bar, and might look like this: 5122130803Smarcel mfc1 $4,$f13 5123130803Smarcel mfc1 $5,$f12 5124130803Smarcel mfc1 $6,$f15 5125130803Smarcel mfc1 $7,$f14 5126130803Smarcel la $1,bar (becomes a lui/addiu pair) 5127130803Smarcel jr $1 5128130803Smarcel So scan down to the lui/addi and extract the target 5129130803Smarcel address from those two instructions. */ 5130130803Smarcel 5131130803Smarcel CORE_ADDR target_pc = read_signed_register (2); 5132130803Smarcel t_inst inst; 5133130803Smarcel int i; 5134130803Smarcel 5135130803Smarcel /* See if the name of the target function is __fn_stub_*. */ 5136130803Smarcel if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 5137130803Smarcel 0) 5138130803Smarcel return target_pc; 5139130803Smarcel if (strncmp (name, "__fn_stub_", 10) != 0 5140130803Smarcel && strcmp (name, "etext") != 0 5141130803Smarcel && strcmp (name, "_etext") != 0) 5142130803Smarcel return target_pc; 5143130803Smarcel 5144130803Smarcel /* Scan through this _fn_stub_ code for the lui/addiu pair. 5145130803Smarcel The limit on the search is arbitrarily set to 20 5146130803Smarcel instructions. FIXME. */ 5147130803Smarcel for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) 5148130803Smarcel { 5149130803Smarcel inst = mips_fetch_instruction (target_pc); 5150130803Smarcel if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ 5151130803Smarcel pc = (inst << 16) & 0xffff0000; /* high word */ 5152130803Smarcel else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ 5153130803Smarcel return pc | (inst & 0xffff); /* low word */ 5154130803Smarcel } 5155130803Smarcel 5156130803Smarcel /* Couldn't find the lui/addui pair, so return stub address. */ 5157130803Smarcel return target_pc; 5158130803Smarcel } 5159130803Smarcel else 5160130803Smarcel /* This is the 'return' part of a call stub. The return 5161130803Smarcel address is in $r18. */ 5162130803Smarcel return read_signed_register (18); 5163130803Smarcel } 5164130803Smarcel } 5165130803Smarcel return 0; /* not a stub */ 5166130803Smarcel} 5167130803Smarcel 5168130803Smarcel 5169130803Smarcel/* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). 5170130803Smarcel This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ 5171130803Smarcel 5172130803Smarcelstatic int 5173130803Smarcelmips_in_call_stub (CORE_ADDR pc, char *name) 5174130803Smarcel{ 5175130803Smarcel CORE_ADDR start_addr; 5176130803Smarcel 5177130803Smarcel /* Find the starting address of the function containing the PC. If the 5178130803Smarcel caller didn't give us a name, look it up at the same time. */ 5179130803Smarcel if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 5180130803Smarcel 0) 5181130803Smarcel return 0; 5182130803Smarcel 5183130803Smarcel if (strncmp (name, "__mips16_call_stub_", 19) == 0) 5184130803Smarcel { 5185130803Smarcel /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ 5186130803Smarcel if (name[19] >= '0' && name[19] <= '9') 5187130803Smarcel return 1; 5188130803Smarcel /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. 5189130803Smarcel before the jal instruction, this is effectively a call stub. */ 5190130803Smarcel else if (name[19] == 's' || name[19] == 'd') 5191130803Smarcel return pc == start_addr; 5192130803Smarcel } 5193130803Smarcel 5194130803Smarcel return 0; /* not a stub */ 5195130803Smarcel} 5196130803Smarcel 5197130803Smarcel 5198130803Smarcel/* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). 5199130803Smarcel This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ 5200130803Smarcel 5201130803Smarcelstatic int 5202130803Smarcelmips_in_return_stub (CORE_ADDR pc, char *name) 5203130803Smarcel{ 5204130803Smarcel CORE_ADDR start_addr; 5205130803Smarcel 5206130803Smarcel /* Find the starting address of the function containing the PC. */ 5207130803Smarcel if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) 5208130803Smarcel return 0; 5209130803Smarcel 5210130803Smarcel /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ 5211130803Smarcel if (strcmp (name, "__mips16_ret_sf") == 0 5212130803Smarcel || strcmp (name, "__mips16_ret_df") == 0) 5213130803Smarcel return 1; 5214130803Smarcel 5215130803Smarcel /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, 5216130803Smarcel i.e. after the jal instruction, this is effectively a return stub. */ 5217130803Smarcel if (strncmp (name, "__mips16_call_stub_", 19) == 0 5218130803Smarcel && (name[19] == 's' || name[19] == 'd') && pc != start_addr) 5219130803Smarcel return 1; 5220130803Smarcel 5221130803Smarcel return 0; /* not a stub */ 5222130803Smarcel} 5223130803Smarcel 5224130803Smarcel 5225130803Smarcel/* Return non-zero if the PC is in a library helper function that should 5226130803Smarcel be ignored. This implements the IGNORE_HELPER_CALL macro. */ 5227130803Smarcel 5228130803Smarcelint 5229130803Smarcelmips_ignore_helper (CORE_ADDR pc) 5230130803Smarcel{ 5231130803Smarcel char *name; 5232130803Smarcel 5233130803Smarcel /* Find the starting address and name of the function containing the PC. */ 5234130803Smarcel if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) 5235130803Smarcel return 0; 5236130803Smarcel 5237130803Smarcel /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function 5238130803Smarcel that we want to ignore. */ 5239130803Smarcel return (strcmp (name, "__mips16_ret_sf") == 0 5240130803Smarcel || strcmp (name, "__mips16_ret_df") == 0); 5241130803Smarcel} 5242130803Smarcel 5243130803Smarcel 5244130803Smarcel/* Convert a dbx stab register number (from `r' declaration) to a GDB 5245130803Smarcel [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ 5246130803Smarcel 5247130803Smarcelstatic int 5248130803Smarcelmips_stab_reg_to_regnum (int num) 5249130803Smarcel{ 5250130803Smarcel int regnum; 5251130803Smarcel if (num >= 0 && num < 32) 5252130803Smarcel regnum = num; 5253130803Smarcel else if (num >= 38 && num < 70) 5254130803Smarcel regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; 5255130803Smarcel else if (num == 70) 5256130803Smarcel regnum = mips_regnum (current_gdbarch)->hi; 5257130803Smarcel else if (num == 71) 5258130803Smarcel regnum = mips_regnum (current_gdbarch)->lo; 5259130803Smarcel else 5260130803Smarcel /* This will hopefully (eventually) provoke a warning. Should 5261130803Smarcel we be calling complaint() here? */ 5262130803Smarcel return NUM_REGS + NUM_PSEUDO_REGS; 5263130803Smarcel return NUM_REGS + regnum; 5264130803Smarcel} 5265130803Smarcel 5266130803Smarcel 5267130803Smarcel/* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * 5268130803Smarcel NUM_REGS .. 2 * NUM_REGS) REGNUM. */ 5269130803Smarcel 5270130803Smarcelstatic int 5271130803Smarcelmips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) 5272130803Smarcel{ 5273130803Smarcel int regnum; 5274130803Smarcel if (num >= 0 && num < 32) 5275130803Smarcel regnum = num; 5276130803Smarcel else if (num >= 32 && num < 64) 5277130803Smarcel regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; 5278130803Smarcel else if (num == 64) 5279130803Smarcel regnum = mips_regnum (current_gdbarch)->hi; 5280130803Smarcel else if (num == 65) 5281130803Smarcel regnum = mips_regnum (current_gdbarch)->lo; 5282130803Smarcel else 5283130803Smarcel /* This will hopefully (eventually) provoke a warning. Should we 5284130803Smarcel be calling complaint() here? */ 5285130803Smarcel return NUM_REGS + NUM_PSEUDO_REGS; 5286130803Smarcel return NUM_REGS + regnum; 5287130803Smarcel} 5288130803Smarcel 5289130803Smarcelstatic int 5290130803Smarcelmips_register_sim_regno (int regnum) 5291130803Smarcel{ 5292130803Smarcel /* Only makes sense to supply raw registers. */ 5293130803Smarcel gdb_assert (regnum >= 0 && regnum < NUM_REGS); 5294130803Smarcel /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to 5295130803Smarcel decide if it is valid. Should instead define a standard sim/gdb 5296130803Smarcel register numbering scheme. */ 5297130803Smarcel if (REGISTER_NAME (NUM_REGS + regnum) != NULL 5298130803Smarcel && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') 5299130803Smarcel return regnum; 5300130803Smarcel else 5301130803Smarcel return LEGACY_SIM_REGNO_IGNORE; 5302130803Smarcel} 5303130803Smarcel 5304130803Smarcel 5305130803Smarcel/* Convert an integer into an address. By first converting the value 5306130803Smarcel into a pointer and then extracting it signed, the address is 5307130803Smarcel guarenteed to be correctly sign extended. */ 5308130803Smarcel 5309130803Smarcelstatic CORE_ADDR 5310130803Smarcelmips_integer_to_address (struct type *type, void *buf) 5311130803Smarcel{ 5312130803Smarcel char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); 5313130803Smarcel LONGEST val = unpack_long (type, buf); 5314130803Smarcel store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); 5315130803Smarcel return extract_signed_integer (tmp, 5316130803Smarcel TYPE_LENGTH (builtin_type_void_data_ptr)); 5317130803Smarcel} 5318130803Smarcel 5319130803Smarcelstatic void 5320130803Smarcelmips_find_abi_section (bfd *abfd, asection *sect, void *obj) 5321130803Smarcel{ 5322130803Smarcel enum mips_abi *abip = (enum mips_abi *) obj; 5323130803Smarcel const char *name = bfd_get_section_name (abfd, sect); 5324130803Smarcel 5325130803Smarcel if (*abip != MIPS_ABI_UNKNOWN) 5326130803Smarcel return; 5327130803Smarcel 5328130803Smarcel if (strncmp (name, ".mdebug.", 8) != 0) 5329130803Smarcel return; 5330130803Smarcel 5331130803Smarcel if (strcmp (name, ".mdebug.abi32") == 0) 5332130803Smarcel *abip = MIPS_ABI_O32; 5333130803Smarcel else if (strcmp (name, ".mdebug.abiN32") == 0) 5334130803Smarcel *abip = MIPS_ABI_N32; 5335130803Smarcel else if (strcmp (name, ".mdebug.abi64") == 0) 5336130803Smarcel *abip = MIPS_ABI_N64; 5337130803Smarcel else if (strcmp (name, ".mdebug.abiO64") == 0) 5338130803Smarcel *abip = MIPS_ABI_O64; 5339130803Smarcel else if (strcmp (name, ".mdebug.eabi32") == 0) 5340130803Smarcel *abip = MIPS_ABI_EABI32; 5341130803Smarcel else if (strcmp (name, ".mdebug.eabi64") == 0) 5342130803Smarcel *abip = MIPS_ABI_EABI64; 5343130803Smarcel else 5344130803Smarcel warning ("unsupported ABI %s.", name + 8); 5345130803Smarcel} 5346130803Smarcel 5347130803Smarcelstatic enum mips_abi 5348130803Smarcelglobal_mips_abi (void) 5349130803Smarcel{ 5350130803Smarcel int i; 5351130803Smarcel 5352130803Smarcel for (i = 0; mips_abi_strings[i] != NULL; i++) 5353130803Smarcel if (mips_abi_strings[i] == mips_abi_string) 5354130803Smarcel return (enum mips_abi) i; 5355130803Smarcel 5356130803Smarcel internal_error (__FILE__, __LINE__, "unknown ABI string"); 5357130803Smarcel} 5358130803Smarcel 5359130803Smarcelstatic struct gdbarch * 5360130803Smarcelmips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 5361130803Smarcel{ 5362130803Smarcel struct gdbarch *gdbarch; 5363130803Smarcel struct gdbarch_tdep *tdep; 5364130803Smarcel int elf_flags; 5365130803Smarcel enum mips_abi mips_abi, found_abi, wanted_abi; 5366130803Smarcel int num_regs; 5367130803Smarcel enum mips_fpu_type fpu_type; 5368130803Smarcel 5369130803Smarcel /* First of all, extract the elf_flags, if available. */ 5370130803Smarcel if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 5371130803Smarcel elf_flags = elf_elfheader (info.abfd)->e_flags; 5372130803Smarcel else if (arches != NULL) 5373130803Smarcel elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; 5374130803Smarcel else 5375130803Smarcel elf_flags = 0; 5376130803Smarcel if (gdbarch_debug) 5377130803Smarcel fprintf_unfiltered (gdb_stdlog, 5378130803Smarcel "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); 5379130803Smarcel 5380130803Smarcel /* Check ELF_FLAGS to see if it specifies the ABI being used. */ 5381130803Smarcel switch ((elf_flags & EF_MIPS_ABI)) 5382130803Smarcel { 5383130803Smarcel case E_MIPS_ABI_O32: 5384130803Smarcel found_abi = MIPS_ABI_O32; 5385130803Smarcel break; 5386130803Smarcel case E_MIPS_ABI_O64: 5387130803Smarcel found_abi = MIPS_ABI_O64; 5388130803Smarcel break; 5389130803Smarcel case E_MIPS_ABI_EABI32: 5390130803Smarcel found_abi = MIPS_ABI_EABI32; 5391130803Smarcel break; 5392130803Smarcel case E_MIPS_ABI_EABI64: 5393130803Smarcel found_abi = MIPS_ABI_EABI64; 5394130803Smarcel break; 5395130803Smarcel default: 5396130803Smarcel if ((elf_flags & EF_MIPS_ABI2)) 5397130803Smarcel found_abi = MIPS_ABI_N32; 5398130803Smarcel else 5399130803Smarcel found_abi = MIPS_ABI_UNKNOWN; 5400130803Smarcel break; 5401130803Smarcel } 5402130803Smarcel 5403130803Smarcel /* GCC creates a pseudo-section whose name describes the ABI. */ 5404130803Smarcel if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) 5405130803Smarcel bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); 5406130803Smarcel 5407130803Smarcel /* If we have no usefu BFD information, use the ABI from the last 5408130803Smarcel MIPS architecture (if there is one). */ 5409130803Smarcel if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) 5410130803Smarcel found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; 5411130803Smarcel 5412130803Smarcel /* Try the architecture for any hint of the correct ABI. */ 5413130803Smarcel if (found_abi == MIPS_ABI_UNKNOWN 5414130803Smarcel && info.bfd_arch_info != NULL 5415130803Smarcel && info.bfd_arch_info->arch == bfd_arch_mips) 5416130803Smarcel { 5417130803Smarcel switch (info.bfd_arch_info->mach) 5418130803Smarcel { 5419130803Smarcel case bfd_mach_mips3900: 5420130803Smarcel found_abi = MIPS_ABI_EABI32; 5421130803Smarcel break; 5422130803Smarcel case bfd_mach_mips4100: 5423130803Smarcel case bfd_mach_mips5000: 5424130803Smarcel found_abi = MIPS_ABI_EABI64; 5425130803Smarcel break; 5426130803Smarcel case bfd_mach_mips8000: 5427130803Smarcel case bfd_mach_mips10000: 5428130803Smarcel /* On Irix, ELF64 executables use the N64 ABI. The 5429130803Smarcel pseudo-sections which describe the ABI aren't present 5430130803Smarcel on IRIX. (Even for executables created by gcc.) */ 5431130803Smarcel if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 5432130803Smarcel && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 5433130803Smarcel found_abi = MIPS_ABI_N64; 5434130803Smarcel else 5435130803Smarcel found_abi = MIPS_ABI_N32; 5436130803Smarcel break; 5437130803Smarcel } 5438130803Smarcel } 5439130803Smarcel 5440233159Sgonzo /* Default 64-bit objects to N64 instead of O32. */ 5441233159Sgonzo if (found_abi == MIPS_ABI_UNKNOWN 5442233159Sgonzo && info.abfd != NULL 5443233159Sgonzo && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 5444233159Sgonzo && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 5445233159Sgonzo found_abi = MIPS_ABI_N64; 5446233159Sgonzo 5447130803Smarcel if (gdbarch_debug) 5448130803Smarcel fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", 5449130803Smarcel found_abi); 5450130803Smarcel 5451130803Smarcel /* What has the user specified from the command line? */ 5452130803Smarcel wanted_abi = global_mips_abi (); 5453130803Smarcel if (gdbarch_debug) 5454130803Smarcel fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", 5455130803Smarcel wanted_abi); 5456130803Smarcel 5457130803Smarcel /* Now that we have found what the ABI for this binary would be, 5458130803Smarcel check whether the user is overriding it. */ 5459130803Smarcel if (wanted_abi != MIPS_ABI_UNKNOWN) 5460130803Smarcel mips_abi = wanted_abi; 5461130803Smarcel else if (found_abi != MIPS_ABI_UNKNOWN) 5462130803Smarcel mips_abi = found_abi; 5463130803Smarcel else 5464130803Smarcel mips_abi = MIPS_ABI_O32; 5465130803Smarcel if (gdbarch_debug) 5466130803Smarcel fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", 5467130803Smarcel mips_abi); 5468130803Smarcel 5469130803Smarcel /* Also used when doing an architecture lookup. */ 5470130803Smarcel if (gdbarch_debug) 5471130803Smarcel fprintf_unfiltered (gdb_stdlog, 5472130803Smarcel "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", 5473130803Smarcel mips64_transfers_32bit_regs_p); 5474130803Smarcel 5475130803Smarcel /* Determine the MIPS FPU type. */ 5476130803Smarcel if (!mips_fpu_type_auto) 5477130803Smarcel fpu_type = mips_fpu_type; 5478130803Smarcel else if (info.bfd_arch_info != NULL 5479130803Smarcel && info.bfd_arch_info->arch == bfd_arch_mips) 5480130803Smarcel switch (info.bfd_arch_info->mach) 5481130803Smarcel { 5482130803Smarcel case bfd_mach_mips3900: 5483130803Smarcel case bfd_mach_mips4100: 5484130803Smarcel case bfd_mach_mips4111: 5485130803Smarcel fpu_type = MIPS_FPU_NONE; 5486130803Smarcel break; 5487130803Smarcel case bfd_mach_mips4650: 5488130803Smarcel fpu_type = MIPS_FPU_SINGLE; 5489130803Smarcel break; 5490130803Smarcel default: 5491130803Smarcel fpu_type = MIPS_FPU_DOUBLE; 5492130803Smarcel break; 5493130803Smarcel } 5494130803Smarcel else if (arches != NULL) 5495130803Smarcel fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; 5496130803Smarcel else 5497130803Smarcel fpu_type = MIPS_FPU_DOUBLE; 5498130803Smarcel if (gdbarch_debug) 5499130803Smarcel fprintf_unfiltered (gdb_stdlog, 5500130803Smarcel "mips_gdbarch_init: fpu_type = %d\n", fpu_type); 5501130803Smarcel 5502130803Smarcel /* try to find a pre-existing architecture */ 5503130803Smarcel for (arches = gdbarch_list_lookup_by_info (arches, &info); 5504130803Smarcel arches != NULL; 5505130803Smarcel arches = gdbarch_list_lookup_by_info (arches->next, &info)) 5506130803Smarcel { 5507130803Smarcel /* MIPS needs to be pedantic about which ABI the object is 5508130803Smarcel using. */ 5509130803Smarcel if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) 5510130803Smarcel continue; 5511130803Smarcel if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) 5512130803Smarcel continue; 5513130803Smarcel /* Need to be pedantic about which register virtual size is 5514130803Smarcel used. */ 5515130803Smarcel if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p 5516130803Smarcel != mips64_transfers_32bit_regs_p) 5517130803Smarcel continue; 5518130803Smarcel /* Be pedantic about which FPU is selected. */ 5519130803Smarcel if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) 5520130803Smarcel continue; 5521130803Smarcel return arches->gdbarch; 5522130803Smarcel } 5523130803Smarcel 5524130803Smarcel /* Need a new architecture. Fill in a target specific vector. */ 5525130803Smarcel tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); 5526130803Smarcel gdbarch = gdbarch_alloc (&info, tdep); 5527130803Smarcel tdep->elf_flags = elf_flags; 5528130803Smarcel tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; 5529130803Smarcel tdep->found_abi = found_abi; 5530130803Smarcel tdep->mips_abi = mips_abi; 5531130803Smarcel tdep->mips_fpu_type = fpu_type; 5532130803Smarcel 5533130803Smarcel /* Initially set everything according to the default ABI/ISA. */ 5534130803Smarcel set_gdbarch_short_bit (gdbarch, 16); 5535130803Smarcel set_gdbarch_int_bit (gdbarch, 32); 5536130803Smarcel set_gdbarch_float_bit (gdbarch, 32); 5537130803Smarcel set_gdbarch_double_bit (gdbarch, 64); 5538130803Smarcel set_gdbarch_long_double_bit (gdbarch, 64); 5539130803Smarcel set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); 5540130803Smarcel set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); 5541130803Smarcel set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); 5542130803Smarcel 5543130803Smarcel set_gdbarch_elf_make_msymbol_special (gdbarch, 5544130803Smarcel mips_elf_make_msymbol_special); 5545130803Smarcel 5546130803Smarcel /* Fill in the OS dependant register numbers and names. */ 5547130803Smarcel { 5548130803Smarcel const char **reg_names; 5549130803Smarcel struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, 5550130803Smarcel struct mips_regnum); 5551130803Smarcel if (info.osabi == GDB_OSABI_IRIX) 5552130803Smarcel { 5553130803Smarcel regnum->fp0 = 32; 5554130803Smarcel regnum->pc = 64; 5555130803Smarcel regnum->cause = 65; 5556130803Smarcel regnum->badvaddr = 66; 5557130803Smarcel regnum->hi = 67; 5558130803Smarcel regnum->lo = 68; 5559130803Smarcel regnum->fp_control_status = 69; 5560130803Smarcel regnum->fp_implementation_revision = 70; 5561130803Smarcel num_regs = 71; 5562130803Smarcel reg_names = mips_irix_reg_names; 5563130803Smarcel } 5564130803Smarcel else 5565130803Smarcel { 5566130803Smarcel regnum->lo = MIPS_EMBED_LO_REGNUM; 5567130803Smarcel regnum->hi = MIPS_EMBED_HI_REGNUM; 5568130803Smarcel regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; 5569130803Smarcel regnum->cause = MIPS_EMBED_CAUSE_REGNUM; 5570130803Smarcel regnum->pc = MIPS_EMBED_PC_REGNUM; 5571130803Smarcel regnum->fp0 = MIPS_EMBED_FP0_REGNUM; 5572130803Smarcel regnum->fp_control_status = 70; 5573130803Smarcel regnum->fp_implementation_revision = 71; 5574130803Smarcel num_regs = 90; 5575130803Smarcel if (info.bfd_arch_info != NULL 5576130803Smarcel && info.bfd_arch_info->mach == bfd_mach_mips3900) 5577130803Smarcel reg_names = mips_tx39_reg_names; 5578130803Smarcel else 5579130803Smarcel reg_names = mips_generic_reg_names; 5580130803Smarcel } 5581130803Smarcel /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been 5582130803Smarcel replaced by read_pc? */ 5583130803Smarcel set_gdbarch_pc_regnum (gdbarch, regnum->pc); 5584130803Smarcel set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); 5585130803Smarcel set_gdbarch_num_regs (gdbarch, num_regs); 5586130803Smarcel set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 5587130803Smarcel set_gdbarch_register_name (gdbarch, mips_register_name); 5588130803Smarcel tdep->mips_processor_reg_names = reg_names; 5589130803Smarcel tdep->regnum = regnum; 5590130803Smarcel } 5591130803Smarcel 5592130803Smarcel switch (mips_abi) 5593130803Smarcel { 5594130803Smarcel case MIPS_ABI_O32: 5595130803Smarcel set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); 5596130803Smarcel set_gdbarch_return_value (gdbarch, mips_o32_return_value); 5597130803Smarcel tdep->mips_default_saved_regsize = 4; 5598130803Smarcel tdep->mips_default_stack_argsize = 4; 5599130803Smarcel tdep->mips_fp_register_double = 0; 5600130803Smarcel tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; 5601130803Smarcel tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 5602130803Smarcel tdep->default_mask_address_p = 0; 5603130803Smarcel set_gdbarch_long_bit (gdbarch, 32); 5604130803Smarcel set_gdbarch_ptr_bit (gdbarch, 32); 5605130803Smarcel set_gdbarch_long_long_bit (gdbarch, 64); 5606130803Smarcel break; 5607130803Smarcel case MIPS_ABI_O64: 5608130803Smarcel set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); 5609130803Smarcel set_gdbarch_deprecated_store_return_value (gdbarch, 5610130803Smarcel mips_o64_store_return_value); 5611130803Smarcel set_gdbarch_deprecated_extract_return_value (gdbarch, 5612130803Smarcel mips_o64_extract_return_value); 5613130803Smarcel tdep->mips_default_saved_regsize = 8; 5614130803Smarcel tdep->mips_default_stack_argsize = 8; 5615130803Smarcel tdep->mips_fp_register_double = 1; 5616130803Smarcel tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1; 5617130803Smarcel tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 5618130803Smarcel tdep->default_mask_address_p = 0; 5619130803Smarcel set_gdbarch_long_bit (gdbarch, 32); 5620130803Smarcel set_gdbarch_ptr_bit (gdbarch, 32); 5621130803Smarcel set_gdbarch_long_long_bit (gdbarch, 64); 5622130803Smarcel set_gdbarch_use_struct_convention (gdbarch, 5623130803Smarcel always_use_struct_convention); 5624130803Smarcel break; 5625130803Smarcel case MIPS_ABI_EABI32: 5626130803Smarcel set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 5627130803Smarcel set_gdbarch_deprecated_store_return_value (gdbarch, 5628130803Smarcel mips_eabi_store_return_value); 5629130803Smarcel set_gdbarch_deprecated_extract_return_value (gdbarch, 5630130803Smarcel mips_eabi_extract_return_value); 5631130803Smarcel tdep->mips_default_saved_regsize = 4; 5632130803Smarcel tdep->mips_default_stack_argsize = 4; 5633130803Smarcel tdep->mips_fp_register_double = 0; 5634130803Smarcel tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; 5635130803Smarcel tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 5636130803Smarcel tdep->default_mask_address_p = 0; 5637130803Smarcel set_gdbarch_long_bit (gdbarch, 32); 5638130803Smarcel set_gdbarch_ptr_bit (gdbarch, 32); 5639130803Smarcel set_gdbarch_long_long_bit (gdbarch, 64); 5640130803Smarcel set_gdbarch_deprecated_reg_struct_has_addr 5641130803Smarcel (gdbarch, mips_eabi_reg_struct_has_addr); 5642130803Smarcel set_gdbarch_use_struct_convention (gdbarch, 5643130803Smarcel mips_eabi_use_struct_convention); 5644130803Smarcel break; 5645130803Smarcel case MIPS_ABI_EABI64: 5646130803Smarcel set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 5647130803Smarcel set_gdbarch_deprecated_store_return_value (gdbarch, 5648130803Smarcel mips_eabi_store_return_value); 5649130803Smarcel set_gdbarch_deprecated_extract_return_value (gdbarch, 5650130803Smarcel mips_eabi_extract_return_value); 5651130803Smarcel tdep->mips_default_saved_regsize = 8; 5652130803Smarcel tdep->mips_default_stack_argsize = 8; 5653130803Smarcel tdep->mips_fp_register_double = 1; 5654130803Smarcel tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; 5655130803Smarcel tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 5656130803Smarcel tdep->default_mask_address_p = 0; 5657130803Smarcel set_gdbarch_long_bit (gdbarch, 64); 5658130803Smarcel set_gdbarch_ptr_bit (gdbarch, 64); 5659130803Smarcel set_gdbarch_long_long_bit (gdbarch, 64); 5660130803Smarcel set_gdbarch_deprecated_reg_struct_has_addr 5661130803Smarcel (gdbarch, mips_eabi_reg_struct_has_addr); 5662130803Smarcel set_gdbarch_use_struct_convention (gdbarch, 5663130803Smarcel mips_eabi_use_struct_convention); 5664130803Smarcel break; 5665130803Smarcel case MIPS_ABI_N32: 5666130803Smarcel set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 5667130803Smarcel set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 5668130803Smarcel tdep->mips_default_saved_regsize = 8; 5669130803Smarcel tdep->mips_default_stack_argsize = 8; 5670130803Smarcel tdep->mips_fp_register_double = 1; 5671130803Smarcel tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; 5672130803Smarcel tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 5673130803Smarcel tdep->default_mask_address_p = 0; 5674130803Smarcel set_gdbarch_long_bit (gdbarch, 32); 5675130803Smarcel set_gdbarch_ptr_bit (gdbarch, 32); 5676130803Smarcel set_gdbarch_long_long_bit (gdbarch, 64); 5677130803Smarcel break; 5678130803Smarcel case MIPS_ABI_N64: 5679130803Smarcel set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 5680130803Smarcel set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 5681130803Smarcel tdep->mips_default_saved_regsize = 8; 5682130803Smarcel tdep->mips_default_stack_argsize = 8; 5683130803Smarcel tdep->mips_fp_register_double = 1; 5684130803Smarcel tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; 5685130803Smarcel tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 5686130803Smarcel tdep->default_mask_address_p = 0; 5687130803Smarcel set_gdbarch_long_bit (gdbarch, 64); 5688130803Smarcel set_gdbarch_ptr_bit (gdbarch, 64); 5689130803Smarcel set_gdbarch_long_long_bit (gdbarch, 64); 5690130803Smarcel break; 5691130803Smarcel default: 5692130803Smarcel internal_error (__FILE__, __LINE__, "unknown ABI in switch"); 5693130803Smarcel } 5694130803Smarcel 5695130803Smarcel /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE 5696130803Smarcel that could indicate -gp32 BUT gas/config/tc-mips.c contains the 5697130803Smarcel comment: 5698130803Smarcel 5699130803Smarcel ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE 5700130803Smarcel flag in object files because to do so would make it impossible to 5701130803Smarcel link with libraries compiled without "-gp32". This is 5702130803Smarcel unnecessarily restrictive. 5703130803Smarcel 5704130803Smarcel We could solve this problem by adding "-gp32" multilibs to gcc, 5705130803Smarcel but to set this flag before gcc is built with such multilibs will 5706130803Smarcel break too many systems.'' 5707130803Smarcel 5708130803Smarcel But even more unhelpfully, the default linker output target for 5709130803Smarcel mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even 5710130803Smarcel for 64-bit programs - you need to change the ABI to change this, 5711130803Smarcel and not all gcc targets support that currently. Therefore using 5712130803Smarcel this flag to detect 32-bit mode would do the wrong thing given 5713130803Smarcel the current gcc - it would make GDB treat these 64-bit programs 5714130803Smarcel as 32-bit programs by default. */ 5715130803Smarcel 5716130803Smarcel set_gdbarch_read_pc (gdbarch, mips_read_pc); 5717130803Smarcel set_gdbarch_write_pc (gdbarch, mips_write_pc); 5718130803Smarcel set_gdbarch_read_sp (gdbarch, mips_read_sp); 5719130803Smarcel 5720130803Smarcel /* Add/remove bits from an address. The MIPS needs be careful to 5721130803Smarcel ensure that all 32 bit addresses are sign extended to 64 bits. */ 5722130803Smarcel set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); 5723130803Smarcel 5724130803Smarcel /* Unwind the frame. */ 5725130803Smarcel set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); 5726130803Smarcel frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); 5727130803Smarcel set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); 5728130803Smarcel frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); 5729130803Smarcel 5730130803Smarcel /* Map debug register numbers onto internal register numbers. */ 5731130803Smarcel set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); 5732130803Smarcel set_gdbarch_ecoff_reg_to_regnum (gdbarch, 5733130803Smarcel mips_dwarf_dwarf2_ecoff_reg_to_regnum); 5734130803Smarcel set_gdbarch_dwarf_reg_to_regnum (gdbarch, 5735130803Smarcel mips_dwarf_dwarf2_ecoff_reg_to_regnum); 5736130803Smarcel set_gdbarch_dwarf2_reg_to_regnum (gdbarch, 5737130803Smarcel mips_dwarf_dwarf2_ecoff_reg_to_regnum); 5738130803Smarcel set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); 5739130803Smarcel 5740130803Smarcel /* MIPS version of CALL_DUMMY */ 5741130803Smarcel 5742130803Smarcel /* NOTE: cagney/2003-08-05: Eventually call dummy location will be 5743130803Smarcel replaced by a command, and all targets will default to on stack 5744130803Smarcel (regardless of the stack's execute status). */ 5745130803Smarcel set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); 5746130803Smarcel set_gdbarch_frame_align (gdbarch, mips_frame_align); 5747130803Smarcel 5748130803Smarcel set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); 5749130803Smarcel set_gdbarch_register_to_value (gdbarch, mips_register_to_value); 5750130803Smarcel set_gdbarch_value_to_register (gdbarch, mips_value_to_register); 5751130803Smarcel 5752130803Smarcel set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 5753130803Smarcel set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); 5754130803Smarcel 5755130803Smarcel set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); 5756130803Smarcel 5757130803Smarcel set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); 5758130803Smarcel set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); 5759130803Smarcel set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); 5760130803Smarcel 5761130803Smarcel set_gdbarch_register_type (gdbarch, mips_register_type); 5762130803Smarcel 5763130803Smarcel set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); 5764130803Smarcel set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp); 5765130803Smarcel 5766130803Smarcel set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); 5767130803Smarcel 5768130803Smarcel /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, 5769130803Smarcel HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT 5770130803Smarcel need to all be folded into the target vector. Since they are 5771130803Smarcel being used as guards for STOPPED_BY_WATCHPOINT, why not have 5772130803Smarcel STOPPED_BY_WATCHPOINT return the type of watchpoint that the code 5773130803Smarcel is sitting on? */ 5774130803Smarcel set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 5775130803Smarcel 5776130803Smarcel set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); 5777130803Smarcel 5778130803Smarcel /* NOTE drow/2004-02-11: We overload the core solib trampoline code 5779130803Smarcel to support MIPS16. This is a bad thing. Make sure not to do it 5780130803Smarcel if we have an OS ABI that actually supports shared libraries, since 5781130803Smarcel shared library support is more important. If we have an OS someday 5782130803Smarcel that supports both shared libraries and MIPS16, we'll have to find 5783130803Smarcel a better place for these. */ 5784130803Smarcel if (info.osabi == GDB_OSABI_UNKNOWN) 5785130803Smarcel { 5786130803Smarcel set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); 5787130803Smarcel set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); 5788130803Smarcel } 5789130803Smarcel 5790130803Smarcel /* Hook in OS ABI-specific overrides, if they have been registered. */ 5791130803Smarcel gdbarch_init_osabi (info, gdbarch); 5792130803Smarcel 5793130803Smarcel return gdbarch; 5794130803Smarcel} 5795130803Smarcel 5796130803Smarcelstatic void 5797130803Smarcelmips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) 5798130803Smarcel{ 5799130803Smarcel struct gdbarch_info info; 5800130803Smarcel 5801130803Smarcel /* Force the architecture to update, and (if it's a MIPS architecture) 5802130803Smarcel mips_gdbarch_init will take care of the rest. */ 5803130803Smarcel gdbarch_info_init (&info); 5804130803Smarcel gdbarch_update_p (info); 5805130803Smarcel} 5806130803Smarcel 5807130803Smarcel/* Print out which MIPS ABI is in use. */ 5808130803Smarcel 5809130803Smarcelstatic void 5810130803Smarcelshow_mips_abi (char *ignore_args, int from_tty) 5811130803Smarcel{ 5812130803Smarcel if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) 5813130803Smarcel printf_filtered 5814130803Smarcel ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); 5815130803Smarcel else 5816130803Smarcel { 5817130803Smarcel enum mips_abi global_abi = global_mips_abi (); 5818130803Smarcel enum mips_abi actual_abi = mips_abi (current_gdbarch); 5819130803Smarcel const char *actual_abi_str = mips_abi_strings[actual_abi]; 5820130803Smarcel 5821130803Smarcel if (global_abi == MIPS_ABI_UNKNOWN) 5822130803Smarcel printf_filtered 5823130803Smarcel ("The MIPS ABI is set automatically (currently \"%s\").\n", 5824130803Smarcel actual_abi_str); 5825130803Smarcel else if (global_abi == actual_abi) 5826130803Smarcel printf_filtered 5827130803Smarcel ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", 5828130803Smarcel actual_abi_str); 5829130803Smarcel else 5830130803Smarcel { 5831130803Smarcel /* Probably shouldn't happen... */ 5832130803Smarcel printf_filtered 5833130803Smarcel ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", 5834130803Smarcel actual_abi_str, mips_abi_strings[global_abi]); 5835130803Smarcel } 5836130803Smarcel } 5837130803Smarcel} 5838130803Smarcel 5839130803Smarcelstatic void 5840130803Smarcelmips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) 5841130803Smarcel{ 5842130803Smarcel struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 5843130803Smarcel if (tdep != NULL) 5844130803Smarcel { 5845130803Smarcel int ef_mips_arch; 5846130803Smarcel int ef_mips_32bitmode; 5847130803Smarcel /* determine the ISA */ 5848130803Smarcel switch (tdep->elf_flags & EF_MIPS_ARCH) 5849130803Smarcel { 5850130803Smarcel case E_MIPS_ARCH_1: 5851130803Smarcel ef_mips_arch = 1; 5852130803Smarcel break; 5853130803Smarcel case E_MIPS_ARCH_2: 5854130803Smarcel ef_mips_arch = 2; 5855130803Smarcel break; 5856130803Smarcel case E_MIPS_ARCH_3: 5857130803Smarcel ef_mips_arch = 3; 5858130803Smarcel break; 5859130803Smarcel case E_MIPS_ARCH_4: 5860130803Smarcel ef_mips_arch = 4; 5861130803Smarcel break; 5862130803Smarcel default: 5863130803Smarcel ef_mips_arch = 0; 5864130803Smarcel break; 5865130803Smarcel } 5866130803Smarcel /* determine the size of a pointer */ 5867130803Smarcel ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); 5868130803Smarcel fprintf_unfiltered (file, 5869130803Smarcel "mips_dump_tdep: tdep->elf_flags = 0x%x\n", 5870130803Smarcel tdep->elf_flags); 5871130803Smarcel fprintf_unfiltered (file, 5872130803Smarcel "mips_dump_tdep: ef_mips_32bitmode = %d\n", 5873130803Smarcel ef_mips_32bitmode); 5874130803Smarcel fprintf_unfiltered (file, 5875130803Smarcel "mips_dump_tdep: ef_mips_arch = %d\n", 5876130803Smarcel ef_mips_arch); 5877130803Smarcel fprintf_unfiltered (file, 5878130803Smarcel "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", 5879130803Smarcel tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); 5880130803Smarcel fprintf_unfiltered (file, 5881130803Smarcel "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", 5882130803Smarcel mips_mask_address_p (tdep), 5883130803Smarcel tdep->default_mask_address_p); 5884130803Smarcel } 5885130803Smarcel fprintf_unfiltered (file, 5886130803Smarcel "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", 5887130803Smarcel FP_REGISTER_DOUBLE); 5888130803Smarcel fprintf_unfiltered (file, 5889130803Smarcel "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", 5890130803Smarcel MIPS_DEFAULT_FPU_TYPE, 5891130803Smarcel (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" 5892130803Smarcel : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" 5893130803Smarcel : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" 5894130803Smarcel : "???")); 5895130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); 5896130803Smarcel fprintf_unfiltered (file, 5897130803Smarcel "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", 5898130803Smarcel MIPS_FPU_TYPE, 5899130803Smarcel (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" 5900130803Smarcel : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" 5901130803Smarcel : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" 5902130803Smarcel : "???")); 5903130803Smarcel fprintf_unfiltered (file, 5904130803Smarcel "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n", 5905130803Smarcel FP_REGISTER_DOUBLE); 5906130803Smarcel fprintf_unfiltered (file, 5907130803Smarcel "mips_dump_tdep: mips_stack_argsize() = %d\n", 5908130803Smarcel mips_stack_argsize (tdep)); 5909130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM); 5910130803Smarcel fprintf_unfiltered (file, 5911130803Smarcel "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", 5912130803Smarcel XSTRING (ADDR_BITS_REMOVE (ADDR))); 5913130803Smarcel fprintf_unfiltered (file, 5914130803Smarcel "mips_dump_tdep: ATTACH_DETACH # %s\n", 5915130803Smarcel XSTRING (ATTACH_DETACH)); 5916130803Smarcel fprintf_unfiltered (file, 5917130803Smarcel "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", 5918130803Smarcel XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); 5919130803Smarcel fprintf_unfiltered (file, 5920130803Smarcel "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", 5921130803Smarcel XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); 5922130803Smarcel fprintf_unfiltered (file, 5923130803Smarcel "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", 5924130803Smarcel FIRST_EMBED_REGNUM); 5925130803Smarcel fprintf_unfiltered (file, 5926130803Smarcel "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n", 5927130803Smarcel XSTRING (IGNORE_HELPER_CALL (PC))); 5928130803Smarcel fprintf_unfiltered (file, 5929130803Smarcel "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", 5930130803Smarcel XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); 5931130803Smarcel fprintf_unfiltered (file, 5932130803Smarcel "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n", 5933130803Smarcel XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME))); 5934130803Smarcel fprintf_unfiltered (file, 5935130803Smarcel "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", 5936130803Smarcel LAST_EMBED_REGNUM); 5937130803Smarcel#ifdef MACHINE_CPROC_FP_OFFSET 5938130803Smarcel fprintf_unfiltered (file, 5939130803Smarcel "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", 5940130803Smarcel MACHINE_CPROC_FP_OFFSET); 5941130803Smarcel#endif 5942130803Smarcel#ifdef MACHINE_CPROC_PC_OFFSET 5943130803Smarcel fprintf_unfiltered (file, 5944130803Smarcel "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", 5945130803Smarcel MACHINE_CPROC_PC_OFFSET); 5946130803Smarcel#endif 5947130803Smarcel#ifdef MACHINE_CPROC_SP_OFFSET 5948130803Smarcel fprintf_unfiltered (file, 5949130803Smarcel "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", 5950130803Smarcel MACHINE_CPROC_SP_OFFSET); 5951130803Smarcel#endif 5952130803Smarcel fprintf_unfiltered (file, 5953130803Smarcel "mips_dump_tdep: MIPS16_INSTLEN = %d\n", 5954130803Smarcel MIPS16_INSTLEN); 5955130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); 5956130803Smarcel fprintf_unfiltered (file, 5957130803Smarcel "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); 5958130803Smarcel fprintf_unfiltered (file, 5959130803Smarcel "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN); 5960130803Smarcel fprintf_unfiltered (file, 5961130803Smarcel "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", 5962130803Smarcel MIPS_LAST_ARG_REGNUM, 5963130803Smarcel MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1); 5964130803Smarcel fprintf_unfiltered (file, 5965130803Smarcel "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); 5966130803Smarcel fprintf_unfiltered (file, 5967130803Smarcel "mips_dump_tdep: mips_saved_regsize() = %d\n", 5968130803Smarcel mips_saved_regsize (tdep)); 5969130803Smarcel fprintf_unfiltered (file, 5970130803Smarcel "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); 5971130803Smarcel fprintf_unfiltered (file, 5972130803Smarcel "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n"); 5973130803Smarcel fprintf_unfiltered (file, 5974130803Smarcel "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); 5975130803Smarcel fprintf_unfiltered (file, 5976130803Smarcel "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); 5977130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); 5978130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); 5979130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); 5980130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); 5981130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); 5982130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); 5983130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); 5984130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); 5985130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); 5986130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); 5987130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM); 5988130803Smarcel#ifdef SAVED_BYTES 5989130803Smarcel fprintf_unfiltered (file, 5990130803Smarcel "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); 5991130803Smarcel#endif 5992130803Smarcel#ifdef SAVED_FP 5993130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); 5994130803Smarcel#endif 5995130803Smarcel#ifdef SAVED_PC 5996130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); 5997130803Smarcel#endif 5998130803Smarcel fprintf_unfiltered (file, 5999130803Smarcel "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", 6000130803Smarcel XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); 6001130803Smarcel fprintf_unfiltered (file, 6002130803Smarcel "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n"); 6003130803Smarcel fprintf_unfiltered (file, 6004130803Smarcel "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n", 6005130803Smarcel XSTRING (SKIP_TRAMPOLINE_CODE (PC))); 6006130803Smarcel fprintf_unfiltered (file, 6007130803Smarcel "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", 6008130803Smarcel XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); 6009130803Smarcel fprintf_unfiltered (file, 6010130803Smarcel "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", 6011130803Smarcel SOFTWARE_SINGLE_STEP_P ()); 6012130803Smarcel fprintf_unfiltered (file, 6013130803Smarcel "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", 6014130803Smarcel XSTRING (STAB_REG_TO_REGNUM (REGNUM))); 6015130803Smarcel#ifdef STACK_END_ADDR 6016130803Smarcel fprintf_unfiltered (file, 6017130803Smarcel "mips_dump_tdep: STACK_END_ADDR = %d\n", 6018130803Smarcel STACK_END_ADDR); 6019130803Smarcel#endif 6020130803Smarcel fprintf_unfiltered (file, 6021130803Smarcel "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", 6022130803Smarcel XSTRING (STEP_SKIPS_DELAY (PC))); 6023130803Smarcel fprintf_unfiltered (file, 6024130803Smarcel "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", 6025130803Smarcel STEP_SKIPS_DELAY_P); 6026130803Smarcel fprintf_unfiltered (file, 6027130803Smarcel "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", 6028130803Smarcel XSTRING (STOPPED_BY_WATCHPOINT (WS))); 6029130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM); 6030130803Smarcel fprintf_unfiltered (file, 6031130803Smarcel "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); 6032130803Smarcel fprintf_unfiltered (file, 6033130803Smarcel "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", 6034130803Smarcel XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT 6035130803Smarcel (TYPE, CNT, OTHERTYPE))); 6036130803Smarcel fprintf_unfiltered (file, 6037130803Smarcel "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n", 6038130803Smarcel XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS)); 6039130803Smarcel#ifdef TRACE_CLEAR 6040130803Smarcel fprintf_unfiltered (file, 6041130803Smarcel "mips_dump_tdep: TRACE_CLEAR # %s\n", 6042130803Smarcel XSTRING (TRACE_CLEAR (THREAD, STATE))); 6043130803Smarcel#endif 6044130803Smarcel#ifdef TRACE_FLAVOR 6045130803Smarcel fprintf_unfiltered (file, 6046130803Smarcel "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); 6047130803Smarcel#endif 6048130803Smarcel#ifdef TRACE_FLAVOR_SIZE 6049130803Smarcel fprintf_unfiltered (file, 6050130803Smarcel "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", 6051130803Smarcel TRACE_FLAVOR_SIZE); 6052130803Smarcel#endif 6053130803Smarcel#ifdef TRACE_SET 6054130803Smarcel fprintf_unfiltered (file, 6055130803Smarcel "mips_dump_tdep: TRACE_SET # %s\n", 6056130803Smarcel XSTRING (TRACE_SET (X, STATE))); 6057130803Smarcel#endif 6058130803Smarcel#ifdef UNUSED_REGNUM 6059130803Smarcel fprintf_unfiltered (file, 6060130803Smarcel "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); 6061130803Smarcel#endif 6062130803Smarcel fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM); 6063130803Smarcel fprintf_unfiltered (file, 6064130803Smarcel "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", 6065130803Smarcel (long) VM_MIN_ADDRESS); 6066130803Smarcel fprintf_unfiltered (file, 6067130803Smarcel "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM); 6068130803Smarcel fprintf_unfiltered (file, 6069130803Smarcel "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_); 6070130803Smarcel} 6071130803Smarcel 6072130803Smarcelextern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ 6073130803Smarcel 6074130803Smarcelvoid 6075130803Smarcel_initialize_mips_tdep (void) 6076130803Smarcel{ 6077130803Smarcel static struct cmd_list_element *mipsfpulist = NULL; 6078130803Smarcel struct cmd_list_element *c; 6079130803Smarcel 6080130803Smarcel mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; 6081130803Smarcel if (MIPS_ABI_LAST + 1 6082130803Smarcel != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) 6083130803Smarcel internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); 6084130803Smarcel 6085130803Smarcel gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); 6086130803Smarcel 6087130803Smarcel mips_pdr_data = register_objfile_data (); 6088130803Smarcel 6089130803Smarcel /* Add root prefix command for all "set mips"/"show mips" commands */ 6090130803Smarcel add_prefix_cmd ("mips", no_class, set_mips_command, 6091130803Smarcel "Various MIPS specific commands.", 6092130803Smarcel &setmipscmdlist, "set mips ", 0, &setlist); 6093130803Smarcel 6094130803Smarcel add_prefix_cmd ("mips", no_class, show_mips_command, 6095130803Smarcel "Various MIPS specific commands.", 6096130803Smarcel &showmipscmdlist, "show mips ", 0, &showlist); 6097130803Smarcel 6098130803Smarcel /* Allow the user to override the saved register size. */ 6099130803Smarcel add_show_from_set (add_set_enum_cmd ("saved-gpreg-size", 6100130803Smarcel class_obscure, 6101130803Smarcel size_enums, 6102130803Smarcel &mips_saved_regsize_string, "\ 6103130803SmarcelSet size of general purpose registers saved on the stack.\n\ 6104130803SmarcelThis option can be set to one of:\n\ 6105130803Smarcel 32 - Force GDB to treat saved GP registers as 32-bit\n\ 6106130803Smarcel 64 - Force GDB to treat saved GP registers as 64-bit\n\ 6107130803Smarcel auto - Allow GDB to use the target's default setting or autodetect the\n\ 6108130803Smarcel saved GP register size from information contained in the executable.\n\ 6109130803Smarcel (default: auto)", &setmipscmdlist), &showmipscmdlist); 6110130803Smarcel 6111130803Smarcel /* Allow the user to override the argument stack size. */ 6112130803Smarcel add_show_from_set (add_set_enum_cmd ("stack-arg-size", 6113130803Smarcel class_obscure, 6114130803Smarcel size_enums, 6115130803Smarcel &mips_stack_argsize_string, "\ 6116130803SmarcelSet the amount of stack space reserved for each argument.\n\ 6117130803SmarcelThis option can be set to one of:\n\ 6118130803Smarcel 32 - Force GDB to allocate 32-bit chunks per argument\n\ 6119130803Smarcel 64 - Force GDB to allocate 64-bit chunks per argument\n\ 6120130803Smarcel auto - Allow GDB to determine the correct setting from the current\n\ 6121130803Smarcel target and executable (default)", &setmipscmdlist), &showmipscmdlist); 6122130803Smarcel 6123130803Smarcel /* Allow the user to override the ABI. */ 6124130803Smarcel c = add_set_enum_cmd 6125130803Smarcel ("abi", class_obscure, mips_abi_strings, &mips_abi_string, 6126130803Smarcel "Set the ABI used by this program.\n" 6127130803Smarcel "This option can be set to one of:\n" 6128130803Smarcel " auto - the default ABI associated with the current binary\n" 6129130803Smarcel " o32\n" 6130130803Smarcel " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); 6131130803Smarcel set_cmd_sfunc (c, mips_abi_update); 6132130803Smarcel add_cmd ("abi", class_obscure, show_mips_abi, 6133130803Smarcel "Show ABI in use by MIPS target", &showmipscmdlist); 6134130803Smarcel 6135130803Smarcel /* Let the user turn off floating point and set the fence post for 6136130803Smarcel heuristic_proc_start. */ 6137130803Smarcel 6138130803Smarcel add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, 6139130803Smarcel "Set use of MIPS floating-point coprocessor.", 6140130803Smarcel &mipsfpulist, "set mipsfpu ", 0, &setlist); 6141130803Smarcel add_cmd ("single", class_support, set_mipsfpu_single_command, 6142130803Smarcel "Select single-precision MIPS floating-point coprocessor.", 6143130803Smarcel &mipsfpulist); 6144130803Smarcel add_cmd ("double", class_support, set_mipsfpu_double_command, 6145130803Smarcel "Select double-precision MIPS floating-point coprocessor.", 6146130803Smarcel &mipsfpulist); 6147130803Smarcel add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); 6148130803Smarcel add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); 6149130803Smarcel add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); 6150130803Smarcel add_cmd ("none", class_support, set_mipsfpu_none_command, 6151130803Smarcel "Select no MIPS floating-point coprocessor.", &mipsfpulist); 6152130803Smarcel add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); 6153130803Smarcel add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); 6154130803Smarcel add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); 6155130803Smarcel add_cmd ("auto", class_support, set_mipsfpu_auto_command, 6156130803Smarcel "Select MIPS floating-point coprocessor automatically.", 6157130803Smarcel &mipsfpulist); 6158130803Smarcel add_cmd ("mipsfpu", class_support, show_mipsfpu_command, 6159130803Smarcel "Show current use of MIPS floating-point coprocessor target.", 6160130803Smarcel &showlist); 6161130803Smarcel 6162130803Smarcel /* We really would like to have both "0" and "unlimited" work, but 6163130803Smarcel command.c doesn't deal with that. So make it a var_zinteger 6164130803Smarcel because the user can always use "999999" or some such for unlimited. */ 6165130803Smarcel c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, 6166130803Smarcel (char *) &heuristic_fence_post, "\ 6167130803SmarcelSet the distance searched for the start of a function.\n\ 6168130803SmarcelIf you are debugging a stripped executable, GDB needs to search through the\n\ 6169130803Smarcelprogram for the start of a function. This command sets the distance of the\n\ 6170130803Smarcelsearch. The only need to set it is when debugging a stripped executable.", &setlist); 6171130803Smarcel /* We need to throw away the frame cache when we set this, since it 6172130803Smarcel might change our ability to get backtraces. */ 6173130803Smarcel set_cmd_sfunc (c, reinit_frame_cache_sfunc); 6174130803Smarcel add_show_from_set (c, &showlist); 6175130803Smarcel 6176130803Smarcel /* Allow the user to control whether the upper bits of 64-bit 6177130803Smarcel addresses should be zeroed. */ 6178130803Smarcel add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ 6179130803SmarcelSet zeroing of upper 32 bits of 64-bit addresses.\n\ 6180130803SmarcelUse \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ 6181130803Smarcelallow GDB to determine the correct value.\n", "\ 6182130803SmarcelShow zeroing of upper 32 bits of 64-bit addresses.", 6183130803Smarcel NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); 6184130803Smarcel 6185130803Smarcel /* Allow the user to control the size of 32 bit registers within the 6186130803Smarcel raw remote packet. */ 6187130803Smarcel add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, 6188130803Smarcel var_boolean, &mips64_transfers_32bit_regs_p, "\ 6189130803SmarcelSet compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ 6190130803SmarcelUse \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ 6191130803Smarcelthat would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ 6192130803Smarcel64 bits for others. Use \"off\" to disable compatibility mode", "\ 6193130803SmarcelShow compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\ 6194130803SmarcelUse \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ 6195130803Smarcelthat would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ 6196130803Smarcel64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); 6197130803Smarcel 6198130803Smarcel /* Debug this files internals. */ 6199130803Smarcel add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger, 6200130803Smarcel &mips_debug, "Set mips debugging.\n\ 6201130803SmarcelWhen non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist); 6202130803Smarcel} 6203