rtl.def revision 96489
1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000 5 Free Software Foundation, Inc. 6 7This file is part of GCC. 8 9GCC is free software; you can redistribute it and/or modify it under 10the terms of the GNU General Public License as published by the Free 11Software Foundation; either version 2, or (at your option) any later 12version. 13 14GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15WARRANTY; without even the implied warranty of MERCHANTABILITY or 16FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17for more details. 18 19You should have received a copy of the GNU General Public License 20along with GCC; see the file COPYING. If not, write to the Free 21Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2202111-1307, USA. */ 23 24 25/* Expression definitions and descriptions for all targets are in this file. 26 Some will not be used for some targets. 27 28 The fields in the cpp macro call "DEF_RTL_EXPR()" 29 are used to create declarations in the C source of the compiler. 30 31 The fields are: 32 33 1. The internal name of the rtx used in the C source. 34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 35 By convention these are in UPPER_CASE. 36 37 2. The name of the rtx in the external ASCII format read by 38 read_rtx(), and printed by print_rtx(). 39 These names are stored in rtx_name[]. 40 By convention these are the internal (field 1) names in lower_case. 41 42 3. The print format, and type of each rtx->fld[] (field) in this rtx. 43 These formats are stored in rtx_format[]. 44 The meaning of the formats is documented in front of this array in rtl.c 45 46 4. The class of the rtx. These are stored in rtx_class and are accessed 47 via the GET_RTX_CLASS macro. They are defined as follows: 48 49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM) 50 "<" an rtx code for a comparison (e.g, EQ, NE, LT) 51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP) 58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL) 59 "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC) 60 "x" everything else 61 62 */ 63 64/* --------------------------------------------------------------------- 65 Expressions (and "meta" expressions) used for structuring the 66 rtl representation of a program. 67 --------------------------------------------------------------------- */ 68 69/* an expression code name unknown to the reader */ 70DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x') 71 72/* (NIL) is used by rtl reader and printer to represent a null pointer. */ 73 74DEF_RTL_EXPR(NIL, "nil", "*", 'x') 75 76 77/* include a file */ 78 79DEF_RTL_EXPR(INCLUDE, "include", "s", 'x') 80 81/* --------------------------------------------------------------------- 82 Expressions used in constructing lists. 83 --------------------------------------------------------------------- */ 84 85/* a linked list of expressions */ 86DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x') 87 88/* a linked list of instructions. 89 The insns are represented in print by their uids. */ 90DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x') 91 92/* ---------------------------------------------------------------------- 93 Expression types for machine descriptions. 94 These do not appear in actual rtl code in the compiler. 95 ---------------------------------------------------------------------- */ 96 97/* Appears only in machine descriptions. 98 Means use the function named by the second arg (the string) 99 as a predicate; if matched, store the structure that was matched 100 in the operand table at index specified by the first arg (the integer). 101 If the second arg is the null string, the structure is just stored. 102 103 A third string argument indicates to the register allocator restrictions 104 on where the operand can be allocated. 105 106 If the target needs no restriction on any instruction this field should 107 be the null string. 108 109 The string is prepended by: 110 '=' to indicate the operand is only written to. 111 '+' to indicate the operand is both read and written to. 112 113 Each character in the string represents an allocable class for an operand. 114 'g' indicates the operand can be any valid class. 115 'i' indicates the operand can be immediate (in the instruction) data. 116 'r' indicates the operand can be in a register. 117 'm' indicates the operand can be in memory. 118 'o' a subset of the 'm' class. Those memory addressing modes that 119 can be offset at compile time (have a constant added to them). 120 121 Other characters indicate target dependent operand classes and 122 are described in each target's machine description. 123 124 For instructions with more than one operand, sets of classes can be 125 separated by a comma to indicate the appropriate multi-operand constraints. 126 There must be a 1 to 1 correspondence between these sets of classes in 127 all operands for an instruction. 128 */ 129DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm') 130 131/* Appears only in machine descriptions. 132 Means match a SCRATCH or a register. When used to generate rtl, a 133 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 134 the desired mode and the first argument is the operand number. 135 The second argument is the constraint. */ 136DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm') 137 138/* Appears only in machine descriptions. 139 Means match only something equal to what is stored in the operand table 140 at the index specified by the argument. */ 141DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm') 142 143/* Appears only in machine descriptions. 144 Means apply a predicate, AND match recursively the operands of the rtx. 145 Operand 0 is the operand-number, as in match_operand. 146 Operand 1 is a predicate to apply (as a string, a function name). 147 Operand 2 is a vector of expressions, each of which must match 148 one subexpression of the rtx this construct is matching. */ 149DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm') 150 151/* Appears only in machine descriptions. 152 Means to match a PARALLEL of arbitrary length. The predicate is applied 153 to the PARALLEL and the initial expressions in the PARALLEL are matched. 154 Operand 0 is the operand-number, as in match_operand. 155 Operand 1 is a predicate to apply to the PARALLEL. 156 Operand 2 is a vector of expressions, each of which must match the 157 corresponding element in the PARALLEL. */ 158DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm') 159 160/* Appears only in machine descriptions. 161 Means match only something equal to what is stored in the operand table 162 at the index specified by the argument. For MATCH_OPERATOR. */ 163DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm') 164 165/* Appears only in machine descriptions. 166 Means match only something equal to what is stored in the operand table 167 at the index specified by the argument. For MATCH_PARALLEL. */ 168DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm') 169 170/* Appears only in machine descriptions. 171 Operand 0 is the operand number, as in match_operand. 172 Operand 1 is the predicate to apply to the insn. */ 173DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm') 174 175/* Appears only in machine descriptions. 176 Defines the pattern for one kind of instruction. 177 Operand: 178 0: names this instruction. 179 If the name is the null string, the instruction is in the 180 machine description just to be recognized, and will never be emitted by 181 the tree to rtl expander. 182 1: is the pattern. 183 2: is a string which is a C expression 184 giving an additional condition for recognizing this pattern. 185 A null string means no extra condition. 186 3: is the action to execute if this pattern is matched. 187 If this assembler code template starts with a * then it is a fragment of 188 C code to run to decide on a template to use. Otherwise, it is the 189 template to use. 190 4: optionally, a vector of attributes for this insn. 191 */ 192DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x') 193 194/* Definition of a peephole optimization. 195 1st operand: vector of insn patterns to match 196 2nd operand: C expression that must be true 197 3rd operand: template or C code to produce assembler output. 198 4: optionally, a vector of attributes for this insn. 199 */ 200DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x') 201 202/* Definition of a split operation. 203 1st operand: insn pattern to match 204 2nd operand: C expression that must be true 205 3rd operand: vector of insn patterns to place into a SEQUENCE 206 4th operand: optionally, some C code to execute before generating the 207 insns. This might, for example, create some RTX's and store them in 208 elements of `recog_data.operand' for use by the vector of 209 insn-patterns. 210 (`operands' is an alias here for `recog_data.operand'). */ 211DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x') 212 213/* Definition of an insn and associated split. 214 This is the concatenation, with a few modifications, of a define_insn 215 and a define_split which share the same pattern. 216 Operand: 217 0: names this instruction. 218 If the name is the null string, the instruction is in the 219 machine description just to be recognized, and will never be emitted by 220 the tree to rtl expander. 221 1: is the pattern. 222 2: is a string which is a C expression 223 giving an additional condition for recognizing this pattern. 224 A null string means no extra condition. 225 3: is the action to execute if this pattern is matched. 226 If this assembler code template starts with a * then it is a fragment of 227 C code to run to decide on a template to use. Otherwise, it is the 228 template to use. 229 4: C expression that must be true for split. This may start with "&&" 230 in which case the split condition is the logical and of the insn 231 condition and what follows the "&&" of this operand. 232 5: vector of insn patterns to place into a SEQUENCE 233 6: optionally, some C code to execute before generating the 234 insns. This might, for example, create some RTX's and store them in 235 elements of `recog_data.operand' for use by the vector of 236 insn-patterns. 237 (`operands' is an alias here for `recog_data.operand'). 238 7: optionally, a vector of attributes for this insn. */ 239DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x') 240 241/* Definition of an RTL peephole operation. 242 Follows the same arguments as define_split. */ 243DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x') 244 245/* Definition of a combiner pattern. 246 Operands not defined yet. */ 247DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x') 248 249/* Define how to generate multiple insns for a standard insn name. 250 1st operand: the insn name. 251 2nd operand: vector of insn-patterns. 252 Use match_operand to substitute an element of `recog_data.operand'. 253 3rd operand: C expression that must be true for this to be available. 254 This may not test any operands. 255 4th operand: Extra C code to execute before generating the insns. 256 This might, for example, create some RTX's and store them in 257 elements of `recog_data.operand' for use by the vector of 258 insn-patterns. 259 (`operands' is an alias here for `recog_data.operand'). */ 260DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x') 261 262/* Define a requirement for delay slots. 263 1st operand: Condition involving insn attributes that, if true, 264 indicates that the insn requires the number of delay slots 265 shown. 266 2nd operand: Vector whose length is the three times the number of delay 267 slots required. 268 Each entry gives three conditions, each involving attributes. 269 The first must be true for an insn to occupy that delay slot 270 location. The second is true for all insns that can be 271 annulled if the branch is true and the third is true for all 272 insns that can be annulled if the branch is false. 273 274 Multiple DEFINE_DELAYs may be present. They indicate differing 275 requirements for delay slots. */ 276DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x') 277 278/* Define a set of insns that requires a function unit. This means that 279 these insns produce their result after a delay and that there may be 280 restrictions on the number of insns of this type that can be scheduled 281 simultaneously. 282 283 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. 284 Each gives a set of operations and associated delays. The first three 285 operands must be the same for each operation for the same function unit. 286 287 All delays are specified in cycles. 288 289 1st operand: Name of function unit (mostly for documentation) 290 2nd operand: Number of identical function units in CPU 291 3rd operand: Total number of simultaneous insns that can execute on this 292 function unit; 0 if unlimited. 293 4th operand: Condition involving insn attribute, that, if true, specifies 294 those insns that this expression applies to. 295 5th operand: Constant delay after which insn result will be 296 available. 297 6th operand: Delay until next insn can be scheduled on the function unit 298 executing this operation. The meaning depends on whether or 299 not the next operand is supplied. 300 7th operand: If this operand is not specified, the 6th operand gives the 301 number of cycles after the instruction matching the 4th 302 operand begins using the function unit until a subsequent 303 insn can begin. A value of zero should be used for a 304 unit with no issue constraints. If only one operation can 305 be executed a time and the unit is busy for the entire time, 306 the 3rd operand should be specified as 1, the 6th operand 307 should be specified as 0, and the 7th operand should not 308 be specified. 309 310 If this operand is specified, it is a list of attribute 311 expressions. If an insn for which any of these expressions 312 is true is currently executing on the function unit, the 313 issue delay will be given by the 6th operand. Otherwise, 314 the insn can be immediately scheduled (subject to the limit 315 on the number of simultaneous operations executing on the 316 unit.) */ 317DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x') 318 319/* Define attribute computation for `asm' instructions. */ 320DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' ) 321 322/* Definition of a conditional execution meta operation. Automatically 323 generates new instances of DEFINE_INSN, selected by having attribute 324 "predicable" true. The new pattern will contain a COND_EXEC and the 325 predicate at top-level. 326 327 Operand: 328 0: The predicate pattern. The top-level form should match a 329 relational operator. Operands should have only one alternative. 330 1: A C expression giving an additional condition for recognizing 331 the generated pattern. 332 2: A template or C code to produce assembler output. */ 333DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x') 334 335/* SEQUENCE appears in the result of a `gen_...' function 336 for a DEFINE_EXPAND that wants to make several insns. 337 Its elements are the bodies of the insns that should be made. 338 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 339DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x') 340 341/* Refers to the address of its argument. This is only used in alias.c. */ 342DEF_RTL_EXPR(ADDRESS, "address", "e", 'm') 343 344/* ---------------------------------------------------------------------- 345 Expressions used for insn attributes. These also do not appear in 346 actual rtl code in the compiler. 347 ---------------------------------------------------------------------- */ 348 349/* Definition of an insn attribute. 350 1st operand: name of the attribute 351 2nd operand: comma-separated list of possible attribute values 352 3rd operand: expression for the default value of the attribute. */ 353DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x') 354 355/* Marker for the name of an attribute. */ 356DEF_RTL_EXPR(ATTR, "attr", "s", 'x') 357 358/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 359 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 360 pattern. 361 362 (set_attr "name" "value") is equivalent to 363 (set (attr "name") (const_string "value")) */ 364DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x') 365 366/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 367 specify that attribute values are to be assigned according to the 368 alternative matched. 369 370 The following three expressions are equivalent: 371 372 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 373 (eq_attrq "alternative" "2") (const_string "a2")] 374 (const_string "a3"))) 375 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 376 (const_string "a3")]) 377 (set_attr "att" "a1,a2,a3") 378 */ 379DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x') 380 381/* A conditional expression true if the value of the specified attribute of 382 the current insn equals the specified value. The first operand is the 383 attribute name and the second is the comparison value. */ 384DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x') 385 386/* A conditional expression which is true if the specified flag is 387 true for the insn being scheduled in reorg. 388 389 genattr.c defines the following flags which can be tested by 390 (attr_flag "foo") expressions in eligible_for_delay. 391 392 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 393 394DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x') 395 396/* ---------------------------------------------------------------------- 397 Expression types used for things in the instruction chain. 398 399 All formats must start with "iuu" to handle the chain. 400 Each insn expression holds an rtl instruction and its semantics 401 during back-end processing. 402 See macros's in "rtl.h" for the meaning of each rtx->fld[]. 403 404 ---------------------------------------------------------------------- */ 405 406/* An instruction that cannot jump. */ 407DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i') 408 409/* An instruction that can possibly jump. 410 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */ 411DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i') 412 413/* An instruction that can possibly call a subroutine 414 but which will not change which instruction comes next 415 in the current function. 416 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE. 417 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */ 418DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i') 419 420/* A marker that indicates that control will not flow through. */ 421DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x') 422 423/* Holds a label that is followed by instructions. 424 Operand: 425 3: is used in jump.c for the use-count of the label. 426 4: is used in flow.c to point to the chain of label_ref's to this label. 427 5: is a number that is unique in the entire compilation. 428 6: is the user-given name of the label, if any. 429 7: is the alternate label name. */ 430DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuu00iss", 'x') 431 432/* Say where in the code a source line starts, for symbol table's sake. 433 Operand: 434 3: filename, if line number > 0, note-specific data otherwise. 435 4: line number if > 0, enum note_insn otherwise. 436 5: unique number if line number == note_insn_deleted_label. */ 437DEF_RTL_EXPR(NOTE, "note", "iuu0ni", 'x') 438 439/* ---------------------------------------------------------------------- 440 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 441 ---------------------------------------------------------------------- */ 442 443/* Conditionally execute code. 444 Operand 0 is the condition that if true, the code is executed. 445 Operand 1 is the code to be executed (typically a SET). 446 447 Semantics are that there are no side effects if the condition 448 is false. This pattern is created automatically by the if_convert 449 pass run after reload or by target-specific splitters. */ 450DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x') 451 452/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 453DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x') 454 455/* A string that is passed through to the assembler as input. 456 One can obviously pass comments through by using the 457 assembler comment syntax. 458 These occur in an insn all by themselves as the PATTERN. 459 They also appear inside an ASM_OPERANDS 460 as a convenient way to hold a string. */ 461DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x') 462 463/* An assembler instruction with operands. 464 1st operand is the instruction template. 465 2nd operand is the constraint for the output. 466 3rd operand is the number of the output this expression refers to. 467 When an insn stores more than one value, a separate ASM_OPERANDS 468 is made for each output; this integer distinguishes them. 469 4th is a vector of values of input operands. 470 5th is a vector of modes and constraints for the input operands. 471 Each element is an ASM_INPUT containing a constraint string 472 and whose mode indicates the mode of the input operand. 473 6th is the name of the containing source file. 474 7th is the source line number. */ 475DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x') 476 477/* A machine-specific operation. 478 1st operand is a vector of operands being used by the operation so that 479 any needed reloads can be done. 480 2nd operand is a unique value saying which of a number of machine-specific 481 operations is to be performed. 482 (Note that the vector must be the first operand because of the way that 483 genrecog.c record positions within an insn.) 484 This can occur all by itself in a PATTERN, as a component of a PARALLEL, 485 or inside an expression. */ 486DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x') 487 488/* Similar, but a volatile operation and one which may trap. */ 489DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x') 490 491/* Vector of addresses, stored as full words. */ 492/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 493DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x') 494 495/* Vector of address differences X0 - BASE, X1 - BASE, ... 496 First operand is BASE; the vector contains the X's. 497 The machine mode of this rtx says how much space to leave 498 for each difference and is adjusted by branch shortening if 499 CASE_VECTOR_SHORTEN_MODE is defined. 500 The third and fourth operands store the target labels with the 501 minimum and maximum addresses respectively. 502 The fifth operand stores flags for use by branch shortening. 503 Set at the start of shorten_branches: 504 min_align: the minimum alignment for any of the target labels. 505 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 506 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 507 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 508 min_after_base: true iff minimum address target label is after BASE. 509 max_after_base: true iff maximum address target label is after BASE. 510 Set by the actual branch shortening process: 511 offset_unsigned: true iff offsets have to be treated as unsigned. 512 scale: scaling that is necessary to make offsets fit into the mode. 513 514 The third, fourth and fifth operands are only valid when 515 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 516 compilations. */ 517 518DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x') 519 520/* Memory prefetch, with attributes supported on some targets. 521 Operand 1 is the address of the memory to fetch. 522 Operand 2 is 1 for a write access, 0 otherwise. 523 Operand 3 is the level of temporal locality; 0 means there is no 524 temporal locality and 1, 2, and 3 are for increasing levels of temporal 525 locality. 526 527 The attributes specified by operands 2 and 3 are ignored for targets 528 whose prefetch instructions do not support them. */ 529DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x') 530 531/* ---------------------------------------------------------------------- 532 At the top level of an instruction (perhaps under PARALLEL). 533 ---------------------------------------------------------------------- */ 534 535/* Assignment. 536 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 537 Operand 2 is the value stored there. 538 ALL assignment must use SET. 539 Instructions that do multiple assignments must use multiple SET, 540 under PARALLEL. */ 541DEF_RTL_EXPR(SET, "set", "ee", 'x') 542 543/* Indicate something is used in a way that we don't want to explain. 544 For example, subroutine calls will use the register 545 in which the static chain is passed. */ 546DEF_RTL_EXPR(USE, "use", "e", 'x') 547 548/* Indicate something is clobbered in a way that we don't want to explain. 549 For example, subroutine calls will clobber some physical registers 550 (the ones that are by convention not saved). */ 551DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x') 552 553/* Call a subroutine. 554 Operand 1 is the address to call. 555 Operand 2 is the number of arguments. */ 556 557DEF_RTL_EXPR(CALL, "call", "ee", 'x') 558 559/* Return from a subroutine. */ 560 561DEF_RTL_EXPR(RETURN, "return", "", 'x') 562 563/* Conditional trap. 564 Operand 1 is the condition. 565 Operand 2 is the trap code. 566 For an unconditional trap, make the condition (const_int 1). */ 567DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x') 568 569/* Placeholder for _Unwind_Resume before we know if a function call 570 or a branch is needed. Operand 1 is the exception region from 571 which control is flowing. */ 572DEF_RTL_EXPR(RESX, "resx", "i", 'x') 573 574/* ---------------------------------------------------------------------- 575 Primitive values for use in expressions. 576 ---------------------------------------------------------------------- */ 577 578/* numeric integer constant */ 579DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o') 580 581/* numeric floating point constant. 582 Operand 0 ('0') is a chain of all CONST_DOUBLEs in use in the 583 current function. 584 Remaining operands hold the actual value. They are all 'w' and 585 there may be from 1 to 4; see rtl.c. */ 586DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o') 587 588/* Describes a vector constant. */ 589DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x') 590 591/* String constant. Used only for attributes right now. */ 592DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o') 593 594/* This is used to encapsulate an expression whose value is constant 595 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 596 recognized as a constant operand rather than by arithmetic instructions. */ 597 598DEF_RTL_EXPR(CONST, "const", "e", 'o') 599 600/* program counter. Ordinary jumps are represented 601 by a SET whose first operand is (PC). */ 602DEF_RTL_EXPR(PC, "pc", "", 'o') 603 604/* Used in the cselib routines to describe a value. */ 605DEF_RTL_EXPR(VALUE, "value", "0", 'o') 606 607/* A register. The "operand" is the register number, accessed with 608 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 609 than a hardware register is being referred to. The second operand 610 holds the original register number - this will be different for a 611 pseudo register that got turned into a hard register. 612 This rtx needs to have as many (or more) fields as a MEM, since we 613 can change REG rtx's into MEMs during reload. */ 614DEF_RTL_EXPR(REG, "reg", "i0", 'o') 615 616/* A scratch register. This represents a register used only within a 617 single insn. It will be turned into a REG during register allocation 618 or reload unless the constraint indicates that the register won't be 619 needed, in which case it can remain a SCRATCH. This code is 620 marked as having one operand so it can be turned into a REG. */ 621DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o') 622 623/* One word of a multi-word value. 624 The first operand is the complete value; the second says which word. 625 The WORDS_BIG_ENDIAN flag controls whether word number 0 626 (as numbered in a SUBREG) is the most or least significant word. 627 628 This is also used to refer to a value in a different machine mode. 629 For example, it can be used to refer to a SImode value as if it were 630 Qimode, or vice versa. Then the word number is always 0. */ 631DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x') 632 633/* This one-argument rtx is used for move instructions 634 that are guaranteed to alter only the low part of a destination. 635 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 636 has an unspecified effect on the high part of REG, 637 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 638 is guaranteed to alter only the bits of REG that are in HImode. 639 640 The actual instruction used is probably the same in both cases, 641 but the register constraints may be tighter when STRICT_LOW_PART 642 is in use. */ 643 644DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x') 645 646/* (CONCAT a b) represents the virtual concatenation of a and b 647 to make a value that has as many bits as a and b put together. 648 This is used for complex values. Normally it appears only 649 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 650DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o') 651 652/* A memory location; operand is the address. The second operand is the 653 alias set to which this MEM belongs. We use `0' instead of `w' for this 654 field so that the field need not be specified in machine descriptions. */ 655DEF_RTL_EXPR(MEM, "mem", "e0", 'o') 656 657/* Reference to an assembler label in the code for this function. 658 The operand is a CODE_LABEL found in the insn chain. 659 The unprinted fields 1 and 2 are used in flow.c for the 660 LABEL_NEXTREF and CONTAINING_INSN. */ 661DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o') 662 663/* Reference to a named label: the string that is the first operand, 664 with `_' added implicitly in front. 665 Exception: if the first character explicitly given is `*', 666 to give it to the assembler, remove the `*' and do not add `_'. */ 667DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o') 668 669/* The condition code register is represented, in our imagination, 670 as a register holding a value that can be compared to zero. 671 In fact, the machine has already compared them and recorded the 672 results; but instructions that look at the condition code 673 pretend to be looking at the entire value and comparing it. */ 674DEF_RTL_EXPR(CC0, "cc0", "", 'o') 675 676/* Reference to the address of a register. Removed by purge_addressof after 677 CSE has elided as many as possible. 678 1st operand: the register we may need the address of. 679 2nd operand: the original pseudo regno we were generated for. 680 3rd operand: the decl for the object in the register, for 681 put_reg_in_stack. */ 682 683DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o') 684 685/* ===================================================================== 686 A QUEUED expression really points to a member of the queue of instructions 687 to be output later for postincrement/postdecrement. 688 QUEUED expressions never become part of instructions. 689 When a QUEUED expression would be put into an instruction, 690 instead either the incremented variable or a copy of its previous 691 value is used. 692 693 Operands are: 694 0. the variable to be incremented (a REG rtx). 695 1. the incrementing instruction, or 0 if it hasn't been output yet. 696 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet. 697 3. the body to use for the incrementing instruction 698 4. the next QUEUED expression in the queue. 699 ====================================================================== */ 700 701DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x') 702 703/* ---------------------------------------------------------------------- 704 Expressions for operators in an rtl pattern 705 ---------------------------------------------------------------------- */ 706 707/* if_then_else. This is used in representing ordinary 708 conditional jump instructions. 709 Operand: 710 0: condition 711 1: then expr 712 2: else expr */ 713DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3') 714 715/* General conditional. The first operand is a vector composed of pairs of 716 expressions. The first element of each pair is evaluated, in turn. 717 The value of the conditional is the second expression of the first pair 718 whose first expression evaluates non-zero. If none of the expressions is 719 true, the second operand will be used as the value of the conditional. 720 721 This should be replaced with use of IF_THEN_ELSE. */ 722DEF_RTL_EXPR(COND, "cond", "Ee", 'x') 723 724/* Comparison, produces a condition code result. */ 725DEF_RTL_EXPR(COMPARE, "compare", "ee", '2') 726 727/* plus */ 728DEF_RTL_EXPR(PLUS, "plus", "ee", 'c') 729 730/* Operand 0 minus operand 1. */ 731DEF_RTL_EXPR(MINUS, "minus", "ee", '2') 732 733/* Minus operand 0. */ 734DEF_RTL_EXPR(NEG, "neg", "e", '1') 735 736DEF_RTL_EXPR(MULT, "mult", "ee", 'c') 737 738/* Operand 0 divided by operand 1. */ 739DEF_RTL_EXPR(DIV, "div", "ee", '2') 740/* Remainder of operand 0 divided by operand 1. */ 741DEF_RTL_EXPR(MOD, "mod", "ee", '2') 742 743/* Unsigned divide and remainder. */ 744DEF_RTL_EXPR(UDIV, "udiv", "ee", '2') 745DEF_RTL_EXPR(UMOD, "umod", "ee", '2') 746 747/* Bitwise operations. */ 748DEF_RTL_EXPR(AND, "and", "ee", 'c') 749 750DEF_RTL_EXPR(IOR, "ior", "ee", 'c') 751 752DEF_RTL_EXPR(XOR, "xor", "ee", 'c') 753 754DEF_RTL_EXPR(NOT, "not", "e", '1') 755 756/* Operand: 757 0: value to be shifted. 758 1: number of bits. */ 759DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */ 760DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */ 761DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */ 762DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */ 763DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */ 764 765/* Minimum and maximum values of two operands. We need both signed and 766 unsigned forms. (We cannot use MIN for SMIN because it conflicts 767 with a macro of the same name.) */ 768 769DEF_RTL_EXPR(SMIN, "smin", "ee", 'c') 770DEF_RTL_EXPR(SMAX, "smax", "ee", 'c') 771DEF_RTL_EXPR(UMIN, "umin", "ee", 'c') 772DEF_RTL_EXPR(UMAX, "umax", "ee", 'c') 773 774/* These unary operations are used to represent incrementation 775 and decrementation as they occur in memory addresses. 776 The amount of increment or decrement are not represented 777 because they can be understood from the machine-mode of the 778 containing MEM. These operations exist in only two cases: 779 1. pushes onto the stack. 780 2. created automatically by the life_analysis pass in flow.c. */ 781DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a') 782DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a') 783DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a') 784DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a') 785 786/* These binary operations are used to represent generic address 787 side-effects in memory addresses, except for simple incrementation 788 or decrementation which use the above operations. They are 789 created automatically by the life_analysis pass in flow.c. 790 The first operand is a REG which is used as the address. 791 The second operand is an expression that is assigned to the 792 register, either before (PRE_MODIFY) or after (POST_MODIFY) 793 evaluating the address. 794 Currently, the compiler can only handle second operands of the 795 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 796 the first operand of the PLUS has to be the same register as 797 the first operand of the *_MODIFY. */ 798DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a') 799DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a') 800 801/* Comparison operations. The ordered comparisons exist in two 802 flavors, signed and unsigned. */ 803DEF_RTL_EXPR(NE, "ne", "ee", '<') 804DEF_RTL_EXPR(EQ, "eq", "ee", '<') 805DEF_RTL_EXPR(GE, "ge", "ee", '<') 806DEF_RTL_EXPR(GT, "gt", "ee", '<') 807DEF_RTL_EXPR(LE, "le", "ee", '<') 808DEF_RTL_EXPR(LT, "lt", "ee", '<') 809DEF_RTL_EXPR(GEU, "geu", "ee", '<') 810DEF_RTL_EXPR(GTU, "gtu", "ee", '<') 811DEF_RTL_EXPR(LEU, "leu", "ee", '<') 812DEF_RTL_EXPR(LTU, "ltu", "ee", '<') 813 814/* Additional floating point unordered comparision flavors. */ 815DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<') 816DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<') 817 818/* These are equivalent to unordered or ... */ 819DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<') 820DEF_RTL_EXPR(UNGE, "unge", "ee", '<') 821DEF_RTL_EXPR(UNGT, "ungt", "ee", '<') 822DEF_RTL_EXPR(UNLE, "unle", "ee", '<') 823DEF_RTL_EXPR(UNLT, "unlt", "ee", '<') 824 825/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 826DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<') 827 828/* Represents the result of sign-extending the sole operand. 829 The machine modes of the operand and of the SIGN_EXTEND expression 830 determine how much sign-extension is going on. */ 831DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1') 832 833/* Similar for zero-extension (such as unsigned short to int). */ 834DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1') 835 836/* Similar but here the operand has a wider mode. */ 837DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1') 838 839/* Similar for extending floating-point values (such as SFmode to DFmode). */ 840DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1') 841DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1') 842 843/* Conversion of fixed point operand to floating point value. */ 844DEF_RTL_EXPR(FLOAT, "float", "e", '1') 845 846/* With fixed-point machine mode: 847 Conversion of floating point operand to fixed point value. 848 Value is defined only when the operand's value is an integer. 849 With floating-point machine mode (and operand with same mode): 850 Operand is rounded toward zero to produce an integer value 851 represented in floating point. */ 852DEF_RTL_EXPR(FIX, "fix", "e", '1') 853 854/* Conversion of unsigned fixed point operand to floating point value. */ 855DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1') 856 857/* With fixed-point machine mode: 858 Conversion of floating point operand to *unsigned* fixed point value. 859 Value is defined only when the operand's value is an integer. */ 860DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1') 861 862/* Absolute value */ 863DEF_RTL_EXPR(ABS, "abs", "e", '1') 864 865/* Square root */ 866DEF_RTL_EXPR(SQRT, "sqrt", "e", '1') 867 868/* Find first bit that is set. 869 Value is 1 + number of trailing zeros in the arg., 870 or 0 if arg is 0. */ 871DEF_RTL_EXPR(FFS, "ffs", "e", '1') 872 873/* Reference to a signed bit-field of specified size and position. 874 Operand 0 is the memory unit (usually SImode or QImode) which 875 contains the field's first bit. Operand 1 is the width, in bits. 876 Operand 2 is the number of bits in the memory unit before the 877 first bit of this field. 878 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 879 operand 2 counts from the msb of the memory unit. 880 Otherwise, the first bit is the lsb and operand 2 counts from 881 the lsb of the memory unit. */ 882DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b') 883 884/* Similar for unsigned bit-field. */ 885DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b') 886 887/* For RISC machines. These save memory when splitting insns. */ 888 889/* HIGH are the high-order bits of a constant expression. */ 890DEF_RTL_EXPR(HIGH, "high", "e", 'o') 891 892/* LO_SUM is the sum of a register and the low-order bits 893 of a constant expression. */ 894DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o') 895 896/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn. 897 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of 898 the registers that can be substituted within this range. Operand 3 is the 899 number of calls in the range. Operand 4 is the number of insns in the 900 range. Operand 5 is the unique range number for this range. Operand 6 is 901 the basic block # of the start of the live range. Operand 7 is the basic 902 block # of the end of the live range. Operand 8 is the loop depth. Operand 903 9 is a bitmap of the registers live at the start of the range. Operand 10 904 is a bitmap of the registers live at the end of the range. Operand 11 is 905 marker number for the start of the range. Operand 12 is the marker number 906 for the end of the range. */ 907DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x') 908 909/* Registers that can be substituted within the range. Operand 0 is the 910 original pseudo register number. Operand 1 will be filled in with the 911 pseudo register the value is copied for the duration of the range. Operand 912 2 is the number of references within the range to the register. Operand 3 913 is the number of sets or clobbers of the register in the range. Operand 4 914 is the number of deaths the register has. Operand 5 is the copy flags that 915 give the status of whether a copy is needed from the original register to 916 the new register at the beginning of the range, or whether a copy from the 917 new register back to the original at the end of the range. Operand 6 is the 918 live length. Operand 7 is the number of calls that this register is live 919 across. Operand 8 is the symbol node of the variable if the register is a 920 user variable. Operand 9 is the block node that the variable is declared 921 in if the register is a user variable. */ 922DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x') 923 924/* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of 925 the different ranges a variable is in where it is copied to a different 926 pseudo register. Operand 1 is the block that the variable is declared in. 927 Operand 2 is the number of distinct ranges. */ 928DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x') 929 930/* Information about the registers that are live at the current point. Operand 931 0 is the live bitmap. Operand 1 is the original block number. */ 932DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x') 933 934/* A unary `__builtin_constant_p' expression. These are only emitted 935 during RTL generation, and then only if optimize > 0. They are 936 eliminated by the first CSE pass. */ 937DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x') 938 939/* A placeholder for a CALL_INSN which may be turned into a normal call, 940 a sibling (tail) call or tail recursion. 941 942 Immediately after RTL generation, this placeholder will be replaced 943 by the insns to perform the call, sibcall or tail recursion. 944 945 This RTX has 4 operands. The first three are lists of instructions to 946 perform the call as a normal call, sibling call and tail recursion 947 respectively. The latter two lists may be NULL, the first may never 948 be NULL. 949 950 The last operand is the tail recursion CODE_LABEL, which may be NULL if no 951 potential tail recursive calls were found. 952 953 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P 954 after we select a call method. 955 956 This method of tail-call elimination is intended to be replaced by 957 tree-based optimizations once front-end conversions are complete. */ 958DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x') 959 960/* Describes a merge operation between two vector values. 961 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 962 that specifies where the parts of the result are taken from. Set bits 963 indicate operand 0, clear bits indicate operand 1. The parts are defined 964 by the mode of the vectors. */ 965DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x') 966 967/* Describes an operation that selects parts of a vector. 968 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 969 a CONST_INT for each of the subparts of the result vector, giving the 970 number of the source subpart that should be stored into it. */ 971DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x') 972 973/* Describes a vector concat operation. Operands 0 and 1 are the source 974 vectors, the result is a vector that is as long as operands 0 and 1 975 combined and is the concatenation of the two source vectors. */ 976DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x') 977 978/* Describes an operation that converts a small vector into a larger one by 979 duplicating the input values. The output vector mode must have the same 980 submodes as the input vector mode, and the number of output parts must be 981 an integer multiple of the number of input parts. */ 982DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x') 983 984/* Addition with signed saturation */ 985DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c') 986 987/* Addition with unsigned saturation */ 988DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c') 989 990/* Operand 0 minus operand 1, with signed saturation. */ 991DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2') 992 993/* Operand 0 minus operand 1, with unsigned saturation. */ 994DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2') 995 996/* Signed saturating truncate. */ 997DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1') 998 999/* Unsigned saturating truncate. */ 1000DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1') 1001 1002/* The SSA phi operator. 1003 1004 The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT 1005 containing the block number of the predecessor through which control 1006 has passed when the register at element 2N is used. 1007 1008 Note that PHI may only appear at the beginning of a basic block. 1009 1010 ??? There may be multiple PHI insns, but they are all evaluated 1011 in parallel. This probably ought to be changed to use a real 1012 PARALLEL, as that would be less confusing and more in the spirit 1013 of canonical RTL. It is, however, easier to manipulate this way. */ 1014DEF_RTL_EXPR(PHI, "phi", "E", 'x') 1015 1016 1017/* 1018Local variables: 1019mode:c 1020End: 1021*/ 1022