rtl.def revision 52284
1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999 Free Software Foundation, Inc. 5 6This file is part of GNU CC. 7 8GNU CC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 2, or (at your option) 11any later version. 12 13GNU CC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GNU CC; see the file COPYING. If not, write to 20the Free Software Foundation, 59 Temple Place - Suite 330, 21Boston, MA 02111-1307, USA. */ 22 23 24/* Expression definitions and descriptions for all targets are in this file. 25 Some will not be used for some targets. 26 27 The fields in the cpp macro call "DEF_RTL_EXPR()" 28 are used to create declarations in the C source of the compiler. 29 30 The fields are: 31 32 1. The internal name of the rtx used in the C source. 33 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 34 By convention these are in UPPER_CASE. 35 36 2. The name of the rtx in the external ASCII format read by 37 read_rtx(), and printed by print_rtx(). 38 These names are stored in rtx_name[]. 39 By convention these are the internal (field 1) names in lower_case. 40 41 3. The print format, and type of each rtx->fld[] (field) in this rtx. 42 These formats are stored in rtx_format[]. 43 The meaning of the formats is documented in front of this array in rtl.c 44 45 4. The class of the rtx. These are stored in rtx_class and are accessed 46 via the GET_RTX_CLASS macro. They are defined as follows: 47 48 "o" an rtx code that can be used to represent an object (e.g, REG, MEM) 49 "<" an rtx code for a comparison (e.g, EQ, NE, LT) 50 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 51 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 52 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 53 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 54 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 55 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 56 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP) 57 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL) 58 "x" everything else 59 60 */ 61 62/* --------------------------------------------------------------------- 63 Expressions (and "meta" expressions) used for structuring the 64 rtl representation of a program. 65 --------------------------------------------------------------------- */ 66 67/* an expression code name unknown to the reader */ 68DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x') 69 70/* (NIL) is used by rtl reader and printer to represent a null pointer. */ 71 72DEF_RTL_EXPR(NIL, "nil", "*", 'x') 73 74/* --------------------------------------------------------------------- 75 Expressions used in constructing lists. 76 --------------------------------------------------------------------- */ 77 78/* a linked list of expressions */ 79DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x') 80 81/* a linked list of instructions. 82 The insns are represented in print by their uids. */ 83DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x') 84 85/* ---------------------------------------------------------------------- 86 Expression types for machine descriptions. 87 These do not appear in actual rtl code in the compiler. 88 ---------------------------------------------------------------------- */ 89 90/* Appears only in machine descriptions. 91 Means use the function named by the second arg (the string) 92 as a predicate; if matched, store the structure that was matched 93 in the operand table at index specified by the first arg (the integer). 94 If the second arg is the null string, the structure is just stored. 95 96 A third string argument indicates to the register allocator restrictions 97 on where the operand can be allocated. 98 99 If the target needs no restriction on any instruction this field should 100 be the null string. 101 102 The string is prepended by: 103 '=' to indicate the operand is only written to. 104 '+' to indicate the operand is both read and written to. 105 106 Each character in the string represents an allocable class for an operand. 107 'g' indicates the operand can be any valid class. 108 'i' indicates the operand can be immediate (in the instruction) data. 109 'r' indicates the operand can be in a register. 110 'm' indicates the operand can be in memory. 111 'o' a subset of the 'm' class. Those memory addressing modes that 112 can be offset at compile time (have a constant added to them). 113 114 Other characters indicate target dependent operand classes and 115 are described in each target's machine description. 116 117 For instructions with more than one operand, sets of classes can be 118 separated by a comma to indicate the appropriate multi-operand constraints. 119 There must be a 1 to 1 correspondence between these sets of classes in 120 all operands for an instruction. 121 */ 122DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm') 123 124/* Appears only in machine descriptions. 125 Means match a SCRATCH or a register. When used to generate rtl, a 126 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 127 the desired mode and the first argument is the operand number. 128 The second argument is the constraint. */ 129DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm') 130 131/* Appears only in machine descriptions. 132 Means match only something equal to what is stored in the operand table 133 at the index specified by the argument. */ 134DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm') 135 136/* Appears only in machine descriptions. 137 Means apply a predicate, AND match recursively the operands of the rtx. 138 Operand 0 is the operand-number, as in match_operand. 139 Operand 1 is a predicate to apply (as a string, a function name). 140 Operand 2 is a vector of expressions, each of which must match 141 one subexpression of the rtx this construct is matching. */ 142DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm') 143 144/* Appears only in machine descriptions. 145 Means to match a PARALLEL of arbitrary length. The predicate is applied 146 to the PARALLEL and the initial expressions in the PARALLEL are matched. 147 Operand 0 is the operand-number, as in match_operand. 148 Operand 1 is a predicate to apply to the PARALLEL. 149 Operand 2 is a vector of expressions, each of which must match the 150 corresponding element in the PARALLEL. */ 151DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm') 152 153/* Appears only in machine descriptions. 154 Means match only something equal to what is stored in the operand table 155 at the index specified by the argument. For MATCH_OPERATOR. */ 156DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm') 157 158/* Appears only in machine descriptions. 159 Means match only something equal to what is stored in the operand table 160 at the index specified by the argument. For MATCH_PARALLEL. */ 161DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm') 162 163/* Appears only in machine descriptions. 164 Should be used only in attribute tests. 165 The predicate in operand 0 is applied to the whole insn being checked. */ 166DEF_RTL_EXPR(MATCH_INSN, "match_insn", "s", 'm') 167 168/* Appears only in machine descriptions. 169 Operand 0 is the operand number, as in match_operand. 170 Operand 1 is the predicate to apply to the insn. */ 171DEF_RTL_EXPR(MATCH_INSN2, "match_insn2", "is", 'm') 172 173/* Appears only in machine descriptions. 174 Defines the pattern for one kind of instruction. 175 Operand: 176 0: names this instruction. 177 If the name is the null string, the instruction is in the 178 machine description just to be recognized, and will never be emitted by 179 the tree to rtl expander. 180 1: is the pattern. 181 2: is a string which is a C expression 182 giving an additional condition for recognizing this pattern. 183 A null string means no extra condition. 184 3: is the action to execute if this pattern is matched. 185 If this assembler code template starts with a * then it is a fragment of 186 C code to run to decide on a template to use. Otherwise, it is the 187 template to use. 188 4: optionally, a vector of attributes for this insn. 189 */ 190DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x') 191 192/* Definition of a peephole optimization. 193 1st operand: vector of insn patterns to match 194 2nd operand: C expression that must be true 195 3rd operand: template or C code to produce assembler output. 196 4: optionally, a vector of attributes for this insn. 197 */ 198DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x') 199 200/* Definition of a split operation. 201 1st operand: insn pattern to match 202 2nd operand: C expression that must be true 203 3rd operand: vector of insn patterns to place into a SEQUENCE 204 4th operand: optionally, some C code to execute before generating the 205 insns. This might, for example, create some RTX's and store them in 206 elements of `recog_operand' for use by the vector of insn-patterns. 207 (`operands' is an alias here for `recog_operand'). */ 208DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x') 209 210/* Definition of a combiner pattern. 211 Operands not defined yet. */ 212DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x') 213 214/* Define how to generate multiple insns for a standard insn name. 215 1st operand: the insn name. 216 2nd operand: vector of insn-patterns. 217 Use match_operand to substitute an element of `recog_operand'. 218 3rd operand: C expression that must be true for this to be available. 219 This may not test any operands. 220 4th operand: Extra C code to execute before generating the insns. 221 This might, for example, create some RTX's and store them in 222 elements of `recog_operand' for use by the vector of insn-patterns. 223 (`operands' is an alias here for `recog_operand'). */ 224DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x') 225 226/* Define a requirement for delay slots. 227 1st operand: Condition involving insn attributes that, if true, 228 indicates that the insn requires the number of delay slots 229 shown. 230 2nd operand: Vector whose length is the three times the number of delay 231 slots required. 232 Each entry gives three conditions, each involving attributes. 233 The first must be true for an insn to occupy that delay slot 234 location. The second is true for all insns that can be 235 annulled if the branch is true and the third is true for all 236 insns that can be annulled if the branch is false. 237 238 Multiple DEFINE_DELAYs may be present. They indicate differing 239 requirements for delay slots. */ 240DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x') 241 242/* Define a set of insns that requires a function unit. This means that 243 these insns produce their result after a delay and that there may be 244 restrictions on the number of insns of this type that can be scheduled 245 simultaneously. 246 247 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. 248 Each gives a set of operations and associated delays. The first three 249 operands must be the same for each operation for the same function unit. 250 251 All delays are specified in cycles. 252 253 1st operand: Name of function unit (mostly for documentation) 254 2nd operand: Number of identical function units in CPU 255 3rd operand: Total number of simultaneous insns that can execute on this 256 function unit; 0 if unlimited. 257 4th operand: Condition involving insn attribute, that, if true, specifies 258 those insns that this expression applies to. 259 5th operand: Constant delay after which insn result will be 260 available. 261 6th operand: Delay until next insn can be scheduled on the function unit 262 executing this operation. The meaning depends on whether or 263 not the next operand is supplied. 264 7th operand: If this operand is not specified, the 6th operand gives the 265 number of cycles after the instruction matching the 4th 266 operand begins using the function unit until a subsequent 267 insn can begin. A value of zero should be used for a 268 unit with no issue constraints. If only one operation can 269 be executed a time and the unit is busy for the entire time, 270 the 3rd operand should be specified as 1, the 6th operand 271 should be specified as 0, and the 7th operand should not 272 be specified. 273 274 If this operand is specified, it is a list of attribute 275 expressions. If an insn for which any of these expressions 276 is true is currently executing on the function unit, the 277 issue delay will be given by the 6th operand. Otherwise, 278 the insn can be immediately scheduled (subject to the limit 279 on the number of simultaneous operations executing on the 280 unit.) */ 281DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x') 282 283/* Define attribute computation for `asm' instructions. */ 284DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' ) 285 286/* SEQUENCE appears in the result of a `gen_...' function 287 for a DEFINE_EXPAND that wants to make several insns. 288 Its elements are the bodies of the insns that should be made. 289 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 290DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x') 291 292/* Refers to the address of its argument. 293 This appears only in machine descriptions, indicating that 294 any expression that would be acceptable as the operand of MEM 295 should be matched. */ 296DEF_RTL_EXPR(ADDRESS, "address", "e", 'm') 297 298/* ---------------------------------------------------------------------- 299 Expressions used for insn attributes. These also do not appear in 300 actual rtl code in the compiler. 301 ---------------------------------------------------------------------- */ 302 303/* Definition of an insn attribute. 304 1st operand: name of the attribute 305 2nd operand: comma-separated list of possible attribute values 306 3rd operand: expression for the default value of the attribute. */ 307DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x') 308 309/* Marker for the name of an attribute. */ 310DEF_RTL_EXPR(ATTR, "attr", "s", 'x') 311 312/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 313 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 314 pattern. 315 316 (set_attr "name" "value") is equivalent to 317 (set (attr "name") (const_string "value")) */ 318DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x') 319 320/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 321 specify that attribute values are to be assigned according to the 322 alternative matched. 323 324 The following three expressions are equivalent: 325 326 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 327 (eq_attrq "alternative" "2") (const_string "a2")] 328 (const_string "a3"))) 329 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 330 (const_string "a3")]) 331 (set_attr "att" "a1,a2,a3") 332 */ 333DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x') 334 335/* A conditional expression true if the value of the specified attribute of 336 the current insn equals the specified value. The first operand is the 337 attribute name and the second is the comparison value. */ 338DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x') 339 340/* A conditional expression which is true if the specified flag is 341 true for the insn being scheduled in reorg. 342 343 genattr.c defines the following flags which can be tested by 344 (attr_flag "foo") expressions in eligible_for_delay. 345 346 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 347 348DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x') 349 350/* ---------------------------------------------------------------------- 351 Expression types used for things in the instruction chain. 352 353 All formats must start with "iuu" to handle the chain. 354 Each insn expression holds an rtl instruction and its semantics 355 during back-end processing. 356 See macros's in "rtl.h" for the meaning of each rtx->fld[]. 357 358 ---------------------------------------------------------------------- */ 359 360/* An instruction that cannot jump. */ 361DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i') 362 363/* An instruction that can possibly jump. 364 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */ 365DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i') 366 367/* An instruction that can possibly call a subroutine 368 but which will not change which instruction comes next 369 in the current function. 370 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE. 371 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */ 372DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i') 373 374/* A marker that indicates that control will not flow through. */ 375DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x') 376 377/* Holds a label that is followed by instructions. 378 Operand: 379 3: is a number that is unique in the entire compilation. 380 4: is the user-given name of the label, if any. 381 5: is used in jump.c for the use-count of the label. 382 6: is used in flow.c to point to the chain of label_ref's to this label. */ 383DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00", 'x') 384 385/* Say where in the code a source line starts, for symbol table's sake. 386 Contains a filename and a line number. Line numbers <= 0 are special: 387 0 is used in a dummy placed at the front of every function 388 just so there will never be a need to delete the first insn; 389 -1 indicates a dummy; insns to be deleted by flow analysis and combining 390 are really changed to NOTEs with a number of -1. 391 -2 means beginning of a name binding contour; output N_LBRAC. 392 -3 means end of a contour; output N_RBRAC. */ 393DEF_RTL_EXPR(NOTE, "note", "iuusn", 'x') 394 395/* INLINE_HEADER is use by inline function machinery. The information 396 it contains helps to build the mapping function between the rtx's of 397 the function to be inlined and the current function being expanded. */ 398 399DEF_RTL_EXPR(INLINE_HEADER, "inline_header", "iuuuiiiiiieeiiEeEssE", 'x') 400 401/* ---------------------------------------------------------------------- 402 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 403 ---------------------------------------------------------------------- */ 404 405/* Several operations to be done in parallel. */ 406DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x') 407 408/* A string that is passed through to the assembler as input. 409 One can obviously pass comments through by using the 410 assembler comment syntax. 411 These occur in an insn all by themselves as the PATTERN. 412 They also appear inside an ASM_OPERANDS 413 as a convenient way to hold a string. */ 414DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x') 415 416/* An assembler instruction with operands. 417 1st operand is the instruction template. 418 2nd operand is the constraint for the output. 419 3rd operand is the number of the output this expression refers to. 420 When an insn stores more than one value, a separate ASM_OPERANDS 421 is made for each output; this integer distinguishes them. 422 4th is a vector of values of input operands. 423 5th is a vector of modes and constraints for the input operands. 424 Each element is an ASM_INPUT containing a constraint string 425 and whose mode indicates the mode of the input operand. 426 6th is the name of the containing source file. 427 7th is the source line number. */ 428DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x') 429 430/* A machine-specific operation. 431 1st operand is a vector of operands being used by the operation so that 432 any needed reloads can be done. 433 2nd operand is a unique value saying which of a number of machine-specific 434 operations is to be performed. 435 (Note that the vector must be the first operand because of the way that 436 genrecog.c record positions within an insn.) 437 This can occur all by itself in a PATTERN, as a component of a PARALLEL, 438 or inside an expression. */ 439DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x') 440 441/* Similar, but a volatile operation and one which may trap. */ 442DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x') 443 444/* Vector of addresses, stored as full words. */ 445/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 446DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x') 447 448/* Vector of address differences X0 - BASE, X1 - BASE, ... 449 First operand is BASE; the vector contains the X's. 450 The machine mode of this rtx says how much space to leave 451 for each difference and is adjusted by branch shortening if 452 CASE_VECTOR_SHORTEN_MODE is defined. 453 The third and fourth operands store the target labels with the 454 minimum and maximum addresses respectively. 455 The fifth operand stores flags for use by branch shortening. 456 Set at the start of shorten_branches: 457 min_align: the minimum alignment for any of the target labels. 458 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 459 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 460 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 461 min_after_base: true iff minimum address target label is after BASE. 462 max_after_base: true iff maximum address target label is after BASE. 463 Set by the actual branch shortening process: 464 offset_unsigned: true iff offsets have to be treated as unsigned. 465 scale: scaling that is necessary to make offsets fit into the mode. 466 467 The third, fourth and fifth operands are only valid when 468 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 469 compilations. */ 470 471DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEeei", 'x') 472 473/* ---------------------------------------------------------------------- 474 At the top level of an instruction (perhaps under PARALLEL). 475 ---------------------------------------------------------------------- */ 476 477/* Assignment. 478 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 479 Operand 2 is the value stored there. 480 ALL assignment must use SET. 481 Instructions that do multiple assignments must use multiple SET, 482 under PARALLEL. */ 483DEF_RTL_EXPR(SET, "set", "ee", 'x') 484 485/* Indicate something is used in a way that we don't want to explain. 486 For example, subroutine calls will use the register 487 in which the static chain is passed. */ 488DEF_RTL_EXPR(USE, "use", "e", 'x') 489 490/* Indicate something is clobbered in a way that we don't want to explain. 491 For example, subroutine calls will clobber some physical registers 492 (the ones that are by convention not saved). */ 493DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x') 494 495/* Call a subroutine. 496 Operand 1 is the address to call. 497 Operand 2 is the number of arguments. */ 498 499DEF_RTL_EXPR(CALL, "call", "ee", 'x') 500 501/* Return from a subroutine. */ 502 503DEF_RTL_EXPR(RETURN, "return", "", 'x') 504 505/* Conditional trap. 506 Operand 1 is the condition. 507 Operand 2 is the trap code. 508 For an unconditional trap, make the condition (const_int 1). */ 509DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x') 510 511/* ---------------------------------------------------------------------- 512 Primitive values for use in expressions. 513 ---------------------------------------------------------------------- */ 514 515/* numeric integer constant */ 516DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o') 517 518/* numeric double constant. 519 Operand 0 is the MEM that stores this constant in memory, 520 or various other things (see comments at immed_double_const in varasm.c). 521 Operand 1 is a chain of all CONST_DOUBLEs in use in the current function. 522 Remaining operands hold the actual value. 523 The number of operands may be more than 2 if cross-compiling; 524 see init_rtl. */ 525DEF_RTL_EXPR(CONST_DOUBLE, "const_double", "e0ww", 'o') 526 527/* String constant. Used only for attributes right now. */ 528DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o') 529 530/* This is used to encapsulate an expression whose value is constant 531 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 532 recognized as a constant operand rather than by arithmetic instructions. */ 533 534DEF_RTL_EXPR(CONST, "const", "e", 'o') 535 536/* program counter. Ordinary jumps are represented 537 by a SET whose first operand is (PC). */ 538DEF_RTL_EXPR(PC, "pc", "", 'o') 539 540/* A register. The "operand" is the register number, accessed with 541 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 542 than a hardware register is being referred to. The second operand 543 doesn't really exist. Unfortunately, however, the compiler 544 implicitly assumes that a REG can be transformed in place into a 545 MEM, and therefore that a REG is at least as big as a MEM. To 546 avoid this memory overhead, which is likely to be substantial, 547 search for uses of PUT_CODE that turn REGs into MEMs, and fix them 548 somehow. Then, the trailing `0' can be removed here. */ 549DEF_RTL_EXPR(REG, "reg", "i0", 'o') 550 551/* A scratch register. This represents a register used only within a 552 single insn. It will be turned into a REG during register allocation 553 or reload unless the constraint indicates that the register won't be 554 needed, in which case it can remain a SCRATCH. This code is 555 marked as having one operand so it can be turned into a REG. */ 556DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o') 557 558/* One word of a multi-word value. 559 The first operand is the complete value; the second says which word. 560 The WORDS_BIG_ENDIAN flag controls whether word number 0 561 (as numbered in a SUBREG) is the most or least significant word. 562 563 This is also used to refer to a value in a different machine mode. 564 For example, it can be used to refer to a SImode value as if it were 565 Qimode, or vice versa. Then the word number is always 0. */ 566DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x') 567 568/* This one-argument rtx is used for move instructions 569 that are guaranteed to alter only the low part of a destination. 570 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 571 has an unspecified effect on the high part of REG, 572 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 573 is guaranteed to alter only the bits of REG that are in HImode. 574 575 The actual instruction used is probably the same in both cases, 576 but the register constraints may be tighter when STRICT_LOW_PART 577 is in use. */ 578 579DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x') 580 581/* (CONCAT a b) represents the virtual concatenation of a and b 582 to make a value that has as many bits as a and b put together. 583 This is used for complex values. Normally it appears only 584 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 585DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o') 586 587/* A memory location; operand is the address. Can be nested inside a 588 VOLATILE. The second operand is the alias set to which this MEM 589 belongs. We use `0' instead of `i' for this field so that the 590 field need not be specified in machine descriptions. */ 591DEF_RTL_EXPR(MEM, "mem", "e0", 'o') 592 593/* Reference to an assembler label in the code for this function. 594 The operand is a CODE_LABEL found in the insn chain. 595 The unprinted fields 1 and 2 are used in flow.c for the 596 LABEL_NEXTREF and CONTAINING_INSN. */ 597DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o') 598 599/* Reference to a named label: the string that is the first operand, 600 with `_' added implicitly in front. 601 Exception: if the first character explicitly given is `*', 602 to give it to the assembler, remove the `*' and do not add `_'. */ 603DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o') 604 605/* The condition code register is represented, in our imagination, 606 as a register holding a value that can be compared to zero. 607 In fact, the machine has already compared them and recorded the 608 results; but instructions that look at the condition code 609 pretend to be looking at the entire value and comparing it. */ 610DEF_RTL_EXPR(CC0, "cc0", "", 'o') 611 612/* Reference to the address of a register. Removed by purge_addressof after 613 CSE has elided as many as possible. 614 1st operand: the register we may need the address of. 615 2nd operand: the original pseudo regno we were generated for. 616 3rd operand: the decl for the object in the register, for 617 put_reg_in_stack. */ 618 619DEF_RTL_EXPR(ADDRESSOF, "addressof", "ei0", 'o') 620 621/* ===================================================================== 622 A QUEUED expression really points to a member of the queue of instructions 623 to be output later for postincrement/postdecrement. 624 QUEUED expressions never become part of instructions. 625 When a QUEUED expression would be put into an instruction, 626 instead either the incremented variable or a copy of its previous 627 value is used. 628 629 Operands are: 630 0. the variable to be incremented (a REG rtx). 631 1. the incrementing instruction, or 0 if it hasn't been output yet. 632 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet. 633 3. the body to use for the incrementing instruction 634 4. the next QUEUED expression in the queue. 635 ====================================================================== */ 636 637DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x') 638 639/* ---------------------------------------------------------------------- 640 Expressions for operators in an rtl pattern 641 ---------------------------------------------------------------------- */ 642 643/* if_then_else. This is used in representing ordinary 644 conditional jump instructions. 645 Operand: 646 0: condition 647 1: then expr 648 2: else expr */ 649DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3') 650 651/* General conditional. The first operand is a vector composed of pairs of 652 expressions. The first element of each pair is evaluated, in turn. 653 The value of the conditional is the second expression of the first pair 654 whose first expression evaluates non-zero. If none of the expressions is 655 true, the second operand will be used as the value of the conditional. 656 657 This should be replaced with use of IF_THEN_ELSE. */ 658DEF_RTL_EXPR(COND, "cond", "Ee", 'x') 659 660/* Comparison, produces a condition code result. */ 661DEF_RTL_EXPR(COMPARE, "compare", "ee", '2') 662 663/* plus */ 664DEF_RTL_EXPR(PLUS, "plus", "ee", 'c') 665 666/* Operand 0 minus operand 1. */ 667DEF_RTL_EXPR(MINUS, "minus", "ee", '2') 668 669/* Minus operand 0. */ 670DEF_RTL_EXPR(NEG, "neg", "e", '1') 671 672DEF_RTL_EXPR(MULT, "mult", "ee", 'c') 673 674/* Operand 0 divided by operand 1. */ 675DEF_RTL_EXPR(DIV, "div", "ee", '2') 676/* Remainder of operand 0 divided by operand 1. */ 677DEF_RTL_EXPR(MOD, "mod", "ee", '2') 678 679/* Unsigned divide and remainder. */ 680DEF_RTL_EXPR(UDIV, "udiv", "ee", '2') 681DEF_RTL_EXPR(UMOD, "umod", "ee", '2') 682 683/* Bitwise operations. */ 684DEF_RTL_EXPR(AND, "and", "ee", 'c') 685 686DEF_RTL_EXPR(IOR, "ior", "ee", 'c') 687 688DEF_RTL_EXPR(XOR, "xor", "ee", 'c') 689 690DEF_RTL_EXPR(NOT, "not", "e", '1') 691 692/* Operand: 693 0: value to be shifted. 694 1: number of bits. */ 695DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') 696DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') 697 698/* Right shift operations, for machines where these are not the same 699 as left shifting with a negative argument. */ 700 701DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') 702DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') 703DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') 704 705/* Minimum and maximum values of two operands. We need both signed and 706 unsigned forms. (We cannot use MIN for SMIN because it conflicts 707 with a macro of the same name.) */ 708 709DEF_RTL_EXPR(SMIN, "smin", "ee", 'c') 710DEF_RTL_EXPR(SMAX, "smax", "ee", 'c') 711DEF_RTL_EXPR(UMIN, "umin", "ee", 'c') 712DEF_RTL_EXPR(UMAX, "umax", "ee", 'c') 713 714/* These unary operations are used to represent incrementation 715 and decrementation as they occur in memory addresses. 716 The amount of increment or decrement are not represented 717 because they can be understood from the machine-mode of the 718 containing MEM. These operations exist in only two cases: 719 1. pushes onto the stack. 720 2. created automatically by the life_analysis pass in flow.c. */ 721DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x') 722DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x') 723DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x') 724DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x') 725 726/* These binary operations are used to represent generic address 727 side-effects in memory addresses, except for simple incrementation 728 or decrementation which use the above operations. They are 729 created automatically by the life_analysis pass in flow.c. 730 (Note that these operators are currently placeholders.) */ 731DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'x') 732DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'x') 733 734/* Comparison operations. The ordered comparisons exist in two 735 flavors, signed and unsigned. */ 736DEF_RTL_EXPR(NE, "ne", "ee", '<') 737DEF_RTL_EXPR(EQ, "eq", "ee", '<') 738DEF_RTL_EXPR(GE, "ge", "ee", '<') 739DEF_RTL_EXPR(GT, "gt", "ee", '<') 740DEF_RTL_EXPR(LE, "le", "ee", '<') 741DEF_RTL_EXPR(LT, "lt", "ee", '<') 742DEF_RTL_EXPR(GEU, "geu", "ee", '<') 743DEF_RTL_EXPR(GTU, "gtu", "ee", '<') 744DEF_RTL_EXPR(LEU, "leu", "ee", '<') 745DEF_RTL_EXPR(LTU, "ltu", "ee", '<') 746 747/* Represents the result of sign-extending the sole operand. 748 The machine modes of the operand and of the SIGN_EXTEND expression 749 determine how much sign-extension is going on. */ 750DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1') 751 752/* Similar for zero-extension (such as unsigned short to int). */ 753DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1') 754 755/* Similar but here the operand has a wider mode. */ 756DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1') 757 758/* Similar for extending floating-point values (such as SFmode to DFmode). */ 759DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1') 760DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1') 761 762/* Conversion of fixed point operand to floating point value. */ 763DEF_RTL_EXPR(FLOAT, "float", "e", '1') 764 765/* With fixed-point machine mode: 766 Conversion of floating point operand to fixed point value. 767 Value is defined only when the operand's value is an integer. 768 With floating-point machine mode (and operand with same mode): 769 Operand is rounded toward zero to produce an integer value 770 represented in floating point. */ 771DEF_RTL_EXPR(FIX, "fix", "e", '1') 772 773/* Conversion of unsigned fixed point operand to floating point value. */ 774DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1') 775 776/* With fixed-point machine mode: 777 Conversion of floating point operand to *unsigned* fixed point value. 778 Value is defined only when the operand's value is an integer. */ 779DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1') 780 781/* Absolute value */ 782DEF_RTL_EXPR(ABS, "abs", "e", '1') 783 784/* Square root */ 785DEF_RTL_EXPR(SQRT, "sqrt", "e", '1') 786 787/* Find first bit that is set. 788 Value is 1 + number of trailing zeros in the arg., 789 or 0 if arg is 0. */ 790DEF_RTL_EXPR(FFS, "ffs", "e", '1') 791 792/* Reference to a signed bit-field of specified size and position. 793 Operand 0 is the memory unit (usually SImode or QImode) which 794 contains the field's first bit. Operand 1 is the width, in bits. 795 Operand 2 is the number of bits in the memory unit before the 796 first bit of this field. 797 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 798 operand 2 counts from the msb of the memory unit. 799 Otherwise, the first bit is the lsb and operand 2 counts from 800 the lsb of the memory unit. */ 801DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b') 802 803/* Similar for unsigned bit-field. */ 804DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b') 805 806/* For RISC machines. These save memory when splitting insns. */ 807 808/* HIGH are the high-order bits of a constant expression. */ 809DEF_RTL_EXPR(HIGH, "high", "e", 'o') 810 811/* LO_SUM is the sum of a register and the low-order bits 812 of a constant expression. */ 813DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o') 814 815/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_START insn. 816 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of 817 the registers that can be substituted within this range. Operand 3 is the 818 number of calls in the range. Operand 4 is the number of insns in the 819 range. Operand 5 is the unique range number for this range. Operand 6 is 820 the basic block # of the start of the live range. Operand 7 is the basic 821 block # of the end of the live range. Operand 8 is the loop depth. Operand 822 9 is a bitmap of the registers live at the start of the range. Operand 10 823 is a bitmap of the registers live at the end of the range. Operand 11 is 824 marker number for the start of the range. Operand 12 is the marker number 825 for the end of the range. */ 826DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x') 827 828/* Registers that can be substituted within the range. Operand 0 is the 829 original pseudo register number. Operand 1 will be filled in with the 830 pseudo register the value is copied for the duration of the range. Operand 831 2 is the number of references within the range to the register. Operand 3 832 is the number of sets or clobbers of the register in the range. Operand 4 833 is the number of deaths the register has. Operand 5 is the copy flags that 834 give the status of whether a copy is needed from the original register to 835 the new register at the beginning of the range, or whether a copy from the 836 new register back to the original at the end of the range. Operand 6 is the 837 live length. Operand 7 is the number of calls that this register is live 838 across. Operand 8 is the symbol node of the variable if the register is a 839 user variable. Operand 9 is the block node that the variable is declared 840 in if the register is a user variable. */ 841DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x') 842 843/* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of 844 the different ranges a variable is in where it is copied to a different 845 pseudo register. Operand 1 is the block that the variable is declared in. 846 Operand 2 is the number of distinct ranges. */ 847DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x') 848 849/* Information about the registers that are live at the current point. Operand 850 0 is the live bitmap. Operand 1 is the original block number. */ 851DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x') 852 853/* A unary `__builtin_constant_p' expression. These are only emitted 854 during RTL generation, and then only if optimize > 0. They are 855 eliminated by the first CSE pass. */ 856DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x') 857 858/* A placeholder for a CALL_INSN which may be turned into a normal call, 859 a sibling (tail) call or tail recursion. 860 861 Immediately after RTL generation, this placeholder will be replaced 862 by the insns to perform the call, sibcall or tail recursion. 863 864 This RTX has 4 operands. The first three are lists of instructions to 865 perform the call as a normal call, sibling call and tail recursion 866 respectively. The latter two lists may be NULL, the first may never 867 be NULL. 868 869 The last operand is the tail recursion CODE_LABEL, which may be NULL if no 870 potential tail recursive calls were found. 871 872 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P 873 after we select a call method. */ 874DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x') 875 876/* 877Local variables: 878mode:c 879End: 880*/ 881