1117395Skan;; Scheduling description for UltraSPARC-III. 2169689Skan;; Copyright (C) 2002, 2004 Free Software Foundation, Inc. 3117395Skan;; 4132718Skan;; This file is part of GCC. 5117395Skan;; 6132718Skan;; GCC is free software; you can redistribute it and/or modify 7117395Skan;; it under the terms of the GNU General Public License as published by 8117395Skan;; the Free Software Foundation; either version 2, or (at your option) 9117395Skan;; any later version. 10117395Skan;; 11132718Skan;; GCC is distributed in the hope that it will be useful, 12117395Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13117395Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14117395Skan;; GNU General Public License for more details. 15117395Skan;; 16117395Skan;; You should have received a copy of the GNU General Public License 17132718Skan;; along with GCC; see the file COPYING. If not, write to 18169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19169689Skan;; Boston, MA 02110-1301, USA. 20117395Skan 21117395Skan;; UltraSPARC-III is a quad-issue processor. 22117395Skan;; 23117395Skan;; It is also a much simpler beast than Ultra-I/II, no silly 24117395Skan;; slotting rules and both integer units are fully symmetric. 25117395Skan;; It does still have single-issue instructions though. 26117395Skan 27117395Skan(define_automaton "ultrasparc3_0,ultrasparc3_1") 28117395Skan 29117395Skan(define_cpu_unit "us3_ms,us3_br,us3_fpm" "ultrasparc3_0") 30117395Skan(define_cpu_unit "us3_a0,us3_a1,us3_slot0,\ 31117395Skan us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1") 32117395Skan(define_cpu_unit "us3_load_writeback" "ultrasparc3_1") 33117395Skan 34117395Skan(define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)") 35117395Skan(define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3") 36117395Skan(define_reservation "us3_ax" "(us3_a0 | us3_a1)") 37117395Skan 38117395Skan(define_insn_reservation "us3_single" 1 39117395Skan (and (eq_attr "cpu" "ultrasparc3") 40169689Skan (eq_attr "type" "multi,savew,flushw,iflush,trap")) 41117395Skan "us3_single_issue") 42117395Skan 43117395Skan(define_insn_reservation "us3_integer" 1 44117395Skan (and (eq_attr "cpu" "ultrasparc3") 45117395Skan (eq_attr "type" "ialu,shift,compare")) 46117395Skan "us3_ax + us3_slotany") 47117395Skan 48117395Skan(define_insn_reservation "us3_ialuX" 5 49117395Skan (and (eq_attr "cpu" "ultrasparc3") 50117395Skan (eq_attr "type" "ialu,shift,compare")) 51117395Skan "us3_single_issue*4, nothing") 52117395Skan 53117395Skan(define_insn_reservation "us3_cmove" 2 54117395Skan (and (eq_attr "cpu" "ultrasparc3") 55117395Skan (eq_attr "type" "cmove")) 56117395Skan "us3_ms + us3_br + us3_slotany, nothing") 57117395Skan 58117395Skan;; ??? Not entirely accurate. 59117395Skan;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe 60117395Skan;; ??? is needed, and the instruction group is broken right after 61117395Skan;; ??? the imul. Then 'helper' instructions are generated to perform 62117395Skan;; ??? each further stage of the multiplication, each such 'helper' is 63117395Skan;; ??? single group. So, the reservation aspect is represented accurately 64117395Skan;; ??? here, but the variable cycles are not. 65117395Skan;; ??? Currently I have no idea how to determine the variability, but once 66117395Skan;; ??? known we can simply add a define_bypass or similar to model it. 67117395Skan(define_insn_reservation "us3_imul" 7 68117395Skan (and (eq_attr "cpu" "ultrasparc3") 69117395Skan (eq_attr "type" "imul")) 70117395Skan "us3_ms + us3_slotany, us3_single_issue*4, nothing*2") 71117395Skan 72117395Skan(define_insn_reservation "us3_idiv" 72 73117395Skan (and (eq_attr "cpu" "ultrasparc3") 74117395Skan (eq_attr "type" "idiv")) 75117395Skan "us3_ms + us3_slotany, us3_single_issue*69, nothing*2") 76117395Skan 77117395Skan;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except 78117395Skan;; that all loads except 32-bit/64-bit unsigned loads take the extra 79117395Skan;; delay for sign/zero extension. 80117395Skan(define_insn_reservation "us3_2cycle_load" 2 81117395Skan (and (eq_attr "cpu" "ultrasparc3") 82117395Skan (and (eq_attr "type" "load,fpload") 83117395Skan (eq_attr "us3load_type" "2cycle"))) 84117395Skan "us3_ms + us3_slotany, us3_load_writeback") 85117395Skan 86117395Skan(define_insn_reservation "us3_load_delayed" 3 87117395Skan (and (eq_attr "cpu" "ultrasparc3") 88117395Skan (and (eq_attr "type" "load,sload") 89117395Skan (eq_attr "us3load_type" "3cycle"))) 90117395Skan "us3_ms + us3_slotany, nothing, us3_load_writeback") 91117395Skan 92117395Skan(define_insn_reservation "us3_store" 1 93117395Skan (and (eq_attr "cpu" "ultrasparc3") 94117395Skan (eq_attr "type" "store,fpstore")) 95117395Skan "us3_ms + us3_slotany") 96117395Skan 97117395Skan(define_insn_reservation "us3_branch" 1 98117395Skan (and (eq_attr "cpu" "ultrasparc3") 99117395Skan (eq_attr "type" "branch")) 100117395Skan "us3_br + us3_slotany") 101117395Skan 102117395Skan(define_insn_reservation "us3_call_jmpl" 1 103117395Skan (and (eq_attr "cpu" "ultrasparc3") 104117395Skan (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) 105117395Skan "us3_br + us3_ms + us3_slotany") 106117395Skan 107117395Skan(define_insn_reservation "us3_fmov" 3 108117395Skan (and (eq_attr "cpu" "ultrasparc3") 109117395Skan (eq_attr "type" "fpmove")) 110117395Skan "us3_fpa + us3_slotany, nothing*2") 111117395Skan 112117395Skan(define_insn_reservation "us3_fcmov" 3 113117395Skan (and (eq_attr "cpu" "ultrasparc3") 114117395Skan (eq_attr "type" "fpcmove")) 115117395Skan "us3_fpa + us3_br + us3_slotany, nothing*2") 116117395Skan 117117395Skan(define_insn_reservation "us3_fcrmov" 3 118117395Skan (and (eq_attr "cpu" "ultrasparc3") 119117395Skan (eq_attr "type" "fpcrmove")) 120117395Skan "us3_fpa + us3_ms + us3_slotany, nothing*2") 121117395Skan 122117395Skan(define_insn_reservation "us3_faddsub" 4 123117395Skan (and (eq_attr "cpu" "ultrasparc3") 124117395Skan (eq_attr "type" "fp")) 125117395Skan "us3_fpa + us3_slotany, nothing*3") 126117395Skan 127117395Skan(define_insn_reservation "us3_fpcmp" 5 128117395Skan (and (eq_attr "cpu" "ultrasparc3") 129117395Skan (eq_attr "type" "fpcmp")) 130117395Skan "us3_fpa + us3_slotany, nothing*4") 131117395Skan 132117395Skan(define_insn_reservation "us3_fmult" 4 133117395Skan (and (eq_attr "cpu" "ultrasparc3") 134117395Skan (eq_attr "type" "fpmul")) 135117395Skan "us3_fpm + us3_slotany, nothing*3") 136117395Skan 137117395Skan(define_insn_reservation "us3_fdivs" 17 138117395Skan (and (eq_attr "cpu" "ultrasparc3") 139117395Skan (eq_attr "type" "fpdivs")) 140117395Skan "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2") 141117395Skan 142117395Skan(define_insn_reservation "us3_fsqrts" 20 143117395Skan (and (eq_attr "cpu" "ultrasparc3") 144117395Skan (eq_attr "type" "fpsqrts")) 145117395Skan "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") 146117395Skan 147117395Skan(define_insn_reservation "us3_fdivd" 20 148117395Skan (and (eq_attr "cpu" "ultrasparc3") 149117395Skan (eq_attr "type" "fpdivd")) 150117395Skan "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") 151117395Skan 152117395Skan(define_insn_reservation "us3_fsqrtd" 29 153117395Skan (and (eq_attr "cpu" "ultrasparc3") 154117395Skan (eq_attr "type" "fpsqrtd")) 155117395Skan "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2") 156117395Skan 157117395Skan;; Any store may multi issue with the insn creating the source 158117395Skan;; data as long as that creating insn is not an FPU div/sqrt. 159117395Skan;; We need a special guard function because this bypass does 160117395Skan;; not apply to the address inputs of the store. 161117395Skan(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store" 162117395Skan "store_data_bypass_p") 163117395Skan 164117395Skan;; An integer branch may execute in the same cycle as the compare 165117395Skan;; creating the condition codes. 166117395Skan(define_bypass 0 "us3_integer" "us3_branch") 167117395Skan 168117395Skan;; If FMOVfcc is user of FPCMP, latency is only 1 cycle. 169117395Skan(define_bypass 1 "us3_fpcmp" "us3_fcmov") 170132718Skan 171132718Skan;; VIS scheduling 172132718Skan(define_insn_reservation "us3_fga" 173132718Skan 3 174132718Skan (and (eq_attr "cpu" "ultrasparc3") 175132718Skan (eq_attr "type" "fga")) 176132718Skan "us3_fpa + us3_slotany, nothing*2") 177132718Skan 178132718Skan(define_insn_reservation "us3_fgm" 179132718Skan 4 180132718Skan (and (eq_attr "cpu" "ultrasparc3") 181132718Skan (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp")) 182132718Skan "us3_fpm + us3_slotany, nothing*3") 183132718Skan 184132718Skan(define_insn_reservation "us3_pdist" 185132718Skan 4 186132718Skan (and (eq_attr "cpu" "ultrasparc3") 187132718Skan (eq_attr "type" "fgm_pdist")) 188132718Skan "us3_fpm + us3_slotany, nothing*3") 189132718Skan 190132718Skan(define_bypass 1 "us3_pdist" "us3_pdist") 191