159024Sobrien/* Definitions for opcode table for the sparc. 2130561Sobrien Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, 3218822Sdim 2003, 2005 Free Software Foundation, Inc. 459024Sobrien 5218822Sdim This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 6218822Sdim the GNU Binutils. 759024Sobrien 8218822Sdim GAS/GDB is free software; you can redistribute it and/or modify 9218822Sdim it under the terms of the GNU General Public License as published by 10218822Sdim the Free Software Foundation; either version 2, or (at your option) 11218822Sdim any later version. 1259024Sobrien 13218822Sdim GAS/GDB is distributed in the hope that it will be useful, 14218822Sdim but WITHOUT ANY WARRANTY; without even the implied warranty of 15218822Sdim MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16218822Sdim GNU General Public License for more details. 1759024Sobrien 18218822Sdim You should have received a copy of the GNU General Public License 19218822Sdim along with GAS or GDB; see the file COPYING. If not, write to 20218822Sdim the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21218822Sdim Boston, MA 02110-1301, USA. */ 2259024Sobrien 23104834Sobrien#include "ansidecl.h" 2459024Sobrien 2559024Sobrien/* The SPARC opcode table (and other related data) is defined in 2659024Sobrien the opcodes library in sparc-opc.c. If you change anything here, make 2759024Sobrien sure you fix up that file, and vice versa. */ 2859024Sobrien 2959024Sobrien /* FIXME-someday: perhaps the ,a's and such should be embedded in the 3059024Sobrien instruction's name rather than the args. This would make gas faster, pinsn 3159024Sobrien slower, but would mess up some macros a bit. xoxorich. */ 3259024Sobrien 3359024Sobrien/* List of instruction sets variations. 3459024Sobrien These values are such that each element is either a superset of a 3559024Sobrien preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 3659024Sobrien returns non-zero. 3759024Sobrien The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 3859024Sobrien Don't change this without updating sparc-opc.c. */ 3959024Sobrien 40218822Sdimenum sparc_opcode_arch_val 41218822Sdim{ 4259024Sobrien SPARC_OPCODE_ARCH_V6 = 0, 4359024Sobrien SPARC_OPCODE_ARCH_V7, 4459024Sobrien SPARC_OPCODE_ARCH_V8, 4559024Sobrien SPARC_OPCODE_ARCH_SPARCLET, 4659024Sobrien SPARC_OPCODE_ARCH_SPARCLITE, 47218822Sdim /* V9 variants must appear last. */ 4859024Sobrien SPARC_OPCODE_ARCH_V9, 49218822Sdim SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ 50218822Sdim SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ 51218822Sdim SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ 5259024Sobrien}; 5359024Sobrien 5459024Sobrien/* The highest architecture in the table. */ 5559024Sobrien#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) 5659024Sobrien 5759024Sobrien/* Given an enum sparc_opcode_arch_val, return the bitmask to use in 5859024Sobrien insn encoding/decoding. */ 5959024Sobrien#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 6059024Sobrien 6159024Sobrien/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 6259024Sobrien#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 6359024Sobrien 6459024Sobrien/* Table of cpu variants. */ 6559024Sobrien 66218822Sdimtypedef struct sparc_opcode_arch 67218822Sdim{ 6859024Sobrien const char *name; 6959024Sobrien /* Mask of sparc_opcode_arch_val's supported. 7059024Sobrien EG: For v7 this would be 7159024Sobrien (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 7259024Sobrien These are short's because sparc_opcode.architecture is. */ 7359024Sobrien short supported; 74218822Sdim} sparc_opcode_arch; 7559024Sobrien 7659024Sobrienextern const struct sparc_opcode_arch sparc_opcode_archs[]; 7759024Sobrien 7859024Sobrien/* Given architecture name, look up it's sparc_opcode_arch_val value. */ 79130561Sobrienextern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); 8059024Sobrien 8159024Sobrien/* Return the bitmask of supported architectures for ARCH. */ 8259024Sobrien#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 8359024Sobrien 8459024Sobrien/* Non-zero if ARCH1 conflicts with ARCH2. 8559024Sobrien IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 8659024Sobrien#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 87218822Sdim (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 88218822Sdim != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 89218822Sdim && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 9059024Sobrien != SPARC_OPCODE_SUPPORTED (ARCH2))) 9159024Sobrien 9259024Sobrien/* Structure of an opcode table entry. */ 9359024Sobrien 94218822Sdimtypedef struct sparc_opcode 95218822Sdim{ 9659024Sobrien const char *name; 97218822Sdim unsigned long match; /* Bits that must be set. */ 98218822Sdim unsigned long lose; /* Bits that must not be set. */ 9959024Sobrien const char *args; 100218822Sdim /* This was called "delayed" in versions before the flags. */ 10159024Sobrien char flags; 10259024Sobrien short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 103218822Sdim} sparc_opcode; 10459024Sobrien 105218822Sdim#define F_DELAYED 1 /* Delayed branch. */ 106218822Sdim#define F_ALIAS 2 /* Alias for a "real" instruction. */ 107218822Sdim#define F_UNBR 4 /* Unconditional branch. */ 108218822Sdim#define F_CONDBR 8 /* Conditional branch. */ 109218822Sdim#define F_JSR 16 /* Subroutine call. */ 110218822Sdim#define F_FLOAT 32 /* Floating point instruction (not a branch). */ 111218822Sdim#define F_FBR 64 /* Floating point branch. */ 11259024Sobrien/* FIXME: Add F_ANACHRONISTIC flag for v9. */ 11359024Sobrien 114218822Sdim/* All sparc opcodes are 32 bits, except for the `set' instruction (really a 115218822Sdim macro), which is 64 bits. It is handled as a special case. 11659024Sobrien 117218822Sdim The match component is a mask saying which bits must match a particular 118218822Sdim opcode in order for an instruction to be an instance of that opcode. 11959024Sobrien 120218822Sdim The args component is a string containing one character for each operand of the 121218822Sdim instruction. 12259024Sobrien 123218822Sdim Kinds of operands: 12459024Sobrien # Number used by optimizer. It is ignored. 12559024Sobrien 1 rs1 register. 12659024Sobrien 2 rs2 register. 12759024Sobrien d rd register. 12859024Sobrien e frs1 floating point register. 12959024Sobrien v frs1 floating point register (double/even). 13059024Sobrien V frs1 floating point register (quad/multiple of 4). 13159024Sobrien f frs2 floating point register. 13259024Sobrien B frs2 floating point register (double/even). 13359024Sobrien R frs2 floating point register (quad/multiple of 4). 13459024Sobrien g frsd floating point register. 13559024Sobrien H frsd floating point register (double/even). 13659024Sobrien J frsd floating point register (quad/multiple of 4). 13759024Sobrien b crs1 coprocessor register 13859024Sobrien c crs2 coprocessor register 13959024Sobrien D crsd coprocessor register 14059024Sobrien m alternate space register (asr) in rd 14159024Sobrien M alternate space register (asr) in rs1 14259024Sobrien h 22 high bits. 14359024Sobrien X 5 bit unsigned immediate 14459024Sobrien Y 6 bit unsigned immediate 14577298Sobrien 3 SIAM mode (3 bits). (v9b) 14659024Sobrien K MEMBAR mask (7 bits). (v9) 14759024Sobrien j 10 bit Immediate. (v9) 14859024Sobrien I 11 bit Immediate. (v9) 14959024Sobrien i 13 bit Immediate. 15059024Sobrien n 22 bit immediate. 15159024Sobrien k 2+14 bit PC relative immediate. (v9) 15259024Sobrien G 19 bit PC relative immediate. (v9) 15359024Sobrien l 22 bit PC relative immediate. 15459024Sobrien L 30 bit PC relative immediate. 15559024Sobrien a Annul. The annul bit is set. 15659024Sobrien A Alternate address space. Stored as 8 bits. 15759024Sobrien C Coprocessor state register. 15859024Sobrien F floating point state register. 15959024Sobrien p Processor state register. 16059024Sobrien N Branch predict clear ",pn" (v9) 16159024Sobrien T Branch predict set ",pt" (v9) 16259024Sobrien z %icc. (v9) 16359024Sobrien Z %xcc. (v9) 16459024Sobrien q Floating point queue. 16559024Sobrien r Single register that is both rs1 and rd. 16659024Sobrien O Single register that is both rs2 and rd. 16759024Sobrien Q Coprocessor queue. 16859024Sobrien S Special case. 16959024Sobrien t Trap base register. 17059024Sobrien w Window invalid mask register. 17159024Sobrien y Y register. 17259024Sobrien u sparclet coprocessor registers in rd position 17359024Sobrien U sparclet coprocessor registers in rs1 position 17459024Sobrien E %ccr. (v9) 17559024Sobrien s %fprs. (v9) 17659024Sobrien P %pc. (v9) 17759024Sobrien W %tick. (v9) 17859024Sobrien o %asi. (v9) 17959024Sobrien 6 %fcc0. (v9) 18059024Sobrien 7 %fcc1. (v9) 18159024Sobrien 8 %fcc2. (v9) 18259024Sobrien 9 %fcc3. (v9) 18359024Sobrien ! Privileged Register in rd (v9) 18459024Sobrien ? Privileged Register in rs1 (v9) 18559024Sobrien * Prefetch function constant. (v9) 18659024Sobrien x OPF field (v9 impdep). 18759024Sobrien 0 32/64 bit immediate for set or setx (v9) insns 18859024Sobrien _ Ancillary state register in rd (v9a) 18959024Sobrien / Ancillary state register in rs1 (v9a) 19059024Sobrien 191218822Sdim The following chars are unused: (note: ,[] are used as punctuation) 192218822Sdim [45]. */ 19359024Sobrien 194218822Sdim#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 195218822Sdim#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ 196218822Sdim#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ 197218822Sdim#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ 198218822Sdim#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ 199218822Sdim#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ 200218822Sdim#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ 201218822Sdim#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ 202218822Sdim#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ 203218822Sdim#define F1(x) (OP (x)) 204218822Sdim#define DISP30(x) ((x) & 0x3fffffff) 205218822Sdim#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ 206218822Sdim#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ 207218822Sdim#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ 208218822Sdim#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ 209218822Sdim#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ 210218822Sdim#define ASI_RS2(x) (SIMM13 (x)) 211218822Sdim#define MEMBAR(x) ((x) & 0x7f) 212218822Sdim#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ 21359024Sobrien 214218822Sdim#define ANNUL (1 << 29) 215218822Sdim#define BPRED (1 << 19) /* V9. */ 216218822Sdim#define IMMED F3I (1) 217218822Sdim#define RD_G0 RD (~0) 218218822Sdim#define RS1_G0 RS1 (~0) 219218822Sdim#define RS2_G0 RS2 (~0) 22059024Sobrien 22159024Sobrienextern const struct sparc_opcode sparc_opcodes[]; 22259024Sobrienextern const int sparc_num_opcodes; 22359024Sobrien 224130561Sobrienextern int sparc_encode_asi (const char *); 225130561Sobrienextern const char *sparc_decode_asi (int); 226130561Sobrienextern int sparc_encode_membar (const char *); 227130561Sobrienextern const char *sparc_decode_membar (int); 228130561Sobrienextern int sparc_encode_prefetch (const char *); 229130561Sobrienextern const char *sparc_decode_prefetch (int); 230130561Sobrienextern int sparc_encode_sparclet_cpreg (const char *); 231130561Sobrienextern const char *sparc_decode_sparclet_cpreg (int); 23259024Sobrien 233218822Sdim/* Local Variables: 234218822Sdim fill-column: 131 235218822Sdim comment-column: 0 236218822Sdim End: */ 23759024Sobrien 238