tc-sparc.c revision 91041
1/* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002 4 Free Software Foundation, Inc. 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public 18 License along with GAS; see the file COPYING. If not, write 19 to the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22#include <stdio.h> 23 24#include "as.h" 25#include "safe-ctype.h" 26#include "subsegs.h" 27 28#include "opcode/sparc.h" 29 30#ifdef OBJ_ELF 31#include "elf/sparc.h" 32#include "dwarf2dbg.h" 33#endif 34 35/* Some ancient Sun C compilers would not take such hex constants as 36 unsigned, and would end up sign-extending them to form an offsetT, 37 so use these constants instead. */ 38#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 39#define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 40 41static struct sparc_arch *lookup_arch PARAMS ((char *)); 42static void init_default_arch PARAMS ((void)); 43static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); 44static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 45static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); 46static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 47static int sparc_ffs PARAMS ((unsigned int)); 48static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); 49static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); 50static void synthetize_setx PARAMS ((const struct sparc_opcode *)); 51static bfd_vma BSR PARAMS ((bfd_vma, int)); 52static int cmp_reg_entry PARAMS ((const PTR, const PTR)); 53static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); 54static int parse_const_expr_arg PARAMS ((char **, int *)); 55static int get_expression PARAMS ((char *str)); 56 57/* Default architecture. */ 58/* ??? The default value should be V8, but sparclite support was added 59 by making it the default. GCC now passes -Asparclite, so maybe sometime in 60 the future we can set this to V8. */ 61#ifndef DEFAULT_ARCH 62#define DEFAULT_ARCH "sparclite" 63#endif 64static char *default_arch = DEFAULT_ARCH; 65 66/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 67 have been set. */ 68static int default_init_p; 69 70/* Current architecture. We don't bump up unless necessary. */ 71static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 72 73/* The maximum architecture level we can bump up to. 74 In a 32 bit environment, don't allow bumping up to v9 by default. 75 The native assembler works this way. The user is required to pass 76 an explicit argument before we'll create v9 object files. However, if 77 we don't see any v9 insns, a v8plus object file is not created. */ 78static enum sparc_opcode_arch_val max_architecture; 79 80/* Either 32 or 64, selects file format. */ 81static int sparc_arch_size; 82/* Initial (default) value, recorded separately in case a user option 83 changes the value before md_show_usage is called. */ 84static int default_arch_size; 85 86#ifdef OBJ_ELF 87/* The currently selected v9 memory model. Currently only used for 88 ELF. */ 89static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 90#endif 91 92static int architecture_requested; 93static int warn_on_bump; 94 95/* If warn_on_bump and the needed architecture is higher than this 96 architecture, issue a warning. */ 97static enum sparc_opcode_arch_val warn_after_architecture; 98 99/* Non-zero if as should generate error if an undeclared g[23] register 100 has been used in -64. */ 101static int no_undeclared_regs; 102 103/* Non-zero if we should try to relax jumps and calls. */ 104static int sparc_relax; 105 106/* Non-zero if we are generating PIC code. */ 107int sparc_pic_code; 108 109/* Non-zero if we should give an error when misaligned data is seen. */ 110static int enforce_aligned_data; 111 112extern int target_big_endian; 113 114static int target_little_endian_data; 115 116/* Symbols for global registers on v9. */ 117static symbolS *globals[8]; 118 119/* V9 and 86x have big and little endian data, but instructions are always big 120 endian. The sparclet has bi-endian support but both data and insns have 121 the same endianness. Global `target_big_endian' is used for data. 122 The following macro is used for instructions. */ 123#ifndef INSN_BIG_ENDIAN 124#define INSN_BIG_ENDIAN (target_big_endian \ 125 || default_arch_type == sparc86x \ 126 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 127#endif 128 129/* Handle of the OPCODE hash table. */ 130static struct hash_control *op_hash; 131 132static int log2 PARAMS ((int)); 133static void s_data1 PARAMS ((void)); 134static void s_seg PARAMS ((int)); 135static void s_proc PARAMS ((int)); 136static void s_reserve PARAMS ((int)); 137static void s_common PARAMS ((int)); 138static void s_empty PARAMS ((int)); 139static void s_uacons PARAMS ((int)); 140static void s_ncons PARAMS ((int)); 141static void s_register PARAMS ((int)); 142 143const pseudo_typeS md_pseudo_table[] = 144{ 145 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 146 {"common", s_common, 0}, 147 {"empty", s_empty, 0}, 148 {"global", s_globl, 0}, 149 {"half", cons, 2}, 150 {"nword", s_ncons, 0}, 151 {"optim", s_ignore, 0}, 152 {"proc", s_proc, 0}, 153 {"reserve", s_reserve, 0}, 154 {"seg", s_seg, 0}, 155 {"skip", s_space, 0}, 156 {"word", cons, 4}, 157 {"xword", cons, 8}, 158 {"uahalf", s_uacons, 2}, 159 {"uaword", s_uacons, 4}, 160 {"uaxword", s_uacons, 8}, 161#ifdef OBJ_ELF 162 {"file", dwarf2_directive_file, 0}, 163 {"loc", dwarf2_directive_loc, 0}, 164 /* These are specific to sparc/svr4. */ 165 {"2byte", s_uacons, 2}, 166 {"4byte", s_uacons, 4}, 167 {"8byte", s_uacons, 8}, 168 {"register", s_register, 0}, 169#endif 170 {NULL, 0, 0}, 171}; 172 173/* Size of relocation record. */ 174const int md_reloc_size = 12; 175 176/* This array holds the chars that always start a comment. If the 177 pre-processor is disabled, these aren't very useful. */ 178const char comment_chars[] = "!"; /* JF removed '|' from 179 comment_chars. */ 180 181/* This array holds the chars that only start a comment at the beginning of 182 a line. If the line seems to have the form '# 123 filename' 183 .line and .file directives will appear in the pre-processed output. */ 184/* Note that input_file.c hand checks for '#' at the beginning of the 185 first line of the input file. This is because the compiler outputs 186 #NO_APP at the beginning of its output. */ 187/* Also note that comments started like this one will always 188 work if '/' isn't otherwise defined. */ 189const char line_comment_chars[] = "#"; 190 191const char line_separator_chars[] = ";"; 192 193/* Chars that can be used to separate mant from exp in floating point 194 nums. */ 195const char EXP_CHARS[] = "eE"; 196 197/* Chars that mean this number is a floating point constant. 198 As in 0f12.456 199 or 0d1.2345e12 */ 200const char FLT_CHARS[] = "rRsSfFdDxXpP"; 201 202/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 203 changed in read.c. Ideally it shouldn't have to know about it at all, 204 but nothing is ideal around here. */ 205 206#define isoctal(c) ((unsigned) ((c) - '0') < '8') 207 208struct sparc_it 209 { 210 char *error; 211 unsigned long opcode; 212 struct nlist *nlistp; 213 expressionS exp; 214 expressionS exp2; 215 int pcrel; 216 bfd_reloc_code_real_type reloc; 217 }; 218 219struct sparc_it the_insn, set_insn; 220 221static void output_insn 222 PARAMS ((const struct sparc_opcode *, struct sparc_it *)); 223 224/* Table of arguments to -A. 225 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 226 for this use. That table is for opcodes only. This table is for opcodes 227 and file formats. */ 228 229enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 230 v8plusa, v9, v9a, v9b, v9_64}; 231 232static struct sparc_arch { 233 char *name; 234 char *opcode_arch; 235 enum sparc_arch_types arch_type; 236 /* Default word size, as specified during configuration. 237 A value of zero means can't be used to specify default architecture. */ 238 int default_arch_size; 239 /* Allowable arg to -A? */ 240 int user_option_p; 241} sparc_arch_table[] = { 242 { "v6", "v6", v6, 0, 1 }, 243 { "v7", "v7", v7, 0, 1 }, 244 { "v8", "v8", v8, 32, 1 }, 245 { "sparclet", "sparclet", sparclet, 32, 1 }, 246 { "sparclite", "sparclite", sparclite, 32, 1 }, 247 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 248 { "v8plus", "v9", v9, 0, 1 }, 249 { "v8plusa", "v9a", v9, 0, 1 }, 250 { "v8plusb", "v9b", v9, 0, 1 }, 251 { "v9", "v9", v9, 0, 1 }, 252 { "v9a", "v9a", v9, 0, 1 }, 253 { "v9b", "v9b", v9, 0, 1 }, 254 /* This exists to allow configure.in/Makefile.in to pass one 255 value to specify both the default machine and default word size. */ 256 { "v9-64", "v9", v9, 64, 0 }, 257 { NULL, NULL, v8, 0, 0 } 258}; 259 260/* Variant of default_arch */ 261static enum sparc_arch_types default_arch_type; 262 263static struct sparc_arch * 264lookup_arch (name) 265 char *name; 266{ 267 struct sparc_arch *sa; 268 269 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 270 if (strcmp (sa->name, name) == 0) 271 break; 272 if (sa->name == NULL) 273 return NULL; 274 return sa; 275} 276 277/* Initialize the default opcode arch and word size from the default 278 architecture name. */ 279 280static void 281init_default_arch () 282{ 283 struct sparc_arch *sa = lookup_arch (default_arch); 284 285 if (sa == NULL 286 || sa->default_arch_size == 0) 287 as_fatal (_("Invalid default architecture, broken assembler.")); 288 289 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 290 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 291 as_fatal (_("Bad opcode table, broken assembler.")); 292 default_arch_size = sparc_arch_size = sa->default_arch_size; 293 default_init_p = 1; 294 default_arch_type = sa->arch_type; 295} 296 297/* Called by TARGET_FORMAT. */ 298 299const char * 300sparc_target_format () 301{ 302 /* We don't get a chance to initialize anything before we're called, 303 so handle that now. */ 304 if (! default_init_p) 305 init_default_arch (); 306 307#ifdef OBJ_AOUT 308#ifdef TE_NetBSD 309 return "a.out-sparc-netbsd"; 310#else 311#ifdef TE_SPARCAOUT 312 if (target_big_endian) 313 return "a.out-sunos-big"; 314 else if (default_arch_type == sparc86x && target_little_endian_data) 315 return "a.out-sunos-big"; 316 else 317 return "a.out-sparc-little"; 318#else 319 return "a.out-sunos-big"; 320#endif 321#endif 322#endif 323 324#ifdef OBJ_BOUT 325 return "b.out.big"; 326#endif 327 328#ifdef OBJ_COFF 329#ifdef TE_LYNX 330 return "coff-sparc-lynx"; 331#else 332 return "coff-sparc"; 333#endif 334#endif 335 336#ifdef OBJ_ELF 337 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; 338#endif 339 340 abort (); 341} 342 343/* md_parse_option 344 * Invocation line includes a switch not recognized by the base assembler. 345 * See if it's a processor-specific option. These are: 346 * 347 * -bump 348 * Warn on architecture bumps. See also -A. 349 * 350 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 351 * Standard 32 bit architectures. 352 * -Av9, -Av9a, -Av9b 353 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 354 * This used to only mean 64 bits, but properly specifying it 355 * complicated gcc's ASM_SPECs, so now opcode selection is 356 * specified orthogonally to word size (except when specifying 357 * the default, but that is an internal implementation detail). 358 * -Av8plus, -Av8plusa, -Av8plusb 359 * Same as -Av9{,a,b}. 360 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 361 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 362 * assembler. 363 * -xarch=v9, -xarch=v9a, -xarch=v9b 364 * Same as -Av9{,a,b} -64, for compatibility with Sun's 365 * assembler. 366 * 367 * Select the architecture and possibly the file format. 368 * Instructions or features not supported by the selected 369 * architecture cause fatal errors. 370 * 371 * The default is to start at v6, and bump the architecture up 372 * whenever an instruction is seen at a higher level. In 32 bit 373 * environments, v9 is not bumped up to, the user must pass 374 * -Av8plus{,a,b}. 375 * 376 * If -bump is specified, a warning is printing when bumping to 377 * higher levels. 378 * 379 * If an architecture is specified, all instructions must match 380 * that architecture. Any higher level instructions are flagged 381 * as errors. Note that in the 32 bit environment specifying 382 * -Av8plus does not automatically create a v8plus object file, a 383 * v9 insn must be seen. 384 * 385 * If both an architecture and -bump are specified, the 386 * architecture starts at the specified level, but bumps are 387 * warnings. Note that we can't set `current_architecture' to 388 * the requested level in this case: in the 32 bit environment, 389 * we still must avoid creating v8plus object files unless v9 390 * insns are seen. 391 * 392 * Note: 393 * Bumping between incompatible architectures is always an 394 * error. For example, from sparclite to v9. 395 */ 396 397#ifdef OBJ_ELF 398CONST char *md_shortopts = "A:K:VQ:sq"; 399#else 400#ifdef OBJ_AOUT 401CONST char *md_shortopts = "A:k"; 402#else 403CONST char *md_shortopts = "A:"; 404#endif 405#endif 406struct option md_longopts[] = { 407#define OPTION_BUMP (OPTION_MD_BASE) 408 {"bump", no_argument, NULL, OPTION_BUMP}, 409#define OPTION_SPARC (OPTION_MD_BASE + 1) 410 {"sparc", no_argument, NULL, OPTION_SPARC}, 411#define OPTION_XARCH (OPTION_MD_BASE + 2) 412 {"xarch", required_argument, NULL, OPTION_XARCH}, 413#ifdef OBJ_ELF 414#define OPTION_32 (OPTION_MD_BASE + 3) 415 {"32", no_argument, NULL, OPTION_32}, 416#define OPTION_64 (OPTION_MD_BASE + 4) 417 {"64", no_argument, NULL, OPTION_64}, 418#define OPTION_TSO (OPTION_MD_BASE + 5) 419 {"TSO", no_argument, NULL, OPTION_TSO}, 420#define OPTION_PSO (OPTION_MD_BASE + 6) 421 {"PSO", no_argument, NULL, OPTION_PSO}, 422#define OPTION_RMO (OPTION_MD_BASE + 7) 423 {"RMO", no_argument, NULL, OPTION_RMO}, 424#endif 425#ifdef SPARC_BIENDIAN 426#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 427 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 428#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 429 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 430#endif 431#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 432 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 433#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 434 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 435#ifdef OBJ_ELF 436#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 437 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 438#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 439 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 440#endif 441#define OPTION_RELAX (OPTION_MD_BASE + 14) 442 {"relax", no_argument, NULL, OPTION_RELAX}, 443#define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 444 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 445 {NULL, no_argument, NULL, 0} 446}; 447 448size_t md_longopts_size = sizeof (md_longopts); 449 450int 451md_parse_option (c, arg) 452 int c; 453 char *arg; 454{ 455 /* We don't get a chance to initialize anything before we're called, 456 so handle that now. */ 457 if (! default_init_p) 458 init_default_arch (); 459 460 switch (c) 461 { 462 case OPTION_BUMP: 463 warn_on_bump = 1; 464 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 465 break; 466 467 case OPTION_XARCH: 468#ifdef OBJ_ELF 469 if (strncmp (arg, "v9", 2) != 0) 470 md_parse_option (OPTION_32, NULL); 471 else 472 md_parse_option (OPTION_64, NULL); 473#endif 474 /* Fall through. */ 475 476 case 'A': 477 { 478 struct sparc_arch *sa; 479 enum sparc_opcode_arch_val opcode_arch; 480 481 sa = lookup_arch (arg); 482 if (sa == NULL 483 || ! sa->user_option_p) 484 { 485 if (c == OPTION_XARCH) 486 as_bad (_("invalid architecture -xarch=%s"), arg); 487 else 488 as_bad (_("invalid architecture -A%s"), arg); 489 return 0; 490 } 491 492 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 493 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 494 as_fatal (_("Bad opcode table, broken assembler.")); 495 496 max_architecture = opcode_arch; 497 architecture_requested = 1; 498 } 499 break; 500 501 case OPTION_SPARC: 502 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 503 break; 504 505 case OPTION_ENFORCE_ALIGNED_DATA: 506 enforce_aligned_data = 1; 507 break; 508 509#ifdef SPARC_BIENDIAN 510 case OPTION_LITTLE_ENDIAN: 511 target_big_endian = 0; 512 if (default_arch_type != sparclet) 513 as_fatal ("This target does not support -EL"); 514 break; 515 case OPTION_LITTLE_ENDIAN_DATA: 516 target_little_endian_data = 1; 517 target_big_endian = 0; 518 if (default_arch_type != sparc86x 519 && default_arch_type != v9) 520 as_fatal ("This target does not support --little-endian-data"); 521 break; 522 case OPTION_BIG_ENDIAN: 523 target_big_endian = 1; 524 break; 525#endif 526 527#ifdef OBJ_AOUT 528 case 'k': 529 sparc_pic_code = 1; 530 break; 531#endif 532 533#ifdef OBJ_ELF 534 case OPTION_32: 535 case OPTION_64: 536 { 537 const char **list, **l; 538 539 sparc_arch_size = c == OPTION_32 ? 32 : 64; 540 list = bfd_target_list (); 541 for (l = list; *l != NULL; l++) 542 { 543 if (sparc_arch_size == 32) 544 { 545 if (strcmp (*l, "elf32-sparc") == 0) 546 break; 547 } 548 else 549 { 550 if (strcmp (*l, "elf64-sparc") == 0) 551 break; 552 } 553 } 554 if (*l == NULL) 555 as_fatal (_("No compiled in support for %d bit object file format"), 556 sparc_arch_size); 557 free (list); 558 } 559 break; 560 561 case OPTION_TSO: 562 sparc_memory_model = MM_TSO; 563 break; 564 565 case OPTION_PSO: 566 sparc_memory_model = MM_PSO; 567 break; 568 569 case OPTION_RMO: 570 sparc_memory_model = MM_RMO; 571 break; 572 573 case 'V': 574 print_version_id (); 575 break; 576 577 case 'Q': 578 /* Qy - do emit .comment 579 Qn - do not emit .comment. */ 580 break; 581 582 case 's': 583 /* Use .stab instead of .stab.excl. */ 584 break; 585 586 case 'q': 587 /* quick -- Native assembler does fewer checks. */ 588 break; 589 590 case 'K': 591 if (strcmp (arg, "PIC") != 0) 592 as_warn (_("Unrecognized option following -K")); 593 else 594 sparc_pic_code = 1; 595 break; 596 597 case OPTION_NO_UNDECLARED_REGS: 598 no_undeclared_regs = 1; 599 break; 600 601 case OPTION_UNDECLARED_REGS: 602 no_undeclared_regs = 0; 603 break; 604#endif 605 606 case OPTION_RELAX: 607 sparc_relax = 1; 608 break; 609 610 case OPTION_NO_RELAX: 611 sparc_relax = 0; 612 break; 613 614 default: 615 return 0; 616 } 617 618 return 1; 619} 620 621void 622md_show_usage (stream) 623 FILE *stream; 624{ 625 const struct sparc_arch *arch; 626 int column; 627 628 /* We don't get a chance to initialize anything before we're called, 629 so handle that now. */ 630 if (! default_init_p) 631 init_default_arch (); 632 633 fprintf (stream, _("SPARC options:\n")); 634 column = 0; 635 for (arch = &sparc_arch_table[0]; arch->name; arch++) 636 { 637 if (!arch->user_option_p) 638 continue; 639 if (arch != &sparc_arch_table[0]) 640 fprintf (stream, " | "); 641 if (column + strlen (arch->name) > 70) 642 { 643 column = 0; 644 fputc ('\n', stream); 645 } 646 column += 5 + 2 + strlen (arch->name); 647 fprintf (stream, "-A%s", arch->name); 648 } 649 for (arch = &sparc_arch_table[0]; arch->name; arch++) 650 { 651 if (!arch->user_option_p) 652 continue; 653 fprintf (stream, " | "); 654 if (column + strlen (arch->name) > 65) 655 { 656 column = 0; 657 fputc ('\n', stream); 658 } 659 column += 5 + 7 + strlen (arch->name); 660 fprintf (stream, "-xarch=%s", arch->name); 661 } 662 fprintf (stream, _("\n\ 663 specify variant of SPARC architecture\n\ 664-bump warn when assembler switches architectures\n\ 665-sparc ignored\n\ 666--enforce-aligned-data force .long, etc., to be aligned correctly\n\ 667-relax relax jumps and branches (default)\n\ 668-no-relax avoid changing any jumps and branches\n")); 669#ifdef OBJ_AOUT 670 fprintf (stream, _("\ 671-k generate PIC\n")); 672#endif 673#ifdef OBJ_ELF 674 fprintf (stream, _("\ 675-32 create 32 bit object file\n\ 676-64 create 64 bit object file\n")); 677 fprintf (stream, _("\ 678 [default is %d]\n"), default_arch_size); 679 fprintf (stream, _("\ 680-TSO use Total Store Ordering\n\ 681-PSO use Partial Store Ordering\n\ 682-RMO use Relaxed Memory Ordering\n")); 683 fprintf (stream, _("\ 684 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 685 fprintf (stream, _("\ 686-KPIC generate PIC\n\ 687-V print assembler version number\n\ 688-undeclared-regs ignore application global register usage without\n\ 689 appropriate .register directive (default)\n\ 690-no-undeclared-regs force error on application global register usage\n\ 691 without appropriate .register directive\n\ 692-q ignored\n\ 693-Qy, -Qn ignored\n\ 694-s ignored\n")); 695#endif 696#ifdef SPARC_BIENDIAN 697 fprintf (stream, _("\ 698-EL generate code for a little endian machine\n\ 699-EB generate code for a big endian machine\n\ 700--little-endian-data generate code for a machine having big endian\n\ 701 instructions and little endian data.\n")); 702#endif 703} 704 705/* Native operand size opcode translation. */ 706struct 707 { 708 char *name; 709 char *name32; 710 char *name64; 711 } native_op_table[] = 712{ 713 {"ldn", "ld", "ldx"}, 714 {"ldna", "lda", "ldxa"}, 715 {"stn", "st", "stx"}, 716 {"stna", "sta", "stxa"}, 717 {"slln", "sll", "sllx"}, 718 {"srln", "srl", "srlx"}, 719 {"sran", "sra", "srax"}, 720 {"casn", "cas", "casx"}, 721 {"casna", "casa", "casxa"}, 722 {"clrn", "clr", "clrx"}, 723 {NULL, NULL, NULL}, 724}; 725 726/* sparc64 priviledged registers. */ 727 728struct priv_reg_entry 729{ 730 char *name; 731 int regnum; 732}; 733 734struct priv_reg_entry priv_reg_table[] = 735{ 736 {"tpc", 0}, 737 {"tnpc", 1}, 738 {"tstate", 2}, 739 {"tt", 3}, 740 {"tick", 4}, 741 {"tba", 5}, 742 {"pstate", 6}, 743 {"tl", 7}, 744 {"pil", 8}, 745 {"cwp", 9}, 746 {"cansave", 10}, 747 {"canrestore", 11}, 748 {"cleanwin", 12}, 749 {"otherwin", 13}, 750 {"wstate", 14}, 751 {"fq", 15}, 752 {"ver", 31}, 753 {"", -1}, /* End marker. */ 754}; 755 756/* v9a specific asrs. */ 757 758struct priv_reg_entry v9a_asr_table[] = 759{ 760 {"tick_cmpr", 23}, 761 {"sys_tick_cmpr", 25}, 762 {"sys_tick", 24}, 763 {"softint", 22}, 764 {"set_softint", 20}, 765 {"pic", 17}, 766 {"pcr", 16}, 767 {"gsr", 19}, 768 {"dcr", 18}, 769 {"clear_softint", 21}, 770 {"", -1}, /* End marker. */ 771}; 772 773static int 774cmp_reg_entry (parg, qarg) 775 const PTR parg; 776 const PTR qarg; 777{ 778 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 779 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 780 781 return strcmp (q->name, p->name); 782} 783 784/* This function is called once, at assembler startup time. It should 785 set up all the tables, etc. that the MD part of the assembler will 786 need. */ 787 788void 789md_begin () 790{ 791 register const char *retval = NULL; 792 int lose = 0; 793 register unsigned int i = 0; 794 795 /* We don't get a chance to initialize anything before md_parse_option 796 is called, and it may not be called, so handle default initialization 797 now if not already done. */ 798 if (! default_init_p) 799 init_default_arch (); 800 801 op_hash = hash_new (); 802 803 while (i < (unsigned int) sparc_num_opcodes) 804 { 805 const char *name = sparc_opcodes[i].name; 806 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); 807 if (retval != NULL) 808 { 809 as_bad (_("Internal error: can't hash `%s': %s\n"), 810 sparc_opcodes[i].name, retval); 811 lose = 1; 812 } 813 do 814 { 815 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 816 { 817 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 818 sparc_opcodes[i].name, sparc_opcodes[i].args); 819 lose = 1; 820 } 821 ++i; 822 } 823 while (i < (unsigned int) sparc_num_opcodes 824 && !strcmp (sparc_opcodes[i].name, name)); 825 } 826 827 for (i = 0; native_op_table[i].name; i++) 828 { 829 const struct sparc_opcode *insn; 830 char *name = ((sparc_arch_size == 32) 831 ? native_op_table[i].name32 832 : native_op_table[i].name64); 833 insn = (struct sparc_opcode *) hash_find (op_hash, name); 834 if (insn == NULL) 835 { 836 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 837 name, native_op_table[i].name); 838 lose = 1; 839 } 840 else 841 { 842 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); 843 if (retval != NULL) 844 { 845 as_bad (_("Internal error: can't hash `%s': %s\n"), 846 sparc_opcodes[i].name, retval); 847 lose = 1; 848 } 849 } 850 } 851 852 if (lose) 853 as_fatal (_("Broken assembler. No assembly attempted.")); 854 855 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 856 sizeof (priv_reg_table[0]), cmp_reg_entry); 857 858 /* If -bump, record the architecture level at which we start issuing 859 warnings. The behaviour is different depending upon whether an 860 architecture was explicitly specified. If it wasn't, we issue warnings 861 for all upwards bumps. If it was, we don't start issuing warnings until 862 we need to bump beyond the requested architecture or when we bump between 863 conflicting architectures. */ 864 865 if (warn_on_bump 866 && architecture_requested) 867 { 868 /* `max_architecture' records the requested architecture. 869 Issue warnings if we go above it. */ 870 warn_after_architecture = max_architecture; 871 872 /* Find the highest architecture level that doesn't conflict with 873 the requested one. */ 874 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 875 max_architecture > warn_after_architecture; 876 --max_architecture) 877 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 878 warn_after_architecture)) 879 break; 880 } 881} 882 883/* Called after all assembly has been done. */ 884 885void 886sparc_md_end () 887{ 888 unsigned long mach = bfd_mach_sparc; 889 890 if (sparc_arch_size == 64) 891 switch (current_architecture) 892 { 893 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 894 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 895 default: mach = bfd_mach_sparc_v9; break; 896 } 897 else 898 switch (current_architecture) 899 { 900 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 901 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 902 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 903 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 904 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 905 be but for now it is (since that's the way it's always been 906 treated). */ 907 default: break; 908 } 909 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 910} 911 912/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 913 914static INLINE int 915in_signed_range (val, max) 916 bfd_signed_vma val, max; 917{ 918 if (max <= 0) 919 abort (); 920 /* Sign-extend the value from the architecture word size, so that 921 0xffffffff is always considered -1 on sparc32. */ 922 if (sparc_arch_size == 32) 923 { 924 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 925 val = ((val & U0xffffffff) ^ sign) - sign; 926 } 927 if (val > max) 928 return 0; 929 if (val < ~max) 930 return 0; 931 return 1; 932} 933 934/* Return non-zero if VAL is in the range 0 to MAX. */ 935 936static INLINE int 937in_unsigned_range (val, max) 938 bfd_vma val, max; 939{ 940 if (val > max) 941 return 0; 942 return 1; 943} 944 945/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 946 (e.g. -15 to +31). */ 947 948static INLINE int 949in_bitfield_range (val, max) 950 bfd_signed_vma val, max; 951{ 952 if (max <= 0) 953 abort (); 954 if (val > max) 955 return 0; 956 if (val < ~(max >> 1)) 957 return 0; 958 return 1; 959} 960 961static int 962sparc_ffs (mask) 963 unsigned int mask; 964{ 965 int i; 966 967 if (mask == 0) 968 return -1; 969 970 for (i = 0; (mask & 1) == 0; ++i) 971 mask >>= 1; 972 return i; 973} 974 975/* Implement big shift right. */ 976static bfd_vma 977BSR (val, amount) 978 bfd_vma val; 979 int amount; 980{ 981 if (sizeof (bfd_vma) <= 4 && amount >= 32) 982 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 983 return val >> amount; 984} 985 986/* For communication between sparc_ip and get_expression. */ 987static char *expr_end; 988 989/* Values for `special_case'. 990 Instructions that require wierd handling because they're longer than 991 4 bytes. */ 992#define SPECIAL_CASE_NONE 0 993#define SPECIAL_CASE_SET 1 994#define SPECIAL_CASE_SETSW 2 995#define SPECIAL_CASE_SETX 3 996/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 997#define SPECIAL_CASE_FDIV 4 998 999/* Bit masks of various insns. */ 1000#define NOP_INSN 0x01000000 1001#define OR_INSN 0x80100000 1002#define XOR_INSN 0x80180000 1003#define FMOVS_INSN 0x81A00020 1004#define SETHI_INSN 0x01000000 1005#define SLLX_INSN 0x81281000 1006#define SRA_INSN 0x81380000 1007 1008/* The last instruction to be assembled. */ 1009static const struct sparc_opcode *last_insn; 1010/* The assembled opcode of `last_insn'. */ 1011static unsigned long last_opcode; 1012 1013/* Handle the set and setuw synthetic instructions. */ 1014 1015static void 1016synthetize_setuw (insn) 1017 const struct sparc_opcode *insn; 1018{ 1019 int need_hi22_p = 0; 1020 int rd = (the_insn.opcode & RD (~0)) >> 25; 1021 1022 if (the_insn.exp.X_op == O_constant) 1023 { 1024 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1025 { 1026 if (sizeof (offsetT) > 4 1027 && (the_insn.exp.X_add_number < 0 1028 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1029 as_warn (_("set: number not in 0..4294967295 range")); 1030 } 1031 else 1032 { 1033 if (sizeof (offsetT) > 4 1034 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1035 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1036 as_warn (_("set: number not in -2147483648..4294967295 range")); 1037 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1038 } 1039 } 1040 1041 /* See if operand is absolute and small; skip sethi if so. */ 1042 if (the_insn.exp.X_op != O_constant 1043 || the_insn.exp.X_add_number >= (1 << 12) 1044 || the_insn.exp.X_add_number < -(1 << 12)) 1045 { 1046 the_insn.opcode = (SETHI_INSN | RD (rd) 1047 | ((the_insn.exp.X_add_number >> 10) 1048 & (the_insn.exp.X_op == O_constant 1049 ? 0x3fffff : 0))); 1050 the_insn.reloc = (the_insn.exp.X_op != O_constant 1051 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1052 output_insn (insn, &the_insn); 1053 need_hi22_p = 1; 1054 } 1055 1056 /* See if operand has no low-order bits; skip OR if so. */ 1057 if (the_insn.exp.X_op != O_constant 1058 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1059 || ! need_hi22_p) 1060 { 1061 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1062 | RD (rd) | IMMED 1063 | (the_insn.exp.X_add_number 1064 & (the_insn.exp.X_op != O_constant 1065 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1066 the_insn.reloc = (the_insn.exp.X_op != O_constant 1067 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1068 output_insn (insn, &the_insn); 1069 } 1070} 1071 1072/* Handle the setsw synthetic instruction. */ 1073 1074static void 1075synthetize_setsw (insn) 1076 const struct sparc_opcode *insn; 1077{ 1078 int low32, rd, opc; 1079 1080 rd = (the_insn.opcode & RD (~0)) >> 25; 1081 1082 if (the_insn.exp.X_op != O_constant) 1083 { 1084 synthetize_setuw (insn); 1085 1086 /* Need to sign extend it. */ 1087 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1088 the_insn.reloc = BFD_RELOC_NONE; 1089 output_insn (insn, &the_insn); 1090 return; 1091 } 1092 1093 if (sizeof (offsetT) > 4 1094 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1095 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1096 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1097 1098 low32 = the_insn.exp.X_add_number; 1099 1100 if (low32 >= 0) 1101 { 1102 synthetize_setuw (insn); 1103 return; 1104 } 1105 1106 opc = OR_INSN; 1107 1108 the_insn.reloc = BFD_RELOC_NONE; 1109 /* See if operand is absolute and small; skip sethi if so. */ 1110 if (low32 < -(1 << 12)) 1111 { 1112 the_insn.opcode = (SETHI_INSN | RD (rd) 1113 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1114 output_insn (insn, &the_insn); 1115 low32 = 0x1c00 | (low32 & 0x3ff); 1116 opc = RS1 (rd) | XOR_INSN; 1117 } 1118 1119 the_insn.opcode = (opc | RD (rd) | IMMED 1120 | (low32 & 0x1fff)); 1121 output_insn (insn, &the_insn); 1122} 1123 1124/* Handle the setsw synthetic instruction. */ 1125 1126static void 1127synthetize_setx (insn) 1128 const struct sparc_opcode *insn; 1129{ 1130 int upper32, lower32; 1131 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1132 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1133 int upper_dstreg; 1134 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1135 int need_xor10_p = 0; 1136 1137#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1138 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1139 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1140#undef SIGNEXT32 1141 1142 upper_dstreg = tmpreg; 1143 /* The tmp reg should not be the dst reg. */ 1144 if (tmpreg == dstreg) 1145 as_warn (_("setx: temporary register same as destination register")); 1146 1147 /* ??? Obviously there are other optimizations we can do 1148 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1149 doing some of these. Later. If you do change things, try to 1150 change all of this to be table driven as well. */ 1151 /* What to output depends on the number if it's constant. 1152 Compute that first, then output what we've decided upon. */ 1153 if (the_insn.exp.X_op != O_constant) 1154 { 1155 if (sparc_arch_size == 32) 1156 { 1157 /* When arch size is 32, we want setx to be equivalent 1158 to setuw for anything but constants. */ 1159 the_insn.exp.X_add_number &= 0xffffffff; 1160 synthetize_setuw (insn); 1161 return; 1162 } 1163 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1164 lower32 = 0; 1165 upper32 = 0; 1166 } 1167 else 1168 { 1169 /* Reset X_add_number, we've extracted it as upper32/lower32. 1170 Otherwise fixup_segment will complain about not being able to 1171 write an 8 byte number in a 4 byte field. */ 1172 the_insn.exp.X_add_number = 0; 1173 1174 /* Only need hh22 if `or' insn can't handle constant. */ 1175 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1176 need_hh22_p = 1; 1177 1178 /* Does bottom part (after sethi) have bits? */ 1179 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1180 /* No hh22, but does upper32 still have bits we can't set 1181 from lower32? */ 1182 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1183 need_hm10_p = 1; 1184 1185 /* If the lower half is all zero, we build the upper half directly 1186 into the dst reg. */ 1187 if (lower32 != 0 1188 /* Need lower half if number is zero or 0xffffffff00000000. */ 1189 || (! need_hh22_p && ! need_hm10_p)) 1190 { 1191 /* No need for sethi if `or' insn can handle constant. */ 1192 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1193 /* Note that we can't use a negative constant in the `or' 1194 insn unless the upper 32 bits are all ones. */ 1195 || (lower32 < 0 && upper32 != -1) 1196 || (lower32 >= 0 && upper32 == -1)) 1197 need_hi22_p = 1; 1198 1199 if (need_hi22_p && upper32 == -1) 1200 need_xor10_p = 1; 1201 1202 /* Does bottom part (after sethi) have bits? */ 1203 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1204 /* No sethi. */ 1205 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1206 /* Need `or' if we didn't set anything else. */ 1207 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1208 need_lo10_p = 1; 1209 } 1210 else 1211 /* Output directly to dst reg if lower 32 bits are all zero. */ 1212 upper_dstreg = dstreg; 1213 } 1214 1215 if (!upper_dstreg && dstreg) 1216 as_warn (_("setx: illegal temporary register g0")); 1217 1218 if (need_hh22_p) 1219 { 1220 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1221 | ((upper32 >> 10) & 0x3fffff)); 1222 the_insn.reloc = (the_insn.exp.X_op != O_constant 1223 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1224 output_insn (insn, &the_insn); 1225 } 1226 1227 if (need_hi22_p) 1228 { 1229 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1230 | (((need_xor10_p ? ~lower32 : lower32) 1231 >> 10) & 0x3fffff)); 1232 the_insn.reloc = (the_insn.exp.X_op != O_constant 1233 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1234 output_insn (insn, &the_insn); 1235 } 1236 1237 if (need_hm10_p) 1238 { 1239 the_insn.opcode = (OR_INSN 1240 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1241 | RD (upper_dstreg) 1242 | IMMED 1243 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1244 the_insn.reloc = (the_insn.exp.X_op != O_constant 1245 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1246 output_insn (insn, &the_insn); 1247 } 1248 1249 if (need_lo10_p) 1250 { 1251 /* FIXME: One nice optimization to do here is to OR the low part 1252 with the highpart if hi22 isn't needed and the low part is 1253 positive. */ 1254 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1255 | RD (dstreg) 1256 | IMMED 1257 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1258 the_insn.reloc = (the_insn.exp.X_op != O_constant 1259 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1260 output_insn (insn, &the_insn); 1261 } 1262 1263 /* If we needed to build the upper part, shift it into place. */ 1264 if (need_hh22_p || need_hm10_p) 1265 { 1266 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1267 | IMMED | 32); 1268 the_insn.reloc = BFD_RELOC_NONE; 1269 output_insn (insn, &the_insn); 1270 } 1271 1272 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1273 if (need_xor10_p) 1274 { 1275 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1276 | 0x1c00 | (lower32 & 0x3ff)); 1277 the_insn.reloc = BFD_RELOC_NONE; 1278 output_insn (insn, &the_insn); 1279 } 1280 1281 /* If we needed to build both upper and lower parts, OR them together. */ 1282 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1283 { 1284 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1285 | RD (dstreg)); 1286 the_insn.reloc = BFD_RELOC_NONE; 1287 output_insn (insn, &the_insn); 1288 } 1289} 1290 1291/* Main entry point to assemble one instruction. */ 1292 1293void 1294md_assemble (str) 1295 char *str; 1296{ 1297 const struct sparc_opcode *insn; 1298 int special_case; 1299 1300 know (str); 1301 special_case = sparc_ip (str, &insn); 1302 1303 /* We warn about attempts to put a floating point branch in a delay slot, 1304 unless the delay slot has been annulled. */ 1305 if (insn != NULL 1306 && last_insn != NULL 1307 && (insn->flags & F_FBR) != 0 1308 && (last_insn->flags & F_DELAYED) != 0 1309 /* ??? This test isn't completely accurate. We assume anything with 1310 F_{UNBR,CONDBR,FBR} set is annullable. */ 1311 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1312 || (last_opcode & ANNUL) == 0)) 1313 as_warn (_("FP branch in delay slot")); 1314 1315 /* SPARC before v9 requires a nop instruction between a floating 1316 point instruction and a floating point branch. We insert one 1317 automatically, with a warning. */ 1318 if (max_architecture < SPARC_OPCODE_ARCH_V9 1319 && insn != NULL 1320 && last_insn != NULL 1321 && (insn->flags & F_FBR) != 0 1322 && (last_insn->flags & F_FLOAT) != 0) 1323 { 1324 struct sparc_it nop_insn; 1325 1326 nop_insn.opcode = NOP_INSN; 1327 nop_insn.reloc = BFD_RELOC_NONE; 1328 output_insn (insn, &nop_insn); 1329 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1330 } 1331 1332 switch (special_case) 1333 { 1334 case SPECIAL_CASE_NONE: 1335 /* Normal insn. */ 1336 output_insn (insn, &the_insn); 1337 break; 1338 1339 case SPECIAL_CASE_SETSW: 1340 synthetize_setsw (insn); 1341 break; 1342 1343 case SPECIAL_CASE_SET: 1344 synthetize_setuw (insn); 1345 break; 1346 1347 case SPECIAL_CASE_SETX: 1348 synthetize_setx (insn); 1349 break; 1350 1351 case SPECIAL_CASE_FDIV: 1352 { 1353 int rd = (the_insn.opcode >> 25) & 0x1f; 1354 1355 output_insn (insn, &the_insn); 1356 1357 /* According to information leaked from Sun, the "fdiv" instructions 1358 on early SPARC machines would produce incorrect results sometimes. 1359 The workaround is to add an fmovs of the destination register to 1360 itself just after the instruction. This was true on machines 1361 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1362 assert (the_insn.reloc == BFD_RELOC_NONE); 1363 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1364 output_insn (insn, &the_insn); 1365 return; 1366 } 1367 1368 default: 1369 as_fatal (_("failed special case insn sanity check")); 1370 } 1371} 1372 1373/* Subroutine of md_assemble to do the actual parsing. */ 1374 1375static int 1376sparc_ip (str, pinsn) 1377 char *str; 1378 const struct sparc_opcode **pinsn; 1379{ 1380 char *error_message = ""; 1381 char *s; 1382 const char *args; 1383 char c; 1384 const struct sparc_opcode *insn; 1385 char *argsStart; 1386 unsigned long opcode; 1387 unsigned int mask = 0; 1388 int match = 0; 1389 int comma = 0; 1390 int v9_arg_p; 1391 int special_case = SPECIAL_CASE_NONE; 1392 1393 s = str; 1394 if (ISLOWER (*s)) 1395 { 1396 do 1397 ++s; 1398 while (ISLOWER (*s) || ISDIGIT (*s)); 1399 } 1400 1401 switch (*s) 1402 { 1403 case '\0': 1404 break; 1405 1406 case ',': 1407 comma = 1; 1408 /* Fall through. */ 1409 1410 case ' ': 1411 *s++ = '\0'; 1412 break; 1413 1414 default: 1415 as_fatal (_("Unknown opcode: `%s'"), str); 1416 } 1417 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1418 *pinsn = insn; 1419 if (insn == NULL) 1420 { 1421 as_bad (_("Unknown opcode: `%s'"), str); 1422 return special_case; 1423 } 1424 if (comma) 1425 { 1426 *--s = ','; 1427 } 1428 1429 argsStart = s; 1430 for (;;) 1431 { 1432 opcode = insn->match; 1433 memset (&the_insn, '\0', sizeof (the_insn)); 1434 the_insn.reloc = BFD_RELOC_NONE; 1435 v9_arg_p = 0; 1436 1437 /* Build the opcode, checking as we go to make sure that the 1438 operands match. */ 1439 for (args = insn->args;; ++args) 1440 { 1441 switch (*args) 1442 { 1443 case 'K': 1444 { 1445 int kmask = 0; 1446 1447 /* Parse a series of masks. */ 1448 if (*s == '#') 1449 { 1450 while (*s == '#') 1451 { 1452 int mask; 1453 1454 if (! parse_keyword_arg (sparc_encode_membar, &s, 1455 &mask)) 1456 { 1457 error_message = _(": invalid membar mask name"); 1458 goto error; 1459 } 1460 kmask |= mask; 1461 while (*s == ' ') 1462 ++s; 1463 if (*s == '|' || *s == '+') 1464 ++s; 1465 while (*s == ' ') 1466 ++s; 1467 } 1468 } 1469 else 1470 { 1471 if (! parse_const_expr_arg (&s, &kmask)) 1472 { 1473 error_message = _(": invalid membar mask expression"); 1474 goto error; 1475 } 1476 if (kmask < 0 || kmask > 127) 1477 { 1478 error_message = _(": invalid membar mask number"); 1479 goto error; 1480 } 1481 } 1482 1483 opcode |= MEMBAR (kmask); 1484 continue; 1485 } 1486 1487 case '3': 1488 { 1489 int smask = 0; 1490 1491 if (! parse_const_expr_arg (&s, &smask)) 1492 { 1493 error_message = _(": invalid siam mode expression"); 1494 goto error; 1495 } 1496 if (smask < 0 || smask > 7) 1497 { 1498 error_message = _(": invalid siam mode number"); 1499 goto error; 1500 } 1501 opcode |= smask; 1502 continue; 1503 } 1504 1505 case '*': 1506 { 1507 int fcn = 0; 1508 1509 /* Parse a prefetch function. */ 1510 if (*s == '#') 1511 { 1512 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1513 { 1514 error_message = _(": invalid prefetch function name"); 1515 goto error; 1516 } 1517 } 1518 else 1519 { 1520 if (! parse_const_expr_arg (&s, &fcn)) 1521 { 1522 error_message = _(": invalid prefetch function expression"); 1523 goto error; 1524 } 1525 if (fcn < 0 || fcn > 31) 1526 { 1527 error_message = _(": invalid prefetch function number"); 1528 goto error; 1529 } 1530 } 1531 opcode |= RD (fcn); 1532 continue; 1533 } 1534 1535 case '!': 1536 case '?': 1537 /* Parse a sparc64 privileged register. */ 1538 if (*s == '%') 1539 { 1540 struct priv_reg_entry *p = priv_reg_table; 1541 unsigned int len = 9999999; /* Init to make gcc happy. */ 1542 1543 s += 1; 1544 while (p->name[0] > s[0]) 1545 p++; 1546 while (p->name[0] == s[0]) 1547 { 1548 len = strlen (p->name); 1549 if (strncmp (p->name, s, len) == 0) 1550 break; 1551 p++; 1552 } 1553 if (p->name[0] != s[0]) 1554 { 1555 error_message = _(": unrecognizable privileged register"); 1556 goto error; 1557 } 1558 if (*args == '?') 1559 opcode |= (p->regnum << 14); 1560 else 1561 opcode |= (p->regnum << 25); 1562 s += len; 1563 continue; 1564 } 1565 else 1566 { 1567 error_message = _(": unrecognizable privileged register"); 1568 goto error; 1569 } 1570 1571 case '_': 1572 case '/': 1573 /* Parse a v9a/v9b ancillary state register. */ 1574 if (*s == '%') 1575 { 1576 struct priv_reg_entry *p = v9a_asr_table; 1577 unsigned int len = 9999999; /* Init to make gcc happy. */ 1578 1579 s += 1; 1580 while (p->name[0] > s[0]) 1581 p++; 1582 while (p->name[0] == s[0]) 1583 { 1584 len = strlen (p->name); 1585 if (strncmp (p->name, s, len) == 0) 1586 break; 1587 p++; 1588 } 1589 if (p->name[0] != s[0]) 1590 { 1591 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1592 goto error; 1593 } 1594 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1595 { 1596 error_message = _(": rd on write only ancillary state register"); 1597 goto error; 1598 } 1599 if (p->regnum >= 24 1600 && (insn->architecture 1601 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1602 { 1603 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1604 error_message = _(": unrecognizable v9a ancillary state register"); 1605 goto error; 1606 } 1607 if (*args == '/') 1608 opcode |= (p->regnum << 14); 1609 else 1610 opcode |= (p->regnum << 25); 1611 s += len; 1612 continue; 1613 } 1614 else 1615 { 1616 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1617 goto error; 1618 } 1619 1620 case 'M': 1621 case 'm': 1622 if (strncmp (s, "%asr", 4) == 0) 1623 { 1624 s += 4; 1625 1626 if (ISDIGIT (*s)) 1627 { 1628 long num = 0; 1629 1630 while (ISDIGIT (*s)) 1631 { 1632 num = num * 10 + *s - '0'; 1633 ++s; 1634 } 1635 1636 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1637 { 1638 if (num < 16 || 31 < num) 1639 { 1640 error_message = _(": asr number must be between 16 and 31"); 1641 goto error; 1642 } 1643 } 1644 else 1645 { 1646 if (num < 0 || 31 < num) 1647 { 1648 error_message = _(": asr number must be between 0 and 31"); 1649 goto error; 1650 } 1651 } 1652 1653 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1654 continue; 1655 } 1656 else 1657 { 1658 error_message = _(": expecting %asrN"); 1659 goto error; 1660 } 1661 } /* if %asr */ 1662 break; 1663 1664 case 'I': 1665 the_insn.reloc = BFD_RELOC_SPARC_11; 1666 goto immediate; 1667 1668 case 'j': 1669 the_insn.reloc = BFD_RELOC_SPARC_10; 1670 goto immediate; 1671 1672 case 'X': 1673 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1674 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1675 the_insn.reloc = BFD_RELOC_SPARC_5; 1676 else 1677 the_insn.reloc = BFD_RELOC_SPARC13; 1678 /* These fields are unsigned, but for upward compatibility, 1679 allow negative values as well. */ 1680 goto immediate; 1681 1682 case 'Y': 1683 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1684 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1685 the_insn.reloc = BFD_RELOC_SPARC_6; 1686 else 1687 the_insn.reloc = BFD_RELOC_SPARC13; 1688 /* These fields are unsigned, but for upward compatibility, 1689 allow negative values as well. */ 1690 goto immediate; 1691 1692 case 'k': 1693 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1694 the_insn.pcrel = 1; 1695 goto immediate; 1696 1697 case 'G': 1698 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1699 the_insn.pcrel = 1; 1700 goto immediate; 1701 1702 case 'N': 1703 if (*s == 'p' && s[1] == 'n') 1704 { 1705 s += 2; 1706 continue; 1707 } 1708 break; 1709 1710 case 'T': 1711 if (*s == 'p' && s[1] == 't') 1712 { 1713 s += 2; 1714 continue; 1715 } 1716 break; 1717 1718 case 'z': 1719 if (*s == ' ') 1720 { 1721 ++s; 1722 } 1723 if (strncmp (s, "%icc", 4) == 0) 1724 { 1725 s += 4; 1726 continue; 1727 } 1728 break; 1729 1730 case 'Z': 1731 if (*s == ' ') 1732 { 1733 ++s; 1734 } 1735 if (strncmp (s, "%xcc", 4) == 0) 1736 { 1737 s += 4; 1738 continue; 1739 } 1740 break; 1741 1742 case '6': 1743 if (*s == ' ') 1744 { 1745 ++s; 1746 } 1747 if (strncmp (s, "%fcc0", 5) == 0) 1748 { 1749 s += 5; 1750 continue; 1751 } 1752 break; 1753 1754 case '7': 1755 if (*s == ' ') 1756 { 1757 ++s; 1758 } 1759 if (strncmp (s, "%fcc1", 5) == 0) 1760 { 1761 s += 5; 1762 continue; 1763 } 1764 break; 1765 1766 case '8': 1767 if (*s == ' ') 1768 { 1769 ++s; 1770 } 1771 if (strncmp (s, "%fcc2", 5) == 0) 1772 { 1773 s += 5; 1774 continue; 1775 } 1776 break; 1777 1778 case '9': 1779 if (*s == ' ') 1780 { 1781 ++s; 1782 } 1783 if (strncmp (s, "%fcc3", 5) == 0) 1784 { 1785 s += 5; 1786 continue; 1787 } 1788 break; 1789 1790 case 'P': 1791 if (strncmp (s, "%pc", 3) == 0) 1792 { 1793 s += 3; 1794 continue; 1795 } 1796 break; 1797 1798 case 'W': 1799 if (strncmp (s, "%tick", 5) == 0) 1800 { 1801 s += 5; 1802 continue; 1803 } 1804 break; 1805 1806 case '\0': /* End of args. */ 1807 if (*s == '\0') 1808 { 1809 match = 1; 1810 } 1811 break; 1812 1813 case '+': 1814 if (*s == '+') 1815 { 1816 ++s; 1817 continue; 1818 } 1819 if (*s == '-') 1820 { 1821 continue; 1822 } 1823 break; 1824 1825 case '[': /* These must match exactly. */ 1826 case ']': 1827 case ',': 1828 case ' ': 1829 if (*s++ == *args) 1830 continue; 1831 break; 1832 1833 case '#': /* Must be at least one digit. */ 1834 if (ISDIGIT (*s++)) 1835 { 1836 while (ISDIGIT (*s)) 1837 { 1838 ++s; 1839 } 1840 continue; 1841 } 1842 break; 1843 1844 case 'C': /* Coprocessor state register. */ 1845 if (strncmp (s, "%csr", 4) == 0) 1846 { 1847 s += 4; 1848 continue; 1849 } 1850 break; 1851 1852 case 'b': /* Next operand is a coprocessor register. */ 1853 case 'c': 1854 case 'D': 1855 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 1856 { 1857 mask = *s++; 1858 if (ISDIGIT (*s)) 1859 { 1860 mask = 10 * (mask - '0') + (*s++ - '0'); 1861 if (mask >= 32) 1862 { 1863 break; 1864 } 1865 } 1866 else 1867 { 1868 mask -= '0'; 1869 } 1870 switch (*args) 1871 { 1872 1873 case 'b': 1874 opcode |= mask << 14; 1875 continue; 1876 1877 case 'c': 1878 opcode |= mask; 1879 continue; 1880 1881 case 'D': 1882 opcode |= mask << 25; 1883 continue; 1884 } 1885 } 1886 break; 1887 1888 case 'r': /* next operand must be a register */ 1889 case 'O': 1890 case '1': 1891 case '2': 1892 case 'd': 1893 if (*s++ == '%') 1894 { 1895 switch (c = *s++) 1896 { 1897 1898 case 'f': /* frame pointer */ 1899 if (*s++ == 'p') 1900 { 1901 mask = 0x1e; 1902 break; 1903 } 1904 goto error; 1905 1906 case 'g': /* global register */ 1907 c = *s++; 1908 if (isoctal (c)) 1909 { 1910 mask = c - '0'; 1911 break; 1912 } 1913 goto error; 1914 1915 case 'i': /* in register */ 1916 c = *s++; 1917 if (isoctal (c)) 1918 { 1919 mask = c - '0' + 24; 1920 break; 1921 } 1922 goto error; 1923 1924 case 'l': /* local register */ 1925 c = *s++; 1926 if (isoctal (c)) 1927 { 1928 mask = (c - '0' + 16); 1929 break; 1930 } 1931 goto error; 1932 1933 case 'o': /* out register */ 1934 c = *s++; 1935 if (isoctal (c)) 1936 { 1937 mask = (c - '0' + 8); 1938 break; 1939 } 1940 goto error; 1941 1942 case 's': /* stack pointer */ 1943 if (*s++ == 'p') 1944 { 1945 mask = 0xe; 1946 break; 1947 } 1948 goto error; 1949 1950 case 'r': /* any register */ 1951 if (!ISDIGIT ((c = *s++))) 1952 { 1953 goto error; 1954 } 1955 /* FALLTHROUGH */ 1956 case '0': 1957 case '1': 1958 case '2': 1959 case '3': 1960 case '4': 1961 case '5': 1962 case '6': 1963 case '7': 1964 case '8': 1965 case '9': 1966 if (ISDIGIT (*s)) 1967 { 1968 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 1969 { 1970 goto error; 1971 } 1972 } 1973 else 1974 { 1975 c -= '0'; 1976 } 1977 mask = c; 1978 break; 1979 1980 default: 1981 goto error; 1982 } 1983 1984 if ((mask & ~1) == 2 && sparc_arch_size == 64 1985 && no_undeclared_regs && ! globals[mask]) 1986 as_bad (_("detected global register use not covered by .register pseudo-op")); 1987 1988 /* Got the register, now figure out where 1989 it goes in the opcode. */ 1990 switch (*args) 1991 { 1992 case '1': 1993 opcode |= mask << 14; 1994 continue; 1995 1996 case '2': 1997 opcode |= mask; 1998 continue; 1999 2000 case 'd': 2001 opcode |= mask << 25; 2002 continue; 2003 2004 case 'r': 2005 opcode |= (mask << 25) | (mask << 14); 2006 continue; 2007 2008 case 'O': 2009 opcode |= (mask << 25) | (mask << 0); 2010 continue; 2011 } 2012 } 2013 break; 2014 2015 case 'e': /* next operand is a floating point register */ 2016 case 'v': 2017 case 'V': 2018 2019 case 'f': 2020 case 'B': 2021 case 'R': 2022 2023 case 'g': 2024 case 'H': 2025 case 'J': 2026 { 2027 char format; 2028 2029 if (*s++ == '%' 2030 && ((format = *s) == 'f') 2031 && ISDIGIT (*++s)) 2032 { 2033 for (mask = 0; ISDIGIT (*s); ++s) 2034 { 2035 mask = 10 * mask + (*s - '0'); 2036 } /* read the number */ 2037 2038 if ((*args == 'v' 2039 || *args == 'B' 2040 || *args == 'H') 2041 && (mask & 1)) 2042 { 2043 break; 2044 } /* register must be even numbered */ 2045 2046 if ((*args == 'V' 2047 || *args == 'R' 2048 || *args == 'J') 2049 && (mask & 3)) 2050 { 2051 break; 2052 } /* register must be multiple of 4 */ 2053 2054 if (mask >= 64) 2055 { 2056 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2057 error_message = _(": There are only 64 f registers; [0-63]"); 2058 else 2059 error_message = _(": There are only 32 f registers; [0-31]"); 2060 goto error; 2061 } /* on error */ 2062 else if (mask >= 32) 2063 { 2064 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2065 { 2066 v9_arg_p = 1; 2067 mask -= 31; /* wrap high bit */ 2068 } 2069 else 2070 { 2071 error_message = _(": There are only 32 f registers; [0-31]"); 2072 goto error; 2073 } 2074 } 2075 } 2076 else 2077 { 2078 break; 2079 } /* if not an 'f' register. */ 2080 2081 switch (*args) 2082 { 2083 case 'v': 2084 case 'V': 2085 case 'e': 2086 opcode |= RS1 (mask); 2087 continue; 2088 2089 case 'f': 2090 case 'B': 2091 case 'R': 2092 opcode |= RS2 (mask); 2093 continue; 2094 2095 case 'g': 2096 case 'H': 2097 case 'J': 2098 opcode |= RD (mask); 2099 continue; 2100 } /* Pack it in. */ 2101 2102 know (0); 2103 break; 2104 } /* float arg */ 2105 2106 case 'F': 2107 if (strncmp (s, "%fsr", 4) == 0) 2108 { 2109 s += 4; 2110 continue; 2111 } 2112 break; 2113 2114 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2115 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2116 goto immediate; 2117 2118 case 'l': /* 22 bit PC relative immediate */ 2119 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2120 the_insn.pcrel = 1; 2121 goto immediate; 2122 2123 case 'L': /* 30 bit immediate */ 2124 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2125 the_insn.pcrel = 1; 2126 goto immediate; 2127 2128 case 'h': 2129 case 'n': /* 22 bit immediate */ 2130 the_insn.reloc = BFD_RELOC_SPARC22; 2131 goto immediate; 2132 2133 case 'i': /* 13 bit immediate */ 2134 the_insn.reloc = BFD_RELOC_SPARC13; 2135 2136 /* fallthrough */ 2137 2138 immediate: 2139 if (*s == ' ') 2140 s++; 2141 2142 { 2143 char *s1; 2144 char *op_arg = NULL; 2145 expressionS op_exp; 2146 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2147 2148 /* Check for %hi, etc. */ 2149 if (*s == '%') 2150 { 2151 static const struct ops { 2152 /* The name as it appears in assembler. */ 2153 char *name; 2154 /* strlen (name), precomputed for speed */ 2155 int len; 2156 /* The reloc this pseudo-op translates to. */ 2157 int reloc; 2158 /* Non-zero if for v9 only. */ 2159 int v9_p; 2160 /* Non-zero if can be used in pc-relative contexts. */ 2161 int pcrel_p;/*FIXME:wip*/ 2162 } ops[] = { 2163 /* hix/lox must appear before hi/lo so %hix won't be 2164 mistaken for %hi. */ 2165 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2166 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2167 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2168 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2169 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2170 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2171 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2172 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2173 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2174 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2175 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2176 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2177 { NULL, 0, 0, 0, 0 } 2178 }; 2179 const struct ops *o; 2180 2181 for (o = ops; o->name; o++) 2182 if (strncmp (s + 1, o->name, o->len) == 0) 2183 break; 2184 if (o->name == NULL) 2185 break; 2186 2187 if (s[o->len + 1] != '(') 2188 { 2189 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2190 return special_case; 2191 } 2192 2193 op_arg = o->name; 2194 the_insn.reloc = o->reloc; 2195 s += o->len + 2; 2196 v9_arg_p = o->v9_p; 2197 } 2198 2199 /* Note that if the get_expression() fails, we will still 2200 have created U entries in the symbol table for the 2201 'symbols' in the input string. Try not to create U 2202 symbols for registers, etc. */ 2203 2204 /* This stuff checks to see if the expression ends in 2205 +%reg. If it does, it removes the register from 2206 the expression, and re-sets 's' to point to the 2207 right place. */ 2208 2209 if (op_arg) 2210 { 2211 int npar = 0; 2212 2213 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2214 if (*s1 == '(') 2215 npar++; 2216 else if (*s1 == ')') 2217 { 2218 if (!npar) 2219 break; 2220 npar--; 2221 } 2222 2223 if (*s1 != ')') 2224 { 2225 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2226 return special_case; 2227 } 2228 2229 *s1 = '\0'; 2230 (void) get_expression (s); 2231 *s1 = ')'; 2232 s = s1 + 1; 2233 if (*s == ',' || *s == ']' || !*s) 2234 continue; 2235 if (*s != '+' && *s != '-') 2236 { 2237 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2238 return special_case; 2239 } 2240 *s1 = '0'; 2241 s = s1; 2242 op_exp = the_insn.exp; 2243 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2244 } 2245 2246 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2247 ; 2248 2249 if (s1 != s && ISDIGIT (s1[-1])) 2250 { 2251 if (s1[-2] == '%' && s1[-3] == '+') 2252 s1 -= 3; 2253 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2254 s1 -= 4; 2255 else 2256 s1 = NULL; 2257 if (s1) 2258 { 2259 *s1 = '\0'; 2260 if (op_arg && s1 == s + 1) 2261 the_insn.exp.X_op = O_absent; 2262 else 2263 (void) get_expression (s); 2264 *s1 = '+'; 2265 if (op_arg) 2266 *s = ')'; 2267 s = s1; 2268 } 2269 } 2270 else 2271 s1 = NULL; 2272 2273 if (!s1) 2274 { 2275 (void) get_expression (s); 2276 if (op_arg) 2277 *s = ')'; 2278 s = expr_end; 2279 } 2280 2281 if (op_arg) 2282 { 2283 the_insn.exp2 = the_insn.exp; 2284 the_insn.exp = op_exp; 2285 if (the_insn.exp2.X_op == O_absent) 2286 the_insn.exp2.X_op = O_illegal; 2287 else if (the_insn.exp.X_op == O_absent) 2288 { 2289 the_insn.exp = the_insn.exp2; 2290 the_insn.exp2.X_op = O_illegal; 2291 } 2292 else if (the_insn.exp.X_op == O_constant) 2293 { 2294 valueT val = the_insn.exp.X_add_number; 2295 switch (the_insn.reloc) 2296 { 2297 default: 2298 break; 2299 2300 case BFD_RELOC_SPARC_HH22: 2301 val = BSR (val, 32); 2302 /* Fall through. */ 2303 2304 case BFD_RELOC_SPARC_LM22: 2305 case BFD_RELOC_HI22: 2306 val = (val >> 10) & 0x3fffff; 2307 break; 2308 2309 case BFD_RELOC_SPARC_HM10: 2310 val = BSR (val, 32); 2311 /* Fall through. */ 2312 2313 case BFD_RELOC_LO10: 2314 val &= 0x3ff; 2315 break; 2316 2317 case BFD_RELOC_SPARC_H44: 2318 val >>= 22; 2319 val &= 0x3fffff; 2320 break; 2321 2322 case BFD_RELOC_SPARC_M44: 2323 val >>= 12; 2324 val &= 0x3ff; 2325 break; 2326 2327 case BFD_RELOC_SPARC_L44: 2328 val &= 0xfff; 2329 break; 2330 2331 case BFD_RELOC_SPARC_HIX22: 2332 val = ~val; 2333 val = (val >> 10) & 0x3fffff; 2334 break; 2335 2336 case BFD_RELOC_SPARC_LOX10: 2337 val = (val & 0x3ff) | 0x1c00; 2338 break; 2339 } 2340 the_insn.exp = the_insn.exp2; 2341 the_insn.exp.X_add_number += val; 2342 the_insn.exp2.X_op = O_illegal; 2343 the_insn.reloc = old_reloc; 2344 } 2345 else if (the_insn.exp2.X_op != O_constant) 2346 { 2347 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2348 return special_case; 2349 } 2350 else 2351 { 2352 if (old_reloc != BFD_RELOC_SPARC13 2353 || the_insn.reloc != BFD_RELOC_LO10 2354 || sparc_arch_size != 64 2355 || sparc_pic_code) 2356 { 2357 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2358 return special_case; 2359 } 2360 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2361 } 2362 } 2363 } 2364 /* Check for constants that don't require emitting a reloc. */ 2365 if (the_insn.exp.X_op == O_constant 2366 && the_insn.exp.X_add_symbol == 0 2367 && the_insn.exp.X_op_symbol == 0) 2368 { 2369 /* For pc-relative call instructions, we reject 2370 constants to get better code. */ 2371 if (the_insn.pcrel 2372 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2373 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2374 { 2375 error_message = _(": PC-relative operand can't be a constant"); 2376 goto error; 2377 } 2378 2379 /* Constants that won't fit are checked in md_apply_fix3 2380 and bfd_install_relocation. 2381 ??? It would be preferable to install the constants 2382 into the insn here and save having to create a fixS 2383 for each one. There already exists code to handle 2384 all the various cases (e.g. in md_apply_fix3 and 2385 bfd_install_relocation) so duplicating all that code 2386 here isn't right. */ 2387 } 2388 2389 continue; 2390 2391 case 'a': 2392 if (*s++ == 'a') 2393 { 2394 opcode |= ANNUL; 2395 continue; 2396 } 2397 break; 2398 2399 case 'A': 2400 { 2401 int asi = 0; 2402 2403 /* Parse an asi. */ 2404 if (*s == '#') 2405 { 2406 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2407 { 2408 error_message = _(": invalid ASI name"); 2409 goto error; 2410 } 2411 } 2412 else 2413 { 2414 if (! parse_const_expr_arg (&s, &asi)) 2415 { 2416 error_message = _(": invalid ASI expression"); 2417 goto error; 2418 } 2419 if (asi < 0 || asi > 255) 2420 { 2421 error_message = _(": invalid ASI number"); 2422 goto error; 2423 } 2424 } 2425 opcode |= ASI (asi); 2426 continue; 2427 } /* Alternate space. */ 2428 2429 case 'p': 2430 if (strncmp (s, "%psr", 4) == 0) 2431 { 2432 s += 4; 2433 continue; 2434 } 2435 break; 2436 2437 case 'q': /* Floating point queue. */ 2438 if (strncmp (s, "%fq", 3) == 0) 2439 { 2440 s += 3; 2441 continue; 2442 } 2443 break; 2444 2445 case 'Q': /* Coprocessor queue. */ 2446 if (strncmp (s, "%cq", 3) == 0) 2447 { 2448 s += 3; 2449 continue; 2450 } 2451 break; 2452 2453 case 'S': 2454 if (strcmp (str, "set") == 0 2455 || strcmp (str, "setuw") == 0) 2456 { 2457 special_case = SPECIAL_CASE_SET; 2458 continue; 2459 } 2460 else if (strcmp (str, "setsw") == 0) 2461 { 2462 special_case = SPECIAL_CASE_SETSW; 2463 continue; 2464 } 2465 else if (strcmp (str, "setx") == 0) 2466 { 2467 special_case = SPECIAL_CASE_SETX; 2468 continue; 2469 } 2470 else if (strncmp (str, "fdiv", 4) == 0) 2471 { 2472 special_case = SPECIAL_CASE_FDIV; 2473 continue; 2474 } 2475 break; 2476 2477 case 'o': 2478 if (strncmp (s, "%asi", 4) != 0) 2479 break; 2480 s += 4; 2481 continue; 2482 2483 case 's': 2484 if (strncmp (s, "%fprs", 5) != 0) 2485 break; 2486 s += 5; 2487 continue; 2488 2489 case 'E': 2490 if (strncmp (s, "%ccr", 4) != 0) 2491 break; 2492 s += 4; 2493 continue; 2494 2495 case 't': 2496 if (strncmp (s, "%tbr", 4) != 0) 2497 break; 2498 s += 4; 2499 continue; 2500 2501 case 'w': 2502 if (strncmp (s, "%wim", 4) != 0) 2503 break; 2504 s += 4; 2505 continue; 2506 2507 case 'x': 2508 { 2509 char *push = input_line_pointer; 2510 expressionS e; 2511 2512 input_line_pointer = s; 2513 expression (&e); 2514 if (e.X_op == O_constant) 2515 { 2516 int n = e.X_add_number; 2517 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2518 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2519 else 2520 opcode |= e.X_add_number << 5; 2521 } 2522 else 2523 as_bad (_("non-immediate OPF operand, ignored")); 2524 s = input_line_pointer; 2525 input_line_pointer = push; 2526 continue; 2527 } 2528 2529 case 'y': 2530 if (strncmp (s, "%y", 2) != 0) 2531 break; 2532 s += 2; 2533 continue; 2534 2535 case 'u': 2536 case 'U': 2537 { 2538 /* Parse a sparclet cpreg. */ 2539 int cpreg; 2540 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2541 { 2542 error_message = _(": invalid cpreg name"); 2543 goto error; 2544 } 2545 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2546 continue; 2547 } 2548 2549 default: 2550 as_fatal (_("failed sanity check.")); 2551 } /* switch on arg code. */ 2552 2553 /* Break out of for() loop. */ 2554 break; 2555 } /* For each arg that we expect. */ 2556 2557 error: 2558 if (match == 0) 2559 { 2560 /* Args don't match. */ 2561 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2562 && (insn->name == insn[1].name 2563 || !strcmp (insn->name, insn[1].name))) 2564 { 2565 ++insn; 2566 s = argsStart; 2567 continue; 2568 } 2569 else 2570 { 2571 as_bad (_("Illegal operands%s"), error_message); 2572 return special_case; 2573 } 2574 } 2575 else 2576 { 2577 /* We have a match. Now see if the architecture is OK. */ 2578 int needed_arch_mask = insn->architecture; 2579 2580 if (v9_arg_p) 2581 { 2582 needed_arch_mask &= 2583 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2584 if (! needed_arch_mask) 2585 needed_arch_mask = 2586 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2587 } 2588 2589 if (needed_arch_mask 2590 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2591 /* OK. */ 2592 ; 2593 /* Can we bump up the architecture? */ 2594 else if (needed_arch_mask 2595 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2596 { 2597 enum sparc_opcode_arch_val needed_architecture = 2598 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2599 & needed_arch_mask); 2600 2601 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2602 if (warn_on_bump 2603 && needed_architecture > warn_after_architecture) 2604 { 2605 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2606 sparc_opcode_archs[current_architecture].name, 2607 sparc_opcode_archs[needed_architecture].name, 2608 str); 2609 warn_after_architecture = needed_architecture; 2610 } 2611 current_architecture = needed_architecture; 2612 } 2613 /* Conflict. */ 2614 /* ??? This seems to be a bit fragile. What if the next entry in 2615 the opcode table is the one we want and it is supported? 2616 It is possible to arrange the table today so that this can't 2617 happen but what about tomorrow? */ 2618 else 2619 { 2620 int arch, printed_one_p = 0; 2621 char *p; 2622 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2623 2624 /* Create a list of the architectures that support the insn. */ 2625 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2626 p = required_archs; 2627 arch = sparc_ffs (needed_arch_mask); 2628 while ((1 << arch) <= needed_arch_mask) 2629 { 2630 if ((1 << arch) & needed_arch_mask) 2631 { 2632 if (printed_one_p) 2633 *p++ = '|'; 2634 strcpy (p, sparc_opcode_archs[arch].name); 2635 p += strlen (p); 2636 printed_one_p = 1; 2637 } 2638 ++arch; 2639 } 2640 2641 as_bad (_("Architecture mismatch on \"%s\"."), str); 2642 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2643 required_archs, 2644 sparc_opcode_archs[max_architecture].name); 2645 return special_case; 2646 } 2647 } /* If no match. */ 2648 2649 break; 2650 } /* Forever looking for a match. */ 2651 2652 the_insn.opcode = opcode; 2653 return special_case; 2654} 2655 2656/* Parse an argument that can be expressed as a keyword. 2657 (eg: #StoreStore or %ccfr). 2658 The result is a boolean indicating success. 2659 If successful, INPUT_POINTER is updated. */ 2660 2661static int 2662parse_keyword_arg (lookup_fn, input_pointerP, valueP) 2663 int (*lookup_fn) PARAMS ((const char *)); 2664 char **input_pointerP; 2665 int *valueP; 2666{ 2667 int value; 2668 char c, *p, *q; 2669 2670 p = *input_pointerP; 2671 for (q = p + (*p == '#' || *p == '%'); 2672 ISALNUM (*q) || *q == '_'; 2673 ++q) 2674 continue; 2675 c = *q; 2676 *q = 0; 2677 value = (*lookup_fn) (p); 2678 *q = c; 2679 if (value == -1) 2680 return 0; 2681 *valueP = value; 2682 *input_pointerP = q; 2683 return 1; 2684} 2685 2686/* Parse an argument that is a constant expression. 2687 The result is a boolean indicating success. */ 2688 2689static int 2690parse_const_expr_arg (input_pointerP, valueP) 2691 char **input_pointerP; 2692 int *valueP; 2693{ 2694 char *save = input_line_pointer; 2695 expressionS exp; 2696 2697 input_line_pointer = *input_pointerP; 2698 /* The next expression may be something other than a constant 2699 (say if we're not processing the right variant of the insn). 2700 Don't call expression unless we're sure it will succeed as it will 2701 signal an error (which we want to defer until later). */ 2702 /* FIXME: It might be better to define md_operand and have it recognize 2703 things like %asi, etc. but continuing that route through to the end 2704 is a lot of work. */ 2705 if (*input_line_pointer == '%') 2706 { 2707 input_line_pointer = save; 2708 return 0; 2709 } 2710 expression (&exp); 2711 *input_pointerP = input_line_pointer; 2712 input_line_pointer = save; 2713 if (exp.X_op != O_constant) 2714 return 0; 2715 *valueP = exp.X_add_number; 2716 return 1; 2717} 2718 2719/* Subroutine of sparc_ip to parse an expression. */ 2720 2721static int 2722get_expression (str) 2723 char *str; 2724{ 2725 char *save_in; 2726 segT seg; 2727 2728 save_in = input_line_pointer; 2729 input_line_pointer = str; 2730 seg = expression (&the_insn.exp); 2731 if (seg != absolute_section 2732 && seg != text_section 2733 && seg != data_section 2734 && seg != bss_section 2735 && seg != undefined_section) 2736 { 2737 the_insn.error = _("bad segment"); 2738 expr_end = input_line_pointer; 2739 input_line_pointer = save_in; 2740 return 1; 2741 } 2742 expr_end = input_line_pointer; 2743 input_line_pointer = save_in; 2744 return 0; 2745} 2746 2747/* Subroutine of md_assemble to output one insn. */ 2748 2749static void 2750output_insn (insn, the_insn) 2751 const struct sparc_opcode *insn; 2752 struct sparc_it *the_insn; 2753{ 2754 char *toP = frag_more (4); 2755 2756 /* Put out the opcode. */ 2757 if (INSN_BIG_ENDIAN) 2758 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2759 else 2760 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2761 2762 /* Put out the symbol-dependent stuff. */ 2763 if (the_insn->reloc != BFD_RELOC_NONE) 2764 { 2765 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 2766 (toP - frag_now->fr_literal), /* Where. */ 2767 4, /* Size. */ 2768 &the_insn->exp, 2769 the_insn->pcrel, 2770 the_insn->reloc); 2771 /* Turn off overflow checking in fixup_segment. We'll do our 2772 own overflow checking in md_apply_fix3. This is necessary because 2773 the insn size is 4 and fixup_segment will signal an overflow for 2774 large 8 byte quantities. */ 2775 fixP->fx_no_overflow = 1; 2776 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2777 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2778 } 2779 2780 last_insn = insn; 2781 last_opcode = the_insn->opcode; 2782 2783#ifdef OBJ_ELF 2784 dwarf2_emit_insn (4); 2785#endif 2786} 2787 2788/* This is identical to the md_atof in m68k.c. I think this is right, 2789 but I'm not sure. 2790 2791 Turn a string in input_line_pointer into a floating point constant 2792 of type TYPE, and store the appropriate bytes in *LITP. The number 2793 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2794 returned, or NULL on OK. */ 2795 2796/* Equal to MAX_PRECISION in atof-ieee.c. */ 2797#define MAX_LITTLENUMS 6 2798 2799char * 2800md_atof (type, litP, sizeP) 2801 char type; 2802 char *litP; 2803 int *sizeP; 2804{ 2805 int i, prec; 2806 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2807 char *t; 2808 2809 switch (type) 2810 { 2811 case 'f': 2812 case 'F': 2813 case 's': 2814 case 'S': 2815 prec = 2; 2816 break; 2817 2818 case 'd': 2819 case 'D': 2820 case 'r': 2821 case 'R': 2822 prec = 4; 2823 break; 2824 2825 case 'x': 2826 case 'X': 2827 prec = 6; 2828 break; 2829 2830 case 'p': 2831 case 'P': 2832 prec = 6; 2833 break; 2834 2835 default: 2836 *sizeP = 0; 2837 return _("Bad call to MD_ATOF()"); 2838 } 2839 2840 t = atof_ieee (input_line_pointer, type, words); 2841 if (t) 2842 input_line_pointer = t; 2843 *sizeP = prec * sizeof (LITTLENUM_TYPE); 2844 2845 if (target_big_endian) 2846 { 2847 for (i = 0; i < prec; i++) 2848 { 2849 md_number_to_chars (litP, (valueT) words[i], 2850 sizeof (LITTLENUM_TYPE)); 2851 litP += sizeof (LITTLENUM_TYPE); 2852 } 2853 } 2854 else 2855 { 2856 for (i = prec - 1; i >= 0; i--) 2857 { 2858 md_number_to_chars (litP, (valueT) words[i], 2859 sizeof (LITTLENUM_TYPE)); 2860 litP += sizeof (LITTLENUM_TYPE); 2861 } 2862 } 2863 2864 return 0; 2865} 2866 2867/* Write a value out to the object file, using the appropriate 2868 endianness. */ 2869 2870void 2871md_number_to_chars (buf, val, n) 2872 char *buf; 2873 valueT val; 2874 int n; 2875{ 2876 if (target_big_endian) 2877 number_to_chars_bigendian (buf, val, n); 2878 else if (target_little_endian_data 2879 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 2880 /* Output debug words, which are not in allocated sections, as big 2881 endian. */ 2882 number_to_chars_bigendian (buf, val, n); 2883 else if (target_little_endian_data || ! target_big_endian) 2884 number_to_chars_littleendian (buf, val, n); 2885} 2886 2887/* Apply a fixS to the frags, now that we know the value it ought to 2888 hold. */ 2889 2890void 2891md_apply_fix3 (fixP, valP, segment) 2892 fixS *fixP; 2893 valueT *valP; 2894 segT segment; 2895{ 2896 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2897 offsetT val = * (offsetT *) valP; 2898 long insn; 2899 2900 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 2901 2902 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 2903 2904#ifdef OBJ_ELF 2905 /* FIXME: SPARC ELF relocations don't use an addend in the data 2906 field itself. This whole approach should be somehow combined 2907 with the calls to bfd_install_relocation. Also, the value passed 2908 in by fixup_segment includes the value of a defined symbol. We 2909 don't want to include the value of an externally visible symbol. */ 2910 if (fixP->fx_addsy != NULL) 2911 { 2912 symbolS * sym = fixP->fx_addsy; 2913 segT seg = S_GET_SEGMENT (sym); 2914 2915 if (symbol_used_in_reloc_p (sym) 2916 && (S_IS_EXTERNAL (sym) 2917 || S_IS_WEAK (sym) 2918 || (seg->flags & SEC_MERGE) 2919 || (sparc_pic_code && ! fixP->fx_pcrel) 2920 || (seg != segment 2921 && (((bfd_get_section_flags (stdoutput, seg) & SEC_LINK_ONCE) != 0) 2922 || (strncmp (segment_name (seg), 2923 ".gnu.linkonce", 2924 sizeof ".gnu.linkonce" - 1) == 0)))) 2925 && seg != absolute_section 2926 && seg != undefined_section 2927 && ! bfd_is_com_section (seg)) 2928 fixP->fx_addnumber -= S_GET_VALUE (sym); 2929 2930 return; 2931 } 2932#endif 2933 2934 /* This is a hack. There should be a better way to 2935 handle this. Probably in terms of howto fields, once 2936 we can look at these fixups in terms of howtos. */ 2937 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 2938 val += fixP->fx_where + fixP->fx_frag->fr_address; 2939 2940#ifdef OBJ_AOUT 2941 /* FIXME: More ridiculous gas reloc hacking. If we are going to 2942 generate a reloc, then we just want to let the reloc addend set 2943 the value. We do not want to also stuff the addend into the 2944 object file. Including the addend in the object file works when 2945 doing a static link, because the linker will ignore the object 2946 file contents. However, the dynamic linker does not ignore the 2947 object file contents. */ 2948 if (fixP->fx_addsy != NULL 2949 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 2950 val = 0; 2951 2952 /* When generating PIC code, we do not want an addend for a reloc 2953 against a local symbol. We adjust fx_addnumber to cancel out the 2954 value already included in val, and to also cancel out the 2955 adjustment which bfd_install_relocation will create. */ 2956 if (sparc_pic_code 2957 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 2958 && fixP->fx_addsy != NULL 2959 && ! S_IS_COMMON (fixP->fx_addsy) 2960 && symbol_section_p (fixP->fx_addsy)) 2961 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 2962 2963 /* When generating PIC code, we need to fiddle to get 2964 bfd_install_relocation to do the right thing for a PC relative 2965 reloc against a local symbol which we are going to keep. */ 2966 if (sparc_pic_code 2967 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 2968 && fixP->fx_addsy != NULL 2969 && (S_IS_EXTERNAL (fixP->fx_addsy) 2970 || S_IS_WEAK (fixP->fx_addsy)) 2971 && S_IS_DEFINED (fixP->fx_addsy) 2972 && ! S_IS_COMMON (fixP->fx_addsy)) 2973 { 2974 val = 0; 2975 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 2976 } 2977#endif 2978 2979 /* If this is a data relocation, just output VAL. */ 2980 2981 if (fixP->fx_r_type == BFD_RELOC_16 2982 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 2983 { 2984 md_number_to_chars (buf, val, 2); 2985 } 2986 else if (fixP->fx_r_type == BFD_RELOC_32 2987 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 2988 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 2989 { 2990 md_number_to_chars (buf, val, 4); 2991 } 2992 else if (fixP->fx_r_type == BFD_RELOC_64 2993 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 2994 { 2995 md_number_to_chars (buf, val, 8); 2996 } 2997 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2998 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 2999 { 3000 fixP->fx_done = 0; 3001 return; 3002 } 3003 else 3004 { 3005 /* It's a relocation against an instruction. */ 3006 3007 if (INSN_BIG_ENDIAN) 3008 insn = bfd_getb32 ((unsigned char *) buf); 3009 else 3010 insn = bfd_getl32 ((unsigned char *) buf); 3011 3012 switch (fixP->fx_r_type) 3013 { 3014 case BFD_RELOC_32_PCREL_S2: 3015 val = val >> 2; 3016 /* FIXME: This increment-by-one deserves a comment of why it's 3017 being done! */ 3018 if (! sparc_pic_code 3019 || fixP->fx_addsy == NULL 3020 || symbol_section_p (fixP->fx_addsy)) 3021 ++val; 3022 3023 insn |= val & 0x3fffffff; 3024 3025 /* See if we have a delay slot. */ 3026 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3027 { 3028#define G0 0 3029#define O7 15 3030#define XCC (2 << 20) 3031#define COND(x) (((x)&0xf)<<25) 3032#define CONDA COND(0x8) 3033#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3034#define INSN_BA (F2(0,2) | CONDA) 3035#define INSN_OR F3(2, 0x2, 0) 3036#define INSN_NOP F2(0,4) 3037 3038 long delay; 3039 3040 /* If the instruction is a call with either: 3041 restore 3042 arithmetic instruction with rd == %o7 3043 where rs1 != %o7 and rs2 if it is register != %o7 3044 then we can optimize if the call destination is near 3045 by changing the call into a branch always. */ 3046 if (INSN_BIG_ENDIAN) 3047 delay = bfd_getb32 ((unsigned char *) buf + 4); 3048 else 3049 delay = bfd_getl32 ((unsigned char *) buf + 4); 3050 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3051 break; 3052 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3053 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3054 || ((delay & RD (~0)) != RD (O7)))) 3055 break; 3056 if ((delay & RS1 (~0)) == RS1 (O7) 3057 || ((delay & F3I (~0)) == 0 3058 && (delay & RS2 (~0)) == RS2 (O7))) 3059 break; 3060 /* Ensure the branch will fit into simm22. */ 3061 if ((val & 0x3fe00000) 3062 && (val & 0x3fe00000) != 0x3fe00000) 3063 break; 3064 /* Check if the arch is v9 and branch will fit 3065 into simm19. */ 3066 if (((val & 0x3c0000) == 0 3067 || (val & 0x3c0000) == 0x3c0000) 3068 && (sparc_arch_size == 64 3069 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3070 /* ba,pt %xcc */ 3071 insn = INSN_BPA | (val & 0x7ffff); 3072 else 3073 /* ba */ 3074 insn = INSN_BA | (val & 0x3fffff); 3075 if (fixP->fx_where >= 4 3076 && ((delay & (0xffffffff ^ RS1 (~0))) 3077 == (INSN_OR | RD (O7) | RS2 (G0)))) 3078 { 3079 long setter; 3080 int reg; 3081 3082 if (INSN_BIG_ENDIAN) 3083 setter = bfd_getb32 ((unsigned char *) buf - 4); 3084 else 3085 setter = bfd_getl32 ((unsigned char *) buf - 4); 3086 if ((setter & (0xffffffff ^ RD (~0))) 3087 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3088 break; 3089 /* The sequence was 3090 or %o7, %g0, %rN 3091 call foo 3092 or %rN, %g0, %o7 3093 3094 If call foo was replaced with ba, replace 3095 or %rN, %g0, %o7 with nop. */ 3096 reg = (delay & RS1 (~0)) >> 14; 3097 if (reg != ((setter & RD (~0)) >> 25) 3098 || reg == G0 || reg == O7) 3099 break; 3100 3101 if (INSN_BIG_ENDIAN) 3102 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3103 else 3104 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3105 } 3106 } 3107 break; 3108 3109 case BFD_RELOC_SPARC_11: 3110 if (! in_signed_range (val, 0x7ff)) 3111 as_bad_where (fixP->fx_file, fixP->fx_line, 3112 _("relocation overflow")); 3113 insn |= val & 0x7ff; 3114 break; 3115 3116 case BFD_RELOC_SPARC_10: 3117 if (! in_signed_range (val, 0x3ff)) 3118 as_bad_where (fixP->fx_file, fixP->fx_line, 3119 _("relocation overflow")); 3120 insn |= val & 0x3ff; 3121 break; 3122 3123 case BFD_RELOC_SPARC_7: 3124 if (! in_bitfield_range (val, 0x7f)) 3125 as_bad_where (fixP->fx_file, fixP->fx_line, 3126 _("relocation overflow")); 3127 insn |= val & 0x7f; 3128 break; 3129 3130 case BFD_RELOC_SPARC_6: 3131 if (! in_bitfield_range (val, 0x3f)) 3132 as_bad_where (fixP->fx_file, fixP->fx_line, 3133 _("relocation overflow")); 3134 insn |= val & 0x3f; 3135 break; 3136 3137 case BFD_RELOC_SPARC_5: 3138 if (! in_bitfield_range (val, 0x1f)) 3139 as_bad_where (fixP->fx_file, fixP->fx_line, 3140 _("relocation overflow")); 3141 insn |= val & 0x1f; 3142 break; 3143 3144 case BFD_RELOC_SPARC_WDISP16: 3145 /* FIXME: simplify. */ 3146 if (((val > 0) && (val & ~0x3fffc)) 3147 || ((val < 0) && (~(val - 1) & ~0x3fffc))) 3148 as_bad_where (fixP->fx_file, fixP->fx_line, 3149 _("relocation overflow")); 3150 /* FIXME: The +1 deserves a comment. */ 3151 val = (val >> 2) + 1; 3152 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3153 break; 3154 3155 case BFD_RELOC_SPARC_WDISP19: 3156 /* FIXME: simplify. */ 3157 if (((val > 0) && (val & ~0x1ffffc)) 3158 || ((val < 0) && (~(val - 1) & ~0x1ffffc))) 3159 as_bad_where (fixP->fx_file, fixP->fx_line, 3160 _("relocation overflow")); 3161 /* FIXME: The +1 deserves a comment. */ 3162 val = (val >> 2) + 1; 3163 insn |= val & 0x7ffff; 3164 break; 3165 3166 case BFD_RELOC_SPARC_HH22: 3167 val = BSR (val, 32); 3168 /* Fall through. */ 3169 3170 case BFD_RELOC_SPARC_LM22: 3171 case BFD_RELOC_HI22: 3172 if (!fixP->fx_addsy) 3173 insn |= (val >> 10) & 0x3fffff; 3174 else 3175 /* FIXME: Need comment explaining why we do this. */ 3176 insn &= ~0xffff; 3177 break; 3178 3179 case BFD_RELOC_SPARC22: 3180 if (val & ~0x003fffff) 3181 as_bad_where (fixP->fx_file, fixP->fx_line, 3182 _("relocation overflow")); 3183 insn |= (val & 0x3fffff); 3184 break; 3185 3186 case BFD_RELOC_SPARC_HM10: 3187 val = BSR (val, 32); 3188 /* Fall through. */ 3189 3190 case BFD_RELOC_LO10: 3191 if (!fixP->fx_addsy) 3192 insn |= val & 0x3ff; 3193 else 3194 /* FIXME: Need comment explaining why we do this. */ 3195 insn &= ~0xff; 3196 break; 3197 3198 case BFD_RELOC_SPARC_OLO10: 3199 val &= 0x3ff; 3200 val += fixP->tc_fix_data; 3201 /* Fall through. */ 3202 3203 case BFD_RELOC_SPARC13: 3204 if (! in_signed_range (val, 0x1fff)) 3205 as_bad_where (fixP->fx_file, fixP->fx_line, 3206 _("relocation overflow")); 3207 insn |= val & 0x1fff; 3208 break; 3209 3210 case BFD_RELOC_SPARC_WDISP22: 3211 val = (val >> 2) + 1; 3212 /* Fall through. */ 3213 case BFD_RELOC_SPARC_BASE22: 3214 insn |= val & 0x3fffff; 3215 break; 3216 3217 case BFD_RELOC_SPARC_H44: 3218 if (!fixP->fx_addsy) 3219 { 3220 bfd_vma tval = val; 3221 tval >>= 22; 3222 insn |= tval & 0x3fffff; 3223 } 3224 break; 3225 3226 case BFD_RELOC_SPARC_M44: 3227 if (!fixP->fx_addsy) 3228 insn |= (val >> 12) & 0x3ff; 3229 break; 3230 3231 case BFD_RELOC_SPARC_L44: 3232 if (!fixP->fx_addsy) 3233 insn |= val & 0xfff; 3234 break; 3235 3236 case BFD_RELOC_SPARC_HIX22: 3237 if (!fixP->fx_addsy) 3238 { 3239 val ^= ~(offsetT) 0; 3240 insn |= (val >> 10) & 0x3fffff; 3241 } 3242 break; 3243 3244 case BFD_RELOC_SPARC_LOX10: 3245 if (!fixP->fx_addsy) 3246 insn |= 0x1c00 | (val & 0x3ff); 3247 break; 3248 3249 case BFD_RELOC_NONE: 3250 default: 3251 as_bad_where (fixP->fx_file, fixP->fx_line, 3252 _("bad or unhandled relocation type: 0x%02x"), 3253 fixP->fx_r_type); 3254 break; 3255 } 3256 3257 if (INSN_BIG_ENDIAN) 3258 bfd_putb32 (insn, (unsigned char *) buf); 3259 else 3260 bfd_putl32 (insn, (unsigned char *) buf); 3261 } 3262 3263 /* Are we finished with this relocation now? */ 3264 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3265 fixP->fx_done = 1; 3266} 3267 3268/* Translate internal representation of relocation info to BFD target 3269 format. */ 3270 3271arelent ** 3272tc_gen_reloc (section, fixp) 3273 asection *section; 3274 fixS *fixp; 3275{ 3276 static arelent *relocs[3]; 3277 arelent *reloc; 3278 bfd_reloc_code_real_type code; 3279 3280 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3281 relocs[1] = NULL; 3282 3283 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3284 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3285 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3286 3287 switch (fixp->fx_r_type) 3288 { 3289 case BFD_RELOC_16: 3290 case BFD_RELOC_32: 3291 case BFD_RELOC_HI22: 3292 case BFD_RELOC_LO10: 3293 case BFD_RELOC_32_PCREL_S2: 3294 case BFD_RELOC_SPARC13: 3295 case BFD_RELOC_SPARC22: 3296 case BFD_RELOC_SPARC_BASE13: 3297 case BFD_RELOC_SPARC_WDISP16: 3298 case BFD_RELOC_SPARC_WDISP19: 3299 case BFD_RELOC_SPARC_WDISP22: 3300 case BFD_RELOC_64: 3301 case BFD_RELOC_SPARC_5: 3302 case BFD_RELOC_SPARC_6: 3303 case BFD_RELOC_SPARC_7: 3304 case BFD_RELOC_SPARC_10: 3305 case BFD_RELOC_SPARC_11: 3306 case BFD_RELOC_SPARC_HH22: 3307 case BFD_RELOC_SPARC_HM10: 3308 case BFD_RELOC_SPARC_LM22: 3309 case BFD_RELOC_SPARC_PC_HH22: 3310 case BFD_RELOC_SPARC_PC_HM10: 3311 case BFD_RELOC_SPARC_PC_LM22: 3312 case BFD_RELOC_SPARC_H44: 3313 case BFD_RELOC_SPARC_M44: 3314 case BFD_RELOC_SPARC_L44: 3315 case BFD_RELOC_SPARC_HIX22: 3316 case BFD_RELOC_SPARC_LOX10: 3317 case BFD_RELOC_SPARC_REV32: 3318 case BFD_RELOC_SPARC_OLO10: 3319 case BFD_RELOC_SPARC_UA16: 3320 case BFD_RELOC_SPARC_UA32: 3321 case BFD_RELOC_SPARC_UA64: 3322 case BFD_RELOC_8_PCREL: 3323 case BFD_RELOC_16_PCREL: 3324 case BFD_RELOC_32_PCREL: 3325 case BFD_RELOC_64_PCREL: 3326 case BFD_RELOC_SPARC_PLT32: 3327 case BFD_RELOC_SPARC_PLT64: 3328 case BFD_RELOC_VTABLE_ENTRY: 3329 case BFD_RELOC_VTABLE_INHERIT: 3330 code = fixp->fx_r_type; 3331 break; 3332 default: 3333 abort (); 3334 return NULL; 3335 } 3336 3337#if defined (OBJ_ELF) || defined (OBJ_AOUT) 3338 /* If we are generating PIC code, we need to generate a different 3339 set of relocs. */ 3340 3341#ifdef OBJ_ELF 3342#define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3343#else 3344#define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3345#endif 3346 3347 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3348 3349 if (sparc_pic_code) 3350 { 3351 switch (code) 3352 { 3353 case BFD_RELOC_32_PCREL_S2: 3354 if (! S_IS_DEFINED (fixp->fx_addsy) 3355 || S_IS_COMMON (fixp->fx_addsy) 3356 || S_IS_EXTERNAL (fixp->fx_addsy) 3357 || S_IS_WEAK (fixp->fx_addsy)) 3358 code = BFD_RELOC_SPARC_WPLT30; 3359 break; 3360 case BFD_RELOC_HI22: 3361 if (fixp->fx_addsy != NULL 3362 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3363 code = BFD_RELOC_SPARC_PC22; 3364 else 3365 code = BFD_RELOC_SPARC_GOT22; 3366 break; 3367 case BFD_RELOC_LO10: 3368 if (fixp->fx_addsy != NULL 3369 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3370 code = BFD_RELOC_SPARC_PC10; 3371 else 3372 code = BFD_RELOC_SPARC_GOT10; 3373 break; 3374 case BFD_RELOC_SPARC13: 3375 code = BFD_RELOC_SPARC_GOT13; 3376 break; 3377 default: 3378 break; 3379 } 3380 } 3381#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3382 3383 if (code == BFD_RELOC_SPARC_OLO10) 3384 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3385 else 3386 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3387 if (reloc->howto == 0) 3388 { 3389 as_bad_where (fixp->fx_file, fixp->fx_line, 3390 _("internal error: can't export reloc type %d (`%s')"), 3391 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3392 xfree (reloc); 3393 relocs[0] = NULL; 3394 return relocs; 3395 } 3396 3397 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3398#ifdef OBJ_AOUT 3399 3400 if (reloc->howto->pc_relative == 0 3401 || code == BFD_RELOC_SPARC_PC10 3402 || code == BFD_RELOC_SPARC_PC22) 3403 reloc->addend = fixp->fx_addnumber; 3404 else if (sparc_pic_code 3405 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3406 && fixp->fx_addsy != NULL 3407 && (S_IS_EXTERNAL (fixp->fx_addsy) 3408 || S_IS_WEAK (fixp->fx_addsy)) 3409 && S_IS_DEFINED (fixp->fx_addsy) 3410 && ! S_IS_COMMON (fixp->fx_addsy)) 3411 reloc->addend = fixp->fx_addnumber; 3412 else 3413 reloc->addend = fixp->fx_offset - reloc->address; 3414 3415#else /* elf or coff */ 3416 3417 if (code != BFD_RELOC_32_PCREL_S2 3418 && code != BFD_RELOC_SPARC_WDISP22 3419 && code != BFD_RELOC_SPARC_WDISP16 3420 && code != BFD_RELOC_SPARC_WDISP19 3421 && code != BFD_RELOC_SPARC_WPLT30) 3422 reloc->addend = fixp->fx_addnumber; 3423 else if (symbol_section_p (fixp->fx_addsy)) 3424 reloc->addend = (section->vma 3425 + fixp->fx_addnumber 3426 + md_pcrel_from (fixp)); 3427 else 3428 reloc->addend = fixp->fx_offset; 3429#endif 3430 3431 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3432 on the same location. */ 3433 if (code == BFD_RELOC_SPARC_OLO10) 3434 { 3435 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3436 relocs[2] = NULL; 3437 3438 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3439 *reloc->sym_ptr_ptr 3440 = symbol_get_bfdsym (section_symbol (absolute_section)); 3441 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3442 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3443 reloc->addend = fixp->tc_fix_data; 3444 } 3445 3446 return relocs; 3447} 3448 3449/* We have no need to default values of symbols. */ 3450 3451symbolS * 3452md_undefined_symbol (name) 3453 char *name ATTRIBUTE_UNUSED; 3454{ 3455 return 0; 3456} 3457 3458/* Round up a section size to the appropriate boundary. */ 3459 3460valueT 3461md_section_align (segment, size) 3462 segT segment ATTRIBUTE_UNUSED; 3463 valueT size; 3464{ 3465#ifndef OBJ_ELF 3466 /* This is not right for ELF; a.out wants it, and COFF will force 3467 the alignment anyways. */ 3468 valueT align = ((valueT) 1 3469 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3470 valueT newsize; 3471 3472 /* Turn alignment value into a mask. */ 3473 align--; 3474 newsize = (size + align) & ~align; 3475 return newsize; 3476#else 3477 return size; 3478#endif 3479} 3480 3481/* Exactly what point is a PC-relative offset relative TO? 3482 On the sparc, they're relative to the address of the offset, plus 3483 its size. This gets us to the following instruction. 3484 (??? Is this right? FIXME-SOON) */ 3485long 3486md_pcrel_from (fixP) 3487 fixS *fixP; 3488{ 3489 long ret; 3490 3491 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3492 if (! sparc_pic_code 3493 || fixP->fx_addsy == NULL 3494 || symbol_section_p (fixP->fx_addsy)) 3495 ret += fixP->fx_size; 3496 return ret; 3497} 3498 3499/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3500 of two. */ 3501 3502static int 3503log2 (value) 3504 int value; 3505{ 3506 int shift; 3507 3508 if (value <= 0) 3509 return -1; 3510 3511 for (shift = 0; (value & 1) == 0; value >>= 1) 3512 ++shift; 3513 3514 return (value == 1) ? shift : -1; 3515} 3516 3517/* Sort of like s_lcomm. */ 3518 3519#ifndef OBJ_ELF 3520static int max_alignment = 15; 3521#endif 3522 3523static void 3524s_reserve (ignore) 3525 int ignore ATTRIBUTE_UNUSED; 3526{ 3527 char *name; 3528 char *p; 3529 char c; 3530 int align; 3531 int size; 3532 int temp; 3533 symbolS *symbolP; 3534 3535 name = input_line_pointer; 3536 c = get_symbol_end (); 3537 p = input_line_pointer; 3538 *p = c; 3539 SKIP_WHITESPACE (); 3540 3541 if (*input_line_pointer != ',') 3542 { 3543 as_bad (_("Expected comma after name")); 3544 ignore_rest_of_line (); 3545 return; 3546 } 3547 3548 ++input_line_pointer; 3549 3550 if ((size = get_absolute_expression ()) < 0) 3551 { 3552 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3553 ignore_rest_of_line (); 3554 return; 3555 } /* Bad length. */ 3556 3557 *p = 0; 3558 symbolP = symbol_find_or_make (name); 3559 *p = c; 3560 3561 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3562 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3563 { 3564 as_bad (_("bad .reserve segment -- expected BSS segment")); 3565 return; 3566 } 3567 3568 if (input_line_pointer[2] == '.') 3569 input_line_pointer += 7; 3570 else 3571 input_line_pointer += 6; 3572 SKIP_WHITESPACE (); 3573 3574 if (*input_line_pointer == ',') 3575 { 3576 ++input_line_pointer; 3577 3578 SKIP_WHITESPACE (); 3579 if (*input_line_pointer == '\n') 3580 { 3581 as_bad (_("missing alignment")); 3582 ignore_rest_of_line (); 3583 return; 3584 } 3585 3586 align = (int) get_absolute_expression (); 3587 3588#ifndef OBJ_ELF 3589 if (align > max_alignment) 3590 { 3591 align = max_alignment; 3592 as_warn (_("alignment too large; assuming %d"), align); 3593 } 3594#endif 3595 3596 if (align < 0) 3597 { 3598 as_bad (_("negative alignment")); 3599 ignore_rest_of_line (); 3600 return; 3601 } 3602 3603 if (align != 0) 3604 { 3605 temp = log2 (align); 3606 if (temp < 0) 3607 { 3608 as_bad (_("alignment not a power of 2")); 3609 ignore_rest_of_line (); 3610 return; 3611 } 3612 3613 align = temp; 3614 } 3615 3616 record_alignment (bss_section, align); 3617 } 3618 else 3619 align = 0; 3620 3621 if (!S_IS_DEFINED (symbolP) 3622#ifdef OBJ_AOUT 3623 && S_GET_OTHER (symbolP) == 0 3624 && S_GET_DESC (symbolP) == 0 3625#endif 3626 ) 3627 { 3628 if (! need_pass_2) 3629 { 3630 char *pfrag; 3631 segT current_seg = now_seg; 3632 subsegT current_subseg = now_subseg; 3633 3634 /* Switch to bss. */ 3635 subseg_set (bss_section, 1); 3636 3637 if (align) 3638 /* Do alignment. */ 3639 frag_align (align, 0, 0); 3640 3641 /* Detach from old frag. */ 3642 if (S_GET_SEGMENT (symbolP) == bss_section) 3643 symbol_get_frag (symbolP)->fr_symbol = NULL; 3644 3645 symbol_set_frag (symbolP, frag_now); 3646 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3647 (offsetT) size, (char *) 0); 3648 *pfrag = 0; 3649 3650 S_SET_SEGMENT (symbolP, bss_section); 3651 3652 subseg_set (current_seg, current_subseg); 3653 3654#ifdef OBJ_ELF 3655 S_SET_SIZE (symbolP, size); 3656#endif 3657 } 3658 } 3659 else 3660 { 3661 as_warn ("Ignoring attempt to re-define symbol %s", 3662 S_GET_NAME (symbolP)); 3663 } /* if not redefining. */ 3664 3665 demand_empty_rest_of_line (); 3666} 3667 3668static void 3669s_common (ignore) 3670 int ignore ATTRIBUTE_UNUSED; 3671{ 3672 char *name; 3673 char c; 3674 char *p; 3675 int temp, size; 3676 symbolS *symbolP; 3677 3678 name = input_line_pointer; 3679 c = get_symbol_end (); 3680 /* Just after name is now '\0'. */ 3681 p = input_line_pointer; 3682 *p = c; 3683 SKIP_WHITESPACE (); 3684 if (*input_line_pointer != ',') 3685 { 3686 as_bad (_("Expected comma after symbol-name")); 3687 ignore_rest_of_line (); 3688 return; 3689 } 3690 3691 /* Skip ','. */ 3692 input_line_pointer++; 3693 3694 if ((temp = get_absolute_expression ()) < 0) 3695 { 3696 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp); 3697 ignore_rest_of_line (); 3698 return; 3699 } 3700 size = temp; 3701 *p = 0; 3702 symbolP = symbol_find_or_make (name); 3703 *p = c; 3704 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3705 { 3706 as_bad (_("Ignoring attempt to re-define symbol")); 3707 ignore_rest_of_line (); 3708 return; 3709 } 3710 if (S_GET_VALUE (symbolP) != 0) 3711 { 3712 if (S_GET_VALUE (symbolP) != (valueT) size) 3713 { 3714 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 3715 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 3716 } 3717 } 3718 else 3719 { 3720#ifndef OBJ_ELF 3721 S_SET_VALUE (symbolP, (valueT) size); 3722 S_SET_EXTERNAL (symbolP); 3723#endif 3724 } 3725 know (symbol_get_frag (symbolP) == &zero_address_frag); 3726 if (*input_line_pointer != ',') 3727 { 3728 as_bad (_("Expected comma after common length")); 3729 ignore_rest_of_line (); 3730 return; 3731 } 3732 input_line_pointer++; 3733 SKIP_WHITESPACE (); 3734 if (*input_line_pointer != '"') 3735 { 3736 temp = get_absolute_expression (); 3737 3738#ifndef OBJ_ELF 3739 if (temp > max_alignment) 3740 { 3741 temp = max_alignment; 3742 as_warn (_("alignment too large; assuming %d"), temp); 3743 } 3744#endif 3745 3746 if (temp < 0) 3747 { 3748 as_bad (_("negative alignment")); 3749 ignore_rest_of_line (); 3750 return; 3751 } 3752 3753#ifdef OBJ_ELF 3754 if (symbol_get_obj (symbolP)->local) 3755 { 3756 segT old_sec; 3757 int old_subsec; 3758 char *p; 3759 int align; 3760 3761 old_sec = now_seg; 3762 old_subsec = now_subseg; 3763 3764 if (temp == 0) 3765 align = 0; 3766 else 3767 align = log2 (temp); 3768 3769 if (align < 0) 3770 { 3771 as_bad (_("alignment not a power of 2")); 3772 ignore_rest_of_line (); 3773 return; 3774 } 3775 3776 record_alignment (bss_section, align); 3777 subseg_set (bss_section, 0); 3778 if (align) 3779 frag_align (align, 0, 0); 3780 if (S_GET_SEGMENT (symbolP) == bss_section) 3781 symbol_get_frag (symbolP)->fr_symbol = 0; 3782 symbol_set_frag (symbolP, frag_now); 3783 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3784 (offsetT) size, (char *) 0); 3785 *p = 0; 3786 S_SET_SEGMENT (symbolP, bss_section); 3787 S_CLEAR_EXTERNAL (symbolP); 3788 S_SET_SIZE (symbolP, size); 3789 subseg_set (old_sec, old_subsec); 3790 } 3791 else 3792#endif /* OBJ_ELF */ 3793 { 3794 allocate_common: 3795 S_SET_VALUE (symbolP, (valueT) size); 3796#ifdef OBJ_ELF 3797 S_SET_ALIGN (symbolP, temp); 3798 S_SET_SIZE (symbolP, size); 3799#endif 3800 S_SET_EXTERNAL (symbolP); 3801 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 3802 } 3803 } 3804 else 3805 { 3806 input_line_pointer++; 3807 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 3808 if (*input_line_pointer == '.') 3809 input_line_pointer++; 3810 /* @@ Some say data, some say bss. */ 3811 if (strncmp (input_line_pointer, "bss\"", 4) 3812 && strncmp (input_line_pointer, "data\"", 5)) 3813 { 3814 while (*--input_line_pointer != '"') 3815 ; 3816 input_line_pointer--; 3817 goto bad_common_segment; 3818 } 3819 while (*input_line_pointer++ != '"') 3820 ; 3821 goto allocate_common; 3822 } 3823 3824#ifdef BFD_ASSEMBLER 3825 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 3826#endif 3827 3828 demand_empty_rest_of_line (); 3829 return; 3830 3831 { 3832 bad_common_segment: 3833 p = input_line_pointer; 3834 while (*p && *p != '\n') 3835 p++; 3836 c = *p; 3837 *p = '\0'; 3838 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 3839 *p = c; 3840 input_line_pointer = p; 3841 ignore_rest_of_line (); 3842 return; 3843 } 3844} 3845 3846/* Handle the .empty pseudo-op. This supresses the warnings about 3847 invalid delay slot usage. */ 3848 3849static void 3850s_empty (ignore) 3851 int ignore ATTRIBUTE_UNUSED; 3852{ 3853 /* The easy way to implement is to just forget about the last 3854 instruction. */ 3855 last_insn = NULL; 3856} 3857 3858static void 3859s_seg (ignore) 3860 int ignore ATTRIBUTE_UNUSED; 3861{ 3862 3863 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 3864 { 3865 input_line_pointer += 6; 3866 s_text (0); 3867 return; 3868 } 3869 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 3870 { 3871 input_line_pointer += 6; 3872 s_data (0); 3873 return; 3874 } 3875 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 3876 { 3877 input_line_pointer += 7; 3878 s_data1 (); 3879 return; 3880 } 3881 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 3882 { 3883 input_line_pointer += 5; 3884 /* We only support 2 segments -- text and data -- for now, so 3885 things in the "bss segment" will have to go into data for now. 3886 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 3887 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 3888 return; 3889 } 3890 as_bad (_("Unknown segment type")); 3891 demand_empty_rest_of_line (); 3892} 3893 3894static void 3895s_data1 () 3896{ 3897 subseg_set (data_section, 1); 3898 demand_empty_rest_of_line (); 3899} 3900 3901static void 3902s_proc (ignore) 3903 int ignore ATTRIBUTE_UNUSED; 3904{ 3905 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 3906 { 3907 ++input_line_pointer; 3908 } 3909 ++input_line_pointer; 3910} 3911 3912/* This static variable is set by s_uacons to tell sparc_cons_align 3913 that the expession does not need to be aligned. */ 3914 3915static int sparc_no_align_cons = 0; 3916 3917/* This static variable is set by sparc_cons to emit requested types 3918 of relocations in cons_fix_new_sparc. */ 3919 3920static const char *sparc_cons_special_reloc; 3921 3922/* This handles the unaligned space allocation pseudo-ops, such as 3923 .uaword. .uaword is just like .word, but the value does not need 3924 to be aligned. */ 3925 3926static void 3927s_uacons (bytes) 3928 int bytes; 3929{ 3930 /* Tell sparc_cons_align not to align this value. */ 3931 sparc_no_align_cons = 1; 3932 cons (bytes); 3933 sparc_no_align_cons = 0; 3934} 3935 3936/* This handles the native word allocation pseudo-op .nword. 3937 For sparc_arch_size 32 it is equivalent to .word, for 3938 sparc_arch_size 64 it is equivalent to .xword. */ 3939 3940static void 3941s_ncons (bytes) 3942 int bytes ATTRIBUTE_UNUSED; 3943{ 3944 cons (sparc_arch_size == 32 ? 4 : 8); 3945} 3946 3947#ifdef OBJ_ELF 3948/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 3949 global register. 3950 The syntax is: 3951 3952 .register %g[2367],{#scratch|symbolname|#ignore} 3953*/ 3954 3955static void 3956s_register (ignore) 3957 int ignore ATTRIBUTE_UNUSED; 3958{ 3959 char c; 3960 int reg; 3961 int flags; 3962 const char *regname; 3963 3964 if (input_line_pointer[0] != '%' 3965 || input_line_pointer[1] != 'g' 3966 || ((input_line_pointer[2] & ~1) != '2' 3967 && (input_line_pointer[2] & ~1) != '6') 3968 || input_line_pointer[3] != ',') 3969 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 3970 reg = input_line_pointer[2] - '0'; 3971 input_line_pointer += 4; 3972 3973 if (*input_line_pointer == '#') 3974 { 3975 ++input_line_pointer; 3976 regname = input_line_pointer; 3977 c = get_symbol_end (); 3978 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 3979 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 3980 if (regname[0] == 'i') 3981 regname = NULL; 3982 else 3983 regname = ""; 3984 } 3985 else 3986 { 3987 regname = input_line_pointer; 3988 c = get_symbol_end (); 3989 } 3990 if (sparc_arch_size == 64) 3991 { 3992 if (globals[reg]) 3993 { 3994 if ((regname && globals[reg] != (symbolS *) 1 3995 && strcmp (S_GET_NAME (globals[reg]), regname)) 3996 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 3997 as_bad (_("redefinition of global register")); 3998 } 3999 else 4000 { 4001 if (regname == NULL) 4002 globals[reg] = (symbolS *) 1; 4003 else 4004 { 4005 if (*regname) 4006 { 4007 if (symbol_find (regname)) 4008 as_bad (_("Register symbol %s already defined."), 4009 regname); 4010 } 4011 globals[reg] = symbol_make (regname); 4012 flags = symbol_get_bfdsym (globals[reg])->flags; 4013 if (! *regname) 4014 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4015 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4016 flags |= BSF_GLOBAL; 4017 symbol_get_bfdsym (globals[reg])->flags = flags; 4018 S_SET_VALUE (globals[reg], (valueT) reg); 4019 S_SET_ALIGN (globals[reg], reg); 4020 S_SET_SIZE (globals[reg], 0); 4021 /* Although we actually want undefined_section here, 4022 we have to use absolute_section, because otherwise 4023 generic as code will make it a COM section. 4024 We fix this up in sparc_adjust_symtab. */ 4025 S_SET_SEGMENT (globals[reg], absolute_section); 4026 S_SET_OTHER (globals[reg], 0); 4027 elf_symbol (symbol_get_bfdsym (globals[reg])) 4028 ->internal_elf_sym.st_info = 4029 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4030 elf_symbol (symbol_get_bfdsym (globals[reg])) 4031 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4032 } 4033 } 4034 } 4035 4036 *input_line_pointer = c; 4037 4038 demand_empty_rest_of_line (); 4039} 4040 4041/* Adjust the symbol table. We set undefined sections for STT_REGISTER 4042 symbols which need it. */ 4043 4044void 4045sparc_adjust_symtab () 4046{ 4047 symbolS *sym; 4048 4049 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4050 { 4051 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4052 ->internal_elf_sym.st_info) != STT_REGISTER) 4053 continue; 4054 4055 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4056 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4057 continue; 4058 4059 S_SET_SEGMENT (sym, undefined_section); 4060 } 4061} 4062#endif 4063 4064/* If the --enforce-aligned-data option is used, we require .word, 4065 et. al., to be aligned correctly. We do it by setting up an 4066 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4067 no unexpected alignment was introduced. 4068 4069 The SunOS and Solaris native assemblers enforce aligned data by 4070 default. We don't want to do that, because gcc can deliberately 4071 generate misaligned data if the packed attribute is used. Instead, 4072 we permit misaligned data by default, and permit the user to set an 4073 option to check for it. */ 4074 4075void 4076sparc_cons_align (nbytes) 4077 int nbytes; 4078{ 4079 int nalign; 4080 char *p; 4081 4082 /* Only do this if we are enforcing aligned data. */ 4083 if (! enforce_aligned_data) 4084 return; 4085 4086 /* Don't align if this is an unaligned pseudo-op. */ 4087 if (sparc_no_align_cons) 4088 return; 4089 4090 nalign = log2 (nbytes); 4091 if (nalign == 0) 4092 return; 4093 4094 assert (nalign > 0); 4095 4096 if (now_seg == absolute_section) 4097 { 4098 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4099 as_bad (_("misaligned data")); 4100 return; 4101 } 4102 4103 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4104 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4105 4106 record_alignment (now_seg, nalign); 4107} 4108 4109/* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4110 4111void 4112sparc_handle_align (fragp) 4113 fragS *fragp; 4114{ 4115 int count, fix; 4116 char *p; 4117 4118 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4119 4120 switch (fragp->fr_type) 4121 { 4122 case rs_align_test: 4123 if (count != 0) 4124 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4125 break; 4126 4127 case rs_align_code: 4128 p = fragp->fr_literal + fragp->fr_fix; 4129 fix = 0; 4130 4131 if (count & 3) 4132 { 4133 fix = count & 3; 4134 memset (p, 0, fix); 4135 p += fix; 4136 count -= fix; 4137 } 4138 4139 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4140 { 4141 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4142 if (INSN_BIG_ENDIAN) 4143 number_to_chars_bigendian (p, wval, 4); 4144 else 4145 number_to_chars_littleendian (p, wval, 4); 4146 p += 4; 4147 count -= 4; 4148 fix += 4; 4149 } 4150 4151 if (INSN_BIG_ENDIAN) 4152 number_to_chars_bigendian (p, 0x01000000, 4); 4153 else 4154 number_to_chars_littleendian (p, 0x01000000, 4); 4155 4156 fragp->fr_fix += fix; 4157 fragp->fr_var = 4; 4158 break; 4159 4160 default: 4161 break; 4162 } 4163} 4164 4165#ifdef OBJ_ELF 4166/* Some special processing for a Sparc ELF file. */ 4167 4168void 4169sparc_elf_final_processing () 4170{ 4171 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4172 sort of BFD interface for this. */ 4173 if (sparc_arch_size == 64) 4174 { 4175 switch (sparc_memory_model) 4176 { 4177 case MM_RMO: 4178 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4179 break; 4180 case MM_PSO: 4181 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4182 break; 4183 default: 4184 break; 4185 } 4186 } 4187 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4188 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4189 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4190 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4191 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4192 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4193} 4194 4195void 4196sparc_cons (exp, size) 4197 expressionS *exp; 4198 int size; 4199{ 4200 char *save; 4201 4202 SKIP_WHITESPACE (); 4203 sparc_cons_special_reloc = NULL; 4204 save = input_line_pointer; 4205 if (input_line_pointer[0] == '%' 4206 && input_line_pointer[1] == 'r' 4207 && input_line_pointer[2] == '_') 4208 { 4209 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4210 { 4211 input_line_pointer += 7; 4212 sparc_cons_special_reloc = "disp"; 4213 } 4214 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4215 { 4216 if (size != 4 && size != 8) 4217 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4218 else 4219 { 4220 input_line_pointer += 6; 4221 sparc_cons_special_reloc = "plt"; 4222 } 4223 } 4224 if (sparc_cons_special_reloc) 4225 { 4226 int bad = 0; 4227 4228 switch (size) 4229 { 4230 case 1: 4231 if (*input_line_pointer != '8') 4232 bad = 1; 4233 input_line_pointer--; 4234 break; 4235 case 2: 4236 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4237 bad = 1; 4238 break; 4239 case 4: 4240 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4241 bad = 1; 4242 break; 4243 case 8: 4244 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4245 bad = 1; 4246 break; 4247 default: 4248 bad = 1; 4249 break; 4250 } 4251 4252 if (bad) 4253 { 4254 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4255 sparc_cons_special_reloc, size * 8, size); 4256 } 4257 else 4258 { 4259 input_line_pointer += 2; 4260 if (*input_line_pointer != '(') 4261 { 4262 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4263 sparc_cons_special_reloc, size * 8); 4264 bad = 1; 4265 } 4266 } 4267 4268 if (bad) 4269 { 4270 input_line_pointer = save; 4271 sparc_cons_special_reloc = NULL; 4272 } 4273 else 4274 { 4275 int c; 4276 char *end = ++input_line_pointer; 4277 int npar = 0; 4278 4279 while (! is_end_of_line[(c = *end)]) 4280 { 4281 if (c == '(') 4282 npar++; 4283 else if (c == ')') 4284 { 4285 if (!npar) 4286 break; 4287 npar--; 4288 } 4289 end++; 4290 } 4291 4292 if (c != ')') 4293 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4294 sparc_cons_special_reloc, size * 8); 4295 else 4296 { 4297 *end = '\0'; 4298 expression (exp); 4299 *end = c; 4300 if (input_line_pointer != end) 4301 { 4302 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4303 sparc_cons_special_reloc, size * 8); 4304 } 4305 else 4306 { 4307 input_line_pointer++; 4308 SKIP_WHITESPACE (); 4309 c = *input_line_pointer; 4310 if (! is_end_of_line[c] && c != ',') 4311 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4312 sparc_cons_special_reloc, size * 8); 4313 } 4314 } 4315 } 4316 } 4317 } 4318 if (sparc_cons_special_reloc == NULL) 4319 expression (exp); 4320} 4321 4322#endif 4323 4324/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4325 reloc for a cons. We could use the definition there, except that 4326 we want to handle little endian relocs specially. */ 4327 4328void 4329cons_fix_new_sparc (frag, where, nbytes, exp) 4330 fragS *frag; 4331 int where; 4332 unsigned int nbytes; 4333 expressionS *exp; 4334{ 4335 bfd_reloc_code_real_type r; 4336 4337 r = (nbytes == 1 ? BFD_RELOC_8 : 4338 (nbytes == 2 ? BFD_RELOC_16 : 4339 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4340 4341 if (target_little_endian_data 4342 && nbytes == 4 4343 && now_seg->flags & SEC_ALLOC) 4344 r = BFD_RELOC_SPARC_REV32; 4345 4346 if (sparc_cons_special_reloc) 4347 { 4348 if (*sparc_cons_special_reloc == 'd') 4349 switch (nbytes) 4350 { 4351 case 1: r = BFD_RELOC_8_PCREL; break; 4352 case 2: r = BFD_RELOC_16_PCREL; break; 4353 case 4: r = BFD_RELOC_32_PCREL; break; 4354 case 8: r = BFD_RELOC_64_PCREL; break; 4355 default: abort (); 4356 } 4357 else 4358 switch (nbytes) 4359 { 4360 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4361 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4362 } 4363 } 4364 else if (sparc_no_align_cons) 4365 { 4366 switch (nbytes) 4367 { 4368 case 2: r = BFD_RELOC_SPARC_UA16; break; 4369 case 4: r = BFD_RELOC_SPARC_UA32; break; 4370 case 8: r = BFD_RELOC_SPARC_UA64; break; 4371 default: abort (); 4372 } 4373 } 4374 4375 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4376} 4377 4378#ifdef OBJ_ELF 4379int 4380elf32_sparc_force_relocation (fixp) 4381 struct fix *fixp; 4382{ 4383 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4384 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4385 return 1; 4386 4387 return 0; 4388} 4389#endif 4390