tc-sparc.c revision 78828
1/* tc-sparc.c -- Assemble for the SPARC 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001 4 Free Software Foundation, Inc. 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public 18 License along with GAS; see the file COPYING. If not, write 19 to the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22#include <stdio.h> 23#include <ctype.h> 24 25#include "as.h" 26#include "subsegs.h" 27 28#include "opcode/sparc.h" 29 30#ifdef OBJ_ELF 31#include "elf/sparc.h" 32#include "dwarf2dbg.h" 33#endif 34 35static struct sparc_arch *lookup_arch PARAMS ((char *)); 36static void init_default_arch PARAMS ((void)); 37static int sparc_ip PARAMS ((char *, const struct sparc_opcode **)); 38static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 39static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma)); 40static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma)); 41static int sparc_ffs PARAMS ((unsigned int)); 42static void synthetize_setuw PARAMS ((const struct sparc_opcode *)); 43static void synthetize_setsw PARAMS ((const struct sparc_opcode *)); 44static void synthetize_setx PARAMS ((const struct sparc_opcode *)); 45static bfd_vma BSR PARAMS ((bfd_vma, int)); 46static int cmp_reg_entry PARAMS ((const PTR, const PTR)); 47static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *)); 48static int parse_const_expr_arg PARAMS ((char **, int *)); 49static int get_expression PARAMS ((char *str)); 50 51/* Default architecture. */ 52/* ??? The default value should be V8, but sparclite support was added 53 by making it the default. GCC now passes -Asparclite, so maybe sometime in 54 the future we can set this to V8. */ 55#ifndef DEFAULT_ARCH 56#define DEFAULT_ARCH "sparclite" 57#endif 58static char *default_arch = DEFAULT_ARCH; 59 60/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 61 have been set. */ 62static int default_init_p; 63 64/* Current architecture. We don't bump up unless necessary. */ 65static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 66 67/* The maximum architecture level we can bump up to. 68 In a 32 bit environment, don't allow bumping up to v9 by default. 69 The native assembler works this way. The user is required to pass 70 an explicit argument before we'll create v9 object files. However, if 71 we don't see any v9 insns, a v8plus object file is not created. */ 72static enum sparc_opcode_arch_val max_architecture; 73 74/* Either 32 or 64, selects file format. */ 75static int sparc_arch_size; 76/* Initial (default) value, recorded separately in case a user option 77 changes the value before md_show_usage is called. */ 78static int default_arch_size; 79 80#ifdef OBJ_ELF 81/* The currently selected v9 memory model. Currently only used for 82 ELF. */ 83static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 84#endif 85 86static int architecture_requested; 87static int warn_on_bump; 88 89/* If warn_on_bump and the needed architecture is higher than this 90 architecture, issue a warning. */ 91static enum sparc_opcode_arch_val warn_after_architecture; 92 93/* Non-zero if as should generate error if an undeclared g[23] register 94 has been used in -64. */ 95static int no_undeclared_regs; 96 97/* Non-zero if we should try to relax jumps and calls. */ 98static int sparc_relax; 99 100/* Non-zero if we are generating PIC code. */ 101int sparc_pic_code; 102 103/* Non-zero if we should give an error when misaligned data is seen. */ 104static int enforce_aligned_data; 105 106extern int target_big_endian; 107 108static int target_little_endian_data; 109 110/* Symbols for global registers on v9. */ 111static symbolS *globals[8]; 112 113/* V9 and 86x have big and little endian data, but instructions are always big 114 endian. The sparclet has bi-endian support but both data and insns have 115 the same endianness. Global `target_big_endian' is used for data. 116 The following macro is used for instructions. */ 117#ifndef INSN_BIG_ENDIAN 118#define INSN_BIG_ENDIAN (target_big_endian \ 119 || default_arch_type == sparc86x \ 120 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 121#endif 122 123/* Handle of the OPCODE hash table. */ 124static struct hash_control *op_hash; 125 126static int log2 PARAMS ((int)); 127static void s_data1 PARAMS ((void)); 128static void s_seg PARAMS ((int)); 129static void s_proc PARAMS ((int)); 130static void s_reserve PARAMS ((int)); 131static void s_common PARAMS ((int)); 132static void s_empty PARAMS ((int)); 133static void s_uacons PARAMS ((int)); 134static void s_ncons PARAMS ((int)); 135static void s_register PARAMS ((int)); 136 137const pseudo_typeS md_pseudo_table[] = 138{ 139 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 140 {"common", s_common, 0}, 141 {"empty", s_empty, 0}, 142 {"global", s_globl, 0}, 143 {"half", cons, 2}, 144 {"nword", s_ncons, 0}, 145 {"optim", s_ignore, 0}, 146 {"proc", s_proc, 0}, 147 {"reserve", s_reserve, 0}, 148 {"seg", s_seg, 0}, 149 {"skip", s_space, 0}, 150 {"word", cons, 4}, 151 {"xword", cons, 8}, 152 {"uahalf", s_uacons, 2}, 153 {"uaword", s_uacons, 4}, 154 {"uaxword", s_uacons, 8}, 155#ifdef OBJ_ELF 156 {"file", dwarf2_directive_file, 0}, 157 {"loc", dwarf2_directive_loc, 0}, 158 /* These are specific to sparc/svr4. */ 159 {"2byte", s_uacons, 2}, 160 {"4byte", s_uacons, 4}, 161 {"8byte", s_uacons, 8}, 162 {"register", s_register, 0}, 163#endif 164 {NULL, 0, 0}, 165}; 166 167/* Size of relocation record. */ 168const int md_reloc_size = 12; 169 170/* This array holds the chars that always start a comment. If the 171 pre-processor is disabled, these aren't very useful. */ 172const char comment_chars[] = "!"; /* JF removed '|' from 173 comment_chars. */ 174 175/* This array holds the chars that only start a comment at the beginning of 176 a line. If the line seems to have the form '# 123 filename' 177 .line and .file directives will appear in the pre-processed output. */ 178/* Note that input_file.c hand checks for '#' at the beginning of the 179 first line of the input file. This is because the compiler outputs 180 #NO_APP at the beginning of its output. */ 181/* Also note that comments started like this one will always 182 work if '/' isn't otherwise defined. */ 183const char line_comment_chars[] = "#"; 184 185const char line_separator_chars[] = ";"; 186 187/* Chars that can be used to separate mant from exp in floating point 188 nums. */ 189const char EXP_CHARS[] = "eE"; 190 191/* Chars that mean this number is a floating point constant. 192 As in 0f12.456 193 or 0d1.2345e12 */ 194const char FLT_CHARS[] = "rRsSfFdDxXpP"; 195 196/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 197 changed in read.c. Ideally it shouldn't have to know about it at all, 198 but nothing is ideal around here. */ 199 200#define isoctal(c) ((unsigned) ((c) - '0') < '8') 201 202struct sparc_it 203 { 204 char *error; 205 unsigned long opcode; 206 struct nlist *nlistp; 207 expressionS exp; 208 expressionS exp2; 209 int pcrel; 210 bfd_reloc_code_real_type reloc; 211 }; 212 213struct sparc_it the_insn, set_insn; 214 215static void output_insn 216 PARAMS ((const struct sparc_opcode *, struct sparc_it *)); 217 218/* Table of arguments to -A. 219 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 220 for this use. That table is for opcodes only. This table is for opcodes 221 and file formats. */ 222 223enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus, 224 v8plusa, v9, v9a, v9b, v9_64}; 225 226static struct sparc_arch { 227 char *name; 228 char *opcode_arch; 229 enum sparc_arch_types arch_type; 230 /* Default word size, as specified during configuration. 231 A value of zero means can't be used to specify default architecture. */ 232 int default_arch_size; 233 /* Allowable arg to -A? */ 234 int user_option_p; 235} sparc_arch_table[] = { 236 { "v6", "v6", v6, 0, 1 }, 237 { "v7", "v7", v7, 0, 1 }, 238 { "v8", "v8", v8, 32, 1 }, 239 { "sparclet", "sparclet", sparclet, 32, 1 }, 240 { "sparclite", "sparclite", sparclite, 32, 1 }, 241 { "sparc86x", "sparclite", sparc86x, 32, 1 }, 242 { "v8plus", "v9", v9, 0, 1 }, 243 { "v8plusa", "v9a", v9, 0, 1 }, 244 { "v8plusb", "v9b", v9, 0, 1 }, 245 { "v9", "v9", v9, 0, 1 }, 246 { "v9a", "v9a", v9, 0, 1 }, 247 { "v9b", "v9b", v9, 0, 1 }, 248 /* This exists to allow configure.in/Makefile.in to pass one 249 value to specify both the default machine and default word size. */ 250 { "v9-64", "v9", v9, 64, 0 }, 251 { NULL, NULL, v8, 0, 0 } 252}; 253 254/* Variant of default_arch */ 255static enum sparc_arch_types default_arch_type; 256 257static struct sparc_arch * 258lookup_arch (name) 259 char *name; 260{ 261 struct sparc_arch *sa; 262 263 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 264 if (strcmp (sa->name, name) == 0) 265 break; 266 if (sa->name == NULL) 267 return NULL; 268 return sa; 269} 270 271/* Initialize the default opcode arch and word size from the default 272 architecture name. */ 273 274static void 275init_default_arch () 276{ 277 struct sparc_arch *sa = lookup_arch (default_arch); 278 279 if (sa == NULL 280 || sa->default_arch_size == 0) 281 as_fatal (_("Invalid default architecture, broken assembler.")); 282 283 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 284 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 285 as_fatal (_("Bad opcode table, broken assembler.")); 286 default_arch_size = sparc_arch_size = sa->default_arch_size; 287 default_init_p = 1; 288 default_arch_type = sa->arch_type; 289} 290 291/* Called by TARGET_FORMAT. */ 292 293const char * 294sparc_target_format () 295{ 296 /* We don't get a chance to initialize anything before we're called, 297 so handle that now. */ 298 if (! default_init_p) 299 init_default_arch (); 300 301#ifdef OBJ_AOUT 302#ifdef TE_NetBSD 303 return "a.out-sparc-netbsd"; 304#else 305#ifdef TE_SPARCAOUT 306 if (target_big_endian) 307 return "a.out-sunos-big"; 308 else if (default_arch_type == sparc86x && target_little_endian_data) 309 return "a.out-sunos-big"; 310 else 311 return "a.out-sparc-little"; 312#else 313 return "a.out-sunos-big"; 314#endif 315#endif 316#endif 317 318#ifdef OBJ_BOUT 319 return "b.out.big"; 320#endif 321 322#ifdef OBJ_COFF 323#ifdef TE_LYNX 324 return "coff-sparc-lynx"; 325#else 326 return "coff-sparc"; 327#endif 328#endif 329 330#ifdef OBJ_ELF 331 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc"; 332#endif 333 334 abort (); 335} 336 337/* md_parse_option 338 * Invocation line includes a switch not recognized by the base assembler. 339 * See if it's a processor-specific option. These are: 340 * 341 * -bump 342 * Warn on architecture bumps. See also -A. 343 * 344 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet 345 * Standard 32 bit architectures. 346 * -Av9, -Av9a, -Av9b 347 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 348 * This used to only mean 64 bits, but properly specifying it 349 * complicated gcc's ASM_SPECs, so now opcode selection is 350 * specified orthogonally to word size (except when specifying 351 * the default, but that is an internal implementation detail). 352 * -Av8plus, -Av8plusa, -Av8plusb 353 * Same as -Av9{,a,b}. 354 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 355 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 356 * assembler. 357 * -xarch=v9, -xarch=v9a, -xarch=v9b 358 * Same as -Av9{,a,b} -64, for compatibility with Sun's 359 * assembler. 360 * 361 * Select the architecture and possibly the file format. 362 * Instructions or features not supported by the selected 363 * architecture cause fatal errors. 364 * 365 * The default is to start at v6, and bump the architecture up 366 * whenever an instruction is seen at a higher level. In 32 bit 367 * environments, v9 is not bumped up to, the user must pass 368 * -Av8plus{,a,b}. 369 * 370 * If -bump is specified, a warning is printing when bumping to 371 * higher levels. 372 * 373 * If an architecture is specified, all instructions must match 374 * that architecture. Any higher level instructions are flagged 375 * as errors. Note that in the 32 bit environment specifying 376 * -Av8plus does not automatically create a v8plus object file, a 377 * v9 insn must be seen. 378 * 379 * If both an architecture and -bump are specified, the 380 * architecture starts at the specified level, but bumps are 381 * warnings. Note that we can't set `current_architecture' to 382 * the requested level in this case: in the 32 bit environment, 383 * we still must avoid creating v8plus object files unless v9 384 * insns are seen. 385 * 386 * Note: 387 * Bumping between incompatible architectures is always an 388 * error. For example, from sparclite to v9. 389 */ 390 391#ifdef OBJ_ELF 392CONST char *md_shortopts = "A:K:VQ:sq"; 393#else 394#ifdef OBJ_AOUT 395CONST char *md_shortopts = "A:k"; 396#else 397CONST char *md_shortopts = "A:"; 398#endif 399#endif 400struct option md_longopts[] = { 401#define OPTION_BUMP (OPTION_MD_BASE) 402 {"bump", no_argument, NULL, OPTION_BUMP}, 403#define OPTION_SPARC (OPTION_MD_BASE + 1) 404 {"sparc", no_argument, NULL, OPTION_SPARC}, 405#define OPTION_XARCH (OPTION_MD_BASE + 2) 406 {"xarch", required_argument, NULL, OPTION_XARCH}, 407#ifdef OBJ_ELF 408#define OPTION_32 (OPTION_MD_BASE + 3) 409 {"32", no_argument, NULL, OPTION_32}, 410#define OPTION_64 (OPTION_MD_BASE + 4) 411 {"64", no_argument, NULL, OPTION_64}, 412#define OPTION_TSO (OPTION_MD_BASE + 5) 413 {"TSO", no_argument, NULL, OPTION_TSO}, 414#define OPTION_PSO (OPTION_MD_BASE + 6) 415 {"PSO", no_argument, NULL, OPTION_PSO}, 416#define OPTION_RMO (OPTION_MD_BASE + 7) 417 {"RMO", no_argument, NULL, OPTION_RMO}, 418#endif 419#ifdef SPARC_BIENDIAN 420#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 421 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 422#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 423 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 424#endif 425#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 426 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 427#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 428 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 429#ifdef OBJ_ELF 430#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 431 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 432#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 433 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 434#endif 435#define OPTION_RELAX (OPTION_MD_BASE + 14) 436 {"relax", no_argument, NULL, OPTION_RELAX}, 437#define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 438 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 439 {NULL, no_argument, NULL, 0} 440}; 441 442size_t md_longopts_size = sizeof (md_longopts); 443 444int 445md_parse_option (c, arg) 446 int c; 447 char *arg; 448{ 449 /* We don't get a chance to initialize anything before we're called, 450 so handle that now. */ 451 if (! default_init_p) 452 init_default_arch (); 453 454 switch (c) 455 { 456 case OPTION_BUMP: 457 warn_on_bump = 1; 458 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 459 break; 460 461 case OPTION_XARCH: 462#ifdef OBJ_ELF 463 if (strncmp (arg, "v9", 2) != 0) 464 md_parse_option (OPTION_32, NULL); 465 else 466 md_parse_option (OPTION_64, NULL); 467#endif 468 /* Fall through. */ 469 470 case 'A': 471 { 472 struct sparc_arch *sa; 473 enum sparc_opcode_arch_val opcode_arch; 474 475 sa = lookup_arch (arg); 476 if (sa == NULL 477 || ! sa->user_option_p) 478 { 479 if (c == OPTION_XARCH) 480 as_bad (_("invalid architecture -xarch=%s"), arg); 481 else 482 as_bad (_("invalid architecture -A%s"), arg); 483 return 0; 484 } 485 486 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 487 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 488 as_fatal (_("Bad opcode table, broken assembler.")); 489 490 max_architecture = opcode_arch; 491 architecture_requested = 1; 492 } 493 break; 494 495 case OPTION_SPARC: 496 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 497 break; 498 499 case OPTION_ENFORCE_ALIGNED_DATA: 500 enforce_aligned_data = 1; 501 break; 502 503#ifdef SPARC_BIENDIAN 504 case OPTION_LITTLE_ENDIAN: 505 target_big_endian = 0; 506 if (default_arch_type != sparclet) 507 as_fatal ("This target does not support -EL"); 508 break; 509 case OPTION_LITTLE_ENDIAN_DATA: 510 target_little_endian_data = 1; 511 target_big_endian = 0; 512 if (default_arch_type != sparc86x 513 && default_arch_type != v9) 514 as_fatal ("This target does not support --little-endian-data"); 515 break; 516 case OPTION_BIG_ENDIAN: 517 target_big_endian = 1; 518 break; 519#endif 520 521#ifdef OBJ_AOUT 522 case 'k': 523 sparc_pic_code = 1; 524 break; 525#endif 526 527#ifdef OBJ_ELF 528 case OPTION_32: 529 case OPTION_64: 530 { 531 const char **list, **l; 532 533 sparc_arch_size = c == OPTION_32 ? 32 : 64; 534 list = bfd_target_list (); 535 for (l = list; *l != NULL; l++) 536 { 537 if (sparc_arch_size == 32) 538 { 539 if (strcmp (*l, "elf32-sparc") == 0) 540 break; 541 } 542 else 543 { 544 if (strcmp (*l, "elf64-sparc") == 0) 545 break; 546 } 547 } 548 if (*l == NULL) 549 as_fatal (_("No compiled in support for %d bit object file format"), 550 sparc_arch_size); 551 free (list); 552 } 553 break; 554 555 case OPTION_TSO: 556 sparc_memory_model = MM_TSO; 557 break; 558 559 case OPTION_PSO: 560 sparc_memory_model = MM_PSO; 561 break; 562 563 case OPTION_RMO: 564 sparc_memory_model = MM_RMO; 565 break; 566 567 case 'V': 568 print_version_id (); 569 break; 570 571 case 'Q': 572 /* Qy - do emit .comment 573 Qn - do not emit .comment. */ 574 break; 575 576 case 's': 577 /* Use .stab instead of .stab.excl. */ 578 break; 579 580 case 'q': 581 /* quick -- Native assembler does fewer checks. */ 582 break; 583 584 case 'K': 585 if (strcmp (arg, "PIC") != 0) 586 as_warn (_("Unrecognized option following -K")); 587 else 588 sparc_pic_code = 1; 589 break; 590 591 case OPTION_NO_UNDECLARED_REGS: 592 no_undeclared_regs = 1; 593 break; 594 595 case OPTION_UNDECLARED_REGS: 596 no_undeclared_regs = 0; 597 break; 598#endif 599 600 case OPTION_RELAX: 601 sparc_relax = 1; 602 break; 603 604 case OPTION_NO_RELAX: 605 sparc_relax = 0; 606 break; 607 608 default: 609 return 0; 610 } 611 612 return 1; 613} 614 615void 616md_show_usage (stream) 617 FILE *stream; 618{ 619 const struct sparc_arch *arch; 620 int column; 621 622 /* We don't get a chance to initialize anything before we're called, 623 so handle that now. */ 624 if (! default_init_p) 625 init_default_arch (); 626 627 fprintf (stream, _("SPARC options:\n")); 628 column = 0; 629 for (arch = &sparc_arch_table[0]; arch->name; arch++) 630 { 631 if (!arch->user_option_p) 632 continue; 633 if (arch != &sparc_arch_table[0]) 634 fprintf (stream, " | "); 635 if (column + strlen(arch->name) > 70) 636 { 637 column = 0; 638 fputc ('\n', stream); 639 } 640 column += 5 + 2 + strlen(arch->name); 641 fprintf (stream, "-A%s", arch->name); 642 } 643 for (arch = &sparc_arch_table[0]; arch->name; arch++) 644 { 645 if (!arch->user_option_p) 646 continue; 647 fprintf (stream, " | "); 648 if (column + strlen(arch->name) > 65) 649 { 650 column = 0; 651 fputc ('\n', stream); 652 } 653 column += 5 + 7 + strlen(arch->name); 654 fprintf (stream, "-xarch=%s", arch->name); 655 } 656 fprintf (stream, _("\n\ 657 specify variant of SPARC architecture\n\ 658-bump warn when assembler switches architectures\n\ 659-sparc ignored\n\ 660--enforce-aligned-data force .long, etc., to be aligned correctly\n\ 661-relax relax jumps and branches (default)\n\ 662-no-relax avoid changing any jumps and branches\n")); 663#ifdef OBJ_AOUT 664 fprintf (stream, _("\ 665-k generate PIC\n")); 666#endif 667#ifdef OBJ_ELF 668 fprintf (stream, _("\ 669-32 create 32 bit object file\n\ 670-64 create 64 bit object file\n")); 671 fprintf (stream, _("\ 672 [default is %d]\n"), default_arch_size); 673 fprintf (stream, _("\ 674-TSO use Total Store Ordering\n\ 675-PSO use Partial Store Ordering\n\ 676-RMO use Relaxed Memory Ordering\n")); 677 fprintf (stream, _("\ 678 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 679 fprintf (stream, _("\ 680-KPIC generate PIC\n\ 681-V print assembler version number\n\ 682-undeclared-regs ignore application global register usage without\n\ 683 appropriate .register directive (default)\n\ 684-no-undeclared-regs force error on application global register usage\n\ 685 without appropriate .register directive\n\ 686-q ignored\n\ 687-Qy, -Qn ignored\n\ 688-s ignored\n")); 689#endif 690#ifdef SPARC_BIENDIAN 691 fprintf (stream, _("\ 692-EL generate code for a little endian machine\n\ 693-EB generate code for a big endian machine\n\ 694--little-endian-data generate code for a machine having big endian\n\ 695 instructions and little endian data.\n")); 696#endif 697} 698 699/* Native operand size opcode translation. */ 700struct 701 { 702 char *name; 703 char *name32; 704 char *name64; 705 } native_op_table[] = 706{ 707 {"ldn", "ld", "ldx"}, 708 {"ldna", "lda", "ldxa"}, 709 {"stn", "st", "stx"}, 710 {"stna", "sta", "stxa"}, 711 {"slln", "sll", "sllx"}, 712 {"srln", "srl", "srlx"}, 713 {"sran", "sra", "srax"}, 714 {"casn", "cas", "casx"}, 715 {"casna", "casa", "casxa"}, 716 {"clrn", "clr", "clrx"}, 717 {NULL, NULL, NULL}, 718}; 719 720/* sparc64 priviledged registers. */ 721 722struct priv_reg_entry 723{ 724 char *name; 725 int regnum; 726}; 727 728struct priv_reg_entry priv_reg_table[] = 729{ 730 {"tpc", 0}, 731 {"tnpc", 1}, 732 {"tstate", 2}, 733 {"tt", 3}, 734 {"tick", 4}, 735 {"tba", 5}, 736 {"pstate", 6}, 737 {"tl", 7}, 738 {"pil", 8}, 739 {"cwp", 9}, 740 {"cansave", 10}, 741 {"canrestore", 11}, 742 {"cleanwin", 12}, 743 {"otherwin", 13}, 744 {"wstate", 14}, 745 {"fq", 15}, 746 {"ver", 31}, 747 {"", -1}, /* End marker. */ 748}; 749 750/* v9a specific asrs. */ 751 752struct priv_reg_entry v9a_asr_table[] = 753{ 754 {"tick_cmpr", 23}, 755 {"sys_tick_cmpr", 25}, 756 {"sys_tick", 24}, 757 {"softint", 22}, 758 {"set_softint", 20}, 759 {"pic", 17}, 760 {"pcr", 16}, 761 {"gsr", 19}, 762 {"dcr", 18}, 763 {"clear_softint", 21}, 764 {"", -1}, /* End marker. */ 765}; 766 767static int 768cmp_reg_entry (parg, qarg) 769 const PTR parg; 770 const PTR qarg; 771{ 772 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 773 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 774 775 return strcmp (q->name, p->name); 776} 777 778/* This function is called once, at assembler startup time. It should 779 set up all the tables, etc. that the MD part of the assembler will 780 need. */ 781 782void 783md_begin () 784{ 785 register const char *retval = NULL; 786 int lose = 0; 787 register unsigned int i = 0; 788 789 /* We don't get a chance to initialize anything before md_parse_option 790 is called, and it may not be called, so handle default initialization 791 now if not already done. */ 792 if (! default_init_p) 793 init_default_arch (); 794 795 op_hash = hash_new (); 796 797 while (i < (unsigned int) sparc_num_opcodes) 798 { 799 const char *name = sparc_opcodes[i].name; 800 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]); 801 if (retval != NULL) 802 { 803 as_bad (_("Internal error: can't hash `%s': %s\n"), 804 sparc_opcodes[i].name, retval); 805 lose = 1; 806 } 807 do 808 { 809 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 810 { 811 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 812 sparc_opcodes[i].name, sparc_opcodes[i].args); 813 lose = 1; 814 } 815 ++i; 816 } 817 while (i < (unsigned int) sparc_num_opcodes 818 && !strcmp (sparc_opcodes[i].name, name)); 819 } 820 821 for (i = 0; native_op_table[i].name; i++) 822 { 823 const struct sparc_opcode *insn; 824 char *name = ((sparc_arch_size == 32) 825 ? native_op_table[i].name32 826 : native_op_table[i].name64); 827 insn = (struct sparc_opcode *) hash_find (op_hash, name); 828 if (insn == NULL) 829 { 830 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 831 name, native_op_table[i].name); 832 lose = 1; 833 } 834 else 835 { 836 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn); 837 if (retval != NULL) 838 { 839 as_bad (_("Internal error: can't hash `%s': %s\n"), 840 sparc_opcodes[i].name, retval); 841 lose = 1; 842 } 843 } 844 } 845 846 if (lose) 847 as_fatal (_("Broken assembler. No assembly attempted.")); 848 849 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 850 sizeof (priv_reg_table[0]), cmp_reg_entry); 851 852 /* If -bump, record the architecture level at which we start issuing 853 warnings. The behaviour is different depending upon whether an 854 architecture was explicitly specified. If it wasn't, we issue warnings 855 for all upwards bumps. If it was, we don't start issuing warnings until 856 we need to bump beyond the requested architecture or when we bump between 857 conflicting architectures. */ 858 859 if (warn_on_bump 860 && architecture_requested) 861 { 862 /* `max_architecture' records the requested architecture. 863 Issue warnings if we go above it. */ 864 warn_after_architecture = max_architecture; 865 866 /* Find the highest architecture level that doesn't conflict with 867 the requested one. */ 868 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 869 max_architecture > warn_after_architecture; 870 --max_architecture) 871 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 872 warn_after_architecture)) 873 break; 874 } 875} 876 877/* Called after all assembly has been done. */ 878 879void 880sparc_md_end () 881{ 882 unsigned long mach = bfd_mach_sparc; 883 884 if (sparc_arch_size == 64) 885 switch (current_architecture) 886 { 887 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 888 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 889 default: mach = bfd_mach_sparc_v9; break; 890 } 891 else 892 switch (current_architecture) 893 { 894 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 895 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 896 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 897 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 898 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 899 be but for now it is (since that's the way it's always been 900 treated). */ 901 default: break; 902 } 903 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 904} 905 906/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 907 908static INLINE int 909in_signed_range (val, max) 910 bfd_signed_vma val, max; 911{ 912 if (max <= 0) 913 abort (); 914 /* Sign-extend the value from the architecture word size, so that 915 0xffffffff is always considered -1 on sparc32. */ 916 if (sparc_arch_size == 32) 917 { 918 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 919 val = ((val & 0xffffffff) ^ sign) - sign; 920 } 921 if (val > max) 922 return 0; 923 if (val < ~max) 924 return 0; 925 return 1; 926} 927 928/* Return non-zero if VAL is in the range 0 to MAX. */ 929 930static INLINE int 931in_unsigned_range (val, max) 932 bfd_vma val, max; 933{ 934 if (val > max) 935 return 0; 936 return 1; 937} 938 939/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 940 (e.g. -15 to +31). */ 941 942static INLINE int 943in_bitfield_range (val, max) 944 bfd_signed_vma val, max; 945{ 946 if (max <= 0) 947 abort (); 948 if (val > max) 949 return 0; 950 if (val < ~(max >> 1)) 951 return 0; 952 return 1; 953} 954 955static int 956sparc_ffs (mask) 957 unsigned int mask; 958{ 959 int i; 960 961 if (mask == 0) 962 return -1; 963 964 for (i = 0; (mask & 1) == 0; ++i) 965 mask >>= 1; 966 return i; 967} 968 969/* Implement big shift right. */ 970static bfd_vma 971BSR (val, amount) 972 bfd_vma val; 973 int amount; 974{ 975 if (sizeof (bfd_vma) <= 4 && amount >= 32) 976 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 977 return val >> amount; 978} 979 980/* For communication between sparc_ip and get_expression. */ 981static char *expr_end; 982 983/* Values for `special_case'. 984 Instructions that require wierd handling because they're longer than 985 4 bytes. */ 986#define SPECIAL_CASE_NONE 0 987#define SPECIAL_CASE_SET 1 988#define SPECIAL_CASE_SETSW 2 989#define SPECIAL_CASE_SETX 3 990/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 991#define SPECIAL_CASE_FDIV 4 992 993/* Bit masks of various insns. */ 994#define NOP_INSN 0x01000000 995#define OR_INSN 0x80100000 996#define XOR_INSN 0x80180000 997#define FMOVS_INSN 0x81A00020 998#define SETHI_INSN 0x01000000 999#define SLLX_INSN 0x81281000 1000#define SRA_INSN 0x81380000 1001 1002/* The last instruction to be assembled. */ 1003static const struct sparc_opcode *last_insn; 1004/* The assembled opcode of `last_insn'. */ 1005static unsigned long last_opcode; 1006 1007/* Handle the set and setuw synthetic instructions. */ 1008 1009static void 1010synthetize_setuw (insn) 1011 const struct sparc_opcode *insn; 1012{ 1013 int need_hi22_p = 0; 1014 int rd = (the_insn.opcode & RD (~0)) >> 25; 1015 1016 if (the_insn.exp.X_op == O_constant) 1017 { 1018 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1019 { 1020 if (sizeof (offsetT) > 4 1021 && (the_insn.exp.X_add_number < 0 1022 || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) 1023 as_warn (_("set: number not in 0..4294967295 range")); 1024 } 1025 else 1026 { 1027 if (sizeof (offsetT) > 4 1028 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 1029 || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) 1030 as_warn (_("set: number not in -2147483648..4294967295 range")); 1031 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1032 } 1033 } 1034 1035 /* See if operand is absolute and small; skip sethi if so. */ 1036 if (the_insn.exp.X_op != O_constant 1037 || the_insn.exp.X_add_number >= (1 << 12) 1038 || the_insn.exp.X_add_number < -(1 << 12)) 1039 { 1040 the_insn.opcode = (SETHI_INSN | RD (rd) 1041 | ((the_insn.exp.X_add_number >> 10) 1042 & (the_insn.exp.X_op == O_constant 1043 ? 0x3fffff : 0))); 1044 the_insn.reloc = (the_insn.exp.X_op != O_constant 1045 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1046 output_insn (insn, &the_insn); 1047 need_hi22_p = 1; 1048 } 1049 1050 /* See if operand has no low-order bits; skip OR if so. */ 1051 if (the_insn.exp.X_op != O_constant 1052 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1053 || ! need_hi22_p) 1054 { 1055 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1056 | RD (rd) | IMMED 1057 | (the_insn.exp.X_add_number 1058 & (the_insn.exp.X_op != O_constant 1059 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1060 the_insn.reloc = (the_insn.exp.X_op != O_constant 1061 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1062 output_insn (insn, &the_insn); 1063 } 1064} 1065 1066/* Handle the setsw synthetic instruction. */ 1067 1068static void 1069synthetize_setsw (insn) 1070 const struct sparc_opcode *insn; 1071{ 1072 int low32, rd, opc; 1073 1074 rd = (the_insn.opcode & RD (~0)) >> 25; 1075 1076 if (the_insn.exp.X_op != O_constant) 1077 { 1078 synthetize_setuw (insn); 1079 1080 /* Need to sign extend it. */ 1081 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1082 the_insn.reloc = BFD_RELOC_NONE; 1083 output_insn (insn, &the_insn); 1084 return; 1085 } 1086 1087 if (sizeof (offsetT) > 4 1088 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000 1089 || the_insn.exp.X_add_number > (offsetT) 0xffffffff)) 1090 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1091 1092 low32 = the_insn.exp.X_add_number; 1093 1094 if (low32 >= 0) 1095 { 1096 synthetize_setuw (insn); 1097 return; 1098 } 1099 1100 opc = OR_INSN; 1101 1102 the_insn.reloc = BFD_RELOC_NONE; 1103 /* See if operand is absolute and small; skip sethi if so. */ 1104 if (low32 < -(1 << 12)) 1105 { 1106 the_insn.opcode = (SETHI_INSN | RD (rd) 1107 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1108 output_insn (insn, &the_insn); 1109 low32 = 0x1c00 | (low32 & 0x3ff); 1110 opc = RS1 (rd) | XOR_INSN; 1111 } 1112 1113 the_insn.opcode = (opc | RD (rd) | IMMED 1114 | (low32 & 0x1fff)); 1115 output_insn (insn, &the_insn); 1116} 1117 1118/* Handle the setsw synthetic instruction. */ 1119 1120static void 1121synthetize_setx (insn) 1122 const struct sparc_opcode *insn; 1123{ 1124 int upper32, lower32; 1125 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1126 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1127 int upper_dstreg; 1128 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1129 int need_xor10_p = 0; 1130 1131#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000) 1132 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1133 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1134#undef SIGNEXT32 1135 1136 upper_dstreg = tmpreg; 1137 /* The tmp reg should not be the dst reg. */ 1138 if (tmpreg == dstreg) 1139 as_warn (_("setx: temporary register same as destination register")); 1140 1141 /* ??? Obviously there are other optimizations we can do 1142 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1143 doing some of these. Later. If you do change things, try to 1144 change all of this to be table driven as well. */ 1145 /* What to output depends on the number if it's constant. 1146 Compute that first, then output what we've decided upon. */ 1147 if (the_insn.exp.X_op != O_constant) 1148 { 1149 if (sparc_arch_size == 32) 1150 { 1151 /* When arch size is 32, we want setx to be equivalent 1152 to setuw for anything but constants. */ 1153 the_insn.exp.X_add_number &= 0xffffffff; 1154 synthetize_setuw (insn); 1155 return; 1156 } 1157 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1158 lower32 = 0; 1159 upper32 = 0; 1160 } 1161 else 1162 { 1163 /* Reset X_add_number, we've extracted it as upper32/lower32. 1164 Otherwise fixup_segment will complain about not being able to 1165 write an 8 byte number in a 4 byte field. */ 1166 the_insn.exp.X_add_number = 0; 1167 1168 /* Only need hh22 if `or' insn can't handle constant. */ 1169 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1170 need_hh22_p = 1; 1171 1172 /* Does bottom part (after sethi) have bits? */ 1173 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1174 /* No hh22, but does upper32 still have bits we can't set 1175 from lower32? */ 1176 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1177 need_hm10_p = 1; 1178 1179 /* If the lower half is all zero, we build the upper half directly 1180 into the dst reg. */ 1181 if (lower32 != 0 1182 /* Need lower half if number is zero or 0xffffffff00000000. */ 1183 || (! need_hh22_p && ! need_hm10_p)) 1184 { 1185 /* No need for sethi if `or' insn can handle constant. */ 1186 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1187 /* Note that we can't use a negative constant in the `or' 1188 insn unless the upper 32 bits are all ones. */ 1189 || (lower32 < 0 && upper32 != -1) 1190 || (lower32 >= 0 && upper32 == -1)) 1191 need_hi22_p = 1; 1192 1193 if (need_hi22_p && upper32 == -1) 1194 need_xor10_p = 1; 1195 1196 /* Does bottom part (after sethi) have bits? */ 1197 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1198 /* No sethi. */ 1199 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1200 /* Need `or' if we didn't set anything else. */ 1201 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1202 need_lo10_p = 1; 1203 } 1204 else 1205 /* Output directly to dst reg if lower 32 bits are all zero. */ 1206 upper_dstreg = dstreg; 1207 } 1208 1209 if (!upper_dstreg && dstreg) 1210 as_warn (_("setx: illegal temporary register g0")); 1211 1212 if (need_hh22_p) 1213 { 1214 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1215 | ((upper32 >> 10) & 0x3fffff)); 1216 the_insn.reloc = (the_insn.exp.X_op != O_constant 1217 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1218 output_insn (insn, &the_insn); 1219 } 1220 1221 if (need_hi22_p) 1222 { 1223 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1224 | (((need_xor10_p ? ~lower32 : lower32) 1225 >> 10) & 0x3fffff)); 1226 the_insn.reloc = (the_insn.exp.X_op != O_constant 1227 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1228 output_insn (insn, &the_insn); 1229 } 1230 1231 if (need_hm10_p) 1232 { 1233 the_insn.opcode = (OR_INSN 1234 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1235 | RD (upper_dstreg) 1236 | IMMED 1237 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1238 the_insn.reloc = (the_insn.exp.X_op != O_constant 1239 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1240 output_insn (insn, &the_insn); 1241 } 1242 1243 if (need_lo10_p) 1244 { 1245 /* FIXME: One nice optimization to do here is to OR the low part 1246 with the highpart if hi22 isn't needed and the low part is 1247 positive. */ 1248 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1249 | RD (dstreg) 1250 | IMMED 1251 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1252 the_insn.reloc = (the_insn.exp.X_op != O_constant 1253 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1254 output_insn (insn, &the_insn); 1255 } 1256 1257 /* If we needed to build the upper part, shift it into place. */ 1258 if (need_hh22_p || need_hm10_p) 1259 { 1260 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1261 | IMMED | 32); 1262 the_insn.reloc = BFD_RELOC_NONE; 1263 output_insn (insn, &the_insn); 1264 } 1265 1266 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1267 if (need_xor10_p) 1268 { 1269 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1270 | 0x1c00 | (lower32 & 0x3ff)); 1271 the_insn.reloc = BFD_RELOC_NONE; 1272 output_insn (insn, &the_insn); 1273 } 1274 1275 /* If we needed to build both upper and lower parts, OR them together. */ 1276 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1277 { 1278 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1279 | RD (dstreg)); 1280 the_insn.reloc = BFD_RELOC_NONE; 1281 output_insn (insn, &the_insn); 1282 } 1283} 1284 1285/* Main entry point to assemble one instruction. */ 1286 1287void 1288md_assemble (str) 1289 char *str; 1290{ 1291 const struct sparc_opcode *insn; 1292 int special_case; 1293 1294 know (str); 1295 special_case = sparc_ip (str, &insn); 1296 1297 /* We warn about attempts to put a floating point branch in a delay slot, 1298 unless the delay slot has been annulled. */ 1299 if (insn != NULL 1300 && last_insn != NULL 1301 && (insn->flags & F_FBR) != 0 1302 && (last_insn->flags & F_DELAYED) != 0 1303 /* ??? This test isn't completely accurate. We assume anything with 1304 F_{UNBR,CONDBR,FBR} set is annullable. */ 1305 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1306 || (last_opcode & ANNUL) == 0)) 1307 as_warn (_("FP branch in delay slot")); 1308 1309 /* SPARC before v9 requires a nop instruction between a floating 1310 point instruction and a floating point branch. We insert one 1311 automatically, with a warning. */ 1312 if (max_architecture < SPARC_OPCODE_ARCH_V9 1313 && insn != NULL 1314 && last_insn != NULL 1315 && (insn->flags & F_FBR) != 0 1316 && (last_insn->flags & F_FLOAT) != 0) 1317 { 1318 struct sparc_it nop_insn; 1319 1320 nop_insn.opcode = NOP_INSN; 1321 nop_insn.reloc = BFD_RELOC_NONE; 1322 output_insn (insn, &nop_insn); 1323 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1324 } 1325 1326 switch (special_case) 1327 { 1328 case SPECIAL_CASE_NONE: 1329 /* Normal insn. */ 1330 output_insn (insn, &the_insn); 1331 break; 1332 1333 case SPECIAL_CASE_SETSW: 1334 synthetize_setsw (insn); 1335 break; 1336 1337 case SPECIAL_CASE_SET: 1338 synthetize_setuw (insn); 1339 break; 1340 1341 case SPECIAL_CASE_SETX: 1342 synthetize_setx (insn); 1343 break; 1344 1345 case SPECIAL_CASE_FDIV: 1346 { 1347 int rd = (the_insn.opcode >> 25) & 0x1f; 1348 1349 output_insn (insn, &the_insn); 1350 1351 /* According to information leaked from Sun, the "fdiv" instructions 1352 on early SPARC machines would produce incorrect results sometimes. 1353 The workaround is to add an fmovs of the destination register to 1354 itself just after the instruction. This was true on machines 1355 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1356 assert (the_insn.reloc == BFD_RELOC_NONE); 1357 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1358 output_insn (insn, &the_insn); 1359 return; 1360 } 1361 1362 default: 1363 as_fatal (_("failed special case insn sanity check")); 1364 } 1365} 1366 1367/* Subroutine of md_assemble to do the actual parsing. */ 1368 1369static int 1370sparc_ip (str, pinsn) 1371 char *str; 1372 const struct sparc_opcode **pinsn; 1373{ 1374 char *error_message = ""; 1375 char *s; 1376 const char *args; 1377 char c; 1378 const struct sparc_opcode *insn; 1379 char *argsStart; 1380 unsigned long opcode; 1381 unsigned int mask = 0; 1382 int match = 0; 1383 int comma = 0; 1384 int v9_arg_p; 1385 int special_case = SPECIAL_CASE_NONE; 1386 1387 s = str; 1388 if (islower ((unsigned char) *s)) 1389 { 1390 do 1391 ++s; 1392 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s)); 1393 } 1394 1395 switch (*s) 1396 { 1397 case '\0': 1398 break; 1399 1400 case ',': 1401 comma = 1; 1402 /* Fall through. */ 1403 1404 case ' ': 1405 *s++ = '\0'; 1406 break; 1407 1408 default: 1409 as_fatal (_("Unknown opcode: `%s'"), str); 1410 } 1411 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1412 *pinsn = insn; 1413 if (insn == NULL) 1414 { 1415 as_bad (_("Unknown opcode: `%s'"), str); 1416 return special_case; 1417 } 1418 if (comma) 1419 { 1420 *--s = ','; 1421 } 1422 1423 argsStart = s; 1424 for (;;) 1425 { 1426 opcode = insn->match; 1427 memset (&the_insn, '\0', sizeof (the_insn)); 1428 the_insn.reloc = BFD_RELOC_NONE; 1429 v9_arg_p = 0; 1430 1431 /* Build the opcode, checking as we go to make sure that the 1432 operands match. */ 1433 for (args = insn->args;; ++args) 1434 { 1435 switch (*args) 1436 { 1437 case 'K': 1438 { 1439 int kmask = 0; 1440 1441 /* Parse a series of masks. */ 1442 if (*s == '#') 1443 { 1444 while (*s == '#') 1445 { 1446 int mask; 1447 1448 if (! parse_keyword_arg (sparc_encode_membar, &s, 1449 &mask)) 1450 { 1451 error_message = _(": invalid membar mask name"); 1452 goto error; 1453 } 1454 kmask |= mask; 1455 while (*s == ' ') 1456 ++s; 1457 if (*s == '|' || *s == '+') 1458 ++s; 1459 while (*s == ' ') 1460 ++s; 1461 } 1462 } 1463 else 1464 { 1465 if (! parse_const_expr_arg (&s, &kmask)) 1466 { 1467 error_message = _(": invalid membar mask expression"); 1468 goto error; 1469 } 1470 if (kmask < 0 || kmask > 127) 1471 { 1472 error_message = _(": invalid membar mask number"); 1473 goto error; 1474 } 1475 } 1476 1477 opcode |= MEMBAR (kmask); 1478 continue; 1479 } 1480 1481 case '3': 1482 { 1483 int smask = 0; 1484 1485 if (! parse_const_expr_arg (&s, &smask)) 1486 { 1487 error_message = _(": invalid siam mode expression"); 1488 goto error; 1489 } 1490 if (smask < 0 || smask > 7) 1491 { 1492 error_message = _(": invalid siam mode number"); 1493 goto error; 1494 } 1495 opcode |= smask; 1496 continue; 1497 } 1498 1499 case '*': 1500 { 1501 int fcn = 0; 1502 1503 /* Parse a prefetch function. */ 1504 if (*s == '#') 1505 { 1506 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1507 { 1508 error_message = _(": invalid prefetch function name"); 1509 goto error; 1510 } 1511 } 1512 else 1513 { 1514 if (! parse_const_expr_arg (&s, &fcn)) 1515 { 1516 error_message = _(": invalid prefetch function expression"); 1517 goto error; 1518 } 1519 if (fcn < 0 || fcn > 31) 1520 { 1521 error_message = _(": invalid prefetch function number"); 1522 goto error; 1523 } 1524 } 1525 opcode |= RD (fcn); 1526 continue; 1527 } 1528 1529 case '!': 1530 case '?': 1531 /* Parse a sparc64 privileged register. */ 1532 if (*s == '%') 1533 { 1534 struct priv_reg_entry *p = priv_reg_table; 1535 unsigned int len = 9999999; /* Init to make gcc happy. */ 1536 1537 s += 1; 1538 while (p->name[0] > s[0]) 1539 p++; 1540 while (p->name[0] == s[0]) 1541 { 1542 len = strlen (p->name); 1543 if (strncmp (p->name, s, len) == 0) 1544 break; 1545 p++; 1546 } 1547 if (p->name[0] != s[0]) 1548 { 1549 error_message = _(": unrecognizable privileged register"); 1550 goto error; 1551 } 1552 if (*args == '?') 1553 opcode |= (p->regnum << 14); 1554 else 1555 opcode |= (p->regnum << 25); 1556 s += len; 1557 continue; 1558 } 1559 else 1560 { 1561 error_message = _(": unrecognizable privileged register"); 1562 goto error; 1563 } 1564 1565 case '_': 1566 case '/': 1567 /* Parse a v9a/v9b ancillary state register. */ 1568 if (*s == '%') 1569 { 1570 struct priv_reg_entry *p = v9a_asr_table; 1571 unsigned int len = 9999999; /* Init to make gcc happy. */ 1572 1573 s += 1; 1574 while (p->name[0] > s[0]) 1575 p++; 1576 while (p->name[0] == s[0]) 1577 { 1578 len = strlen (p->name); 1579 if (strncmp (p->name, s, len) == 0) 1580 break; 1581 p++; 1582 } 1583 if (p->name[0] != s[0]) 1584 { 1585 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1586 goto error; 1587 } 1588 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1589 { 1590 error_message = _(": rd on write only ancillary state register"); 1591 goto error; 1592 } 1593 if (p->regnum >= 24 1594 && (insn->architecture 1595 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1596 { 1597 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1598 error_message = _(": unrecognizable v9a ancillary state register"); 1599 goto error; 1600 } 1601 if (*args == '/') 1602 opcode |= (p->regnum << 14); 1603 else 1604 opcode |= (p->regnum << 25); 1605 s += len; 1606 continue; 1607 } 1608 else 1609 { 1610 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1611 goto error; 1612 } 1613 1614 case 'M': 1615 case 'm': 1616 if (strncmp (s, "%asr", 4) == 0) 1617 { 1618 s += 4; 1619 1620 if (isdigit ((unsigned char) *s)) 1621 { 1622 long num = 0; 1623 1624 while (isdigit ((unsigned char) *s)) 1625 { 1626 num = num * 10 + *s - '0'; 1627 ++s; 1628 } 1629 1630 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1631 { 1632 if (num < 16 || 31 < num) 1633 { 1634 error_message = _(": asr number must be between 16 and 31"); 1635 goto error; 1636 } 1637 } 1638 else 1639 { 1640 if (num < 0 || 31 < num) 1641 { 1642 error_message = _(": asr number must be between 0 and 31"); 1643 goto error; 1644 } 1645 } 1646 1647 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1648 continue; 1649 } 1650 else 1651 { 1652 error_message = _(": expecting %asrN"); 1653 goto error; 1654 } 1655 } /* if %asr */ 1656 break; 1657 1658 case 'I': 1659 the_insn.reloc = BFD_RELOC_SPARC_11; 1660 goto immediate; 1661 1662 case 'j': 1663 the_insn.reloc = BFD_RELOC_SPARC_10; 1664 goto immediate; 1665 1666 case 'X': 1667 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1668 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1669 the_insn.reloc = BFD_RELOC_SPARC_5; 1670 else 1671 the_insn.reloc = BFD_RELOC_SPARC13; 1672 /* These fields are unsigned, but for upward compatibility, 1673 allow negative values as well. */ 1674 goto immediate; 1675 1676 case 'Y': 1677 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1678 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1679 the_insn.reloc = BFD_RELOC_SPARC_6; 1680 else 1681 the_insn.reloc = BFD_RELOC_SPARC13; 1682 /* These fields are unsigned, but for upward compatibility, 1683 allow negative values as well. */ 1684 goto immediate; 1685 1686 case 'k': 1687 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1688 the_insn.pcrel = 1; 1689 goto immediate; 1690 1691 case 'G': 1692 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1693 the_insn.pcrel = 1; 1694 goto immediate; 1695 1696 case 'N': 1697 if (*s == 'p' && s[1] == 'n') 1698 { 1699 s += 2; 1700 continue; 1701 } 1702 break; 1703 1704 case 'T': 1705 if (*s == 'p' && s[1] == 't') 1706 { 1707 s += 2; 1708 continue; 1709 } 1710 break; 1711 1712 case 'z': 1713 if (*s == ' ') 1714 { 1715 ++s; 1716 } 1717 if (strncmp (s, "%icc", 4) == 0) 1718 { 1719 s += 4; 1720 continue; 1721 } 1722 break; 1723 1724 case 'Z': 1725 if (*s == ' ') 1726 { 1727 ++s; 1728 } 1729 if (strncmp (s, "%xcc", 4) == 0) 1730 { 1731 s += 4; 1732 continue; 1733 } 1734 break; 1735 1736 case '6': 1737 if (*s == ' ') 1738 { 1739 ++s; 1740 } 1741 if (strncmp (s, "%fcc0", 5) == 0) 1742 { 1743 s += 5; 1744 continue; 1745 } 1746 break; 1747 1748 case '7': 1749 if (*s == ' ') 1750 { 1751 ++s; 1752 } 1753 if (strncmp (s, "%fcc1", 5) == 0) 1754 { 1755 s += 5; 1756 continue; 1757 } 1758 break; 1759 1760 case '8': 1761 if (*s == ' ') 1762 { 1763 ++s; 1764 } 1765 if (strncmp (s, "%fcc2", 5) == 0) 1766 { 1767 s += 5; 1768 continue; 1769 } 1770 break; 1771 1772 case '9': 1773 if (*s == ' ') 1774 { 1775 ++s; 1776 } 1777 if (strncmp (s, "%fcc3", 5) == 0) 1778 { 1779 s += 5; 1780 continue; 1781 } 1782 break; 1783 1784 case 'P': 1785 if (strncmp (s, "%pc", 3) == 0) 1786 { 1787 s += 3; 1788 continue; 1789 } 1790 break; 1791 1792 case 'W': 1793 if (strncmp (s, "%tick", 5) == 0) 1794 { 1795 s += 5; 1796 continue; 1797 } 1798 break; 1799 1800 case '\0': /* End of args. */ 1801 if (*s == '\0') 1802 { 1803 match = 1; 1804 } 1805 break; 1806 1807 case '+': 1808 if (*s == '+') 1809 { 1810 ++s; 1811 continue; 1812 } 1813 if (*s == '-') 1814 { 1815 continue; 1816 } 1817 break; 1818 1819 case '[': /* These must match exactly. */ 1820 case ']': 1821 case ',': 1822 case ' ': 1823 if (*s++ == *args) 1824 continue; 1825 break; 1826 1827 case '#': /* Must be at least one digit. */ 1828 if (isdigit ((unsigned char) *s++)) 1829 { 1830 while (isdigit ((unsigned char) *s)) 1831 { 1832 ++s; 1833 } 1834 continue; 1835 } 1836 break; 1837 1838 case 'C': /* Coprocessor state register. */ 1839 if (strncmp (s, "%csr", 4) == 0) 1840 { 1841 s += 4; 1842 continue; 1843 } 1844 break; 1845 1846 case 'b': /* Next operand is a coprocessor register. */ 1847 case 'c': 1848 case 'D': 1849 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s)) 1850 { 1851 mask = *s++; 1852 if (isdigit ((unsigned char) *s)) 1853 { 1854 mask = 10 * (mask - '0') + (*s++ - '0'); 1855 if (mask >= 32) 1856 { 1857 break; 1858 } 1859 } 1860 else 1861 { 1862 mask -= '0'; 1863 } 1864 switch (*args) 1865 { 1866 1867 case 'b': 1868 opcode |= mask << 14; 1869 continue; 1870 1871 case 'c': 1872 opcode |= mask; 1873 continue; 1874 1875 case 'D': 1876 opcode |= mask << 25; 1877 continue; 1878 } 1879 } 1880 break; 1881 1882 case 'r': /* next operand must be a register */ 1883 case 'O': 1884 case '1': 1885 case '2': 1886 case 'd': 1887 if (*s++ == '%') 1888 { 1889 switch (c = *s++) 1890 { 1891 1892 case 'f': /* frame pointer */ 1893 if (*s++ == 'p') 1894 { 1895 mask = 0x1e; 1896 break; 1897 } 1898 goto error; 1899 1900 case 'g': /* global register */ 1901 c = *s++; 1902 if (isoctal (c)) 1903 { 1904 mask = c - '0'; 1905 break; 1906 } 1907 goto error; 1908 1909 case 'i': /* in register */ 1910 c = *s++; 1911 if (isoctal (c)) 1912 { 1913 mask = c - '0' + 24; 1914 break; 1915 } 1916 goto error; 1917 1918 case 'l': /* local register */ 1919 c = *s++; 1920 if (isoctal (c)) 1921 { 1922 mask = (c - '0' + 16); 1923 break; 1924 } 1925 goto error; 1926 1927 case 'o': /* out register */ 1928 c = *s++; 1929 if (isoctal (c)) 1930 { 1931 mask = (c - '0' + 8); 1932 break; 1933 } 1934 goto error; 1935 1936 case 's': /* stack pointer */ 1937 if (*s++ == 'p') 1938 { 1939 mask = 0xe; 1940 break; 1941 } 1942 goto error; 1943 1944 case 'r': /* any register */ 1945 if (!isdigit ((unsigned char) (c = *s++))) 1946 { 1947 goto error; 1948 } 1949 /* FALLTHROUGH */ 1950 case '0': 1951 case '1': 1952 case '2': 1953 case '3': 1954 case '4': 1955 case '5': 1956 case '6': 1957 case '7': 1958 case '8': 1959 case '9': 1960 if (isdigit ((unsigned char) *s)) 1961 { 1962 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 1963 { 1964 goto error; 1965 } 1966 } 1967 else 1968 { 1969 c -= '0'; 1970 } 1971 mask = c; 1972 break; 1973 1974 default: 1975 goto error; 1976 } 1977 1978 if ((mask & ~1) == 2 && sparc_arch_size == 64 1979 && no_undeclared_regs && ! globals[mask]) 1980 as_bad (_("detected global register use not covered by .register pseudo-op")); 1981 1982 /* Got the register, now figure out where 1983 it goes in the opcode. */ 1984 switch (*args) 1985 { 1986 case '1': 1987 opcode |= mask << 14; 1988 continue; 1989 1990 case '2': 1991 opcode |= mask; 1992 continue; 1993 1994 case 'd': 1995 opcode |= mask << 25; 1996 continue; 1997 1998 case 'r': 1999 opcode |= (mask << 25) | (mask << 14); 2000 continue; 2001 2002 case 'O': 2003 opcode |= (mask << 25) | (mask << 0); 2004 continue; 2005 } 2006 } 2007 break; 2008 2009 case 'e': /* next operand is a floating point register */ 2010 case 'v': 2011 case 'V': 2012 2013 case 'f': 2014 case 'B': 2015 case 'R': 2016 2017 case 'g': 2018 case 'H': 2019 case 'J': 2020 { 2021 char format; 2022 2023 if (*s++ == '%' 2024 && ((format = *s) == 'f') 2025 && isdigit ((unsigned char) *++s)) 2026 { 2027 for (mask = 0; isdigit ((unsigned char) *s); ++s) 2028 { 2029 mask = 10 * mask + (*s - '0'); 2030 } /* read the number */ 2031 2032 if ((*args == 'v' 2033 || *args == 'B' 2034 || *args == 'H') 2035 && (mask & 1)) 2036 { 2037 break; 2038 } /* register must be even numbered */ 2039 2040 if ((*args == 'V' 2041 || *args == 'R' 2042 || *args == 'J') 2043 && (mask & 3)) 2044 { 2045 break; 2046 } /* register must be multiple of 4 */ 2047 2048 if (mask >= 64) 2049 { 2050 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2051 error_message = _(": There are only 64 f registers; [0-63]"); 2052 else 2053 error_message = _(": There are only 32 f registers; [0-31]"); 2054 goto error; 2055 } /* on error */ 2056 else if (mask >= 32) 2057 { 2058 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2059 { 2060 v9_arg_p = 1; 2061 mask -= 31; /* wrap high bit */ 2062 } 2063 else 2064 { 2065 error_message = _(": There are only 32 f registers; [0-31]"); 2066 goto error; 2067 } 2068 } 2069 } 2070 else 2071 { 2072 break; 2073 } /* if not an 'f' register. */ 2074 2075 switch (*args) 2076 { 2077 case 'v': 2078 case 'V': 2079 case 'e': 2080 opcode |= RS1 (mask); 2081 continue; 2082 2083 case 'f': 2084 case 'B': 2085 case 'R': 2086 opcode |= RS2 (mask); 2087 continue; 2088 2089 case 'g': 2090 case 'H': 2091 case 'J': 2092 opcode |= RD (mask); 2093 continue; 2094 } /* Pack it in. */ 2095 2096 know (0); 2097 break; 2098 } /* float arg */ 2099 2100 case 'F': 2101 if (strncmp (s, "%fsr", 4) == 0) 2102 { 2103 s += 4; 2104 continue; 2105 } 2106 break; 2107 2108 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2109 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2110 goto immediate; 2111 2112 case 'l': /* 22 bit PC relative immediate */ 2113 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2114 the_insn.pcrel = 1; 2115 goto immediate; 2116 2117 case 'L': /* 30 bit immediate */ 2118 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2119 the_insn.pcrel = 1; 2120 goto immediate; 2121 2122 case 'h': 2123 case 'n': /* 22 bit immediate */ 2124 the_insn.reloc = BFD_RELOC_SPARC22; 2125 goto immediate; 2126 2127 case 'i': /* 13 bit immediate */ 2128 the_insn.reloc = BFD_RELOC_SPARC13; 2129 2130 /* fallthrough */ 2131 2132 immediate: 2133 if (*s == ' ') 2134 s++; 2135 2136 { 2137 char *s1; 2138 char *op_arg = NULL; 2139 expressionS op_exp; 2140 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2141 2142 /* Check for %hi, etc. */ 2143 if (*s == '%') 2144 { 2145 static const struct ops { 2146 /* The name as it appears in assembler. */ 2147 char *name; 2148 /* strlen (name), precomputed for speed */ 2149 int len; 2150 /* The reloc this pseudo-op translates to. */ 2151 int reloc; 2152 /* Non-zero if for v9 only. */ 2153 int v9_p; 2154 /* Non-zero if can be used in pc-relative contexts. */ 2155 int pcrel_p;/*FIXME:wip*/ 2156 } ops[] = { 2157 /* hix/lox must appear before hi/lo so %hix won't be 2158 mistaken for %hi. */ 2159 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2160 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2161 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2162 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2163 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2164 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2165 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2166 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2167 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2168 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2169 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2170 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2171 { NULL, 0, 0, 0, 0 } 2172 }; 2173 const struct ops *o; 2174 2175 for (o = ops; o->name; o++) 2176 if (strncmp (s + 1, o->name, o->len) == 0) 2177 break; 2178 if (o->name == NULL) 2179 break; 2180 2181 if (s[o->len + 1] != '(') 2182 { 2183 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2184 return special_case; 2185 } 2186 2187 op_arg = o->name; 2188 the_insn.reloc = o->reloc; 2189 s += o->len + 2; 2190 v9_arg_p = o->v9_p; 2191 } 2192 2193 /* Note that if the get_expression() fails, we will still 2194 have created U entries in the symbol table for the 2195 'symbols' in the input string. Try not to create U 2196 symbols for registers, etc. */ 2197 2198 /* This stuff checks to see if the expression ends in 2199 +%reg. If it does, it removes the register from 2200 the expression, and re-sets 's' to point to the 2201 right place. */ 2202 2203 if (op_arg) 2204 { 2205 int npar = 0; 2206 2207 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2208 if (*s1 == '(') 2209 npar++; 2210 else if (*s1 == ')') 2211 { 2212 if (!npar) 2213 break; 2214 npar--; 2215 } 2216 2217 if (*s1 != ')') 2218 { 2219 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2220 return special_case; 2221 } 2222 2223 *s1 = '\0'; 2224 (void) get_expression (s); 2225 *s1 = ')'; 2226 s = s1 + 1; 2227 if (*s == ',' || *s == ']' || !*s) 2228 continue; 2229 if (*s != '+' && *s != '-') 2230 { 2231 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2232 return special_case; 2233 } 2234 *s1 = '0'; 2235 s = s1; 2236 op_exp = the_insn.exp; 2237 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2238 } 2239 2240 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2241 ; 2242 2243 if (s1 != s && isdigit ((unsigned char) s1[-1])) 2244 { 2245 if (s1[-2] == '%' && s1[-3] == '+') 2246 s1 -= 3; 2247 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2248 s1 -= 4; 2249 else 2250 s1 = NULL; 2251 if (s1) 2252 { 2253 *s1 = '\0'; 2254 if (op_arg && s1 == s + 1) 2255 the_insn.exp.X_op = O_absent; 2256 else 2257 (void) get_expression (s); 2258 *s1 = '+'; 2259 if (op_arg) 2260 *s = ')'; 2261 s = s1; 2262 } 2263 } 2264 else 2265 s1 = NULL; 2266 2267 if (!s1) 2268 { 2269 (void) get_expression (s); 2270 if (op_arg) 2271 *s = ')'; 2272 s = expr_end; 2273 } 2274 2275 if (op_arg) 2276 { 2277 the_insn.exp2 = the_insn.exp; 2278 the_insn.exp = op_exp; 2279 if (the_insn.exp2.X_op == O_absent) 2280 the_insn.exp2.X_op = O_illegal; 2281 else if (the_insn.exp.X_op == O_absent) 2282 { 2283 the_insn.exp = the_insn.exp2; 2284 the_insn.exp2.X_op = O_illegal; 2285 } 2286 else if (the_insn.exp.X_op == O_constant) 2287 { 2288 valueT val = the_insn.exp.X_add_number; 2289 switch (the_insn.reloc) 2290 { 2291 default: 2292 break; 2293 2294 case BFD_RELOC_SPARC_HH22: 2295 val = BSR (val, 32); 2296 /* Fall through. */ 2297 2298 case BFD_RELOC_SPARC_LM22: 2299 case BFD_RELOC_HI22: 2300 val = (val >> 10) & 0x3fffff; 2301 break; 2302 2303 case BFD_RELOC_SPARC_HM10: 2304 val = BSR (val, 32); 2305 /* Fall through. */ 2306 2307 case BFD_RELOC_LO10: 2308 val &= 0x3ff; 2309 break; 2310 2311 case BFD_RELOC_SPARC_H44: 2312 val >>= 22; 2313 val &= 0x3fffff; 2314 break; 2315 2316 case BFD_RELOC_SPARC_M44: 2317 val >>= 12; 2318 val &= 0x3ff; 2319 break; 2320 2321 case BFD_RELOC_SPARC_L44: 2322 val &= 0xfff; 2323 break; 2324 2325 case BFD_RELOC_SPARC_HIX22: 2326 val = ~val; 2327 val = (val >> 10) & 0x3fffff; 2328 break; 2329 2330 case BFD_RELOC_SPARC_LOX10: 2331 val = (val & 0x3ff) | 0x1c00; 2332 break; 2333 } 2334 the_insn.exp = the_insn.exp2; 2335 the_insn.exp.X_add_number += val; 2336 the_insn.exp2.X_op = O_illegal; 2337 the_insn.reloc = old_reloc; 2338 } 2339 else if (the_insn.exp2.X_op != O_constant) 2340 { 2341 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2342 return special_case; 2343 } 2344 else 2345 { 2346 if (old_reloc != BFD_RELOC_SPARC13 2347 || the_insn.reloc != BFD_RELOC_LO10 2348 || sparc_arch_size != 64 2349 || sparc_pic_code) 2350 { 2351 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2352 return special_case; 2353 } 2354 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2355 } 2356 } 2357 } 2358 /* Check for constants that don't require emitting a reloc. */ 2359 if (the_insn.exp.X_op == O_constant 2360 && the_insn.exp.X_add_symbol == 0 2361 && the_insn.exp.X_op_symbol == 0) 2362 { 2363 /* For pc-relative call instructions, we reject 2364 constants to get better code. */ 2365 if (the_insn.pcrel 2366 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2367 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2368 { 2369 error_message = _(": PC-relative operand can't be a constant"); 2370 goto error; 2371 } 2372 2373 /* Constants that won't fit are checked in md_apply_fix3 2374 and bfd_install_relocation. 2375 ??? It would be preferable to install the constants 2376 into the insn here and save having to create a fixS 2377 for each one. There already exists code to handle 2378 all the various cases (e.g. in md_apply_fix3 and 2379 bfd_install_relocation) so duplicating all that code 2380 here isn't right. */ 2381 } 2382 2383 continue; 2384 2385 case 'a': 2386 if (*s++ == 'a') 2387 { 2388 opcode |= ANNUL; 2389 continue; 2390 } 2391 break; 2392 2393 case 'A': 2394 { 2395 int asi = 0; 2396 2397 /* Parse an asi. */ 2398 if (*s == '#') 2399 { 2400 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2401 { 2402 error_message = _(": invalid ASI name"); 2403 goto error; 2404 } 2405 } 2406 else 2407 { 2408 if (! parse_const_expr_arg (&s, &asi)) 2409 { 2410 error_message = _(": invalid ASI expression"); 2411 goto error; 2412 } 2413 if (asi < 0 || asi > 255) 2414 { 2415 error_message = _(": invalid ASI number"); 2416 goto error; 2417 } 2418 } 2419 opcode |= ASI (asi); 2420 continue; 2421 } /* Alternate space. */ 2422 2423 case 'p': 2424 if (strncmp (s, "%psr", 4) == 0) 2425 { 2426 s += 4; 2427 continue; 2428 } 2429 break; 2430 2431 case 'q': /* Floating point queue. */ 2432 if (strncmp (s, "%fq", 3) == 0) 2433 { 2434 s += 3; 2435 continue; 2436 } 2437 break; 2438 2439 case 'Q': /* Coprocessor queue. */ 2440 if (strncmp (s, "%cq", 3) == 0) 2441 { 2442 s += 3; 2443 continue; 2444 } 2445 break; 2446 2447 case 'S': 2448 if (strcmp (str, "set") == 0 2449 || strcmp (str, "setuw") == 0) 2450 { 2451 special_case = SPECIAL_CASE_SET; 2452 continue; 2453 } 2454 else if (strcmp (str, "setsw") == 0) 2455 { 2456 special_case = SPECIAL_CASE_SETSW; 2457 continue; 2458 } 2459 else if (strcmp (str, "setx") == 0) 2460 { 2461 special_case = SPECIAL_CASE_SETX; 2462 continue; 2463 } 2464 else if (strncmp (str, "fdiv", 4) == 0) 2465 { 2466 special_case = SPECIAL_CASE_FDIV; 2467 continue; 2468 } 2469 break; 2470 2471 case 'o': 2472 if (strncmp (s, "%asi", 4) != 0) 2473 break; 2474 s += 4; 2475 continue; 2476 2477 case 's': 2478 if (strncmp (s, "%fprs", 5) != 0) 2479 break; 2480 s += 5; 2481 continue; 2482 2483 case 'E': 2484 if (strncmp (s, "%ccr", 4) != 0) 2485 break; 2486 s += 4; 2487 continue; 2488 2489 case 't': 2490 if (strncmp (s, "%tbr", 4) != 0) 2491 break; 2492 s += 4; 2493 continue; 2494 2495 case 'w': 2496 if (strncmp (s, "%wim", 4) != 0) 2497 break; 2498 s += 4; 2499 continue; 2500 2501 case 'x': 2502 { 2503 char *push = input_line_pointer; 2504 expressionS e; 2505 2506 input_line_pointer = s; 2507 expression (&e); 2508 if (e.X_op == O_constant) 2509 { 2510 int n = e.X_add_number; 2511 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2512 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2513 else 2514 opcode |= e.X_add_number << 5; 2515 } 2516 else 2517 as_bad (_("non-immediate OPF operand, ignored")); 2518 s = input_line_pointer; 2519 input_line_pointer = push; 2520 continue; 2521 } 2522 2523 case 'y': 2524 if (strncmp (s, "%y", 2) != 0) 2525 break; 2526 s += 2; 2527 continue; 2528 2529 case 'u': 2530 case 'U': 2531 { 2532 /* Parse a sparclet cpreg. */ 2533 int cpreg; 2534 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2535 { 2536 error_message = _(": invalid cpreg name"); 2537 goto error; 2538 } 2539 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2540 continue; 2541 } 2542 2543 default: 2544 as_fatal (_("failed sanity check.")); 2545 } /* switch on arg code. */ 2546 2547 /* Break out of for() loop. */ 2548 break; 2549 } /* For each arg that we expect. */ 2550 2551 error: 2552 if (match == 0) 2553 { 2554 /* Args don't match. */ 2555 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2556 && (insn->name == insn[1].name 2557 || !strcmp (insn->name, insn[1].name))) 2558 { 2559 ++insn; 2560 s = argsStart; 2561 continue; 2562 } 2563 else 2564 { 2565 as_bad (_("Illegal operands%s"), error_message); 2566 return special_case; 2567 } 2568 } 2569 else 2570 { 2571 /* We have a match. Now see if the architecture is OK. */ 2572 int needed_arch_mask = insn->architecture; 2573 2574 if (v9_arg_p) 2575 { 2576 needed_arch_mask &= 2577 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 2578 if (! needed_arch_mask) 2579 needed_arch_mask = 2580 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 2581 } 2582 2583 if (needed_arch_mask 2584 & SPARC_OPCODE_SUPPORTED (current_architecture)) 2585 /* OK. */ 2586 ; 2587 /* Can we bump up the architecture? */ 2588 else if (needed_arch_mask 2589 & SPARC_OPCODE_SUPPORTED (max_architecture)) 2590 { 2591 enum sparc_opcode_arch_val needed_architecture = 2592 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 2593 & needed_arch_mask); 2594 2595 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 2596 if (warn_on_bump 2597 && needed_architecture > warn_after_architecture) 2598 { 2599 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 2600 sparc_opcode_archs[current_architecture].name, 2601 sparc_opcode_archs[needed_architecture].name, 2602 str); 2603 warn_after_architecture = needed_architecture; 2604 } 2605 current_architecture = needed_architecture; 2606 } 2607 /* Conflict. */ 2608 /* ??? This seems to be a bit fragile. What if the next entry in 2609 the opcode table is the one we want and it is supported? 2610 It is possible to arrange the table today so that this can't 2611 happen but what about tomorrow? */ 2612 else 2613 { 2614 int arch, printed_one_p = 0; 2615 char *p; 2616 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 2617 2618 /* Create a list of the architectures that support the insn. */ 2619 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 2620 p = required_archs; 2621 arch = sparc_ffs (needed_arch_mask); 2622 while ((1 << arch) <= needed_arch_mask) 2623 { 2624 if ((1 << arch) & needed_arch_mask) 2625 { 2626 if (printed_one_p) 2627 *p++ = '|'; 2628 strcpy (p, sparc_opcode_archs[arch].name); 2629 p += strlen (p); 2630 printed_one_p = 1; 2631 } 2632 ++arch; 2633 } 2634 2635 as_bad (_("Architecture mismatch on \"%s\"."), str); 2636 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 2637 required_archs, 2638 sparc_opcode_archs[max_architecture].name); 2639 return special_case; 2640 } 2641 } /* If no match. */ 2642 2643 break; 2644 } /* Forever looking for a match. */ 2645 2646 the_insn.opcode = opcode; 2647 return special_case; 2648} 2649 2650/* Parse an argument that can be expressed as a keyword. 2651 (eg: #StoreStore or %ccfr). 2652 The result is a boolean indicating success. 2653 If successful, INPUT_POINTER is updated. */ 2654 2655static int 2656parse_keyword_arg (lookup_fn, input_pointerP, valueP) 2657 int (*lookup_fn) PARAMS ((const char *)); 2658 char **input_pointerP; 2659 int *valueP; 2660{ 2661 int value; 2662 char c, *p, *q; 2663 2664 p = *input_pointerP; 2665 for (q = p + (*p == '#' || *p == '%'); 2666 isalnum ((unsigned char) *q) || *q == '_'; 2667 ++q) 2668 continue; 2669 c = *q; 2670 *q = 0; 2671 value = (*lookup_fn) (p); 2672 *q = c; 2673 if (value == -1) 2674 return 0; 2675 *valueP = value; 2676 *input_pointerP = q; 2677 return 1; 2678} 2679 2680/* Parse an argument that is a constant expression. 2681 The result is a boolean indicating success. */ 2682 2683static int 2684parse_const_expr_arg (input_pointerP, valueP) 2685 char **input_pointerP; 2686 int *valueP; 2687{ 2688 char *save = input_line_pointer; 2689 expressionS exp; 2690 2691 input_line_pointer = *input_pointerP; 2692 /* The next expression may be something other than a constant 2693 (say if we're not processing the right variant of the insn). 2694 Don't call expression unless we're sure it will succeed as it will 2695 signal an error (which we want to defer until later). */ 2696 /* FIXME: It might be better to define md_operand and have it recognize 2697 things like %asi, etc. but continuing that route through to the end 2698 is a lot of work. */ 2699 if (*input_line_pointer == '%') 2700 { 2701 input_line_pointer = save; 2702 return 0; 2703 } 2704 expression (&exp); 2705 *input_pointerP = input_line_pointer; 2706 input_line_pointer = save; 2707 if (exp.X_op != O_constant) 2708 return 0; 2709 *valueP = exp.X_add_number; 2710 return 1; 2711} 2712 2713/* Subroutine of sparc_ip to parse an expression. */ 2714 2715static int 2716get_expression (str) 2717 char *str; 2718{ 2719 char *save_in; 2720 segT seg; 2721 2722 save_in = input_line_pointer; 2723 input_line_pointer = str; 2724 seg = expression (&the_insn.exp); 2725 if (seg != absolute_section 2726 && seg != text_section 2727 && seg != data_section 2728 && seg != bss_section 2729 && seg != undefined_section) 2730 { 2731 the_insn.error = _("bad segment"); 2732 expr_end = input_line_pointer; 2733 input_line_pointer = save_in; 2734 return 1; 2735 } 2736 expr_end = input_line_pointer; 2737 input_line_pointer = save_in; 2738 return 0; 2739} 2740 2741/* Subroutine of md_assemble to output one insn. */ 2742 2743static void 2744output_insn (insn, the_insn) 2745 const struct sparc_opcode *insn; 2746 struct sparc_it *the_insn; 2747{ 2748 char *toP = frag_more (4); 2749 2750 /* Put out the opcode. */ 2751 if (INSN_BIG_ENDIAN) 2752 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4); 2753 else 2754 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4); 2755 2756 /* Put out the symbol-dependent stuff. */ 2757 if (the_insn->reloc != BFD_RELOC_NONE) 2758 { 2759 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 2760 (toP - frag_now->fr_literal), /* Where. */ 2761 4, /* Size. */ 2762 &the_insn->exp, 2763 the_insn->pcrel, 2764 the_insn->reloc); 2765 /* Turn off overflow checking in fixup_segment. We'll do our 2766 own overflow checking in md_apply_fix3. This is necessary because 2767 the insn size is 4 and fixup_segment will signal an overflow for 2768 large 8 byte quantities. */ 2769 fixP->fx_no_overflow = 1; 2770 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10) 2771 fixP->tc_fix_data = the_insn->exp2.X_add_number; 2772 } 2773 2774 last_insn = insn; 2775 last_opcode = the_insn->opcode; 2776 2777#ifdef OBJ_ELF 2778 dwarf2_emit_insn (4); 2779#endif 2780} 2781 2782/* This is identical to the md_atof in m68k.c. I think this is right, 2783 but I'm not sure. 2784 2785 Turn a string in input_line_pointer into a floating point constant 2786 of type TYPE, and store the appropriate bytes in *LITP. The number 2787 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2788 returned, or NULL on OK. */ 2789 2790/* Equal to MAX_PRECISION in atof-ieee.c. */ 2791#define MAX_LITTLENUMS 6 2792 2793char * 2794md_atof (type, litP, sizeP) 2795 char type; 2796 char *litP; 2797 int *sizeP; 2798{ 2799 int i, prec; 2800 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2801 char *t; 2802 2803 switch (type) 2804 { 2805 case 'f': 2806 case 'F': 2807 case 's': 2808 case 'S': 2809 prec = 2; 2810 break; 2811 2812 case 'd': 2813 case 'D': 2814 case 'r': 2815 case 'R': 2816 prec = 4; 2817 break; 2818 2819 case 'x': 2820 case 'X': 2821 prec = 6; 2822 break; 2823 2824 case 'p': 2825 case 'P': 2826 prec = 6; 2827 break; 2828 2829 default: 2830 *sizeP = 0; 2831 return _("Bad call to MD_ATOF()"); 2832 } 2833 2834 t = atof_ieee (input_line_pointer, type, words); 2835 if (t) 2836 input_line_pointer = t; 2837 *sizeP = prec * sizeof (LITTLENUM_TYPE); 2838 2839 if (target_big_endian) 2840 { 2841 for (i = 0; i < prec; i++) 2842 { 2843 md_number_to_chars (litP, (valueT) words[i], 2844 sizeof (LITTLENUM_TYPE)); 2845 litP += sizeof (LITTLENUM_TYPE); 2846 } 2847 } 2848 else 2849 { 2850 for (i = prec - 1; i >= 0; i--) 2851 { 2852 md_number_to_chars (litP, (valueT) words[i], 2853 sizeof (LITTLENUM_TYPE)); 2854 litP += sizeof (LITTLENUM_TYPE); 2855 } 2856 } 2857 2858 return 0; 2859} 2860 2861/* Write a value out to the object file, using the appropriate 2862 endianness. */ 2863 2864void 2865md_number_to_chars (buf, val, n) 2866 char *buf; 2867 valueT val; 2868 int n; 2869{ 2870 if (target_big_endian) 2871 number_to_chars_bigendian (buf, val, n); 2872 else if (target_little_endian_data 2873 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 2874 /* Output debug words, which are not in allocated sections, as big 2875 endian. */ 2876 number_to_chars_bigendian (buf, val, n); 2877 else if (target_little_endian_data || ! target_big_endian) 2878 number_to_chars_littleendian (buf, val, n); 2879} 2880 2881/* Apply a fixS to the frags, now that we know the value it ought to 2882 hold. */ 2883 2884int 2885md_apply_fix3 (fixP, value, segment) 2886 fixS *fixP; 2887 valueT *value; 2888 segT segment; 2889{ 2890 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2891 offsetT val; 2892 long insn; 2893 2894 val = *value; 2895 2896 assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 2897 2898 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 2899 2900#ifdef OBJ_ELF 2901 /* FIXME: SPARC ELF relocations don't use an addend in the data 2902 field itself. This whole approach should be somehow combined 2903 with the calls to bfd_install_relocation. Also, the value passed 2904 in by fixup_segment includes the value of a defined symbol. We 2905 don't want to include the value of an externally visible symbol. */ 2906 if (fixP->fx_addsy != NULL) 2907 { 2908 if (symbol_used_in_reloc_p (fixP->fx_addsy) 2909 && (S_IS_EXTERNAL (fixP->fx_addsy) 2910 || S_IS_WEAK (fixP->fx_addsy) 2911 || (sparc_pic_code && ! fixP->fx_pcrel) 2912 || (S_GET_SEGMENT (fixP->fx_addsy) != segment 2913 && ((bfd_get_section_flags (stdoutput, 2914 S_GET_SEGMENT (fixP->fx_addsy)) 2915 & SEC_LINK_ONCE) != 0 2916 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), 2917 ".gnu.linkonce", 2918 sizeof ".gnu.linkonce" - 1) == 0))) 2919 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section 2920 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section 2921 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy))) 2922 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy); 2923 return 1; 2924 } 2925#endif 2926 2927 /* This is a hack. There should be a better way to 2928 handle this. Probably in terms of howto fields, once 2929 we can look at these fixups in terms of howtos. */ 2930 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 2931 val += fixP->fx_where + fixP->fx_frag->fr_address; 2932 2933#ifdef OBJ_AOUT 2934 /* FIXME: More ridiculous gas reloc hacking. If we are going to 2935 generate a reloc, then we just want to let the reloc addend set 2936 the value. We do not want to also stuff the addend into the 2937 object file. Including the addend in the object file works when 2938 doing a static link, because the linker will ignore the object 2939 file contents. However, the dynamic linker does not ignore the 2940 object file contents. */ 2941 if (fixP->fx_addsy != NULL 2942 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 2943 val = 0; 2944 2945 /* When generating PIC code, we do not want an addend for a reloc 2946 against a local symbol. We adjust fx_addnumber to cancel out the 2947 value already included in val, and to also cancel out the 2948 adjustment which bfd_install_relocation will create. */ 2949 if (sparc_pic_code 2950 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 2951 && fixP->fx_addsy != NULL 2952 && ! S_IS_COMMON (fixP->fx_addsy) 2953 && symbol_section_p (fixP->fx_addsy)) 2954 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 2955 2956 /* When generating PIC code, we need to fiddle to get 2957 bfd_install_relocation to do the right thing for a PC relative 2958 reloc against a local symbol which we are going to keep. */ 2959 if (sparc_pic_code 2960 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 2961 && fixP->fx_addsy != NULL 2962 && (S_IS_EXTERNAL (fixP->fx_addsy) 2963 || S_IS_WEAK (fixP->fx_addsy)) 2964 && S_IS_DEFINED (fixP->fx_addsy) 2965 && ! S_IS_COMMON (fixP->fx_addsy)) 2966 { 2967 val = 0; 2968 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 2969 } 2970#endif 2971 2972 /* If this is a data relocation, just output VAL. */ 2973 2974 if (fixP->fx_r_type == BFD_RELOC_16 2975 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 2976 { 2977 md_number_to_chars (buf, val, 2); 2978 } 2979 else if (fixP->fx_r_type == BFD_RELOC_32 2980 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 2981 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 2982 { 2983 md_number_to_chars (buf, val, 4); 2984 } 2985 else if (fixP->fx_r_type == BFD_RELOC_64 2986 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 2987 { 2988 md_number_to_chars (buf, val, 8); 2989 } 2990 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2991 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 2992 { 2993 fixP->fx_done = 0; 2994 return 1; 2995 } 2996 else 2997 { 2998 /* It's a relocation against an instruction. */ 2999 3000 if (INSN_BIG_ENDIAN) 3001 insn = bfd_getb32 ((unsigned char *) buf); 3002 else 3003 insn = bfd_getl32 ((unsigned char *) buf); 3004 3005 switch (fixP->fx_r_type) 3006 { 3007 case BFD_RELOC_32_PCREL_S2: 3008 val = val >> 2; 3009 /* FIXME: This increment-by-one deserves a comment of why it's 3010 being done! */ 3011 if (! sparc_pic_code 3012 || fixP->fx_addsy == NULL 3013 || symbol_section_p (fixP->fx_addsy)) 3014 ++val; 3015 3016 insn |= val & 0x3fffffff; 3017 3018 /* See if we have a delay slot. */ 3019 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3020 { 3021#define G0 0 3022#define O7 15 3023#define XCC (2 << 20) 3024#define COND(x) (((x)&0xf)<<25) 3025#define CONDA COND(0x8) 3026#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3027#define INSN_BA (F2(0,2) | CONDA) 3028#define INSN_OR F3(2, 0x2, 0) 3029#define INSN_NOP F2(0,4) 3030 3031 long delay; 3032 3033 /* If the instruction is a call with either: 3034 restore 3035 arithmetic instruction with rd == %o7 3036 where rs1 != %o7 and rs2 if it is register != %o7 3037 then we can optimize if the call destination is near 3038 by changing the call into a branch always. */ 3039 if (INSN_BIG_ENDIAN) 3040 delay = bfd_getb32 ((unsigned char *) buf + 4); 3041 else 3042 delay = bfd_getl32 ((unsigned char *) buf + 4); 3043 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3044 break; 3045 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3046 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3047 || ((delay & RD (~0)) != RD (O7)))) 3048 break; 3049 if ((delay & RS1 (~0)) == RS1 (O7) 3050 || ((delay & F3I (~0)) == 0 3051 && (delay & RS2 (~0)) == RS2 (O7))) 3052 break; 3053 /* Ensure the branch will fit into simm22. */ 3054 if ((val & 0x3fe00000) 3055 && (val & 0x3fe00000) != 0x3fe00000) 3056 break; 3057 /* Check if the arch is v9 and branch will fit 3058 into simm19. */ 3059 if (((val & 0x3c0000) == 0 3060 || (val & 0x3c0000) == 0x3c0000) 3061 && (sparc_arch_size == 64 3062 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3063 /* ba,pt %xcc */ 3064 insn = INSN_BPA | (val & 0x7ffff); 3065 else 3066 /* ba */ 3067 insn = INSN_BA | (val & 0x3fffff); 3068 if (fixP->fx_where >= 4 3069 && ((delay & (0xffffffff ^ RS1 (~0))) 3070 == (INSN_OR | RD (O7) | RS2 (G0)))) 3071 { 3072 long setter; 3073 int reg; 3074 3075 if (INSN_BIG_ENDIAN) 3076 setter = bfd_getb32 ((unsigned char *) buf - 4); 3077 else 3078 setter = bfd_getl32 ((unsigned char *) buf - 4); 3079 if ((setter & (0xffffffff ^ RD (~0))) 3080 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3081 break; 3082 /* The sequence was 3083 or %o7, %g0, %rN 3084 call foo 3085 or %rN, %g0, %o7 3086 3087 If call foo was replaced with ba, replace 3088 or %rN, %g0, %o7 with nop. */ 3089 reg = (delay & RS1 (~0)) >> 14; 3090 if (reg != ((setter & RD (~0)) >> 25) 3091 || reg == G0 || reg == O7) 3092 break; 3093 3094 if (INSN_BIG_ENDIAN) 3095 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3096 else 3097 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3098 } 3099 } 3100 break; 3101 3102 case BFD_RELOC_SPARC_11: 3103 if (! in_signed_range (val, 0x7ff)) 3104 as_bad_where (fixP->fx_file, fixP->fx_line, 3105 _("relocation overflow")); 3106 insn |= val & 0x7ff; 3107 break; 3108 3109 case BFD_RELOC_SPARC_10: 3110 if (! in_signed_range (val, 0x3ff)) 3111 as_bad_where (fixP->fx_file, fixP->fx_line, 3112 _("relocation overflow")); 3113 insn |= val & 0x3ff; 3114 break; 3115 3116 case BFD_RELOC_SPARC_7: 3117 if (! in_bitfield_range (val, 0x7f)) 3118 as_bad_where (fixP->fx_file, fixP->fx_line, 3119 _("relocation overflow")); 3120 insn |= val & 0x7f; 3121 break; 3122 3123 case BFD_RELOC_SPARC_6: 3124 if (! in_bitfield_range (val, 0x3f)) 3125 as_bad_where (fixP->fx_file, fixP->fx_line, 3126 _("relocation overflow")); 3127 insn |= val & 0x3f; 3128 break; 3129 3130 case BFD_RELOC_SPARC_5: 3131 if (! in_bitfield_range (val, 0x1f)) 3132 as_bad_where (fixP->fx_file, fixP->fx_line, 3133 _("relocation overflow")); 3134 insn |= val & 0x1f; 3135 break; 3136 3137 case BFD_RELOC_SPARC_WDISP16: 3138 /* FIXME: simplify. */ 3139 if (((val > 0) && (val & ~0x3fffc)) 3140 || ((val < 0) && (~(val - 1) & ~0x3fffc))) 3141 as_bad_where (fixP->fx_file, fixP->fx_line, 3142 _("relocation overflow")); 3143 /* FIXME: The +1 deserves a comment. */ 3144 val = (val >> 2) + 1; 3145 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3146 break; 3147 3148 case BFD_RELOC_SPARC_WDISP19: 3149 /* FIXME: simplify. */ 3150 if (((val > 0) && (val & ~0x1ffffc)) 3151 || ((val < 0) && (~(val - 1) & ~0x1ffffc))) 3152 as_bad_where (fixP->fx_file, fixP->fx_line, 3153 _("relocation overflow")); 3154 /* FIXME: The +1 deserves a comment. */ 3155 val = (val >> 2) + 1; 3156 insn |= val & 0x7ffff; 3157 break; 3158 3159 case BFD_RELOC_SPARC_HH22: 3160 val = BSR (val, 32); 3161 /* Fall through. */ 3162 3163 case BFD_RELOC_SPARC_LM22: 3164 case BFD_RELOC_HI22: 3165 if (!fixP->fx_addsy) 3166 { 3167 insn |= (val >> 10) & 0x3fffff; 3168 } 3169 else 3170 { 3171 /* FIXME: Need comment explaining why we do this. */ 3172 insn &= ~0xffff; 3173 } 3174 break; 3175 3176 case BFD_RELOC_SPARC22: 3177 if (val & ~0x003fffff) 3178 as_bad_where (fixP->fx_file, fixP->fx_line, 3179 _("relocation overflow")); 3180 insn |= (val & 0x3fffff); 3181 break; 3182 3183 case BFD_RELOC_SPARC_HM10: 3184 val = BSR (val, 32); 3185 /* Fall through. */ 3186 3187 case BFD_RELOC_LO10: 3188 if (!fixP->fx_addsy) 3189 { 3190 insn |= val & 0x3ff; 3191 } 3192 else 3193 { 3194 /* FIXME: Need comment explaining why we do this. */ 3195 insn &= ~0xff; 3196 } 3197 break; 3198 3199 case BFD_RELOC_SPARC_OLO10: 3200 val &= 0x3ff; 3201 val += fixP->tc_fix_data; 3202 /* Fall through. */ 3203 3204 case BFD_RELOC_SPARC13: 3205 if (! in_signed_range (val, 0x1fff)) 3206 as_bad_where (fixP->fx_file, fixP->fx_line, 3207 _("relocation overflow")); 3208 insn |= val & 0x1fff; 3209 break; 3210 3211 case BFD_RELOC_SPARC_WDISP22: 3212 val = (val >> 2) + 1; 3213 /* Fall through. */ 3214 case BFD_RELOC_SPARC_BASE22: 3215 insn |= val & 0x3fffff; 3216 break; 3217 3218 case BFD_RELOC_SPARC_H44: 3219 if (!fixP->fx_addsy) 3220 { 3221 bfd_vma tval = val; 3222 tval >>= 22; 3223 insn |= tval & 0x3fffff; 3224 } 3225 break; 3226 3227 case BFD_RELOC_SPARC_M44: 3228 if (!fixP->fx_addsy) 3229 insn |= (val >> 12) & 0x3ff; 3230 break; 3231 3232 case BFD_RELOC_SPARC_L44: 3233 if (!fixP->fx_addsy) 3234 insn |= val & 0xfff; 3235 break; 3236 3237 case BFD_RELOC_SPARC_HIX22: 3238 if (!fixP->fx_addsy) 3239 { 3240 val ^= ~(offsetT) 0; 3241 insn |= (val >> 10) & 0x3fffff; 3242 } 3243 break; 3244 3245 case BFD_RELOC_SPARC_LOX10: 3246 if (!fixP->fx_addsy) 3247 insn |= 0x1c00 | (val & 0x3ff); 3248 break; 3249 3250 case BFD_RELOC_NONE: 3251 default: 3252 as_bad_where (fixP->fx_file, fixP->fx_line, 3253 _("bad or unhandled relocation type: 0x%02x"), 3254 fixP->fx_r_type); 3255 break; 3256 } 3257 3258 if (INSN_BIG_ENDIAN) 3259 bfd_putb32 (insn, (unsigned char *) buf); 3260 else 3261 bfd_putl32 (insn, (unsigned char *) buf); 3262 } 3263 3264 /* Are we finished with this relocation now? */ 3265 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3266 fixP->fx_done = 1; 3267 3268 return 1; 3269} 3270 3271/* Translate internal representation of relocation info to BFD target 3272 format. */ 3273 3274arelent ** 3275tc_gen_reloc (section, fixp) 3276 asection *section; 3277 fixS *fixp; 3278{ 3279 static arelent *relocs[3]; 3280 arelent *reloc; 3281 bfd_reloc_code_real_type code; 3282 3283 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3284 relocs[1] = NULL; 3285 3286 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3287 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3288 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3289 3290 switch (fixp->fx_r_type) 3291 { 3292 case BFD_RELOC_16: 3293 case BFD_RELOC_32: 3294 case BFD_RELOC_HI22: 3295 case BFD_RELOC_LO10: 3296 case BFD_RELOC_32_PCREL_S2: 3297 case BFD_RELOC_SPARC13: 3298 case BFD_RELOC_SPARC22: 3299 case BFD_RELOC_SPARC_BASE13: 3300 case BFD_RELOC_SPARC_WDISP16: 3301 case BFD_RELOC_SPARC_WDISP19: 3302 case BFD_RELOC_SPARC_WDISP22: 3303 case BFD_RELOC_64: 3304 case BFD_RELOC_SPARC_5: 3305 case BFD_RELOC_SPARC_6: 3306 case BFD_RELOC_SPARC_7: 3307 case BFD_RELOC_SPARC_10: 3308 case BFD_RELOC_SPARC_11: 3309 case BFD_RELOC_SPARC_HH22: 3310 case BFD_RELOC_SPARC_HM10: 3311 case BFD_RELOC_SPARC_LM22: 3312 case BFD_RELOC_SPARC_PC_HH22: 3313 case BFD_RELOC_SPARC_PC_HM10: 3314 case BFD_RELOC_SPARC_PC_LM22: 3315 case BFD_RELOC_SPARC_H44: 3316 case BFD_RELOC_SPARC_M44: 3317 case BFD_RELOC_SPARC_L44: 3318 case BFD_RELOC_SPARC_HIX22: 3319 case BFD_RELOC_SPARC_LOX10: 3320 case BFD_RELOC_SPARC_REV32: 3321 case BFD_RELOC_SPARC_OLO10: 3322 case BFD_RELOC_SPARC_UA16: 3323 case BFD_RELOC_SPARC_UA32: 3324 case BFD_RELOC_SPARC_UA64: 3325 case BFD_RELOC_VTABLE_ENTRY: 3326 case BFD_RELOC_VTABLE_INHERIT: 3327 code = fixp->fx_r_type; 3328 break; 3329 default: 3330 abort (); 3331 return NULL; 3332 } 3333 3334#if defined (OBJ_ELF) || defined (OBJ_AOUT) 3335 /* If we are generating PIC code, we need to generate a different 3336 set of relocs. */ 3337 3338#ifdef OBJ_ELF 3339#define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3340#else 3341#define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3342#endif 3343 3344 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3345 3346 if (sparc_pic_code) 3347 { 3348 switch (code) 3349 { 3350 case BFD_RELOC_32_PCREL_S2: 3351 if (! S_IS_DEFINED (fixp->fx_addsy) 3352 || S_IS_COMMON (fixp->fx_addsy) 3353 || S_IS_EXTERNAL (fixp->fx_addsy) 3354 || S_IS_WEAK (fixp->fx_addsy)) 3355 code = BFD_RELOC_SPARC_WPLT30; 3356 break; 3357 case BFD_RELOC_HI22: 3358 if (fixp->fx_addsy != NULL 3359 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3360 code = BFD_RELOC_SPARC_PC22; 3361 else 3362 code = BFD_RELOC_SPARC_GOT22; 3363 break; 3364 case BFD_RELOC_LO10: 3365 if (fixp->fx_addsy != NULL 3366 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3367 code = BFD_RELOC_SPARC_PC10; 3368 else 3369 code = BFD_RELOC_SPARC_GOT10; 3370 break; 3371 case BFD_RELOC_SPARC13: 3372 code = BFD_RELOC_SPARC_GOT13; 3373 break; 3374 default: 3375 break; 3376 } 3377 } 3378#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3379 3380 if (code == BFD_RELOC_SPARC_OLO10) 3381 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3382 else 3383 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3384 if (reloc->howto == 0) 3385 { 3386 as_bad_where (fixp->fx_file, fixp->fx_line, 3387 _("internal error: can't export reloc type %d (`%s')"), 3388 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3389 xfree (reloc); 3390 relocs[0] = NULL; 3391 return relocs; 3392 } 3393 3394 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3395#ifdef OBJ_AOUT 3396 3397 if (reloc->howto->pc_relative == 0 3398 || code == BFD_RELOC_SPARC_PC10 3399 || code == BFD_RELOC_SPARC_PC22) 3400 reloc->addend = fixp->fx_addnumber; 3401 else if (sparc_pic_code 3402 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3403 && fixp->fx_addsy != NULL 3404 && (S_IS_EXTERNAL (fixp->fx_addsy) 3405 || S_IS_WEAK (fixp->fx_addsy)) 3406 && S_IS_DEFINED (fixp->fx_addsy) 3407 && ! S_IS_COMMON (fixp->fx_addsy)) 3408 reloc->addend = fixp->fx_addnumber; 3409 else 3410 reloc->addend = fixp->fx_offset - reloc->address; 3411 3412#else /* elf or coff */ 3413 3414 if (reloc->howto->pc_relative == 0 3415 || code == BFD_RELOC_SPARC_PC10 3416 || code == BFD_RELOC_SPARC_PC22) 3417 reloc->addend = fixp->fx_addnumber; 3418 else if (symbol_section_p (fixp->fx_addsy)) 3419 reloc->addend = (section->vma 3420 + fixp->fx_addnumber 3421 + md_pcrel_from (fixp)); 3422 else 3423 reloc->addend = fixp->fx_offset; 3424#endif 3425 3426 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3427 on the same location. */ 3428 if (code == BFD_RELOC_SPARC_OLO10) 3429 { 3430 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3431 relocs[2] = NULL; 3432 3433 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3434 *reloc->sym_ptr_ptr 3435 = symbol_get_bfdsym (section_symbol (absolute_section)); 3436 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3437 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3438 reloc->addend = fixp->tc_fix_data; 3439 } 3440 3441 return relocs; 3442} 3443 3444/* We have no need to default values of symbols. */ 3445 3446symbolS * 3447md_undefined_symbol (name) 3448 char *name ATTRIBUTE_UNUSED; 3449{ 3450 return 0; 3451} 3452 3453/* Round up a section size to the appropriate boundary. */ 3454 3455valueT 3456md_section_align (segment, size) 3457 segT segment ATTRIBUTE_UNUSED; 3458 valueT size; 3459{ 3460#ifndef OBJ_ELF 3461 /* This is not right for ELF; a.out wants it, and COFF will force 3462 the alignment anyways. */ 3463 valueT align = ((valueT) 1 3464 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3465 valueT newsize; 3466 3467 /* Turn alignment value into a mask. */ 3468 align--; 3469 newsize = (size + align) & ~align; 3470 return newsize; 3471#else 3472 return size; 3473#endif 3474} 3475 3476/* Exactly what point is a PC-relative offset relative TO? 3477 On the sparc, they're relative to the address of the offset, plus 3478 its size. This gets us to the following instruction. 3479 (??? Is this right? FIXME-SOON) */ 3480long 3481md_pcrel_from (fixP) 3482 fixS *fixP; 3483{ 3484 long ret; 3485 3486 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3487 if (! sparc_pic_code 3488 || fixP->fx_addsy == NULL 3489 || symbol_section_p (fixP->fx_addsy)) 3490 ret += fixP->fx_size; 3491 return ret; 3492} 3493 3494/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3495 of two. */ 3496 3497static int 3498log2 (value) 3499 int value; 3500{ 3501 int shift; 3502 3503 if (value <= 0) 3504 return -1; 3505 3506 for (shift = 0; (value & 1) == 0; value >>= 1) 3507 ++shift; 3508 3509 return (value == 1) ? shift : -1; 3510} 3511 3512/* Sort of like s_lcomm. */ 3513 3514#ifndef OBJ_ELF 3515static int max_alignment = 15; 3516#endif 3517 3518static void 3519s_reserve (ignore) 3520 int ignore ATTRIBUTE_UNUSED; 3521{ 3522 char *name; 3523 char *p; 3524 char c; 3525 int align; 3526 int size; 3527 int temp; 3528 symbolS *symbolP; 3529 3530 name = input_line_pointer; 3531 c = get_symbol_end (); 3532 p = input_line_pointer; 3533 *p = c; 3534 SKIP_WHITESPACE (); 3535 3536 if (*input_line_pointer != ',') 3537 { 3538 as_bad (_("Expected comma after name")); 3539 ignore_rest_of_line (); 3540 return; 3541 } 3542 3543 ++input_line_pointer; 3544 3545 if ((size = get_absolute_expression ()) < 0) 3546 { 3547 as_bad (_("BSS length (%d.) <0! Ignored."), size); 3548 ignore_rest_of_line (); 3549 return; 3550 } /* Bad length. */ 3551 3552 *p = 0; 3553 symbolP = symbol_find_or_make (name); 3554 *p = c; 3555 3556 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 3557 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 3558 { 3559 as_bad (_("bad .reserve segment -- expected BSS segment")); 3560 return; 3561 } 3562 3563 if (input_line_pointer[2] == '.') 3564 input_line_pointer += 7; 3565 else 3566 input_line_pointer += 6; 3567 SKIP_WHITESPACE (); 3568 3569 if (*input_line_pointer == ',') 3570 { 3571 ++input_line_pointer; 3572 3573 SKIP_WHITESPACE (); 3574 if (*input_line_pointer == '\n') 3575 { 3576 as_bad (_("missing alignment")); 3577 ignore_rest_of_line (); 3578 return; 3579 } 3580 3581 align = (int) get_absolute_expression (); 3582 3583#ifndef OBJ_ELF 3584 if (align > max_alignment) 3585 { 3586 align = max_alignment; 3587 as_warn (_("alignment too large; assuming %d"), align); 3588 } 3589#endif 3590 3591 if (align < 0) 3592 { 3593 as_bad (_("negative alignment")); 3594 ignore_rest_of_line (); 3595 return; 3596 } 3597 3598 if (align != 0) 3599 { 3600 temp = log2 (align); 3601 if (temp < 0) 3602 { 3603 as_bad (_("alignment not a power of 2")); 3604 ignore_rest_of_line (); 3605 return; 3606 } 3607 3608 align = temp; 3609 } 3610 3611 record_alignment (bss_section, align); 3612 } 3613 else 3614 align = 0; 3615 3616 if (!S_IS_DEFINED (symbolP) 3617#ifdef OBJ_AOUT 3618 && S_GET_OTHER (symbolP) == 0 3619 && S_GET_DESC (symbolP) == 0 3620#endif 3621 ) 3622 { 3623 if (! need_pass_2) 3624 { 3625 char *pfrag; 3626 segT current_seg = now_seg; 3627 subsegT current_subseg = now_subseg; 3628 3629 /* Switch to bss. */ 3630 subseg_set (bss_section, 1); 3631 3632 if (align) 3633 /* Do alignment. */ 3634 frag_align (align, 0, 0); 3635 3636 /* Detach from old frag. */ 3637 if (S_GET_SEGMENT (symbolP) == bss_section) 3638 symbol_get_frag (symbolP)->fr_symbol = NULL; 3639 3640 symbol_set_frag (symbolP, frag_now); 3641 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3642 (offsetT) size, (char *) 0); 3643 *pfrag = 0; 3644 3645 S_SET_SEGMENT (symbolP, bss_section); 3646 3647 subseg_set (current_seg, current_subseg); 3648 3649#ifdef OBJ_ELF 3650 S_SET_SIZE (symbolP, size); 3651#endif 3652 } 3653 } 3654 else 3655 { 3656 as_warn ("Ignoring attempt to re-define symbol %s", 3657 S_GET_NAME (symbolP)); 3658 } /* if not redefining. */ 3659 3660 demand_empty_rest_of_line (); 3661} 3662 3663static void 3664s_common (ignore) 3665 int ignore ATTRIBUTE_UNUSED; 3666{ 3667 char *name; 3668 char c; 3669 char *p; 3670 int temp, size; 3671 symbolS *symbolP; 3672 3673 name = input_line_pointer; 3674 c = get_symbol_end (); 3675 /* Just after name is now '\0'. */ 3676 p = input_line_pointer; 3677 *p = c; 3678 SKIP_WHITESPACE (); 3679 if (*input_line_pointer != ',') 3680 { 3681 as_bad (_("Expected comma after symbol-name")); 3682 ignore_rest_of_line (); 3683 return; 3684 } 3685 3686 /* Skip ','. */ 3687 input_line_pointer++; 3688 3689 if ((temp = get_absolute_expression ()) < 0) 3690 { 3691 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp); 3692 ignore_rest_of_line (); 3693 return; 3694 } 3695 size = temp; 3696 *p = 0; 3697 symbolP = symbol_find_or_make (name); 3698 *p = c; 3699 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 3700 { 3701 as_bad (_("Ignoring attempt to re-define symbol")); 3702 ignore_rest_of_line (); 3703 return; 3704 } 3705 if (S_GET_VALUE (symbolP) != 0) 3706 { 3707 if (S_GET_VALUE (symbolP) != (valueT) size) 3708 { 3709 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), 3710 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); 3711 } 3712 } 3713 else 3714 { 3715#ifndef OBJ_ELF 3716 S_SET_VALUE (symbolP, (valueT) size); 3717 S_SET_EXTERNAL (symbolP); 3718#endif 3719 } 3720 know (symbol_get_frag (symbolP) == &zero_address_frag); 3721 if (*input_line_pointer != ',') 3722 { 3723 as_bad (_("Expected comma after common length")); 3724 ignore_rest_of_line (); 3725 return; 3726 } 3727 input_line_pointer++; 3728 SKIP_WHITESPACE (); 3729 if (*input_line_pointer != '"') 3730 { 3731 temp = get_absolute_expression (); 3732 3733#ifndef OBJ_ELF 3734 if (temp > max_alignment) 3735 { 3736 temp = max_alignment; 3737 as_warn (_("alignment too large; assuming %d"), temp); 3738 } 3739#endif 3740 3741 if (temp < 0) 3742 { 3743 as_bad (_("negative alignment")); 3744 ignore_rest_of_line (); 3745 return; 3746 } 3747 3748#ifdef OBJ_ELF 3749 if (symbol_get_obj (symbolP)->local) 3750 { 3751 segT old_sec; 3752 int old_subsec; 3753 char *p; 3754 int align; 3755 3756 old_sec = now_seg; 3757 old_subsec = now_subseg; 3758 3759 if (temp == 0) 3760 align = 0; 3761 else 3762 align = log2 (temp); 3763 3764 if (align < 0) 3765 { 3766 as_bad (_("alignment not a power of 2")); 3767 ignore_rest_of_line (); 3768 return; 3769 } 3770 3771 record_alignment (bss_section, align); 3772 subseg_set (bss_section, 0); 3773 if (align) 3774 frag_align (align, 0, 0); 3775 if (S_GET_SEGMENT (symbolP) == bss_section) 3776 symbol_get_frag (symbolP)->fr_symbol = 0; 3777 symbol_set_frag (symbolP, frag_now); 3778 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 3779 (offsetT) size, (char *) 0); 3780 *p = 0; 3781 S_SET_SEGMENT (symbolP, bss_section); 3782 S_CLEAR_EXTERNAL (symbolP); 3783 S_SET_SIZE (symbolP, size); 3784 subseg_set (old_sec, old_subsec); 3785 } 3786 else 3787#endif /* OBJ_ELF */ 3788 { 3789 allocate_common: 3790 S_SET_VALUE (symbolP, (valueT) size); 3791#ifdef OBJ_ELF 3792 S_SET_ALIGN (symbolP, temp); 3793 S_SET_SIZE (symbolP, size); 3794#endif 3795 S_SET_EXTERNAL (symbolP); 3796 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 3797 } 3798 } 3799 else 3800 { 3801 input_line_pointer++; 3802 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 3803 if (*input_line_pointer == '.') 3804 input_line_pointer++; 3805 /* @@ Some say data, some say bss. */ 3806 if (strncmp (input_line_pointer, "bss\"", 4) 3807 && strncmp (input_line_pointer, "data\"", 5)) 3808 { 3809 while (*--input_line_pointer != '"') 3810 ; 3811 input_line_pointer--; 3812 goto bad_common_segment; 3813 } 3814 while (*input_line_pointer++ != '"') 3815 ; 3816 goto allocate_common; 3817 } 3818 3819#ifdef BFD_ASSEMBLER 3820 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 3821#endif 3822 3823 demand_empty_rest_of_line (); 3824 return; 3825 3826 { 3827 bad_common_segment: 3828 p = input_line_pointer; 3829 while (*p && *p != '\n') 3830 p++; 3831 c = *p; 3832 *p = '\0'; 3833 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 3834 *p = c; 3835 input_line_pointer = p; 3836 ignore_rest_of_line (); 3837 return; 3838 } 3839} 3840 3841/* Handle the .empty pseudo-op. This supresses the warnings about 3842 invalid delay slot usage. */ 3843 3844static void 3845s_empty (ignore) 3846 int ignore ATTRIBUTE_UNUSED; 3847{ 3848 /* The easy way to implement is to just forget about the last 3849 instruction. */ 3850 last_insn = NULL; 3851} 3852 3853static void 3854s_seg (ignore) 3855 int ignore ATTRIBUTE_UNUSED; 3856{ 3857 3858 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 3859 { 3860 input_line_pointer += 6; 3861 s_text (0); 3862 return; 3863 } 3864 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 3865 { 3866 input_line_pointer += 6; 3867 s_data (0); 3868 return; 3869 } 3870 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 3871 { 3872 input_line_pointer += 7; 3873 s_data1 (); 3874 return; 3875 } 3876 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 3877 { 3878 input_line_pointer += 5; 3879 /* We only support 2 segments -- text and data -- for now, so 3880 things in the "bss segment" will have to go into data for now. 3881 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 3882 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 3883 return; 3884 } 3885 as_bad (_("Unknown segment type")); 3886 demand_empty_rest_of_line (); 3887} 3888 3889static void 3890s_data1 () 3891{ 3892 subseg_set (data_section, 1); 3893 demand_empty_rest_of_line (); 3894} 3895 3896static void 3897s_proc (ignore) 3898 int ignore ATTRIBUTE_UNUSED; 3899{ 3900 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 3901 { 3902 ++input_line_pointer; 3903 } 3904 ++input_line_pointer; 3905} 3906 3907/* This static variable is set by s_uacons to tell sparc_cons_align 3908 that the expession does not need to be aligned. */ 3909 3910static int sparc_no_align_cons = 0; 3911 3912/* This handles the unaligned space allocation pseudo-ops, such as 3913 .uaword. .uaword is just like .word, but the value does not need 3914 to be aligned. */ 3915 3916static void 3917s_uacons (bytes) 3918 int bytes; 3919{ 3920 /* Tell sparc_cons_align not to align this value. */ 3921 sparc_no_align_cons = 1; 3922 cons (bytes); 3923} 3924 3925/* This handles the native word allocation pseudo-op .nword. 3926 For sparc_arch_size 32 it is equivalent to .word, for 3927 sparc_arch_size 64 it is equivalent to .xword. */ 3928 3929static void 3930s_ncons (bytes) 3931 int bytes ATTRIBUTE_UNUSED; 3932{ 3933 cons (sparc_arch_size == 32 ? 4 : 8); 3934} 3935 3936#ifdef OBJ_ELF 3937/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 3938 global register. 3939 The syntax is: 3940 3941 .register %g[2367],{#scratch|symbolname|#ignore} 3942*/ 3943 3944static void 3945s_register (ignore) 3946 int ignore ATTRIBUTE_UNUSED; 3947{ 3948 char c; 3949 int reg; 3950 int flags; 3951 const char *regname; 3952 3953 if (input_line_pointer[0] != '%' 3954 || input_line_pointer[1] != 'g' 3955 || ((input_line_pointer[2] & ~1) != '2' 3956 && (input_line_pointer[2] & ~1) != '6') 3957 || input_line_pointer[3] != ',') 3958 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 3959 reg = input_line_pointer[2] - '0'; 3960 input_line_pointer += 4; 3961 3962 if (*input_line_pointer == '#') 3963 { 3964 ++input_line_pointer; 3965 regname = input_line_pointer; 3966 c = get_symbol_end (); 3967 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 3968 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 3969 if (regname[0] == 'i') 3970 regname = NULL; 3971 else 3972 regname = ""; 3973 } 3974 else 3975 { 3976 regname = input_line_pointer; 3977 c = get_symbol_end (); 3978 } 3979 if (sparc_arch_size == 64) 3980 { 3981 if (globals[reg]) 3982 { 3983 if ((regname && globals[reg] != (symbolS *) 1 3984 && strcmp (S_GET_NAME (globals[reg]), regname)) 3985 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 3986 as_bad (_("redefinition of global register")); 3987 } 3988 else 3989 { 3990 if (regname == NULL) 3991 globals[reg] = (symbolS *) 1; 3992 else 3993 { 3994 if (*regname) 3995 { 3996 if (symbol_find (regname)) 3997 as_bad (_("Register symbol %s already defined."), 3998 regname); 3999 } 4000 globals[reg] = symbol_make (regname); 4001 flags = symbol_get_bfdsym (globals[reg])->flags; 4002 if (! *regname) 4003 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4004 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4005 flags |= BSF_GLOBAL; 4006 symbol_get_bfdsym (globals[reg])->flags = flags; 4007 S_SET_VALUE (globals[reg], (valueT) reg); 4008 S_SET_ALIGN (globals[reg], reg); 4009 S_SET_SIZE (globals[reg], 0); 4010 /* Although we actually want undefined_section here, 4011 we have to use absolute_section, because otherwise 4012 generic as code will make it a COM section. 4013 We fix this up in sparc_adjust_symtab. */ 4014 S_SET_SEGMENT (globals[reg], absolute_section); 4015 S_SET_OTHER (globals[reg], 0); 4016 elf_symbol (symbol_get_bfdsym (globals[reg])) 4017 ->internal_elf_sym.st_info = 4018 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4019 elf_symbol (symbol_get_bfdsym (globals[reg])) 4020 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4021 } 4022 } 4023 } 4024 4025 *input_line_pointer = c; 4026 4027 demand_empty_rest_of_line (); 4028} 4029 4030/* Adjust the symbol table. We set undefined sections for STT_REGISTER 4031 symbols which need it. */ 4032 4033void 4034sparc_adjust_symtab () 4035{ 4036 symbolS *sym; 4037 4038 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4039 { 4040 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4041 ->internal_elf_sym.st_info) != STT_REGISTER) 4042 continue; 4043 4044 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4045 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4046 continue; 4047 4048 S_SET_SEGMENT (sym, undefined_section); 4049 } 4050} 4051#endif 4052 4053/* If the --enforce-aligned-data option is used, we require .word, 4054 et. al., to be aligned correctly. We do it by setting up an 4055 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4056 no unexpected alignment was introduced. 4057 4058 The SunOS and Solaris native assemblers enforce aligned data by 4059 default. We don't want to do that, because gcc can deliberately 4060 generate misaligned data if the packed attribute is used. Instead, 4061 we permit misaligned data by default, and permit the user to set an 4062 option to check for it. */ 4063 4064void 4065sparc_cons_align (nbytes) 4066 int nbytes; 4067{ 4068 int nalign; 4069 char *p; 4070 4071 /* Only do this if we are enforcing aligned data. */ 4072 if (! enforce_aligned_data) 4073 return; 4074 4075 /* Don't align if this is an unaligned pseudo-op. */ 4076 if (sparc_no_align_cons) 4077 return; 4078 4079 nalign = log2 (nbytes); 4080 if (nalign == 0) 4081 return; 4082 4083 assert (nalign > 0); 4084 4085 if (now_seg == absolute_section) 4086 { 4087 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4088 as_bad (_("misaligned data")); 4089 return; 4090 } 4091 4092 p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4093 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4094 4095 record_alignment (now_seg, nalign); 4096} 4097 4098/* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4099 4100void 4101sparc_handle_align (fragp) 4102 fragS *fragp; 4103{ 4104 int count, fix; 4105 char *p; 4106 4107 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4108 4109 switch (fragp->fr_type) 4110 { 4111 case rs_align_test: 4112 if (count != 0) 4113 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4114 break; 4115 4116 case rs_align_code: 4117 p = fragp->fr_literal + fragp->fr_fix; 4118 fix = 0; 4119 4120 if (count & 3) 4121 { 4122 fix = count & 3; 4123 memset (p, 0, fix); 4124 p += fix; 4125 count -= fix; 4126 } 4127 4128 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4129 { 4130 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4131 if (INSN_BIG_ENDIAN) 4132 number_to_chars_bigendian (p, wval, 4); 4133 else 4134 number_to_chars_littleendian (p, wval, 4); 4135 p += 4; 4136 count -= 4; 4137 fix += 4; 4138 } 4139 4140 if (INSN_BIG_ENDIAN) 4141 number_to_chars_bigendian (p, 0x01000000, 4); 4142 else 4143 number_to_chars_littleendian (p, 0x01000000, 4); 4144 4145 fragp->fr_fix += fix; 4146 fragp->fr_var = 4; 4147 break; 4148 4149 default: 4150 break; 4151 } 4152} 4153 4154#ifdef OBJ_ELF 4155/* Some special processing for a Sparc ELF file. */ 4156 4157void 4158sparc_elf_final_processing () 4159{ 4160 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4161 sort of BFD interface for this. */ 4162 if (sparc_arch_size == 64) 4163 { 4164 switch (sparc_memory_model) 4165 { 4166 case MM_RMO: 4167 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4168 break; 4169 case MM_PSO: 4170 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4171 break; 4172 default: 4173 break; 4174 } 4175 } 4176 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4177 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4178 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4179 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4180 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4181 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4182} 4183#endif 4184 4185/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4186 reloc for a cons. We could use the definition there, except that 4187 we want to handle little endian relocs specially. */ 4188 4189void 4190cons_fix_new_sparc (frag, where, nbytes, exp) 4191 fragS *frag; 4192 int where; 4193 unsigned int nbytes; 4194 expressionS *exp; 4195{ 4196 bfd_reloc_code_real_type r; 4197 4198 r = (nbytes == 1 ? BFD_RELOC_8 : 4199 (nbytes == 2 ? BFD_RELOC_16 : 4200 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4201 4202 if (target_little_endian_data 4203 && nbytes == 4 4204 && now_seg->flags & SEC_ALLOC) 4205 r = BFD_RELOC_SPARC_REV32; 4206 4207 if (sparc_no_align_cons) 4208 { 4209 switch (nbytes) 4210 { 4211 case 2: r = BFD_RELOC_SPARC_UA16; break; 4212 case 4: r = BFD_RELOC_SPARC_UA32; break; 4213 case 8: r = BFD_RELOC_SPARC_UA64; break; 4214 default: abort (); 4215 } 4216 sparc_no_align_cons = 0; 4217 } 4218 4219 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4220} 4221 4222#ifdef OBJ_ELF 4223int 4224elf32_sparc_force_relocation (fixp) 4225 struct fix *fixp; 4226{ 4227 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4228 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4229 return 1; 4230 4231 return 0; 4232} 4233#endif 4234