tc-i386.c revision 60519
1/* i386.c -- Assemble code for the Intel 80386 2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 3 Free Software Foundation. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 20 02111-1307, USA. */ 21 22/* $FreeBSD: head/contrib/binutils/gas/config/tc-i386.c 60519 2000-05-13 17:16:40Z obrien $ */ 23 24/* 25 Intel 80386 machine specific gas. 26 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 27 Bugs & suggestions are completely welcome. This is free software. 28 Please help us make it better. 29 */ 30 31#include <ctype.h> 32 33#include "as.h" 34#include "subsegs.h" 35#include "opcode/i386.h" 36 37#ifndef REGISTER_WARNINGS 38#define REGISTER_WARNINGS 1 39#endif 40 41#ifndef INFER_ADDR_PREFIX 42#define INFER_ADDR_PREFIX 1 43#endif 44 45#ifndef SCALE1_WHEN_NO_INDEX 46/* Specifying a scale factor besides 1 when there is no index is 47 futile. eg. `mov (%ebx,2),%al' does exactly the same as 48 `mov (%ebx),%al'. To slavishly follow what the programmer 49 specified, set SCALE1_WHEN_NO_INDEX to 0. */ 50#define SCALE1_WHEN_NO_INDEX 1 51#endif 52 53#define true 1 54#define false 0 55 56static unsigned int mode_from_disp_size PARAMS ((unsigned int)); 57static int fits_in_signed_byte PARAMS ((long)); 58static int fits_in_unsigned_byte PARAMS ((long)); 59static int fits_in_unsigned_word PARAMS ((long)); 60static int fits_in_signed_word PARAMS ((long)); 61static int smallest_imm_type PARAMS ((long)); 62static int add_prefix PARAMS ((unsigned int)); 63static void set_16bit_code_flag PARAMS ((int)); 64static void set_16bit_gcc_code_flag PARAMS((int)); 65static void set_intel_syntax PARAMS ((int)); 66 67#ifdef BFD_ASSEMBLER 68static bfd_reloc_code_real_type reloc 69 PARAMS ((int, int, bfd_reloc_code_real_type)); 70#endif 71 72/* 'md_assemble ()' gathers together information and puts it into a 73 i386_insn. */ 74 75union i386_op 76 { 77 expressionS *disps; 78 expressionS *imms; 79 const reg_entry *regs; 80 }; 81 82struct _i386_insn 83 { 84 /* TM holds the template for the insn were currently assembling. */ 85 template tm; 86 87 /* SUFFIX holds the instruction mnemonic suffix if given. 88 (e.g. 'l' for 'movl') */ 89 char suffix; 90 91 /* OPERANDS gives the number of given operands. */ 92 unsigned int operands; 93 94 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 95 of given register, displacement, memory operands and immediate 96 operands. */ 97 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 98 99 /* TYPES [i] is the type (see above #defines) which tells us how to 100 use OP[i] for the corresponding operand. */ 101 unsigned int types[MAX_OPERANDS]; 102 103 /* Displacement expression, immediate expression, or register for each 104 operand. */ 105 union i386_op op[MAX_OPERANDS]; 106 107 /* Relocation type for operand */ 108#ifdef BFD_ASSEMBLER 109 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; 110#else 111 int disp_reloc[MAX_OPERANDS]; 112#endif 113 114 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 115 the base index byte below. */ 116 const reg_entry *base_reg; 117 const reg_entry *index_reg; 118 unsigned int log2_scale_factor; 119 120 /* SEG gives the seg_entries of this insn. They are zero unless 121 explicit segment overrides are given. */ 122 const seg_entry *seg[2]; /* segments for memory operands (if given) */ 123 124 /* PREFIX holds all the given prefix opcodes (usually null). 125 PREFIXES is the number of prefix opcodes. */ 126 unsigned int prefixes; 127 unsigned char prefix[MAX_PREFIXES]; 128 129 /* RM and SIB are the modrm byte and the sib byte where the 130 addressing modes of this insn are encoded. */ 131 132 modrm_byte rm; 133 sib_byte sib; 134 }; 135 136typedef struct _i386_insn i386_insn; 137 138/* List of chars besides those in app.c:symbol_chars that can start an 139 operand. Used to prevent the scrubber eating vital white-space. */ 140#ifdef LEX_AT 141const char extra_symbol_chars[] = "*%-(@"; 142#else 143const char extra_symbol_chars[] = "*%-("; 144#endif 145 146/* This array holds the chars that always start a comment. If the 147 pre-processor is disabled, these aren't very useful */ 148#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) 149/* Putting '/' here makes it impossible to use the divide operator. 150 However, we need it for compatibility with SVR4 systems. */ 151const char comment_chars[] = "#/"; 152#define PREFIX_SEPARATOR '\\' 153#else 154const char comment_chars[] = "#"; 155#define PREFIX_SEPARATOR '/' 156#endif 157 158/* This array holds the chars that only start a comment at the beginning of 159 a line. If the line seems to have the form '# 123 filename' 160 .line and .file directives will appear in the pre-processed output */ 161/* Note that input_file.c hand checks for '#' at the beginning of the 162 first line of the input file. This is because the compiler outputs 163 #NO_APP at the beginning of its output. */ 164/* Also note that comments started like this one will always work if 165 '/' isn't otherwise defined. */ 166#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) 167const char line_comment_chars[] = ""; 168#else 169const char line_comment_chars[] = "/"; 170#endif 171 172const char line_separator_chars[] = ""; 173 174/* Chars that can be used to separate mant from exp in floating point nums */ 175const char EXP_CHARS[] = "eE"; 176 177/* Chars that mean this number is a floating point constant */ 178/* As in 0f12.456 */ 179/* or 0d1.2345e12 */ 180const char FLT_CHARS[] = "fFdDxX"; 181 182/* tables for lexical analysis */ 183static char mnemonic_chars[256]; 184static char register_chars[256]; 185static char operand_chars[256]; 186static char identifier_chars[256]; 187static char digit_chars[256]; 188 189/* lexical macros */ 190#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 191#define is_operand_char(x) (operand_chars[(unsigned char) x]) 192#define is_register_char(x) (register_chars[(unsigned char) x]) 193#define is_space_char(x) ((x) == ' ') 194#define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 195#define is_digit_char(x) (digit_chars[(unsigned char) x]) 196 197/* put here all non-digit non-letter charcters that may occur in an operand */ 198static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 199 200/* md_assemble() always leaves the strings it's passed unaltered. To 201 effect this we maintain a stack of saved characters that we've smashed 202 with '\0's (indicating end of strings for various sub-fields of the 203 assembler instruction). */ 204static char save_stack[32]; 205static char *save_stack_p; /* stack pointer */ 206#define END_STRING_AND_SAVE(s) \ 207 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 208#define RESTORE_END_STRING(s) \ 209 do { *(s) = *--save_stack_p; } while (0) 210 211/* The instruction we're assembling. */ 212static i386_insn i; 213 214/* Possible templates for current insn. */ 215static const templates *current_templates; 216 217/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ 218static expressionS disp_expressions[2], im_expressions[2]; 219 220static int this_operand; /* current operand we are working on */ 221 222static int flag_do_long_jump; /* FIXME what does this do? */ 223 224static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ 225 226static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax */ 227 228static int allow_naked_reg = 0; /* 1 if register prefix % not required */ 229 230static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l 231 suffix to call, ret, enter, leave, push, 232 and pop instructions so that gcc has the 233 same stack frame as in 32 bit mode. */ 234 235/* Interface to relax_segment. 236 There are 2 relax states for 386 jump insns: one for conditional & 237 one for unconditional jumps. This is because these two types of 238 jumps add different sizes to frags when we're figuring out what 239 sort of jump to choose to reach a given label. */ 240 241/* types */ 242#define COND_JUMP 1 /* conditional jump */ 243#define UNCOND_JUMP 2 /* unconditional jump */ 244/* sizes */ 245#define CODE16 1 246#define SMALL 0 247#define SMALL16 (SMALL|CODE16) 248#define BIG 2 249#define BIG16 (BIG|CODE16) 250 251#ifndef INLINE 252#ifdef __GNUC__ 253#define INLINE __inline__ 254#else 255#define INLINE 256#endif 257#endif 258 259#define ENCODE_RELAX_STATE(type,size) \ 260 ((relax_substateT)((type<<2) | (size))) 261#define SIZE_FROM_RELAX_STATE(s) \ 262 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) 263 264/* This table is used by relax_frag to promote short jumps to long 265 ones where necessary. SMALL (short) jumps may be promoted to BIG 266 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 267 don't allow a short jump in a 32 bit code segment to be promoted to 268 a 16 bit offset jump because it's slower (requires data size 269 prefix), and doesn't work, unless the destination is in the bottom 270 64k of the code segment (The top 16 bits of eip are zeroed). */ 271 272const relax_typeS md_relax_table[] = 273{ 274 /* The fields are: 275 1) most positive reach of this state, 276 2) most negative reach of this state, 277 3) how many bytes this mode will add to the size of the current frag 278 4) which index into the table to try if we can't fit into this one. 279 */ 280 {1, 1, 0, 0}, 281 {1, 1, 0, 0}, 282 {1, 1, 0, 0}, 283 {1, 1, 0, 0}, 284 285 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 286 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 287 /* dword conditionals adds 4 bytes to frag: 288 1 extra opcode byte, 3 extra displacement bytes. */ 289 {0, 0, 4, 0}, 290 /* word conditionals add 2 bytes to frag: 291 1 extra opcode byte, 1 extra displacement byte. */ 292 {0, 0, 2, 0}, 293 294 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 295 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 296 /* dword jmp adds 3 bytes to frag: 297 0 extra opcode bytes, 3 extra displacement bytes. */ 298 {0, 0, 3, 0}, 299 /* word jmp adds 1 byte to frag: 300 0 extra opcode bytes, 1 extra displacement byte. */ 301 {0, 0, 1, 0} 302 303}; 304 305 306void 307i386_align_code (fragP, count) 308 fragS *fragP; 309 int count; 310{ 311 /* Various efficient no-op patterns for aligning code labels. */ 312 /* Note: Don't try to assemble the instructions in the comments. */ 313 /* 0L and 0w are not legal */ 314 static const char f32_1[] = 315 {0x90}; /* nop */ 316 static const char f32_2[] = 317 {0x89,0xf6}; /* movl %esi,%esi */ 318 static const char f32_3[] = 319 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 320 static const char f32_4[] = 321 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 322 static const char f32_5[] = 323 {0x90, /* nop */ 324 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 325 static const char f32_6[] = 326 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 327 static const char f32_7[] = 328 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 329 static const char f32_8[] = 330 {0x90, /* nop */ 331 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 332 static const char f32_9[] = 333 {0x89,0xf6, /* movl %esi,%esi */ 334 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 335 static const char f32_10[] = 336 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 337 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 338 static const char f32_11[] = 339 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 340 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 341 static const char f32_12[] = 342 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 343 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 344 static const char f32_13[] = 345 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 346 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 347 static const char f32_14[] = 348 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 349 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 350 static const char f32_15[] = 351 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ 352 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 353 static const char f16_3[] = 354 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 355 static const char f16_4[] = 356 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 357 static const char f16_5[] = 358 {0x90, /* nop */ 359 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 360 static const char f16_6[] = 361 {0x89,0xf6, /* mov %si,%si */ 362 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 363 static const char f16_7[] = 364 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 365 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 366 static const char f16_8[] = 367 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 368 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 369 static const char *const f32_patt[] = { 370 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 371 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 372 }; 373 static const char *const f16_patt[] = { 374 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, 375 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 376 }; 377 378 if (count > 0 && count <= 15) 379 { 380 if (flag_16bit_code) 381 { 382 memcpy(fragP->fr_literal + fragP->fr_fix, 383 f16_patt[count - 1], count); 384 if (count > 8) /* adjust jump offset */ 385 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 386 } 387 else 388 memcpy(fragP->fr_literal + fragP->fr_fix, 389 f32_patt[count - 1], count); 390 fragP->fr_var = count; 391 } 392} 393 394static char *output_invalid PARAMS ((int c)); 395static int i386_operand PARAMS ((char *operand_string)); 396static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); 397static const reg_entry *parse_register PARAMS ((char *reg_string, 398 char **end_op)); 399 400#ifndef I386COFF 401static void s_bss PARAMS ((int)); 402#endif 403 404symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 405 406static INLINE unsigned int 407mode_from_disp_size (t) 408 unsigned int t; 409{ 410 return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0; 411} 412 413static INLINE int 414fits_in_signed_byte (num) 415 long num; 416{ 417 return (num >= -128) && (num <= 127); 418} /* fits_in_signed_byte() */ 419 420static INLINE int 421fits_in_unsigned_byte (num) 422 long num; 423{ 424 return (num & 0xff) == num; 425} /* fits_in_unsigned_byte() */ 426 427static INLINE int 428fits_in_unsigned_word (num) 429 long num; 430{ 431 return (num & 0xffff) == num; 432} /* fits_in_unsigned_word() */ 433 434static INLINE int 435fits_in_signed_word (num) 436 long num; 437{ 438 return (-32768 <= num) && (num <= 32767); 439} /* fits_in_signed_word() */ 440 441static int 442smallest_imm_type (num) 443 long num; 444{ 445#if 0 446 /* This code is disabled because all the Imm1 forms in the opcode table 447 are slower on the i486, and they're the versions with the implicitly 448 specified single-position displacement, which has another syntax if 449 you really want to use that form. If you really prefer to have the 450 one-byte-shorter Imm1 form despite these problems, re-enable this 451 code. */ 452 if (num == 1) 453 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; 454#endif 455 return (fits_in_signed_byte (num) 456 ? (Imm8S | Imm8 | Imm16 | Imm32) 457 : fits_in_unsigned_byte (num) 458 ? (Imm8 | Imm16 | Imm32) 459 : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 460 ? (Imm16 | Imm32) 461 : (Imm32)); 462} /* smallest_imm_type() */ 463 464/* Returns 0 if attempting to add a prefix where one from the same 465 class already exists, 1 if non rep/repne added, 2 if rep/repne 466 added. */ 467static int 468add_prefix (prefix) 469 unsigned int prefix; 470{ 471 int ret = 1; 472 int q; 473 474 switch (prefix) 475 { 476 default: 477 abort (); 478 479 case CS_PREFIX_OPCODE: 480 case DS_PREFIX_OPCODE: 481 case ES_PREFIX_OPCODE: 482 case FS_PREFIX_OPCODE: 483 case GS_PREFIX_OPCODE: 484 case SS_PREFIX_OPCODE: 485 q = SEG_PREFIX; 486 break; 487 488 case REPNE_PREFIX_OPCODE: 489 case REPE_PREFIX_OPCODE: 490 ret = 2; 491 /* fall thru */ 492 case LOCK_PREFIX_OPCODE: 493 q = LOCKREP_PREFIX; 494 break; 495 496 case FWAIT_OPCODE: 497 q = WAIT_PREFIX; 498 break; 499 500 case ADDR_PREFIX_OPCODE: 501 q = ADDR_PREFIX; 502 break; 503 504 case DATA_PREFIX_OPCODE: 505 q = DATA_PREFIX; 506 break; 507 } 508 509 if (i.prefix[q]) 510 { 511 as_bad (_("same type of prefix used twice")); 512 return 0; 513 } 514 515 i.prefixes += 1; 516 i.prefix[q] = prefix; 517 return ret; 518} 519 520static void 521set_16bit_code_flag (new_16bit_code_flag) 522 int new_16bit_code_flag; 523{ 524 flag_16bit_code = new_16bit_code_flag; 525 stackop_size = '\0'; 526} 527 528static void 529set_16bit_gcc_code_flag (new_16bit_code_flag) 530 int new_16bit_code_flag; 531{ 532 flag_16bit_code = new_16bit_code_flag; 533 stackop_size = new_16bit_code_flag ? 'l' : '\0'; 534} 535 536static void 537set_intel_syntax (syntax_flag) 538 int syntax_flag; 539{ 540 /* Find out if register prefixing is specified. */ 541 int ask_naked_reg = 0; 542 543 SKIP_WHITESPACE (); 544 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 545 { 546 char *string = input_line_pointer; 547 int e = get_symbol_end (); 548 549 if (strcmp(string, "prefix") == 0) 550 ask_naked_reg = 1; 551 else if (strcmp(string, "noprefix") == 0) 552 ask_naked_reg = -1; 553 else 554 as_bad (_("bad argument to syntax directive.")); 555 *input_line_pointer = e; 556 } 557 demand_empty_rest_of_line (); 558 559 intel_syntax = syntax_flag; 560 561 if (ask_naked_reg == 0) 562 { 563#ifdef BFD_ASSEMBLER 564 allow_naked_reg = (intel_syntax 565 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 566#else 567 allow_naked_reg = 0; /* conservative default */ 568#endif 569 } 570 else 571 allow_naked_reg = (ask_naked_reg < 0); 572} 573 574const pseudo_typeS md_pseudo_table[] = 575{ 576#ifndef I386COFF 577 {"bss", s_bss, 0}, 578#endif 579#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 580 {"align", s_align_bytes, 0}, 581#else 582 {"align", s_align_ptwo, 0}, 583#endif 584 {"ffloat", float_cons, 'f'}, 585 {"dfloat", float_cons, 'd'}, 586 {"tfloat", float_cons, 'x'}, 587 {"value", cons, 2}, 588 {"noopt", s_ignore, 0}, 589 {"optim", s_ignore, 0}, 590 {"code16gcc", set_16bit_gcc_code_flag, 1}, 591 {"code16", set_16bit_code_flag, 1}, 592 {"code32", set_16bit_code_flag, 0}, 593 {"intel_syntax", set_intel_syntax, 1}, 594 {"att_syntax", set_intel_syntax, 0}, 595 {0, 0, 0} 596}; 597 598/* for interface with expression () */ 599extern char *input_line_pointer; 600 601/* hash table for instruction mnemonic lookup */ 602static struct hash_control *op_hash; 603/* hash table for register lookup */ 604static struct hash_control *reg_hash; 605 606 607void 608md_begin () 609{ 610 const char *hash_err; 611 612 /* initialize op_hash hash table */ 613 op_hash = hash_new (); 614 615 { 616 register const template *optab; 617 register templates *core_optab; 618 619 optab = i386_optab; /* setup for loop */ 620 core_optab = (templates *) xmalloc (sizeof (templates)); 621 core_optab->start = optab; 622 623 while (1) 624 { 625 ++optab; 626 if (optab->name == NULL 627 || strcmp (optab->name, (optab - 1)->name) != 0) 628 { 629 /* different name --> ship out current template list; 630 add to hash table; & begin anew */ 631 core_optab->end = optab; 632 hash_err = hash_insert (op_hash, 633 (optab - 1)->name, 634 (PTR) core_optab); 635 if (hash_err) 636 { 637 hash_error: 638 as_fatal (_("Internal Error: Can't hash %s: %s"), 639 (optab - 1)->name, 640 hash_err); 641 } 642 if (optab->name == NULL) 643 break; 644 core_optab = (templates *) xmalloc (sizeof (templates)); 645 core_optab->start = optab; 646 } 647 } 648 } 649 650 /* initialize reg_hash hash table */ 651 reg_hash = hash_new (); 652 { 653 register const reg_entry *regtab; 654 655 for (regtab = i386_regtab; 656 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); 657 regtab++) 658 { 659 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); 660 if (hash_err) 661 goto hash_error; 662 } 663 } 664 665 /* fill in lexical tables: mnemonic_chars, operand_chars. */ 666 { 667 register int c; 668 register char *p; 669 670 for (c = 0; c < 256; c++) 671 { 672 if (isdigit (c)) 673 { 674 digit_chars[c] = c; 675 mnemonic_chars[c] = c; 676 register_chars[c] = c; 677 operand_chars[c] = c; 678 } 679 else if (islower (c)) 680 { 681 mnemonic_chars[c] = c; 682 register_chars[c] = c; 683 operand_chars[c] = c; 684 } 685 else if (isupper (c)) 686 { 687 mnemonic_chars[c] = tolower (c); 688 register_chars[c] = mnemonic_chars[c]; 689 operand_chars[c] = c; 690 } 691 692 if (isalpha (c) || isdigit (c)) 693 identifier_chars[c] = c; 694 else if (c >= 128) 695 { 696 identifier_chars[c] = c; 697 operand_chars[c] = c; 698 } 699 } 700 701#ifdef LEX_AT 702 identifier_chars['@'] = '@'; 703#endif 704 digit_chars['-'] = '-'; 705 identifier_chars['_'] = '_'; 706 identifier_chars['.'] = '.'; 707 708 for (p = operand_special_chars; *p != '\0'; p++) 709 operand_chars[(unsigned char) *p] = *p; 710 } 711 712#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 713 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 714 { 715 record_alignment (text_section, 2); 716 record_alignment (data_section, 2); 717 record_alignment (bss_section, 2); 718 } 719#endif 720} 721 722void 723i386_print_statistics (file) 724 FILE *file; 725{ 726 hash_print_statistics (file, "i386 opcode", op_hash); 727 hash_print_statistics (file, "i386 register", reg_hash); 728} 729 730 731#ifdef DEBUG386 732 733/* debugging routines for md_assemble */ 734static void pi PARAMS ((char *, i386_insn *)); 735static void pte PARAMS ((template *)); 736static void pt PARAMS ((unsigned int)); 737static void pe PARAMS ((expressionS *)); 738static void ps PARAMS ((symbolS *)); 739 740static void 741pi (line, x) 742 char *line; 743 i386_insn *x; 744{ 745 register template *p; 746 int i; 747 748 fprintf (stdout, "%s: template ", line); 749 pte (&x->tm); 750 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", 751 x->rm.mode, x->rm.reg, x->rm.regmem); 752 fprintf (stdout, " base %x index %x scale %x\n", 753 x->bi.base, x->bi.index, x->bi.scale); 754 for (i = 0; i < x->operands; i++) 755 { 756 fprintf (stdout, " #%d: ", i + 1); 757 pt (x->types[i]); 758 fprintf (stdout, "\n"); 759 if (x->types[i] 760 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) 761 fprintf (stdout, "%s\n", x->op[i].regs->reg_name); 762 if (x->types[i] & Imm) 763 pe (x->op[i].imms); 764 if (x->types[i] & Disp) 765 pe (x->op[i].disps); 766 } 767} 768 769static void 770pte (t) 771 template *t; 772{ 773 int i; 774 fprintf (stdout, " %d operands ", t->operands); 775 fprintf (stdout, "opcode %x ", 776 t->base_opcode); 777 if (t->extension_opcode != None) 778 fprintf (stdout, "ext %x ", t->extension_opcode); 779 if (t->opcode_modifier & D) 780 fprintf (stdout, "D"); 781 if (t->opcode_modifier & W) 782 fprintf (stdout, "W"); 783 fprintf (stdout, "\n"); 784 for (i = 0; i < t->operands; i++) 785 { 786 fprintf (stdout, " #%d type ", i + 1); 787 pt (t->operand_types[i]); 788 fprintf (stdout, "\n"); 789 } 790} 791 792static void 793pe (e) 794 expressionS *e; 795{ 796 fprintf (stdout, " operation %d\n", e->X_op); 797 fprintf (stdout, " add_number %ld (%lx)\n", 798 (long) e->X_add_number, (long) e->X_add_number); 799 if (e->X_add_symbol) 800 { 801 fprintf (stdout, " add_symbol "); 802 ps (e->X_add_symbol); 803 fprintf (stdout, "\n"); 804 } 805 if (e->X_op_symbol) 806 { 807 fprintf (stdout, " op_symbol "); 808 ps (e->X_op_symbol); 809 fprintf (stdout, "\n"); 810 } 811} 812 813static void 814ps (s) 815 symbolS *s; 816{ 817 fprintf (stdout, "%s type %s%s", 818 S_GET_NAME (s), 819 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 820 segment_name (S_GET_SEGMENT (s))); 821} 822 823struct type_name 824 { 825 unsigned int mask; 826 char *tname; 827 } 828 829type_names[] = 830{ 831 { Reg8, "r8" }, 832 { Reg16, "r16" }, 833 { Reg32, "r32" }, 834 { Imm8, "i8" }, 835 { Imm8S, "i8s" }, 836 { Imm16, "i16" }, 837 { Imm32, "i32" }, 838 { Imm1, "i1" }, 839 { BaseIndex, "BaseIndex" }, 840 { Disp8, "d8" }, 841 { Disp16, "d16" }, 842 { Disp32, "d32" }, 843 { InOutPortReg, "InOutPortReg" }, 844 { ShiftCount, "ShiftCount" }, 845 { Control, "control reg" }, 846 { Test, "test reg" }, 847 { Debug, "debug reg" }, 848 { FloatReg, "FReg" }, 849 { FloatAcc, "FAcc" }, 850 { SReg2, "SReg2" }, 851 { SReg3, "SReg3" }, 852 { Acc, "Acc" }, 853 { JumpAbsolute, "Jump Absolute" }, 854 { RegMMX, "rMMX" }, 855 { RegXMM, "rXMM" }, 856 { EsSeg, "es" }, 857 { 0, "" } 858}; 859 860static void 861pt (t) 862 unsigned int t; 863{ 864 register struct type_name *ty; 865 866 if (t == Unknown) 867 { 868 fprintf (stdout, _("Unknown")); 869 } 870 else 871 { 872 for (ty = type_names; ty->mask; ty++) 873 if (t & ty->mask) 874 fprintf (stdout, "%s, ", ty->tname); 875 } 876 fflush (stdout); 877} 878 879#endif /* DEBUG386 */ 880 881int 882tc_i386_force_relocation (fixp) 883 struct fix *fixp; 884{ 885#ifdef BFD_ASSEMBLER 886 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 887 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 888 return 1; 889 return 0; 890#else 891 /* For COFF */ 892 return fixp->fx_r_type == 7; 893#endif 894} 895 896#ifdef BFD_ASSEMBLER 897static bfd_reloc_code_real_type reloc 898 PARAMS ((int, int, bfd_reloc_code_real_type)); 899 900static bfd_reloc_code_real_type 901reloc (size, pcrel, other) 902 int size; 903 int pcrel; 904 bfd_reloc_code_real_type other; 905{ 906 if (other != NO_RELOC) return other; 907 908 if (pcrel) 909 { 910 switch (size) 911 { 912 case 1: return BFD_RELOC_8_PCREL; 913 case 2: return BFD_RELOC_16_PCREL; 914 case 4: return BFD_RELOC_32_PCREL; 915 } 916 as_bad (_("can not do %d byte pc-relative relocation"), size); 917 } 918 else 919 { 920 switch (size) 921 { 922 case 1: return BFD_RELOC_8; 923 case 2: return BFD_RELOC_16; 924 case 4: return BFD_RELOC_32; 925 } 926 as_bad (_("can not do %d byte relocation"), size); 927 } 928 929 return BFD_RELOC_NONE; 930} 931 932/* 933 * Here we decide which fixups can be adjusted to make them relative to 934 * the beginning of the section instead of the symbol. Basically we need 935 * to make sure that the dynamic relocations are done correctly, so in 936 * some cases we force the original symbol to be used. 937 */ 938int 939tc_i386_fix_adjustable (fixP) 940 fixS *fixP; 941{ 942#if defined (OBJ_ELF) || defined (TE_PE) 943 /* Prevent all adjustments to global symbols, or else dynamic 944 linking will not work correctly. */ 945 if (S_IS_EXTERN (fixP->fx_addsy)) 946 return 0; 947 if (S_IS_WEAK (fixP->fx_addsy)) 948 return 0; 949#endif 950 /* adjust_reloc_syms doesn't know about the GOT */ 951 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF 952 || fixP->fx_r_type == BFD_RELOC_386_PLT32 953 || fixP->fx_r_type == BFD_RELOC_386_GOT32 954 || fixP->fx_r_type == BFD_RELOC_RVA 955 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 956 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 957 return 0; 958 return 1; 959} 960#else 961#define reloc(SIZE,PCREL,OTHER) 0 962#define BFD_RELOC_16 0 963#define BFD_RELOC_32 0 964#define BFD_RELOC_16_PCREL 0 965#define BFD_RELOC_32_PCREL 0 966#define BFD_RELOC_386_PLT32 0 967#define BFD_RELOC_386_GOT32 0 968#define BFD_RELOC_386_GOTOFF 0 969#endif 970 971static int 972intel_float_operand PARAMS ((char *mnemonic)); 973 974static int 975intel_float_operand (mnemonic) 976 char *mnemonic; 977{ 978 if (mnemonic[0] == 'f' && mnemonic[1] =='i') 979 return 2; 980 981 if (mnemonic[0] == 'f') 982 return 1; 983 984 return 0; 985} 986 987/* This is the guts of the machine-dependent assembler. LINE points to a 988 machine dependent instruction. This function is supposed to emit 989 the frags/bytes it assembles to. */ 990 991void 992md_assemble (line) 993 char *line; 994{ 995 /* Points to template once we've found it. */ 996 const template *t; 997 998 /* Count the size of the instruction generated. */ 999 int insn_size = 0; 1000 1001 int j; 1002 1003 char mnemonic[MAX_MNEM_SIZE]; 1004 1005 /* Initialize globals. */ 1006 memset (&i, '\0', sizeof (i)); 1007 for (j = 0; j < MAX_OPERANDS; j++) 1008 i.disp_reloc[j] = NO_RELOC; 1009 memset (disp_expressions, '\0', sizeof (disp_expressions)); 1010 memset (im_expressions, '\0', sizeof (im_expressions)); 1011 save_stack_p = save_stack; /* reset stack pointer */ 1012 1013 /* First parse an instruction mnemonic & call i386_operand for the operands. 1014 We assume that the scrubber has arranged it so that line[0] is the valid 1015 start of a (possibly prefixed) mnemonic. */ 1016 { 1017 char *l = line; 1018 char *token_start = l; 1019 char *mnem_p; 1020 1021 /* Non-zero if we found a prefix only acceptable with string insns. */ 1022 const char *expecting_string_instruction = NULL; 1023 1024 while (1) 1025 { 1026 mnem_p = mnemonic; 1027 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 1028 { 1029 mnem_p++; 1030 if (mnem_p >= mnemonic + sizeof (mnemonic)) 1031 { 1032 as_bad (_("no such 386 instruction: `%s'"), token_start); 1033 return; 1034 } 1035 l++; 1036 } 1037 if (!is_space_char (*l) 1038 && *l != END_OF_INSN 1039 && *l != PREFIX_SEPARATOR) 1040 { 1041 as_bad (_("invalid character %s in mnemonic"), 1042 output_invalid (*l)); 1043 return; 1044 } 1045 if (token_start == l) 1046 { 1047 if (*l == PREFIX_SEPARATOR) 1048 as_bad (_("expecting prefix; got nothing")); 1049 else 1050 as_bad (_("expecting mnemonic; got nothing")); 1051 return; 1052 } 1053 1054 /* Look up instruction (or prefix) via hash table. */ 1055 current_templates = hash_find (op_hash, mnemonic); 1056 1057 if (*l != END_OF_INSN 1058 && (! is_space_char (*l) || l[1] != END_OF_INSN) 1059 && current_templates 1060 && (current_templates->start->opcode_modifier & IsPrefix)) 1061 { 1062 /* If we are in 16-bit mode, do not allow addr16 or data16. 1063 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 1064 if ((current_templates->start->opcode_modifier & (Size16 | Size32)) 1065 && (((current_templates->start->opcode_modifier & Size32) != 0) 1066 ^ flag_16bit_code)) 1067 { 1068 as_bad (_("redundant %s prefix"), 1069 current_templates->start->name); 1070 return; 1071 } 1072 /* Add prefix, checking for repeated prefixes. */ 1073 switch (add_prefix (current_templates->start->base_opcode)) 1074 { 1075 case 0: 1076 return; 1077 case 2: 1078 expecting_string_instruction = 1079 current_templates->start->name; 1080 break; 1081 } 1082 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 1083 token_start = ++l; 1084 } 1085 else 1086 break; 1087 } 1088 1089 if (!current_templates) 1090 { 1091 /* See if we can get a match by trimming off a suffix. */ 1092 switch (mnem_p[-1]) 1093 { 1094 case WORD_MNEM_SUFFIX: 1095 case BYTE_MNEM_SUFFIX: 1096 case SHORT_MNEM_SUFFIX: 1097 case LONG_MNEM_SUFFIX: 1098 i.suffix = mnem_p[-1]; 1099 mnem_p[-1] = '\0'; 1100 current_templates = hash_find (op_hash, mnemonic); 1101 break; 1102 1103 /* Intel Syntax */ 1104 case DWORD_MNEM_SUFFIX: 1105 if (intel_syntax) 1106 { 1107 i.suffix = mnem_p[-1]; 1108 mnem_p[-1] = '\0'; 1109 current_templates = hash_find (op_hash, mnemonic); 1110 break; 1111 } 1112 } 1113 if (!current_templates) 1114 { 1115 as_bad (_("no such 386 instruction: `%s'"), token_start); 1116 return; 1117 } 1118 } 1119 1120 /* check for rep/repne without a string instruction */ 1121 if (expecting_string_instruction 1122 && !(current_templates->start->opcode_modifier & IsString)) 1123 { 1124 as_bad (_("expecting string instruction after `%s'"), 1125 expecting_string_instruction); 1126 return; 1127 } 1128 1129 /* There may be operands to parse. */ 1130 if (*l != END_OF_INSN) 1131 { 1132 /* parse operands */ 1133 1134 /* 1 if operand is pending after ','. */ 1135 unsigned int expecting_operand = 0; 1136 1137 /* Non-zero if operand parens not balanced. */ 1138 unsigned int paren_not_balanced; 1139 1140 do 1141 { 1142 /* skip optional white space before operand */ 1143 if (is_space_char (*l)) 1144 ++l; 1145 if (!is_operand_char (*l) && *l != END_OF_INSN) 1146 { 1147 as_bad (_("invalid character %s before operand %d"), 1148 output_invalid (*l), 1149 i.operands + 1); 1150 return; 1151 } 1152 token_start = l; /* after white space */ 1153 paren_not_balanced = 0; 1154 while (paren_not_balanced || *l != ',') 1155 { 1156 if (*l == END_OF_INSN) 1157 { 1158 if (paren_not_balanced) 1159 { 1160 if (!intel_syntax) 1161 as_bad (_("unbalanced parenthesis in operand %d."), 1162 i.operands + 1); 1163 else 1164 as_bad (_("unbalanced brackets in operand %d."), 1165 i.operands + 1); 1166 return; 1167 } 1168 else 1169 break; /* we are done */ 1170 } 1171 else if (!is_operand_char (*l) && !is_space_char (*l)) 1172 { 1173 as_bad (_("invalid character %s in operand %d"), 1174 output_invalid (*l), 1175 i.operands + 1); 1176 return; 1177 } 1178 if (!intel_syntax) 1179 { 1180 if (*l == '(') 1181 ++paren_not_balanced; 1182 if (*l == ')') 1183 --paren_not_balanced; 1184 } 1185 else 1186 { 1187 if (*l == '[') 1188 ++paren_not_balanced; 1189 if (*l == ']') 1190 --paren_not_balanced; 1191 } 1192 l++; 1193 } 1194 if (l != token_start) 1195 { /* yes, we've read in another operand */ 1196 unsigned int operand_ok; 1197 this_operand = i.operands++; 1198 if (i.operands > MAX_OPERANDS) 1199 { 1200 as_bad (_("spurious operands; (%d operands/instruction max)"), 1201 MAX_OPERANDS); 1202 return; 1203 } 1204 /* now parse operand adding info to 'i' as we go along */ 1205 END_STRING_AND_SAVE (l); 1206 1207 if (intel_syntax) 1208 operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic)); 1209 else 1210 operand_ok = i386_operand (token_start); 1211 1212 RESTORE_END_STRING (l); /* restore old contents */ 1213 if (!operand_ok) 1214 return; 1215 } 1216 else 1217 { 1218 if (expecting_operand) 1219 { 1220 expecting_operand_after_comma: 1221 as_bad (_("expecting operand after ','; got nothing")); 1222 return; 1223 } 1224 if (*l == ',') 1225 { 1226 as_bad (_("expecting operand before ','; got nothing")); 1227 return; 1228 } 1229 } 1230 1231 /* now *l must be either ',' or END_OF_INSN */ 1232 if (*l == ',') 1233 { 1234 if (*++l == END_OF_INSN) 1235 { /* just skip it, if it's \n complain */ 1236 goto expecting_operand_after_comma; 1237 } 1238 expecting_operand = 1; 1239 } 1240 } 1241 while (*l != END_OF_INSN); /* until we get end of insn */ 1242 } 1243 } 1244 1245 /* Now we've parsed the mnemonic into a set of templates, and have the 1246 operands at hand. 1247 1248 Next, we find a template that matches the given insn, 1249 making sure the overlap of the given operands types is consistent 1250 with the template operand types. */ 1251 1252#define MATCH(overlap, given, template) \ 1253 ((overlap & ~JumpAbsolute) \ 1254 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) 1255 1256 /* If given types r0 and r1 are registers they must be of the same type 1257 unless the expected operand type register overlap is null. 1258 Note that Acc in a template matches every size of reg. */ 1259#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ 1260 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ 1261 ((g0) & Reg) == ((g1) & Reg) || \ 1262 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) 1263 1264 { 1265 register unsigned int overlap0, overlap1; 1266 unsigned int overlap2; 1267 unsigned int found_reverse_match; 1268 int suffix_check; 1269 1270 /* All intel opcodes have reversed operands except for "bound" and 1271 "enter". We also don't reverse intersegment "jmp" and "call" 1272 instructions with 2 immediate operands so that the immediate segment 1273 precedes the offset, as it does when in AT&T mode. "enter" and the 1274 intersegment "jmp" and "call" instructions are the only ones that 1275 have two immediate operands. */ 1276 if (intel_syntax && i.operands > 1 1277 && (strcmp (mnemonic, "bound") != 0) 1278 && !((i.types[0] & Imm) && (i.types[1] & Imm))) 1279 { 1280 union i386_op temp_op; 1281 unsigned int temp_type; 1282 int xchg1 = 0; 1283 int xchg2 = 0; 1284 1285 if (i.operands == 2) 1286 { 1287 xchg1 = 0; 1288 xchg2 = 1; 1289 } 1290 else if (i.operands == 3) 1291 { 1292 xchg1 = 0; 1293 xchg2 = 2; 1294 } 1295 temp_type = i.types[xchg2]; 1296 i.types[xchg2] = i.types[xchg1]; 1297 i.types[xchg1] = temp_type; 1298 temp_op = i.op[xchg2]; 1299 i.op[xchg2] = i.op[xchg1]; 1300 i.op[xchg1] = temp_op; 1301 1302 if (i.mem_operands == 2) 1303 { 1304 const seg_entry *temp_seg; 1305 temp_seg = i.seg[0]; 1306 i.seg[0] = i.seg[1]; 1307 i.seg[1] = temp_seg; 1308 } 1309 } 1310 1311 if (i.imm_operands) 1312 { 1313 /* Try to ensure constant immediates are represented in the smallest 1314 opcode possible. */ 1315 char guess_suffix = 0; 1316 int op; 1317 1318 if (i.suffix) 1319 guess_suffix = i.suffix; 1320 else if (i.reg_operands) 1321 { 1322 /* Figure out a suffix from the last register operand specified. 1323 We can't do this properly yet, ie. excluding InOutPortReg, 1324 but the following works for instructions with immediates. 1325 In any case, we can't set i.suffix yet. */ 1326 for (op = i.operands; --op >= 0; ) 1327 if (i.types[op] & Reg) 1328 { 1329 if (i.types[op] & Reg8) 1330 guess_suffix = BYTE_MNEM_SUFFIX; 1331 else if (i.types[op] & Reg16) 1332 guess_suffix = WORD_MNEM_SUFFIX; 1333 break; 1334 } 1335 } 1336 else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) 1337 guess_suffix = WORD_MNEM_SUFFIX; 1338 1339 for (op = i.operands; --op >= 0; ) 1340 if ((i.types[op] & Imm) 1341 && i.op[op].imms->X_op == O_constant) 1342 { 1343 /* If a suffix is given, this operand may be shortened. */ 1344 switch (guess_suffix) 1345 { 1346 case WORD_MNEM_SUFFIX: 1347 i.types[op] |= Imm16; 1348 break; 1349 case BYTE_MNEM_SUFFIX: 1350 i.types[op] |= Imm16 | Imm8 | Imm8S; 1351 break; 1352 } 1353 1354 /* If this operand is at most 16 bits, convert it to a 1355 signed 16 bit number before trying to see whether it will 1356 fit in an even smaller size. This allows a 16-bit operand 1357 such as $0xffe0 to be recognised as within Imm8S range. */ 1358 if ((i.types[op] & Imm16) 1359 && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) 1360 { 1361 i.op[op].imms->X_add_number = 1362 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 1363 } 1364 i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); 1365 } 1366 } 1367 1368 overlap0 = 0; 1369 overlap1 = 0; 1370 overlap2 = 0; 1371 found_reverse_match = 0; 1372 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX 1373 ? No_bSuf 1374 : (i.suffix == WORD_MNEM_SUFFIX 1375 ? No_wSuf 1376 : (i.suffix == SHORT_MNEM_SUFFIX 1377 ? No_sSuf 1378 : (i.suffix == LONG_MNEM_SUFFIX 1379 ? No_lSuf 1380 : (i.suffix == DWORD_MNEM_SUFFIX 1381 ? No_dSuf 1382 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); 1383 1384 for (t = current_templates->start; 1385 t < current_templates->end; 1386 t++) 1387 { 1388 /* Must have right number of operands. */ 1389 if (i.operands != t->operands) 1390 continue; 1391 1392 /* Check the suffix, except for some instructions in intel mode. */ 1393 if ((t->opcode_modifier & suffix_check) 1394 && !(intel_syntax 1395 && t->base_opcode == 0xd9 1396 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ 1397 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ 1398 continue; 1399 1400 else if (!t->operands) 1401 break; /* 0 operands always matches */ 1402 1403 overlap0 = i.types[0] & t->operand_types[0]; 1404 switch (t->operands) 1405 { 1406 case 1: 1407 if (!MATCH (overlap0, i.types[0], t->operand_types[0])) 1408 continue; 1409 break; 1410 case 2: 1411 case 3: 1412 overlap1 = i.types[1] & t->operand_types[1]; 1413 if (!MATCH (overlap0, i.types[0], t->operand_types[0]) 1414 || !MATCH (overlap1, i.types[1], t->operand_types[1]) 1415 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 1416 t->operand_types[0], 1417 overlap1, i.types[1], 1418 t->operand_types[1])) 1419 { 1420 1421 /* check if other direction is valid ... */ 1422 if ((t->opcode_modifier & (D|FloatD)) == 0) 1423 continue; 1424 1425 /* try reversing direction of operands */ 1426 overlap0 = i.types[0] & t->operand_types[1]; 1427 overlap1 = i.types[1] & t->operand_types[0]; 1428 if (!MATCH (overlap0, i.types[0], t->operand_types[1]) 1429 || !MATCH (overlap1, i.types[1], t->operand_types[0]) 1430 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 1431 t->operand_types[1], 1432 overlap1, i.types[1], 1433 t->operand_types[0])) 1434 { 1435 /* does not match either direction */ 1436 continue; 1437 } 1438 /* found_reverse_match holds which of D or FloatDR 1439 we've found. */ 1440 found_reverse_match = t->opcode_modifier & (D|FloatDR); 1441 break; 1442 } 1443 /* found a forward 2 operand match here */ 1444 if (t->operands == 3) 1445 { 1446 /* Here we make use of the fact that there are no 1447 reverse match 3 operand instructions, and all 3 1448 operand instructions only need to be checked for 1449 register consistency between operands 2 and 3. */ 1450 overlap2 = i.types[2] & t->operand_types[2]; 1451 if (!MATCH (overlap2, i.types[2], t->operand_types[2]) 1452 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], 1453 t->operand_types[1], 1454 overlap2, i.types[2], 1455 t->operand_types[2])) 1456 1457 continue; 1458 } 1459 /* found either forward/reverse 2 or 3 operand match here: 1460 slip through to break */ 1461 } 1462 break; /* we've found a match; break out of loop */ 1463 } /* for (t = ... */ 1464 if (t == current_templates->end) 1465 { /* we found no match */ 1466 as_bad (_("suffix or operands invalid for `%s'"), 1467 current_templates->start->name); 1468 return; 1469 } 1470 1471 if (!intel_syntax 1472 && (i.types[0] & JumpAbsolute) != (t->operand_types[0] & JumpAbsolute)) 1473 { 1474 as_warn (_("indirect %s without `*'"), t->name); 1475 } 1476 1477 if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize)) 1478 { 1479 /* Warn them that a data or address size prefix doesn't affect 1480 assembly of the next line of code. */ 1481 as_warn (_("stand-alone `%s' prefix"), t->name); 1482 } 1483 1484 /* Copy the template we found. */ 1485 i.tm = *t; 1486 if (found_reverse_match) 1487 { 1488 /* If we found a reverse match we must alter the opcode 1489 direction bit. found_reverse_match holds bits to change 1490 (different for int & float insns). */ 1491 1492 i.tm.base_opcode ^= found_reverse_match; 1493 1494 i.tm.operand_types[0] = t->operand_types[1]; 1495 i.tm.operand_types[1] = t->operand_types[0]; 1496 } 1497 1498 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ 1499 if (SYSV386_COMPAT 1500 && intel_syntax 1501 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) 1502 i.tm.base_opcode ^= FloatR; 1503 1504 if (i.tm.opcode_modifier & FWait) 1505 if (! add_prefix (FWAIT_OPCODE)) 1506 return; 1507 1508 /* Check string instruction segment overrides */ 1509 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) 1510 { 1511 int mem_op = (i.types[0] & AnyMem) ? 0 : 1; 1512 if ((i.tm.operand_types[mem_op] & EsSeg) != 0) 1513 { 1514 if (i.seg[0] != NULL && i.seg[0] != &es) 1515 { 1516 as_bad (_("`%s' operand %d must use `%%es' segment"), 1517 i.tm.name, 1518 mem_op + 1); 1519 return; 1520 } 1521 /* There's only ever one segment override allowed per instruction. 1522 This instruction possibly has a legal segment override on the 1523 second operand, so copy the segment to where non-string 1524 instructions store it, allowing common code. */ 1525 i.seg[0] = i.seg[1]; 1526 } 1527 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) 1528 { 1529 if (i.seg[1] != NULL && i.seg[1] != &es) 1530 { 1531 as_bad (_("`%s' operand %d must use `%%es' segment"), 1532 i.tm.name, 1533 mem_op + 2); 1534 return; 1535 } 1536 } 1537 } 1538 1539 /* If matched instruction specifies an explicit instruction mnemonic 1540 suffix, use it. */ 1541 if (i.tm.opcode_modifier & (Size16 | Size32)) 1542 { 1543 if (i.tm.opcode_modifier & Size16) 1544 i.suffix = WORD_MNEM_SUFFIX; 1545 else 1546 i.suffix = LONG_MNEM_SUFFIX; 1547 } 1548 else if (i.reg_operands) 1549 { 1550 /* If there's no instruction mnemonic suffix we try to invent one 1551 based on register operands. */ 1552 if (!i.suffix) 1553 { 1554 /* We take i.suffix from the last register operand specified, 1555 Destination register type is more significant than source 1556 register type. */ 1557 int op; 1558 for (op = i.operands; --op >= 0; ) 1559 if ((i.types[op] & Reg) 1560 && !(i.tm.operand_types[op] & InOutPortReg)) 1561 { 1562 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : 1563 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : 1564 LONG_MNEM_SUFFIX); 1565 break; 1566 } 1567 } 1568 else if (i.suffix == BYTE_MNEM_SUFFIX) 1569 { 1570 int op; 1571 for (op = i.operands; --op >= 0; ) 1572 { 1573 /* If this is an eight bit register, it's OK. If it's 1574 the 16 or 32 bit version of an eight bit register, 1575 we will just use the low portion, and that's OK too. */ 1576 if (i.types[op] & Reg8) 1577 continue; 1578 1579 /* movzx and movsx should not generate this warning. */ 1580 if (intel_syntax 1581 && (i.tm.base_opcode == 0xfb7 1582 || i.tm.base_opcode == 0xfb6 1583 || i.tm.base_opcode == 0xfbe 1584 || i.tm.base_opcode == 0xfbf)) 1585 continue; 1586 1587 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 1588#if 0 1589 /* Check that the template allows eight bit regs 1590 This kills insns such as `orb $1,%edx', which 1591 maybe should be allowed. */ 1592 && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) 1593#endif 1594 ) 1595 { 1596#if REGISTER_WARNINGS 1597 if ((i.tm.operand_types[op] & InOutPortReg) == 0) 1598 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 1599 (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, 1600 i.op[op].regs->reg_name, 1601 i.suffix); 1602#endif 1603 continue; 1604 } 1605 /* Any other register is bad */ 1606 if (i.types[op] & (Reg | RegMMX | RegXMM 1607 | SReg2 | SReg3 1608 | Control | Debug | Test 1609 | FloatReg | FloatAcc)) 1610 { 1611 as_bad (_("`%%%s' not allowed with `%s%c'"), 1612 i.op[op].regs->reg_name, 1613 i.tm.name, 1614 i.suffix); 1615 return; 1616 } 1617 } 1618 } 1619 else if (i.suffix == LONG_MNEM_SUFFIX) 1620 { 1621 int op; 1622 for (op = i.operands; --op >= 0; ) 1623 /* Reject eight bit registers, except where the template 1624 requires them. (eg. movzb) */ 1625 if ((i.types[op] & Reg8) != 0 1626 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) 1627 { 1628 as_bad (_("`%%%s' not allowed with `%s%c'"), 1629 i.op[op].regs->reg_name, 1630 i.tm.name, 1631 i.suffix); 1632 return; 1633 } 1634#if REGISTER_WARNINGS 1635 /* Warn if the e prefix on a general reg is missing. */ 1636 else if ((i.types[op] & Reg16) != 0 1637 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) 1638 { 1639 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 1640 (i.op[op].regs + 8)->reg_name, 1641 i.op[op].regs->reg_name, 1642 i.suffix); 1643 } 1644#endif 1645 } 1646 else if (i.suffix == WORD_MNEM_SUFFIX) 1647 { 1648 int op; 1649 for (op = i.operands; --op >= 0; ) 1650 /* Reject eight bit registers, except where the template 1651 requires them. (eg. movzb) */ 1652 if ((i.types[op] & Reg8) != 0 1653 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) 1654 { 1655 as_bad (_("`%%%s' not allowed with `%s%c'"), 1656 i.op[op].regs->reg_name, 1657 i.tm.name, 1658 i.suffix); 1659 return; 1660 } 1661#if REGISTER_WARNINGS 1662 /* Warn if the e prefix on a general reg is present. */ 1663 else if ((i.types[op] & Reg32) != 0 1664 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) 1665 { 1666 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 1667 (i.op[op].regs - 8)->reg_name, 1668 i.op[op].regs->reg_name, 1669 i.suffix); 1670 } 1671#endif 1672 } 1673 else 1674 abort(); 1675 } 1676 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) 1677 { 1678 i.suffix = stackop_size; 1679 } 1680 1681 /* Make still unresolved immediate matches conform to size of immediate 1682 given in i.suffix. Note: overlap2 cannot be an immediate! */ 1683 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) 1684 && overlap0 != Imm8 && overlap0 != Imm8S 1685 && overlap0 != Imm16 && overlap0 != Imm32) 1686 { 1687 if (i.suffix) 1688 { 1689 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : 1690 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); 1691 } 1692 else if (overlap0 == (Imm16 | Imm32)) 1693 { 1694 overlap0 = 1695 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; 1696 } 1697 else 1698 { 1699 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); 1700 return; 1701 } 1702 } 1703 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) 1704 && overlap1 != Imm8 && overlap1 != Imm8S 1705 && overlap1 != Imm16 && overlap1 != Imm32) 1706 { 1707 if (i.suffix) 1708 { 1709 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : 1710 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); 1711 } 1712 else if (overlap1 == (Imm16 | Imm32)) 1713 { 1714 overlap1 = 1715 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; 1716 } 1717 else 1718 { 1719 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); 1720 return; 1721 } 1722 } 1723 assert ((overlap2 & Imm) == 0); 1724 1725 i.types[0] = overlap0; 1726 if (overlap0 & ImplicitRegister) 1727 i.reg_operands--; 1728 if (overlap0 & Imm1) 1729 i.imm_operands = 0; /* kludge for shift insns */ 1730 1731 i.types[1] = overlap1; 1732 if (overlap1 & ImplicitRegister) 1733 i.reg_operands--; 1734 1735 i.types[2] = overlap2; 1736 if (overlap2 & ImplicitRegister) 1737 i.reg_operands--; 1738 1739 /* Finalize opcode. First, we change the opcode based on the operand 1740 size given by i.suffix: We need not change things for byte insns. */ 1741 1742 if (!i.suffix && (i.tm.opcode_modifier & W)) 1743 { 1744 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); 1745 return; 1746 } 1747 1748 /* For movzx and movsx, need to check the register type */ 1749 if (intel_syntax 1750 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) 1751 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) 1752 { 1753 unsigned int prefix = DATA_PREFIX_OPCODE; 1754 1755 if ((i.op[1].regs->reg_type & Reg16) != 0) 1756 if (!add_prefix (prefix)) 1757 return; 1758 } 1759 1760 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) 1761 { 1762 /* It's not a byte, select word/dword operation. */ 1763 if (i.tm.opcode_modifier & W) 1764 { 1765 if (i.tm.opcode_modifier & ShortForm) 1766 i.tm.base_opcode |= 8; 1767 else 1768 i.tm.base_opcode |= 1; 1769 } 1770 /* Now select between word & dword operations via the operand 1771 size prefix, except for instructions that will ignore this 1772 prefix anyway. */ 1773 if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) 1774 || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code 1775 && !(i.tm.opcode_modifier & IgnoreSize)) 1776 { 1777 unsigned int prefix = DATA_PREFIX_OPCODE; 1778 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ 1779 prefix = ADDR_PREFIX_OPCODE; 1780 1781 if (! add_prefix (prefix)) 1782 return; 1783 } 1784 /* Size floating point instruction. */ 1785 if (i.suffix == LONG_MNEM_SUFFIX 1786 || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) 1787 { 1788 if (i.tm.opcode_modifier & FloatMF) 1789 i.tm.base_opcode ^= 4; 1790 } 1791 } 1792 1793 if (i.tm.opcode_modifier & ImmExt) 1794 { 1795 /* These AMD 3DNow! and Intel Katmai New Instructions have an 1796 opcode suffix which is coded in the same place as an 8-bit 1797 immediate field would be. Here we fake an 8-bit immediate 1798 operand from the opcode suffix stored in tm.extension_opcode. */ 1799 1800 expressionS *exp; 1801 1802 assert(i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); 1803 1804 exp = &im_expressions[i.imm_operands++]; 1805 i.op[i.operands].imms = exp; 1806 i.types[i.operands++] = Imm8; 1807 exp->X_op = O_constant; 1808 exp->X_add_number = i.tm.extension_opcode; 1809 i.tm.extension_opcode = None; 1810 } 1811 1812 /* For insns with operands there are more diddles to do to the opcode. */ 1813 if (i.operands) 1814 { 1815 /* Default segment register this instruction will use 1816 for memory accesses. 0 means unknown. 1817 This is only for optimizing out unnecessary segment overrides. */ 1818 const seg_entry *default_seg = 0; 1819 1820 /* The imul $imm, %reg instruction is converted into 1821 imul $imm, %reg, %reg, and the clr %reg instruction 1822 is converted into xor %reg, %reg. */ 1823 if (i.tm.opcode_modifier & regKludge) 1824 { 1825 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; 1826 /* Pretend we saw the extra register operand. */ 1827 assert (i.op[first_reg_op+1].regs == 0); 1828 i.op[first_reg_op+1].regs = i.op[first_reg_op].regs; 1829 i.types[first_reg_op+1] = i.types[first_reg_op]; 1830 i.reg_operands = 2; 1831 } 1832 1833 if (i.tm.opcode_modifier & ShortForm) 1834 { 1835 /* The register or float register operand is in operand 0 or 1. */ 1836 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; 1837 /* Register goes in low 3 bits of opcode. */ 1838 i.tm.base_opcode |= i.op[op].regs->reg_num; 1839 if ((i.tm.opcode_modifier & Ugh) != 0) 1840 { 1841 /* Warn about some common errors, but press on regardless. 1842 The first case can be generated by gcc (<= 2.8.1). */ 1843 if (i.operands == 2) 1844 { 1845 /* reversed arguments on faddp, fsubp, etc. */ 1846 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, 1847 i.op[1].regs->reg_name, 1848 i.op[0].regs->reg_name); 1849 } 1850 else 1851 { 1852 /* extraneous `l' suffix on fp insn */ 1853 as_warn (_("translating to `%s %%%s'"), i.tm.name, 1854 i.op[0].regs->reg_name); 1855 } 1856 } 1857 } 1858 else if (i.tm.opcode_modifier & Modrm) 1859 { 1860 /* The opcode is completed (modulo i.tm.extension_opcode which 1861 must be put into the modrm byte). 1862 Now, we make the modrm & index base bytes based on all the 1863 info we've collected. */ 1864 1865 /* i.reg_operands MUST be the number of real register operands; 1866 implicit registers do not count. */ 1867 if (i.reg_operands == 2) 1868 { 1869 unsigned int source, dest; 1870 source = ((i.types[0] 1871 & (Reg | RegMMX | RegXMM 1872 | SReg2 | SReg3 1873 | Control | Debug | Test)) 1874 ? 0 : 1); 1875 dest = source + 1; 1876 1877 i.rm.mode = 3; 1878 /* One of the register operands will be encoded in the 1879 i.tm.reg field, the other in the combined i.tm.mode 1880 and i.tm.regmem fields. If no form of this 1881 instruction supports a memory destination operand, 1882 then we assume the source operand may sometimes be 1883 a memory operand and so we need to store the 1884 destination in the i.rm.reg field. */ 1885 if ((i.tm.operand_types[dest] & AnyMem) == 0) 1886 { 1887 i.rm.reg = i.op[dest].regs->reg_num; 1888 i.rm.regmem = i.op[source].regs->reg_num; 1889 } 1890 else 1891 { 1892 i.rm.reg = i.op[source].regs->reg_num; 1893 i.rm.regmem = i.op[dest].regs->reg_num; 1894 } 1895 } 1896 else 1897 { /* if it's not 2 reg operands... */ 1898 if (i.mem_operands) 1899 { 1900 unsigned int fake_zero_displacement = 0; 1901 unsigned int op = ((i.types[0] & AnyMem) 1902 ? 0 1903 : (i.types[1] & AnyMem) ? 1 : 2); 1904 1905 default_seg = &ds; 1906 1907 if (! i.base_reg) 1908 { 1909 i.rm.mode = 0; 1910 if (! i.disp_operands) 1911 fake_zero_displacement = 1; 1912 if (! i.index_reg) 1913 { 1914 /* Operand is just <disp> */ 1915 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) 1916 { 1917 i.rm.regmem = NO_BASE_REGISTER_16; 1918 i.types[op] &= ~Disp; 1919 i.types[op] |= Disp16; 1920 } 1921 else 1922 { 1923 i.rm.regmem = NO_BASE_REGISTER; 1924 i.types[op] &= ~Disp; 1925 i.types[op] |= Disp32; 1926 } 1927 } 1928 else /* ! i.base_reg && i.index_reg */ 1929 { 1930 i.sib.index = i.index_reg->reg_num; 1931 i.sib.base = NO_BASE_REGISTER; 1932 i.sib.scale = i.log2_scale_factor; 1933 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 1934 i.types[op] &= ~Disp; 1935 i.types[op] |= Disp32; /* Must be 32 bit */ 1936 } 1937 } 1938 else if (i.base_reg->reg_type & Reg16) 1939 { 1940 switch (i.base_reg->reg_num) 1941 { 1942 case 3: /* (%bx) */ 1943 if (! i.index_reg) 1944 i.rm.regmem = 7; 1945 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 1946 i.rm.regmem = i.index_reg->reg_num - 6; 1947 break; 1948 case 5: /* (%bp) */ 1949 default_seg = &ss; 1950 if (! i.index_reg) 1951 { 1952 i.rm.regmem = 6; 1953 if ((i.types[op] & Disp) == 0) 1954 { 1955 /* fake (%bp) into 0(%bp) */ 1956 i.types[op] |= Disp8; 1957 fake_zero_displacement = 1; 1958 } 1959 } 1960 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 1961 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 1962 break; 1963 default: /* (%si) -> 4 or (%di) -> 5 */ 1964 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 1965 } 1966 i.rm.mode = mode_from_disp_size (i.types[op]); 1967 } 1968 else /* i.base_reg and 32 bit mode */ 1969 { 1970 i.rm.regmem = i.base_reg->reg_num; 1971 i.sib.base = i.base_reg->reg_num; 1972 if (i.base_reg->reg_num == EBP_REG_NUM) 1973 { 1974 default_seg = &ss; 1975 if (i.disp_operands == 0) 1976 { 1977 fake_zero_displacement = 1; 1978 i.types[op] |= Disp8; 1979 } 1980 } 1981 else if (i.base_reg->reg_num == ESP_REG_NUM) 1982 { 1983 default_seg = &ss; 1984 } 1985 i.sib.scale = i.log2_scale_factor; 1986 if (! i.index_reg) 1987 { 1988 /* <disp>(%esp) becomes two byte modrm 1989 with no index register. We've already 1990 stored the code for esp in i.rm.regmem 1991 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any 1992 base register besides %esp will not use 1993 the extra modrm byte. */ 1994 i.sib.index = NO_INDEX_REGISTER; 1995#if ! SCALE1_WHEN_NO_INDEX 1996 /* Another case where we force the second 1997 modrm byte. */ 1998 if (i.log2_scale_factor) 1999 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 2000#endif 2001 } 2002 else 2003 { 2004 i.sib.index = i.index_reg->reg_num; 2005 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 2006 } 2007 i.rm.mode = mode_from_disp_size (i.types[op]); 2008 } 2009 2010 if (fake_zero_displacement) 2011 { 2012 /* Fakes a zero displacement assuming that i.types[op] 2013 holds the correct displacement size. */ 2014 expressionS *exp; 2015 2016 assert (i.op[op].disps == 0); 2017 exp = &disp_expressions[i.disp_operands++]; 2018 i.op[op].disps = exp; 2019 exp->X_op = O_constant; 2020 exp->X_add_number = 0; 2021 exp->X_add_symbol = (symbolS *) 0; 2022 exp->X_op_symbol = (symbolS *) 0; 2023 } 2024 } 2025 2026 /* Fill in i.rm.reg or i.rm.regmem field with register 2027 operand (if any) based on i.tm.extension_opcode. 2028 Again, we must be careful to make sure that 2029 segment/control/debug/test/MMX registers are coded 2030 into the i.rm.reg field. */ 2031 if (i.reg_operands) 2032 { 2033 unsigned int op = 2034 ((i.types[0] 2035 & (Reg | RegMMX | RegXMM 2036 | SReg2 | SReg3 2037 | Control | Debug | Test)) 2038 ? 0 2039 : ((i.types[1] 2040 & (Reg | RegMMX | RegXMM 2041 | SReg2 | SReg3 2042 | Control | Debug | Test)) 2043 ? 1 2044 : 2)); 2045 /* If there is an extension opcode to put here, the 2046 register number must be put into the regmem field. */ 2047 if (i.tm.extension_opcode != None) 2048 i.rm.regmem = i.op[op].regs->reg_num; 2049 else 2050 i.rm.reg = i.op[op].regs->reg_num; 2051 2052 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 2053 we must set it to 3 to indicate this is a register 2054 operand in the regmem field. */ 2055 if (!i.mem_operands) 2056 i.rm.mode = 3; 2057 } 2058 2059 /* Fill in i.rm.reg field with extension opcode (if any). */ 2060 if (i.tm.extension_opcode != None) 2061 i.rm.reg = i.tm.extension_opcode; 2062 } 2063 } 2064 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) 2065 { 2066 if (i.tm.base_opcode == POP_SEG_SHORT && i.op[0].regs->reg_num == 1) 2067 { 2068 as_bad (_("you can't `pop %%cs'")); 2069 return; 2070 } 2071 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 2072 } 2073 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) 2074 { 2075 default_seg = &ds; 2076 } 2077 else if ((i.tm.opcode_modifier & IsString) != 0) 2078 { 2079 /* For the string instructions that allow a segment override 2080 on one of their operands, the default segment is ds. */ 2081 default_seg = &ds; 2082 } 2083 2084 /* If a segment was explicitly specified, 2085 and the specified segment is not the default, 2086 use an opcode prefix to select it. 2087 If we never figured out what the default segment is, 2088 then default_seg will be zero at this point, 2089 and the specified segment prefix will always be used. */ 2090 if ((i.seg[0]) && (i.seg[0] != default_seg)) 2091 { 2092 if (! add_prefix (i.seg[0]->seg_prefix)) 2093 return; 2094 } 2095 } 2096 else if ((i.tm.opcode_modifier & Ugh) != 0) 2097 { 2098 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 2099 as_warn (_("translating to `%sp'"), i.tm.name); 2100 } 2101 } 2102 2103 /* Handle conversion of 'int $3' --> special int3 insn. */ 2104 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) 2105 { 2106 i.tm.base_opcode = INT3_OPCODE; 2107 i.imm_operands = 0; 2108 } 2109 2110 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) 2111 && i.op[0].disps->X_op == O_constant) 2112 { 2113 /* Convert "jmp constant" (and "call constant") to a jump (call) to 2114 the absolute address given by the constant. Since ix86 jumps and 2115 calls are pc relative, we need to generate a reloc. */ 2116 i.op[0].disps->X_add_symbol = &abs_symbol; 2117 i.op[0].disps->X_op = O_symbol; 2118 } 2119 2120 /* We are ready to output the insn. */ 2121 { 2122 register char *p; 2123 2124 /* Output jumps. */ 2125 if (i.tm.opcode_modifier & Jump) 2126 { 2127 int size; 2128 int code16; 2129 int prefix; 2130 2131 code16 = 0; 2132 if (flag_16bit_code) 2133 code16 = CODE16; 2134 2135 prefix = 0; 2136 if (i.prefix[DATA_PREFIX]) 2137 { 2138 prefix = 1; 2139 i.prefixes -= 1; 2140 code16 ^= CODE16; 2141 } 2142 2143 size = 4; 2144 if (code16) 2145 size = 2; 2146 2147 if (i.prefixes != 0 && !intel_syntax) 2148 as_warn (_("skipping prefixes on this instruction")); 2149 2150 /* It's always a symbol; End frag & setup for relax. 2151 Make sure there is enough room in this frag for the largest 2152 instruction we may generate in md_convert_frag. This is 2 2153 bytes for the opcode and room for the prefix and largest 2154 displacement. */ 2155 frag_grow (prefix + 2 + size); 2156 insn_size += prefix + 1; 2157 /* Prefix and 1 opcode byte go in fr_fix. */ 2158 p = frag_more (prefix + 1); 2159 if (prefix) 2160 *p++ = DATA_PREFIX_OPCODE; 2161 *p = i.tm.base_opcode; 2162 /* 1 possible extra opcode + displacement go in fr_var. */ 2163 frag_var (rs_machine_dependent, 2164 1 + size, 2165 1, 2166 ((unsigned char) *p == JUMP_PC_RELATIVE 2167 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 2168 : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), 2169 i.op[0].disps->X_add_symbol, 2170 i.op[0].disps->X_add_number, 2171 p); 2172 } 2173 else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) 2174 { 2175 int size; 2176 2177 if (i.tm.opcode_modifier & JumpByte) 2178 { 2179 /* This is a loop or jecxz type instruction. */ 2180 size = 1; 2181 if (i.prefix[ADDR_PREFIX]) 2182 { 2183 insn_size += 1; 2184 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 2185 i.prefixes -= 1; 2186 } 2187 } 2188 else 2189 { 2190 int code16; 2191 2192 code16 = 0; 2193 if (flag_16bit_code) 2194 code16 = CODE16; 2195 2196 if (i.prefix[DATA_PREFIX]) 2197 { 2198 insn_size += 1; 2199 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 2200 i.prefixes -= 1; 2201 code16 ^= CODE16; 2202 } 2203 2204 size = 4; 2205 if (code16) 2206 size = 2; 2207 } 2208 2209 if (i.prefixes != 0 && !intel_syntax) 2210 as_warn (_("skipping prefixes on this instruction")); 2211 2212 if (fits_in_unsigned_byte (i.tm.base_opcode)) 2213 { 2214 insn_size += 1 + size; 2215 p = frag_more (1 + size); 2216 } 2217 else 2218 { 2219 /* opcode can be at most two bytes */ 2220 insn_size += 2 + size; 2221 p = frag_more (2 + size); 2222 *p++ = (i.tm.base_opcode >> 8) & 0xff; 2223 } 2224 *p++ = i.tm.base_opcode & 0xff; 2225 2226 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 2227 i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); 2228 } 2229 else if (i.tm.opcode_modifier & JumpInterSegment) 2230 { 2231 int size; 2232 int prefix; 2233 int code16; 2234 2235 code16 = 0; 2236 if (flag_16bit_code) 2237 code16 = CODE16; 2238 2239 prefix = 0; 2240 if (i.prefix[DATA_PREFIX]) 2241 { 2242 prefix = 1; 2243 i.prefixes -= 1; 2244 code16 ^= CODE16; 2245 } 2246 2247 size = 4; 2248 if (code16) 2249 size = 2; 2250 2251 if (i.prefixes != 0 && !intel_syntax) 2252 as_warn (_("skipping prefixes on this instruction")); 2253 2254 insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */ 2255 p = frag_more (prefix + 1 + 2 + size); 2256 if (prefix) 2257 *p++ = DATA_PREFIX_OPCODE; 2258 *p++ = i.tm.base_opcode; 2259 if (i.op[1].imms->X_op == O_constant) 2260 { 2261 long n = (long) i.op[1].imms->X_add_number; 2262 2263 if (size == 2 2264 && !fits_in_unsigned_word (n) 2265 && !fits_in_signed_word (n)) 2266 { 2267 as_bad (_("16-bit jump out of range")); 2268 return; 2269 } 2270 md_number_to_chars (p, (valueT) n, size); 2271 } 2272 else 2273 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 2274 i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); 2275 if (i.op[0].imms->X_op != O_constant) 2276 as_bad (_("can't handle non absolute segment in `%s'"), 2277 i.tm.name); 2278 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 2279 } 2280 else 2281 { 2282 /* Output normal instructions here. */ 2283 unsigned char *q; 2284 2285 /* The prefix bytes. */ 2286 for (q = i.prefix; 2287 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); 2288 q++) 2289 { 2290 if (*q) 2291 { 2292 insn_size += 1; 2293 p = frag_more (1); 2294 md_number_to_chars (p, (valueT) *q, 1); 2295 } 2296 } 2297 2298 /* Now the opcode; be careful about word order here! */ 2299 if (fits_in_unsigned_byte (i.tm.base_opcode)) 2300 { 2301 insn_size += 1; 2302 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 2303 } 2304 else if (fits_in_unsigned_word (i.tm.base_opcode)) 2305 { 2306 insn_size += 2; 2307 p = frag_more (2); 2308 /* put out high byte first: can't use md_number_to_chars! */ 2309 *p++ = (i.tm.base_opcode >> 8) & 0xff; 2310 *p = i.tm.base_opcode & 0xff; 2311 } 2312 else 2313 { /* opcode is either 3 or 4 bytes */ 2314 if (i.tm.base_opcode & 0xff000000) 2315 { 2316 insn_size += 4; 2317 p = frag_more (4); 2318 *p++ = (i.tm.base_opcode >> 24) & 0xff; 2319 } 2320 else 2321 { 2322 insn_size += 3; 2323 p = frag_more (3); 2324 } 2325 *p++ = (i.tm.base_opcode >> 16) & 0xff; 2326 *p++ = (i.tm.base_opcode >> 8) & 0xff; 2327 *p = (i.tm.base_opcode) & 0xff; 2328 } 2329 2330 /* Now the modrm byte and sib byte (if present). */ 2331 if (i.tm.opcode_modifier & Modrm) 2332 { 2333 insn_size += 1; 2334 p = frag_more (1); 2335 md_number_to_chars (p, 2336 (valueT) (i.rm.regmem << 0 2337 | i.rm.reg << 3 2338 | i.rm.mode << 6), 2339 1); 2340 /* If i.rm.regmem == ESP (4) 2341 && i.rm.mode != (Register mode) 2342 && not 16 bit 2343 ==> need second modrm byte. */ 2344 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 2345 && i.rm.mode != 3 2346 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) 2347 { 2348 insn_size += 1; 2349 p = frag_more (1); 2350 md_number_to_chars (p, 2351 (valueT) (i.sib.base << 0 2352 | i.sib.index << 3 2353 | i.sib.scale << 6), 2354 1); 2355 } 2356 } 2357 2358 if (i.disp_operands) 2359 { 2360 register unsigned int n; 2361 2362 for (n = 0; n < i.operands; n++) 2363 { 2364 if (i.types[n] & Disp) 2365 { 2366 if (i.op[n].disps->X_op == O_constant) 2367 { 2368 int size = 4; 2369 long val = (long) i.op[n].disps->X_add_number; 2370 2371 if (i.types[n] & (Disp8 | Disp16)) 2372 { 2373 long mask; 2374 2375 size = 2; 2376 mask = ~ (long) 0xffff; 2377 if (i.types[n] & Disp8) 2378 { 2379 size = 1; 2380 mask = ~ (long) 0xff; 2381 } 2382 2383 if ((val & mask) != 0 && (val & mask) != mask) 2384 as_warn (_("%ld shortened to %ld"), 2385 val, val & ~mask); 2386 } 2387 insn_size += size; 2388 p = frag_more (size); 2389 md_number_to_chars (p, (valueT) val, size); 2390 } 2391 else 2392 { 2393 int size = 4; 2394 2395 if (i.types[n] & Disp16) 2396 size = 2; 2397 2398 insn_size += size; 2399 p = frag_more (size); 2400 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 2401 i.op[n].disps, 0, 2402 reloc (size, 0, i.disp_reloc[n])); 2403 } 2404 } 2405 } 2406 } /* end displacement output */ 2407 2408 /* output immediate */ 2409 if (i.imm_operands) 2410 { 2411 register unsigned int n; 2412 2413 for (n = 0; n < i.operands; n++) 2414 { 2415 if (i.types[n] & Imm) 2416 { 2417 if (i.op[n].imms->X_op == O_constant) 2418 { 2419 int size = 4; 2420 long val = (long) i.op[n].imms->X_add_number; 2421 2422 if (i.types[n] & (Imm8 | Imm8S | Imm16)) 2423 { 2424 long mask; 2425 2426 size = 2; 2427 mask = ~ (long) 0xffff; 2428 if (i.types[n] & (Imm8 | Imm8S)) 2429 { 2430 size = 1; 2431 mask = ~ (long) 0xff; 2432 } 2433 if ((val & mask) != 0 && (val & mask) != mask) 2434 as_warn (_("%ld shortened to %ld"), 2435 val, val & ~mask); 2436 } 2437 insn_size += size; 2438 p = frag_more (size); 2439 md_number_to_chars (p, (valueT) val, size); 2440 } 2441 else 2442 { /* not absolute_section */ 2443 /* Need a 32-bit fixup (don't support 8bit 2444 non-absolute imms). Try to support other 2445 sizes ... */ 2446#ifdef BFD_ASSEMBLER 2447 enum bfd_reloc_code_real reloc_type; 2448#else 2449 int reloc_type; 2450#endif 2451 int size = 4; 2452 2453 if (i.types[n] & Imm16) 2454 size = 2; 2455 else if (i.types[n] & (Imm8 | Imm8S)) 2456 size = 1; 2457 2458 insn_size += size; 2459 p = frag_more (size); 2460 reloc_type = reloc (size, 0, i.disp_reloc[0]); 2461#ifdef BFD_ASSEMBLER 2462 if (reloc_type == BFD_RELOC_32 2463 && GOT_symbol 2464 && GOT_symbol == i.op[n].imms->X_add_symbol 2465 && (i.op[n].imms->X_op == O_symbol 2466 || (i.op[n].imms->X_op == O_add 2467 && ((symbol_get_value_expression 2468 (i.op[n].imms->X_op_symbol)->X_op) 2469 == O_subtract)))) 2470 { 2471 reloc_type = BFD_RELOC_386_GOTPC; 2472 i.op[n].imms->X_add_number += 3; 2473 } 2474#endif 2475 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 2476 i.op[n].imms, 0, reloc_type); 2477 } 2478 } 2479 } 2480 } /* end immediate output */ 2481 } 2482 2483#ifdef DEBUG386 2484 if (flag_debug) 2485 { 2486 pi (line, &i); 2487 } 2488#endif /* DEBUG386 */ 2489 } 2490} 2491 2492static int i386_immediate PARAMS ((char *)); 2493 2494static int 2495i386_immediate (imm_start) 2496 char *imm_start; 2497{ 2498 char *save_input_line_pointer; 2499 segT exp_seg = 0; 2500 expressionS * exp; 2501 2502 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 2503 { 2504 as_bad (_("only 1 or 2 immediate operands are allowed")); 2505 return 0; 2506 } 2507 2508 exp = &im_expressions[i.imm_operands++]; 2509 i.op[this_operand].imms = exp; 2510 2511 if (is_space_char (*imm_start)) 2512 ++imm_start; 2513 2514 save_input_line_pointer = input_line_pointer; 2515 input_line_pointer = imm_start; 2516 2517#ifndef LEX_AT 2518 { 2519 /* 2520 * We can have operands of the form 2521 * <symbol>@GOTOFF+<nnn> 2522 * Take the easy way out here and copy everything 2523 * into a temporary buffer... 2524 */ 2525 register char *cp; 2526 2527 cp = strchr (input_line_pointer, '@'); 2528 if (cp != NULL) 2529 { 2530 char *tmpbuf; 2531 int len = 0; 2532 int first; 2533 2534 /* GOT relocations are not supported in 16 bit mode */ 2535 if (flag_16bit_code) 2536 as_bad (_("GOT relocations not supported in 16 bit mode")); 2537 2538 if (GOT_symbol == NULL) 2539 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 2540 2541 if (strncmp (cp + 1, "PLT", 3) == 0) 2542 { 2543 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; 2544 len = 3; 2545 } 2546 else if (strncmp (cp + 1, "GOTOFF", 6) == 0) 2547 { 2548 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; 2549 len = 6; 2550 } 2551 else if (strncmp (cp + 1, "GOT", 3) == 0) 2552 { 2553 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; 2554 len = 3; 2555 } 2556 else 2557 as_bad (_("bad reloc specifier in expression")); 2558 2559 /* Replace the relocation token with ' ', so that errors like 2560 foo@GOTOFF1 will be detected. */ 2561 first = cp - input_line_pointer; 2562 tmpbuf = (char *) alloca (strlen(input_line_pointer)); 2563 memcpy (tmpbuf, input_line_pointer, first); 2564 tmpbuf[first] = ' '; 2565 strcpy (tmpbuf + first + 1, cp + 1 + len); 2566 input_line_pointer = tmpbuf; 2567 } 2568 } 2569#endif 2570 2571 exp_seg = expression (exp); 2572 2573 SKIP_WHITESPACE (); 2574 if (*input_line_pointer) 2575 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); 2576 2577 input_line_pointer = save_input_line_pointer; 2578 2579 if (exp->X_op == O_absent || exp->X_op == O_big) 2580 { 2581 /* missing or bad expr becomes absolute 0 */ 2582 as_bad (_("missing or invalid immediate expression `%s' taken as 0"), 2583 imm_start); 2584 exp->X_op = O_constant; 2585 exp->X_add_number = 0; 2586 exp->X_add_symbol = (symbolS *) 0; 2587 exp->X_op_symbol = (symbolS *) 0; 2588 } 2589 2590 if (exp->X_op == O_constant) 2591 { 2592 i.types[this_operand] |= Imm32; /* Size it properly later. */ 2593 } 2594#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 2595 else if ( 2596#ifdef BFD_ASSEMBLER 2597 OUTPUT_FLAVOR == bfd_target_aout_flavour && 2598#endif 2599 exp_seg != text_section 2600 && exp_seg != data_section 2601 && exp_seg != bss_section 2602 && exp_seg != undefined_section 2603#ifdef BFD_ASSEMBLER 2604 && !bfd_is_com_section (exp_seg) 2605#endif 2606 ) 2607 { 2608#ifdef BFD_ASSEMBLER 2609 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 2610#else 2611 as_bad (_("unimplemented segment type %d in operand"), exp_seg); 2612#endif 2613 return 0; 2614 } 2615#endif 2616 else 2617 { 2618 /* This is an address. The size of the address will be 2619 determined later, depending on destination register, 2620 suffix, or the default for the section. We exclude 2621 Imm8S here so that `push $foo' and other instructions 2622 with an Imm8S form will use Imm16 or Imm32. */ 2623 i.types[this_operand] |= (Imm8 | Imm16 | Imm32); 2624 } 2625 2626 return 1; 2627} 2628 2629static int i386_scale PARAMS ((char *)); 2630 2631static int 2632i386_scale (scale) 2633 char *scale; 2634{ 2635 if (!isdigit (*scale)) 2636 goto bad_scale; 2637 2638 switch (*scale) 2639 { 2640 case '0': 2641 case '1': 2642 i.log2_scale_factor = 0; 2643 break; 2644 case '2': 2645 i.log2_scale_factor = 1; 2646 break; 2647 case '4': 2648 i.log2_scale_factor = 2; 2649 break; 2650 case '8': 2651 i.log2_scale_factor = 3; 2652 break; 2653 default: 2654 bad_scale: 2655 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 2656 scale); 2657 return 0; 2658 } 2659 if (i.log2_scale_factor != 0 && ! i.index_reg) 2660 { 2661 as_warn (_("scale factor of %d without an index register"), 2662 1 << i.log2_scale_factor); 2663#if SCALE1_WHEN_NO_INDEX 2664 i.log2_scale_factor = 0; 2665#endif 2666 } 2667 return 1; 2668} 2669 2670static int i386_displacement PARAMS ((char *, char *)); 2671 2672static int 2673i386_displacement (disp_start, disp_end) 2674 char *disp_start; 2675 char *disp_end; 2676{ 2677 register expressionS *exp; 2678 segT exp_seg = 0; 2679 char *save_input_line_pointer; 2680 int bigdisp = Disp32; 2681 2682 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) 2683 bigdisp = Disp16; 2684 i.types[this_operand] |= bigdisp; 2685 2686 exp = &disp_expressions[i.disp_operands]; 2687 i.op[this_operand].disps = exp; 2688 i.disp_operands++; 2689 save_input_line_pointer = input_line_pointer; 2690 input_line_pointer = disp_start; 2691 END_STRING_AND_SAVE (disp_end); 2692 2693#ifndef GCC_ASM_O_HACK 2694#define GCC_ASM_O_HACK 0 2695#endif 2696#if GCC_ASM_O_HACK 2697 END_STRING_AND_SAVE (disp_end + 1); 2698 if ((i.types[this_operand] & BaseIndex) != 0 2699 && displacement_string_end[-1] == '+') 2700 { 2701 /* This hack is to avoid a warning when using the "o" 2702 constraint within gcc asm statements. 2703 For instance: 2704 2705 #define _set_tssldt_desc(n,addr,limit,type) \ 2706 __asm__ __volatile__ ( \ 2707 "movw %w2,%0\n\t" \ 2708 "movw %w1,2+%0\n\t" \ 2709 "rorl $16,%1\n\t" \ 2710 "movb %b1,4+%0\n\t" \ 2711 "movb %4,5+%0\n\t" \ 2712 "movb $0,6+%0\n\t" \ 2713 "movb %h1,7+%0\n\t" \ 2714 "rorl $16,%1" \ 2715 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 2716 2717 This works great except that the output assembler ends 2718 up looking a bit weird if it turns out that there is 2719 no offset. You end up producing code that looks like: 2720 2721 #APP 2722 movw $235,(%eax) 2723 movw %dx,2+(%eax) 2724 rorl $16,%edx 2725 movb %dl,4+(%eax) 2726 movb $137,5+(%eax) 2727 movb $0,6+(%eax) 2728 movb %dh,7+(%eax) 2729 rorl $16,%edx 2730 #NO_APP 2731 2732 So here we provide the missing zero. 2733 */ 2734 2735 *displacement_string_end = '0'; 2736 } 2737#endif 2738#ifndef LEX_AT 2739 { 2740 /* 2741 * We can have operands of the form 2742 * <symbol>@GOTOFF+<nnn> 2743 * Take the easy way out here and copy everything 2744 * into a temporary buffer... 2745 */ 2746 register char *cp; 2747 2748 cp = strchr (input_line_pointer, '@'); 2749 if (cp != NULL) 2750 { 2751 char *tmpbuf; 2752 int len = 0; 2753 int first; 2754 2755 /* GOT relocations are not supported in 16 bit mode */ 2756 if (flag_16bit_code) 2757 as_bad (_("GOT relocations not supported in 16 bit mode")); 2758 2759 if (GOT_symbol == NULL) 2760 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 2761 2762 if (strncmp (cp + 1, "PLT", 3) == 0) 2763 { 2764 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; 2765 len = 3; 2766 } 2767 else if (strncmp (cp + 1, "GOTOFF", 6) == 0) 2768 { 2769 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; 2770 len = 6; 2771 } 2772 else if (strncmp (cp + 1, "GOT", 3) == 0) 2773 { 2774 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; 2775 len = 3; 2776 } 2777 else 2778 as_bad (_("bad reloc specifier in expression")); 2779 2780 /* Replace the relocation token with ' ', so that errors like 2781 foo@GOTOFF1 will be detected. */ 2782 first = cp - input_line_pointer; 2783 tmpbuf = (char *) alloca (strlen(input_line_pointer)); 2784 memcpy (tmpbuf, input_line_pointer, first); 2785 tmpbuf[first] = ' '; 2786 strcpy (tmpbuf + first + 1, cp + 1 + len); 2787 input_line_pointer = tmpbuf; 2788 } 2789 } 2790#endif 2791 2792 exp_seg = expression (exp); 2793 2794#ifdef BFD_ASSEMBLER 2795 /* We do this to make sure that the section symbol is in 2796 the symbol table. We will ultimately change the relocation 2797 to be relative to the beginning of the section */ 2798 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) 2799 { 2800 if (S_IS_LOCAL(exp->X_add_symbol) 2801 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) 2802 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 2803 assert (exp->X_op == O_symbol); 2804 exp->X_op = O_subtract; 2805 exp->X_op_symbol = GOT_symbol; 2806 i.disp_reloc[this_operand] = BFD_RELOC_32; 2807 } 2808#endif 2809 2810 SKIP_WHITESPACE (); 2811 if (*input_line_pointer) 2812 as_bad (_("ignoring junk `%s' after expression"), 2813 input_line_pointer); 2814#if GCC_ASM_O_HACK 2815 RESTORE_END_STRING (disp_end + 1); 2816#endif 2817 RESTORE_END_STRING (disp_end); 2818 input_line_pointer = save_input_line_pointer; 2819 2820 if (exp->X_op == O_absent || exp->X_op == O_big) 2821 { 2822 /* missing or bad expr becomes absolute 0 */ 2823 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 2824 disp_start); 2825 exp->X_op = O_constant; 2826 exp->X_add_number = 0; 2827 exp->X_add_symbol = (symbolS *) 0; 2828 exp->X_op_symbol = (symbolS *) 0; 2829 } 2830 2831 if (exp->X_op == O_constant) 2832 { 2833 if (i.types[this_operand] & Disp16) 2834 { 2835 /* We know this operand is at most 16 bits, so convert to a 2836 signed 16 bit number before trying to see whether it will 2837 fit in an even smaller size. */ 2838 exp->X_add_number = 2839 (((exp->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 2840 } 2841 if (fits_in_signed_byte (exp->X_add_number)) 2842 i.types[this_operand] |= Disp8; 2843 } 2844#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 2845 else if ( 2846#ifdef BFD_ASSEMBLER 2847 OUTPUT_FLAVOR == bfd_target_aout_flavour && 2848#endif 2849 exp_seg != text_section 2850 && exp_seg != data_section 2851 && exp_seg != bss_section 2852 && exp_seg != undefined_section) 2853 { 2854#ifdef BFD_ASSEMBLER 2855 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 2856#else 2857 as_bad (_("unimplemented segment type %d in operand"), exp_seg); 2858#endif 2859 return 0; 2860 } 2861#endif 2862 return 1; 2863} 2864 2865static int i386_operand_modifier PARAMS ((char **, int)); 2866 2867static int 2868i386_operand_modifier (op_string, got_a_float) 2869 char **op_string; 2870 int got_a_float; 2871{ 2872 if (!strncasecmp (*op_string, "BYTE PTR", 8)) 2873 { 2874 i.suffix = BYTE_MNEM_SUFFIX; 2875 *op_string += 8; 2876 return BYTE_PTR; 2877 2878 } 2879 else if (!strncasecmp (*op_string, "WORD PTR", 8)) 2880 { 2881 if (got_a_float == 2) /* "fi..." */ 2882 i.suffix = SHORT_MNEM_SUFFIX; 2883 else 2884 i.suffix = WORD_MNEM_SUFFIX; 2885 *op_string += 8; 2886 return WORD_PTR; 2887 } 2888 2889 else if (!strncasecmp (*op_string, "DWORD PTR", 9)) 2890 { 2891 if (got_a_float == 1) /* "f..." */ 2892 i.suffix = SHORT_MNEM_SUFFIX; 2893 else 2894 i.suffix = LONG_MNEM_SUFFIX; 2895 *op_string += 9; 2896 return DWORD_PTR; 2897 } 2898 2899 else if (!strncasecmp (*op_string, "QWORD PTR", 9)) 2900 { 2901 i.suffix = DWORD_MNEM_SUFFIX; 2902 *op_string += 9; 2903 return QWORD_PTR; 2904 } 2905 2906 else if (!strncasecmp (*op_string, "XWORD PTR", 9)) 2907 { 2908 i.suffix = LONG_DOUBLE_MNEM_SUFFIX; 2909 *op_string += 9; 2910 return XWORD_PTR; 2911 } 2912 2913 else if (!strncasecmp (*op_string, "SHORT", 5)) 2914 { 2915 *op_string += 5; 2916 return SHORT; 2917 } 2918 2919 else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12)) 2920 { 2921 *op_string += 12; 2922 return OFFSET_FLAT; 2923 } 2924 2925 else if (!strncasecmp (*op_string, "FLAT", 4)) 2926 { 2927 *op_string += 4; 2928 return FLAT; 2929 } 2930 2931 else return NONE_FOUND; 2932} 2933 2934static char * build_displacement_string PARAMS ((int, char *)); 2935 2936static char * 2937build_displacement_string (initial_disp, op_string) 2938 int initial_disp; 2939 char *op_string; 2940{ 2941 char *temp_string = (char *) malloc (strlen (op_string) + 1); 2942 char *end_of_operand_string; 2943 char *tc; 2944 char *temp_disp; 2945 2946 temp_string[0] = '\0'; 2947 tc = end_of_operand_string = strchr (op_string, '['); 2948 if (initial_disp && !end_of_operand_string) 2949 { 2950 strcpy (temp_string, op_string); 2951 return temp_string; 2952 } 2953 2954 /* Build the whole displacement string */ 2955 if (initial_disp) 2956 { 2957 strncpy (temp_string, op_string, end_of_operand_string - op_string); 2958 temp_string[end_of_operand_string - op_string] = '\0'; 2959 temp_disp = tc; 2960 } 2961 else 2962 temp_disp = op_string; 2963 2964 while (*temp_disp != '\0') 2965 { 2966 char *end_op; 2967 int add_minus = (*temp_disp == '-'); 2968 2969 if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[') 2970 temp_disp++; 2971 2972 if (is_space_char (*temp_disp)) 2973 temp_disp++; 2974 2975 /* Don't consider registers */ 2976 if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg) 2977 && parse_register (temp_disp, &end_op)) ) 2978 { 2979 char *string_start = temp_disp; 2980 2981 while (*temp_disp != ']' 2982 && *temp_disp != '+' 2983 && *temp_disp != '-' 2984 && *temp_disp != '*') 2985 ++temp_disp; 2986 2987 if (add_minus) 2988 strcat (temp_string, "-"); 2989 else 2990 strcat (temp_string, "+"); 2991 2992 strncat (temp_string, string_start, temp_disp - string_start); 2993 if (*temp_disp == '+' || *temp_disp == '-') 2994 --temp_disp; 2995 } 2996 2997 while (*temp_disp != '\0' 2998 && *temp_disp != '+' 2999 && *temp_disp != '-') 3000 ++temp_disp; 3001 } 3002 3003 return temp_string; 3004} 3005 3006static int i386_parse_seg PARAMS ((char *)); 3007 3008static int 3009i386_parse_seg (op_string) 3010 char *op_string; 3011{ 3012 if (is_space_char (*op_string)) 3013 ++op_string; 3014 3015 /* Should be one of es, cs, ss, ds fs or gs */ 3016 switch (*op_string++) 3017 { 3018 case 'e': 3019 i.seg[i.mem_operands] = &es; 3020 break; 3021 case 'c': 3022 i.seg[i.mem_operands] = &cs; 3023 break; 3024 case 's': 3025 i.seg[i.mem_operands] = &ss; 3026 break; 3027 case 'd': 3028 i.seg[i.mem_operands] = &ds; 3029 break; 3030 case 'f': 3031 i.seg[i.mem_operands] = &fs; 3032 break; 3033 case 'g': 3034 i.seg[i.mem_operands] = &gs; 3035 break; 3036 default: 3037 as_bad (_("bad segment name `%s'"), op_string); 3038 return 0; 3039 } 3040 3041 if (*op_string++ != 's') 3042 { 3043 as_bad (_("bad segment name `%s'"), op_string); 3044 return 0; 3045 } 3046 3047 if (is_space_char (*op_string)) 3048 ++op_string; 3049 3050 if (*op_string != ':') 3051 { 3052 as_bad (_("bad segment name `%s'"), op_string); 3053 return 0; 3054 } 3055 3056 return 1; 3057 3058} 3059 3060static int i386_index_check PARAMS((const char *)); 3061 3062/* Make sure the memory operand we've been dealt is valid. 3063 Returns 1 on success, 0 on a failure. 3064*/ 3065static int 3066i386_index_check (operand_string) 3067 const char *operand_string; 3068{ 3069#if INFER_ADDR_PREFIX 3070 int fudged = 0; 3071 3072 tryprefix: 3073#endif 3074 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) 3075 /* 16 bit mode checks */ 3076 ? ((i.base_reg 3077 && ((i.base_reg->reg_type & (Reg16|BaseIndex)) 3078 != (Reg16|BaseIndex))) 3079 || (i.index_reg 3080 && (((i.index_reg->reg_type & (Reg16|BaseIndex)) 3081 != (Reg16|BaseIndex)) 3082 || ! (i.base_reg 3083 && i.base_reg->reg_num < 6 3084 && i.index_reg->reg_num >= 6 3085 && i.log2_scale_factor == 0)))) 3086 /* 32 bit mode checks */ 3087 : ((i.base_reg 3088 && (i.base_reg->reg_type & Reg32) == 0) 3089 || (i.index_reg 3090 && ((i.index_reg->reg_type & (Reg32|BaseIndex)) 3091 != (Reg32|BaseIndex))))) 3092 { 3093#if INFER_ADDR_PREFIX 3094 if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') 3095 { 3096 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 3097 i.prefixes += 1; 3098 /* Change the size of any displacement too. At most one of 3099 Disp16 or Disp32 is set. 3100 FIXME. There doesn't seem to be any real need for separate 3101 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. 3102 Removing them would probably clean up the code quite a lot. 3103 */ 3104 if (i.types[this_operand] & (Disp16|Disp32)) 3105 i.types[this_operand] ^= (Disp16|Disp32); 3106 fudged = 1; 3107 goto tryprefix; 3108 } 3109 if (fudged) 3110 as_bad (_("`%s' is not a valid base/index expression"), 3111 operand_string); 3112 else 3113#endif 3114 as_bad (_("`%s' is not a valid %s bit base/index expression"), 3115 operand_string, 3116 flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); 3117 return 0; 3118 } 3119 return 1; 3120} 3121 3122static int i386_intel_memory_operand PARAMS ((char *)); 3123 3124static int 3125i386_intel_memory_operand (operand_string) 3126 char *operand_string; 3127{ 3128 char *op_string = operand_string; 3129 char *end_of_operand_string; 3130 3131 if ((i.mem_operands == 1 3132 && (current_templates->start->opcode_modifier & IsString) == 0) 3133 || i.mem_operands == 2) 3134 { 3135 as_bad (_("too many memory references for `%s'"), 3136 current_templates->start->name); 3137 return 0; 3138 } 3139 3140 /* First check for a segment override. */ 3141 if (*op_string != '[') 3142 { 3143 char *end_seg; 3144 3145 end_seg = strchr (op_string, ':'); 3146 if (end_seg) 3147 { 3148 if (!i386_parse_seg (op_string)) 3149 return 0; 3150 op_string = end_seg + 1; 3151 } 3152 } 3153 3154 /* Look for displacement preceding open bracket */ 3155 if (*op_string != '[') 3156 { 3157 char *temp_string; 3158 3159 if (i.disp_operands) 3160 return 0; 3161 3162 temp_string = build_displacement_string (true, op_string); 3163 3164 if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) 3165 { 3166 free (temp_string); 3167 return 0; 3168 } 3169 free (temp_string); 3170 3171 end_of_operand_string = strchr (op_string, '['); 3172 if (!end_of_operand_string) 3173 end_of_operand_string = op_string + strlen (op_string); 3174 3175 if (is_space_char (*end_of_operand_string)) 3176 --end_of_operand_string; 3177 3178 op_string = end_of_operand_string; 3179 } 3180 3181 if (*op_string == '[') 3182 { 3183 ++op_string; 3184 3185 /* Pick off each component and figure out where it belongs */ 3186 3187 end_of_operand_string = op_string; 3188 3189 while (*op_string != ']') 3190 { 3191 const reg_entry *temp_reg; 3192 char *end_op; 3193 char *temp_string; 3194 3195 while (*end_of_operand_string != '+' 3196 && *end_of_operand_string != '-' 3197 && *end_of_operand_string != '*' 3198 && *end_of_operand_string != ']') 3199 end_of_operand_string++; 3200 3201 temp_string = op_string; 3202 if (*temp_string == '+') 3203 { 3204 ++temp_string; 3205 if (is_space_char (*temp_string)) 3206 ++temp_string; 3207 } 3208 3209 if ((*temp_string == REGISTER_PREFIX || allow_naked_reg) 3210 && (temp_reg = parse_register (temp_string, &end_op)) != NULL) 3211 { 3212 if (i.base_reg == NULL) 3213 i.base_reg = temp_reg; 3214 else 3215 i.index_reg = temp_reg; 3216 3217 i.types[this_operand] |= BaseIndex; 3218 } 3219 else if (*temp_string == REGISTER_PREFIX) 3220 { 3221 as_bad (_("bad register name `%s'"), temp_string); 3222 return 0; 3223 } 3224 else if (is_digit_char (*op_string) 3225 || *op_string == '+' || *op_string == '-') 3226 { 3227 char *temp_str; 3228 3229 if (i.disp_operands != 0) 3230 return 0; 3231 3232 temp_string = build_displacement_string (false, op_string); 3233 3234 temp_str = temp_string; 3235 if (*temp_str == '+') 3236 ++temp_str; 3237 3238 if (!i386_displacement (temp_str, temp_str + strlen (temp_str))) 3239 { 3240 free (temp_string); 3241 return 0; 3242 } 3243 free (temp_string); 3244 3245 ++op_string; 3246 end_of_operand_string = op_string; 3247 while (*end_of_operand_string != ']' 3248 && *end_of_operand_string != '+' 3249 && *end_of_operand_string != '-' 3250 && *end_of_operand_string != '*') 3251 ++end_of_operand_string; 3252 } 3253 else if (*op_string == '*') 3254 { 3255 ++op_string; 3256 3257 if (i.base_reg && !i.index_reg) 3258 { 3259 i.index_reg = i.base_reg; 3260 i.base_reg = 0; 3261 } 3262 3263 if (!i386_scale (op_string)) 3264 return 0; 3265 } 3266 op_string = end_of_operand_string; 3267 ++end_of_operand_string; 3268 } 3269 } 3270 3271 if (i386_index_check (operand_string) == 0) 3272 return 0; 3273 3274 i.mem_operands++; 3275 return 1; 3276} 3277 3278static int 3279i386_intel_operand (operand_string, got_a_float) 3280 char *operand_string; 3281 int got_a_float; 3282{ 3283 const reg_entry * r; 3284 char *end_op; 3285 char *op_string = operand_string; 3286 3287 int operand_modifier = i386_operand_modifier (&op_string, got_a_float); 3288 if (is_space_char (*op_string)) 3289 ++op_string; 3290 3291 switch (operand_modifier) 3292 { 3293 case BYTE_PTR: 3294 case WORD_PTR: 3295 case DWORD_PTR: 3296 case QWORD_PTR: 3297 case XWORD_PTR: 3298 if (!i386_intel_memory_operand (op_string)) 3299 return 0; 3300 break; 3301 3302 case FLAT: 3303 case OFFSET_FLAT: 3304 if (!i386_immediate (op_string)) 3305 return 0; 3306 break; 3307 3308 case SHORT: 3309 case NONE_FOUND: 3310 /* Should be register or immediate */ 3311 if (is_digit_char (*op_string) 3312 && strchr (op_string, '[') == 0) 3313 { 3314 if (!i386_immediate (op_string)) 3315 return 0; 3316 } 3317 else if ((*op_string == REGISTER_PREFIX || allow_naked_reg) 3318 && (r = parse_register (op_string, &end_op)) != NULL) 3319 { 3320 /* Check for a segment override by searching for ':' after a 3321 segment register. */ 3322 op_string = end_op; 3323 if (is_space_char (*op_string)) 3324 ++op_string; 3325 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) 3326 { 3327 switch (r->reg_num) 3328 { 3329 case 0: 3330 i.seg[i.mem_operands] = &es; 3331 break; 3332 case 1: 3333 i.seg[i.mem_operands] = &cs; 3334 break; 3335 case 2: 3336 i.seg[i.mem_operands] = &ss; 3337 break; 3338 case 3: 3339 i.seg[i.mem_operands] = &ds; 3340 break; 3341 case 4: 3342 i.seg[i.mem_operands] = &fs; 3343 break; 3344 case 5: 3345 i.seg[i.mem_operands] = &gs; 3346 break; 3347 } 3348 3349 } 3350 i.types[this_operand] |= r->reg_type & ~BaseIndex; 3351 i.op[this_operand].regs = r; 3352 i.reg_operands++; 3353 } 3354 else if (*op_string == REGISTER_PREFIX) 3355 { 3356 as_bad (_("bad register name `%s'"), op_string); 3357 return 0; 3358 } 3359 else if (!i386_intel_memory_operand (op_string)) 3360 return 0; 3361 3362 break; 3363 } /* end switch */ 3364 3365 return 1; 3366} 3367 3368/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero 3369 on error. */ 3370 3371static int 3372i386_operand (operand_string) 3373 char *operand_string; 3374{ 3375 const reg_entry *r; 3376 char *end_op; 3377 char *op_string = operand_string; 3378 3379 if (is_space_char (*op_string)) 3380 ++op_string; 3381 3382 /* We check for an absolute prefix (differentiating, 3383 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 3384 if (*op_string == ABSOLUTE_PREFIX) 3385 { 3386 ++op_string; 3387 if (is_space_char (*op_string)) 3388 ++op_string; 3389 i.types[this_operand] |= JumpAbsolute; 3390 } 3391 3392 /* Check if operand is a register. */ 3393 if ((*op_string == REGISTER_PREFIX || allow_naked_reg) 3394 && (r = parse_register (op_string, &end_op)) != NULL) 3395 { 3396 /* Check for a segment override by searching for ':' after a 3397 segment register. */ 3398 op_string = end_op; 3399 if (is_space_char (*op_string)) 3400 ++op_string; 3401 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) 3402 { 3403 switch (r->reg_num) 3404 { 3405 case 0: 3406 i.seg[i.mem_operands] = &es; 3407 break; 3408 case 1: 3409 i.seg[i.mem_operands] = &cs; 3410 break; 3411 case 2: 3412 i.seg[i.mem_operands] = &ss; 3413 break; 3414 case 3: 3415 i.seg[i.mem_operands] = &ds; 3416 break; 3417 case 4: 3418 i.seg[i.mem_operands] = &fs; 3419 break; 3420 case 5: 3421 i.seg[i.mem_operands] = &gs; 3422 break; 3423 } 3424 3425 /* Skip the ':' and whitespace. */ 3426 ++op_string; 3427 if (is_space_char (*op_string)) 3428 ++op_string; 3429 3430 if (!is_digit_char (*op_string) 3431 && !is_identifier_char (*op_string) 3432 && *op_string != '(' 3433 && *op_string != ABSOLUTE_PREFIX) 3434 { 3435 as_bad (_("bad memory operand `%s'"), op_string); 3436 return 0; 3437 } 3438 /* Handle case of %es:*foo. */ 3439 if (*op_string == ABSOLUTE_PREFIX) 3440 { 3441 ++op_string; 3442 if (is_space_char (*op_string)) 3443 ++op_string; 3444 i.types[this_operand] |= JumpAbsolute; 3445 } 3446 goto do_memory_reference; 3447 } 3448 if (*op_string) 3449 { 3450 as_bad (_("junk `%s' after register"), op_string); 3451 return 0; 3452 } 3453 i.types[this_operand] |= r->reg_type & ~BaseIndex; 3454 i.op[this_operand].regs = r; 3455 i.reg_operands++; 3456 } 3457 else if (*op_string == REGISTER_PREFIX) 3458 { 3459 as_bad (_("bad register name `%s'"), op_string); 3460 return 0; 3461 } 3462 else if (*op_string == IMMEDIATE_PREFIX) 3463 { /* ... or an immediate */ 3464 ++op_string; 3465 if (i.types[this_operand] & JumpAbsolute) 3466 { 3467 as_bad (_("immediate operand illegal with absolute jump")); 3468 return 0; 3469 } 3470 if (!i386_immediate (op_string)) 3471 return 0; 3472 } 3473 else if (is_digit_char (*op_string) 3474 || is_identifier_char (*op_string) 3475 || *op_string == '(' ) 3476 { 3477 /* This is a memory reference of some sort. */ 3478 char *base_string; 3479 3480 /* Start and end of displacement string expression (if found). */ 3481 char *displacement_string_start; 3482 char *displacement_string_end; 3483 3484 do_memory_reference: 3485 if ((i.mem_operands == 1 3486 && (current_templates->start->opcode_modifier & IsString) == 0) 3487 || i.mem_operands == 2) 3488 { 3489 as_bad (_("too many memory references for `%s'"), 3490 current_templates->start->name); 3491 return 0; 3492 } 3493 3494 /* Check for base index form. We detect the base index form by 3495 looking for an ')' at the end of the operand, searching 3496 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 3497 after the '('. */ 3498 base_string = op_string + strlen (op_string); 3499 3500 --base_string; 3501 if (is_space_char (*base_string)) 3502 --base_string; 3503 3504 /* If we only have a displacement, set-up for it to be parsed later. */ 3505 displacement_string_start = op_string; 3506 displacement_string_end = base_string + 1; 3507 3508 if (*base_string == ')') 3509 { 3510 char *temp_string; 3511 unsigned int parens_balanced = 1; 3512 /* We've already checked that the number of left & right ()'s are 3513 equal, so this loop will not be infinite. */ 3514 do 3515 { 3516 base_string--; 3517 if (*base_string == ')') 3518 parens_balanced++; 3519 if (*base_string == '(') 3520 parens_balanced--; 3521 } 3522 while (parens_balanced); 3523 3524 temp_string = base_string; 3525 3526 /* Skip past '(' and whitespace. */ 3527 ++base_string; 3528 if (is_space_char (*base_string)) 3529 ++base_string; 3530 3531 if (*base_string == ',' 3532 || ((*base_string == REGISTER_PREFIX || allow_naked_reg) 3533 && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) 3534 { 3535 displacement_string_end = temp_string; 3536 3537 i.types[this_operand] |= BaseIndex; 3538 3539 if (i.base_reg) 3540 { 3541 base_string = end_op; 3542 if (is_space_char (*base_string)) 3543 ++base_string; 3544 } 3545 3546 /* There may be an index reg or scale factor here. */ 3547 if (*base_string == ',') 3548 { 3549 ++base_string; 3550 if (is_space_char (*base_string)) 3551 ++base_string; 3552 3553 if ((*base_string == REGISTER_PREFIX || allow_naked_reg) 3554 && (i.index_reg = parse_register (base_string, &end_op)) != NULL) 3555 { 3556 base_string = end_op; 3557 if (is_space_char (*base_string)) 3558 ++base_string; 3559 if (*base_string == ',') 3560 { 3561 ++base_string; 3562 if (is_space_char (*base_string)) 3563 ++base_string; 3564 } 3565 else if (*base_string != ')' ) 3566 { 3567 as_bad (_("expecting `,' or `)' after index register in `%s'"), 3568 operand_string); 3569 return 0; 3570 } 3571 } 3572 else if (*base_string == REGISTER_PREFIX) 3573 { 3574 as_bad (_("bad register name `%s'"), base_string); 3575 return 0; 3576 } 3577 3578 /* Check for scale factor. */ 3579 if (isdigit ((unsigned char) *base_string)) 3580 { 3581 if (!i386_scale (base_string)) 3582 return 0; 3583 3584 ++base_string; 3585 if (is_space_char (*base_string)) 3586 ++base_string; 3587 if (*base_string != ')') 3588 { 3589 as_bad (_("expecting `)' after scale factor in `%s'"), 3590 operand_string); 3591 return 0; 3592 } 3593 } 3594 else if (!i.index_reg) 3595 { 3596 as_bad (_("expecting index register or scale factor after `,'; got '%c'"), 3597 *base_string); 3598 return 0; 3599 } 3600 } 3601 else if (*base_string != ')') 3602 { 3603 as_bad (_("expecting `,' or `)' after base register in `%s'"), 3604 operand_string); 3605 return 0; 3606 } 3607 } 3608 else if (*base_string == REGISTER_PREFIX) 3609 { 3610 as_bad (_("bad register name `%s'"), base_string); 3611 return 0; 3612 } 3613 } 3614 3615 /* If there's an expression beginning the operand, parse it, 3616 assuming displacement_string_start and 3617 displacement_string_end are meaningful. */ 3618 if (displacement_string_start != displacement_string_end) 3619 { 3620 if (!i386_displacement (displacement_string_start, 3621 displacement_string_end)) 3622 return 0; 3623 } 3624 3625 /* Special case for (%dx) while doing input/output op. */ 3626 if (i.base_reg 3627 && i.base_reg->reg_type == (Reg16 | InOutPortReg) 3628 && i.index_reg == 0 3629 && i.log2_scale_factor == 0 3630 && i.seg[i.mem_operands] == 0 3631 && (i.types[this_operand] & Disp) == 0) 3632 { 3633 i.types[this_operand] = InOutPortReg; 3634 return 1; 3635 } 3636 3637 if (i386_index_check (operand_string) == 0) 3638 return 0; 3639 i.mem_operands++; 3640 } 3641 else 3642 { /* it's not a memory operand; argh! */ 3643 as_bad (_("invalid char %s beginning operand %d `%s'"), 3644 output_invalid (*op_string), 3645 this_operand + 1, 3646 op_string); 3647 return 0; 3648 } 3649 return 1; /* normal return */ 3650} 3651 3652/* 3653 * md_estimate_size_before_relax() 3654 * 3655 * Called just before relax(). 3656 * Any symbol that is now undefined will not become defined. 3657 * Return the correct fr_subtype in the frag. 3658 * Return the initial "guess for fr_var" to caller. 3659 * The guess for fr_var is ACTUALLY the growth beyond fr_fix. 3660 * Whatever we do to grow fr_fix or fr_var contributes to our returned value. 3661 * Although it may not be explicit in the frag, pretend fr_var starts with a 3662 * 0 value. 3663 */ 3664int 3665md_estimate_size_before_relax (fragP, segment) 3666 register fragS *fragP; 3667 register segT segment; 3668{ 3669 register unsigned char *opcode; 3670 register int old_fr_fix; 3671 3672 old_fr_fix = fragP->fr_fix; 3673 opcode = (unsigned char *) fragP->fr_opcode; 3674 /* We've already got fragP->fr_subtype right; all we have to do is 3675 check for un-relaxable symbols. */ 3676 if (S_GET_SEGMENT (fragP->fr_symbol) != segment) 3677 { 3678 /* symbol is undefined in this segment */ 3679 int code16 = fragP->fr_subtype & CODE16; 3680 int size = code16 ? 2 : 4; 3681#ifdef BFD_ASSEMBLER 3682 enum bfd_reloc_code_real reloc_type; 3683#else 3684 int reloc_type; 3685#endif 3686 3687 if (GOT_symbol /* Not quite right - we should switch on presence of 3688 @PLT, but I cannot see how to get to that from 3689 here. We should have done this in md_assemble to 3690 really get it right all of the time, but I think it 3691 does not matter that much, as this will be right 3692 most of the time. ERY */ 3693 && S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) 3694 reloc_type = BFD_RELOC_386_PLT32; 3695 else if (code16) 3696 reloc_type = BFD_RELOC_16_PCREL; 3697 else 3698 reloc_type = BFD_RELOC_32_PCREL; 3699 3700 switch (opcode[0]) 3701 { 3702 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ 3703 opcode[0] = 0xe9; /* dword disp jmp */ 3704 fragP->fr_fix += size; 3705 fix_new (fragP, old_fr_fix, size, 3706 fragP->fr_symbol, 3707 fragP->fr_offset, 1, 3708 reloc_type); 3709 break; 3710 3711 default: 3712 /* This changes the byte-displacement jump 0x7N 3713 to the dword-displacement jump 0x0f,0x8N. */ 3714 opcode[1] = opcode[0] + 0x10; 3715 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 3716 fragP->fr_fix += 1 + size; /* we've added an opcode byte */ 3717 fix_new (fragP, old_fr_fix + 1, size, 3718 fragP->fr_symbol, 3719 fragP->fr_offset, 1, 3720 reloc_type); 3721 break; 3722 } 3723 frag_wane (fragP); 3724 } 3725 return (fragP->fr_var + fragP->fr_fix - old_fr_fix); 3726} /* md_estimate_size_before_relax() */ 3727 3728/* 3729 * md_convert_frag(); 3730 * 3731 * Called after relax() is finished. 3732 * In: Address of frag. 3733 * fr_type == rs_machine_dependent. 3734 * fr_subtype is what the address relaxed to. 3735 * 3736 * Out: Any fixSs and constants are set up. 3737 * Caller will turn frag into a ".space 0". 3738 */ 3739#ifndef BFD_ASSEMBLER 3740void 3741md_convert_frag (headers, sec, fragP) 3742 object_headers *headers ATTRIBUTE_UNUSED; 3743 segT sec ATTRIBUTE_UNUSED; 3744 register fragS *fragP; 3745#else 3746void 3747md_convert_frag (abfd, sec, fragP) 3748 bfd *abfd ATTRIBUTE_UNUSED; 3749 segT sec ATTRIBUTE_UNUSED; 3750 register fragS *fragP; 3751#endif 3752{ 3753 register unsigned char *opcode; 3754 unsigned char *where_to_put_displacement = NULL; 3755 unsigned int target_address; 3756 unsigned int opcode_address; 3757 unsigned int extension = 0; 3758 int displacement_from_opcode_start; 3759 3760 opcode = (unsigned char *) fragP->fr_opcode; 3761 3762 /* Address we want to reach in file space. */ 3763 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 3764#ifdef BFD_ASSEMBLER /* not needed otherwise? */ 3765 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; 3766#endif 3767 3768 /* Address opcode resides at in file space. */ 3769 opcode_address = fragP->fr_address + fragP->fr_fix; 3770 3771 /* Displacement from opcode start to fill into instruction. */ 3772 displacement_from_opcode_start = target_address - opcode_address; 3773 3774 switch (fragP->fr_subtype) 3775 { 3776 case ENCODE_RELAX_STATE (COND_JUMP, SMALL): 3777 case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): 3778 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): 3779 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): 3780 /* don't have to change opcode */ 3781 extension = 1; /* 1 opcode + 1 displacement */ 3782 where_to_put_displacement = &opcode[1]; 3783 break; 3784 3785 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 3786 extension = 5; /* 2 opcode + 4 displacement */ 3787 opcode[1] = opcode[0] + 0x10; 3788 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 3789 where_to_put_displacement = &opcode[2]; 3790 break; 3791 3792 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 3793 extension = 4; /* 1 opcode + 4 displacement */ 3794 opcode[0] = 0xe9; 3795 where_to_put_displacement = &opcode[1]; 3796 break; 3797 3798 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 3799 extension = 3; /* 2 opcode + 2 displacement */ 3800 opcode[1] = opcode[0] + 0x10; 3801 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 3802 where_to_put_displacement = &opcode[2]; 3803 break; 3804 3805 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 3806 extension = 2; /* 1 opcode + 2 displacement */ 3807 opcode[0] = 0xe9; 3808 where_to_put_displacement = &opcode[1]; 3809 break; 3810 3811 default: 3812 BAD_CASE (fragP->fr_subtype); 3813 break; 3814 } 3815 /* now put displacement after opcode */ 3816 md_number_to_chars ((char *) where_to_put_displacement, 3817 (valueT) (displacement_from_opcode_start - extension), 3818 SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 3819 fragP->fr_fix += extension; 3820} 3821 3822 3823int md_short_jump_size = 2; /* size of byte displacement jmp */ 3824int md_long_jump_size = 5; /* size of dword displacement jmp */ 3825const int md_reloc_size = 8; /* Size of relocation record */ 3826 3827void 3828md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) 3829 char *ptr; 3830 addressT from_addr, to_addr; 3831 fragS *frag ATTRIBUTE_UNUSED; 3832 symbolS *to_symbol ATTRIBUTE_UNUSED; 3833{ 3834 long offset; 3835 3836 offset = to_addr - (from_addr + 2); 3837 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ 3838 md_number_to_chars (ptr + 1, (valueT) offset, 1); 3839} 3840 3841void 3842md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) 3843 char *ptr; 3844 addressT from_addr, to_addr; 3845 fragS *frag; 3846 symbolS *to_symbol; 3847{ 3848 long offset; 3849 3850 if (flag_do_long_jump) 3851 { 3852 offset = to_addr - S_GET_VALUE (to_symbol); 3853 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ 3854 md_number_to_chars (ptr + 1, (valueT) offset, 4); 3855 fix_new (frag, (ptr + 1) - frag->fr_literal, 4, 3856 to_symbol, (offsetT) 0, 0, BFD_RELOC_32); 3857 } 3858 else 3859 { 3860 offset = to_addr - (from_addr + 5); 3861 md_number_to_chars (ptr, (valueT) 0xe9, 1); 3862 md_number_to_chars (ptr + 1, (valueT) offset, 4); 3863 } 3864} 3865 3866/* Apply a fixup (fixS) to segment data, once it has been determined 3867 by our caller that we have all the info we need to fix it up. 3868 3869 On the 386, immediates, displacements, and data pointers are all in 3870 the same (little-endian) format, so we don't need to care about which 3871 we are handling. */ 3872 3873int 3874md_apply_fix3 (fixP, valp, seg) 3875 fixS *fixP; /* The fix we're to put in. */ 3876 valueT *valp; /* Pointer to the value of the bits. */ 3877 segT seg ATTRIBUTE_UNUSED; /* Segment fix is from. */ 3878{ 3879 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 3880 valueT value = *valp; 3881 3882#if defined (BFD_ASSEMBLER) && !defined (TE_Mach) 3883 if (fixP->fx_pcrel) 3884 { 3885 switch (fixP->fx_r_type) 3886 { 3887 default: 3888 break; 3889 3890 case BFD_RELOC_32: 3891 fixP->fx_r_type = BFD_RELOC_32_PCREL; 3892 break; 3893 case BFD_RELOC_16: 3894 fixP->fx_r_type = BFD_RELOC_16_PCREL; 3895 break; 3896 case BFD_RELOC_8: 3897 fixP->fx_r_type = BFD_RELOC_8_PCREL; 3898 break; 3899 } 3900 } 3901 3902 /* This is a hack. There should be a better way to handle this. 3903 This covers for the fact that bfd_install_relocation will 3904 subtract the current location (for partial_inplace, PC relative 3905 relocations); see more below. */ 3906 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL 3907 || fixP->fx_r_type == BFD_RELOC_16_PCREL 3908 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 3909 && fixP->fx_addsy) 3910 { 3911#ifndef OBJ_AOUT 3912 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 3913#ifdef TE_PE 3914 || OUTPUT_FLAVOR == bfd_target_coff_flavour 3915#endif 3916 ) 3917 value += fixP->fx_where + fixP->fx_frag->fr_address; 3918#endif 3919#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 3920 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 3921 { 3922 segT fseg = S_GET_SEGMENT (fixP->fx_addsy); 3923 3924 if ((fseg == seg 3925 || (symbol_section_p (fixP->fx_addsy) 3926 && fseg != absolute_section)) 3927 && ! S_IS_EXTERNAL (fixP->fx_addsy) 3928 && ! S_IS_WEAK (fixP->fx_addsy) 3929 && S_IS_DEFINED (fixP->fx_addsy) 3930 && ! S_IS_COMMON (fixP->fx_addsy)) 3931 { 3932 /* Yes, we add the values in twice. This is because 3933 bfd_perform_relocation subtracts them out again. I think 3934 bfd_perform_relocation is broken, but I don't dare change 3935 it. FIXME. */ 3936 value += fixP->fx_where + fixP->fx_frag->fr_address; 3937 } 3938 } 3939#endif 3940#if defined (OBJ_COFF) && defined (TE_PE) 3941 /* For some reason, the PE format does not store a section 3942 address offset for a PC relative symbol. */ 3943 if (S_GET_SEGMENT (fixP->fx_addsy) != seg) 3944 value += md_pcrel_from (fixP); 3945 else if (S_IS_EXTERNAL (fixP->fx_addsy) 3946 || S_IS_WEAK (fixP->fx_addsy)) 3947 { 3948 /* We are generating an external relocation for this defined 3949 symbol. We add the address, because 3950 bfd_install_relocation will subtract it. VALUE already 3951 holds the symbol value, because fixup_segment added it 3952 in. We subtract it out, and then we subtract it out 3953 again because bfd_install_relocation will add it in 3954 again. */ 3955 value += md_pcrel_from (fixP); 3956 value -= 2 * S_GET_VALUE (fixP->fx_addsy); 3957 } 3958#endif 3959 } 3960#ifdef TE_PE 3961 else if (fixP->fx_addsy != NULL 3962 && S_IS_DEFINED (fixP->fx_addsy) 3963 && (S_IS_EXTERNAL (fixP->fx_addsy) 3964 || S_IS_WEAK (fixP->fx_addsy))) 3965 { 3966 /* We are generating an external relocation for this defined 3967 symbol. VALUE already holds the symbol value, and 3968 bfd_install_relocation will add it in again. We don't want 3969 either addition. */ 3970 value -= 2 * S_GET_VALUE (fixP->fx_addsy); 3971 } 3972#endif 3973 3974 /* Fix a few things - the dynamic linker expects certain values here, 3975 and we must not dissappoint it. */ 3976#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 3977 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 3978 && fixP->fx_addsy) 3979 switch (fixP->fx_r_type) { 3980 case BFD_RELOC_386_PLT32: 3981 /* Make the jump instruction point to the address of the operand. At 3982 runtime we merely add the offset to the actual PLT entry. */ 3983 value = 0xfffffffc; 3984 break; 3985 case BFD_RELOC_386_GOTPC: 3986/* 3987 * This is tough to explain. We end up with this one if we have 3988 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal 3989 * here is to obtain the absolute address of the GOT, and it is strongly 3990 * preferable from a performance point of view to avoid using a runtime 3991 * relocation for this. The actual sequence of instructions often look 3992 * something like: 3993 * 3994 * call .L66 3995 * .L66: 3996 * popl %ebx 3997 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 3998 * 3999 * The call and pop essentially return the absolute address of 4000 * the label .L66 and store it in %ebx. The linker itself will 4001 * ultimately change the first operand of the addl so that %ebx points to 4002 * the GOT, but to keep things simple, the .o file must have this operand 4003 * set so that it generates not the absolute address of .L66, but the 4004 * absolute address of itself. This allows the linker itself simply 4005 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be 4006 * added in, and the addend of the relocation is stored in the operand 4007 * field for the instruction itself. 4008 * 4009 * Our job here is to fix the operand so that it would add the correct 4010 * offset so that %ebx would point to itself. The thing that is tricky is 4011 * that .-.L66 will point to the beginning of the instruction, so we need 4012 * to further modify the operand so that it will point to itself. 4013 * There are other cases where you have something like: 4014 * 4015 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 4016 * 4017 * and here no correction would be required. Internally in the assembler 4018 * we treat operands of this form as not being pcrel since the '.' is 4019 * explicitly mentioned, and I wonder whether it would simplify matters 4020 * to do it this way. Who knows. In earlier versions of the PIC patches, 4021 * the pcrel_adjust field was used to store the correction, but since the 4022 * expression is not pcrel, I felt it would be confusing to do it this way. 4023 */ 4024 value -= 1; 4025 break; 4026 case BFD_RELOC_386_GOT32: 4027 value = 0; /* Fully resolved at runtime. No addend. */ 4028 break; 4029 case BFD_RELOC_386_GOTOFF: 4030 break; 4031 4032 case BFD_RELOC_VTABLE_INHERIT: 4033 case BFD_RELOC_VTABLE_ENTRY: 4034 fixP->fx_done = 0; 4035 return 1; 4036 4037 default: 4038 break; 4039 } 4040#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 4041 *valp = value; 4042#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ 4043 md_number_to_chars (p, value, fixP->fx_size); 4044 4045 return 1; 4046} 4047 4048#if 0 4049/* This is never used. */ 4050long /* Knows about the byte order in a word. */ 4051md_chars_to_number (con, nbytes) 4052 unsigned char con[]; /* Low order byte 1st. */ 4053 int nbytes; /* Number of bytes in the input. */ 4054{ 4055 long retval; 4056 for (retval = 0, con += nbytes - 1; nbytes--; con--) 4057 { 4058 retval <<= BITS_PER_CHAR; 4059 retval |= *con; 4060 } 4061 return retval; 4062} 4063#endif /* 0 */ 4064 4065 4066#define MAX_LITTLENUMS 6 4067 4068/* Turn the string pointed to by litP into a floating point constant of type 4069 type, and emit the appropriate bytes. The number of LITTLENUMS emitted 4070 is stored in *sizeP . An error message is returned, or NULL on OK. */ 4071char * 4072md_atof (type, litP, sizeP) 4073 int type; 4074 char *litP; 4075 int *sizeP; 4076{ 4077 int prec; 4078 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4079 LITTLENUM_TYPE *wordP; 4080 char *t; 4081 4082 switch (type) 4083 { 4084 case 'f': 4085 case 'F': 4086 prec = 2; 4087 break; 4088 4089 case 'd': 4090 case 'D': 4091 prec = 4; 4092 break; 4093 4094 case 'x': 4095 case 'X': 4096 prec = 5; 4097 break; 4098 4099 default: 4100 *sizeP = 0; 4101 return _("Bad call to md_atof ()"); 4102 } 4103 t = atof_ieee (input_line_pointer, type, words); 4104 if (t) 4105 input_line_pointer = t; 4106 4107 *sizeP = prec * sizeof (LITTLENUM_TYPE); 4108 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with 4109 the bigendian 386. */ 4110 for (wordP = words + prec - 1; prec--;) 4111 { 4112 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); 4113 litP += sizeof (LITTLENUM_TYPE); 4114 } 4115 return 0; 4116} 4117 4118char output_invalid_buf[8]; 4119 4120static char * output_invalid PARAMS ((int)); 4121 4122static char * 4123output_invalid (c) 4124 int c; 4125{ 4126 if (isprint (c)) 4127 sprintf (output_invalid_buf, "'%c'", c); 4128 else 4129 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); 4130 return output_invalid_buf; 4131} 4132 4133 4134/* REG_STRING starts *before* REGISTER_PREFIX. */ 4135 4136static const reg_entry * 4137parse_register (reg_string, end_op) 4138 char *reg_string; 4139 char **end_op; 4140{ 4141 char *s = reg_string; 4142 char *p; 4143 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 4144 const reg_entry *r; 4145 4146 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 4147 if (*s == REGISTER_PREFIX) 4148 ++s; 4149 4150 if (is_space_char (*s)) 4151 ++s; 4152 4153 p = reg_name_given; 4154 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 4155 { 4156 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 4157 return (const reg_entry *) NULL; 4158 s++; 4159 } 4160 4161 *end_op = s; 4162 4163 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 4164 4165 /* Handle floating point regs, allowing spaces in the (i) part. */ 4166 if (r == i386_regtab /* %st is first entry of table */) 4167 { 4168 if (is_space_char (*s)) 4169 ++s; 4170 if (*s == '(') 4171 { 4172 ++s; 4173 if (is_space_char (*s)) 4174 ++s; 4175 if (*s >= '0' && *s <= '7') 4176 { 4177 r = &i386_float_regtab[*s - '0']; 4178 ++s; 4179 if (is_space_char (*s)) 4180 ++s; 4181 if (*s == ')') 4182 { 4183 *end_op = s + 1; 4184 return r; 4185 } 4186 } 4187 /* We have "%st(" then garbage */ 4188 return (const reg_entry *) NULL; 4189 } 4190 } 4191 4192 return r; 4193} 4194 4195#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4196CONST char *md_shortopts = "kmVQ:sq"; 4197#else 4198CONST char *md_shortopts = "m"; 4199#endif 4200struct option md_longopts[] = { 4201 {NULL, no_argument, NULL, 0} 4202}; 4203size_t md_longopts_size = sizeof (md_longopts); 4204 4205int 4206md_parse_option (c, arg) 4207 int c; 4208 char *arg ATTRIBUTE_UNUSED; 4209{ 4210 switch (c) 4211 { 4212 case 'm': 4213 flag_do_long_jump = 1; 4214 break; 4215 4216#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4217 /* -k: Ignore for FreeBSD compatibility. */ 4218 case 'k': 4219 break; 4220 4221 /* -V: SVR4 argument to print version ID. */ 4222 case 'V': 4223 print_version_id (); 4224 break; 4225 4226 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 4227 should be emitted or not. FIXME: Not implemented. */ 4228 case 'Q': 4229 break; 4230 4231 case 's': 4232 /* -s: On i386 Solaris, this tells the native assembler to use 4233 .stab instead of .stab.excl. We always use .stab anyhow. */ 4234 break; 4235 4236 case 'q': 4237 /* -q: On i386 Solaris, this tells the native assembler does 4238 fewer checks. */ 4239 break; 4240#endif 4241 4242 default: 4243 return 0; 4244 } 4245 return 1; 4246} 4247 4248void 4249md_show_usage (stream) 4250 FILE *stream; 4251{ 4252 fprintf (stream, _("\ 4253 -m do long jump\n")); 4254#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4255 fprintf (stream, _("\ 4256 -V print assembler version number\n\ 4257 -k ignored\n\ 4258 -Qy, -Qn ignored\n\ 4259 -q ignored\n\ 4260 -s ignored\n")); 4261#endif 4262} 4263 4264#ifdef BFD_ASSEMBLER 4265#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ 4266 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ 4267 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) 4268 4269/* Pick the target format to use. */ 4270 4271const char * 4272i386_target_format () 4273{ 4274 switch (OUTPUT_FLAVOR) 4275 { 4276#ifdef OBJ_MAYBE_AOUT 4277 case bfd_target_aout_flavour: 4278 return AOUT_TARGET_FORMAT; 4279#endif 4280#ifdef OBJ_MAYBE_COFF 4281 case bfd_target_coff_flavour: 4282 return "coff-i386"; 4283#endif 4284#ifdef OBJ_MAYBE_ELF 4285 case bfd_target_elf_flavour: 4286 return "elf32-i386"; 4287#endif 4288 default: 4289 abort (); 4290 return NULL; 4291 } 4292} 4293 4294#endif /* OBJ_MAYBE_ more than one */ 4295#endif /* BFD_ASSEMBLER */ 4296 4297symbolS * 4298md_undefined_symbol (name) 4299 char *name; 4300{ 4301 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 4302 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 4303 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 4304 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 4305 { 4306 if (!GOT_symbol) 4307 { 4308 if (symbol_find (name)) 4309 as_bad (_("GOT already in symbol table")); 4310 GOT_symbol = symbol_new (name, undefined_section, 4311 (valueT) 0, &zero_address_frag); 4312 }; 4313 return GOT_symbol; 4314 } 4315 return 0; 4316} 4317 4318/* Round up a section size to the appropriate boundary. */ 4319valueT 4320md_section_align (segment, size) 4321 segT segment ATTRIBUTE_UNUSED; 4322 valueT size; 4323{ 4324#ifdef BFD_ASSEMBLER 4325#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4326 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 4327 { 4328 /* For a.out, force the section size to be aligned. If we don't do 4329 this, BFD will align it for us, but it will not write out the 4330 final bytes of the section. This may be a bug in BFD, but it is 4331 easier to fix it here since that is how the other a.out targets 4332 work. */ 4333 int align; 4334 4335 align = bfd_get_section_alignment (stdoutput, segment); 4336 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 4337 } 4338#endif 4339#endif 4340 4341 return size; 4342} 4343 4344/* On the i386, PC-relative offsets are relative to the start of the 4345 next instruction. That is, the address of the offset, plus its 4346 size, since the offset is always the last part of the insn. */ 4347 4348long 4349md_pcrel_from (fixP) 4350 fixS *fixP; 4351{ 4352 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 4353} 4354 4355#ifndef I386COFF 4356 4357static void 4358s_bss (ignore) 4359 int ignore ATTRIBUTE_UNUSED; 4360{ 4361 register int temp; 4362 4363 temp = get_absolute_expression (); 4364 subseg_set (bss_section, (subsegT) temp); 4365 demand_empty_rest_of_line (); 4366} 4367 4368#endif 4369 4370 4371#ifdef BFD_ASSEMBLER 4372 4373void 4374i386_validate_fix (fixp) 4375 fixS *fixp; 4376{ 4377 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 4378 { 4379 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 4380 fixp->fx_subsy = 0; 4381 } 4382} 4383 4384arelent * 4385tc_gen_reloc (section, fixp) 4386 asection *section ATTRIBUTE_UNUSED; 4387 fixS *fixp; 4388{ 4389 arelent *rel; 4390 bfd_reloc_code_real_type code; 4391 4392 switch (fixp->fx_r_type) 4393 { 4394 case BFD_RELOC_386_PLT32: 4395 case BFD_RELOC_386_GOT32: 4396 case BFD_RELOC_386_GOTOFF: 4397 case BFD_RELOC_386_GOTPC: 4398 case BFD_RELOC_RVA: 4399 case BFD_RELOC_VTABLE_ENTRY: 4400 case BFD_RELOC_VTABLE_INHERIT: 4401 code = fixp->fx_r_type; 4402 break; 4403 default: 4404 if (fixp->fx_pcrel) 4405 { 4406 switch (fixp->fx_size) 4407 { 4408 default: 4409 as_bad (_("can not do %d byte pc-relative relocation"), 4410 fixp->fx_size); 4411 code = BFD_RELOC_32_PCREL; 4412 break; 4413 case 1: code = BFD_RELOC_8_PCREL; break; 4414 case 2: code = BFD_RELOC_16_PCREL; break; 4415 case 4: code = BFD_RELOC_32_PCREL; break; 4416 } 4417 } 4418 else 4419 { 4420 switch (fixp->fx_size) 4421 { 4422 default: 4423 as_bad (_("can not do %d byte relocation"), fixp->fx_size); 4424 code = BFD_RELOC_32; 4425 break; 4426 case 1: code = BFD_RELOC_8; break; 4427 case 2: code = BFD_RELOC_16; break; 4428 case 4: code = BFD_RELOC_32; break; 4429 } 4430 } 4431 break; 4432 } 4433 4434 if (code == BFD_RELOC_32 4435 && GOT_symbol 4436 && fixp->fx_addsy == GOT_symbol) 4437 code = BFD_RELOC_386_GOTPC; 4438 4439 rel = (arelent *) xmalloc (sizeof (arelent)); 4440 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 4441 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 4442 4443 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 4444 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 4445 vtable entry to be used in the relocation's section offset. */ 4446 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4447 rel->address = fixp->fx_offset; 4448 4449 if (fixp->fx_pcrel) 4450 rel->addend = fixp->fx_addnumber; 4451 else 4452 rel->addend = 0; 4453 4454 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 4455 if (rel->howto == NULL) 4456 { 4457 as_bad_where (fixp->fx_file, fixp->fx_line, 4458 _("cannot represent relocation type %s"), 4459 bfd_get_reloc_code_name (code)); 4460 /* Set howto to a garbage value so that we can keep going. */ 4461 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 4462 assert (rel->howto != NULL); 4463 } 4464 4465 return rel; 4466} 4467 4468#else /* ! BFD_ASSEMBLER */ 4469 4470#if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) 4471void 4472tc_aout_fix_to_chars (where, fixP, segment_address_in_file) 4473 char *where; 4474 fixS *fixP; 4475 relax_addressT segment_address_in_file; 4476{ 4477 /* 4478 * In: length of relocation (or of address) in chars: 1, 2 or 4. 4479 * Out: GNU LD relocation length code: 0, 1, or 2. 4480 */ 4481 4482 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; 4483 long r_symbolnum; 4484 4485 know (fixP->fx_addsy != NULL); 4486 4487 md_number_to_chars (where, 4488 (valueT) (fixP->fx_frag->fr_address 4489 + fixP->fx_where - segment_address_in_file), 4490 4); 4491 4492 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) 4493 ? S_GET_TYPE (fixP->fx_addsy) 4494 : fixP->fx_addsy->sy_number); 4495 4496 where[6] = (r_symbolnum >> 16) & 0x0ff; 4497 where[5] = (r_symbolnum >> 8) & 0x0ff; 4498 where[4] = r_symbolnum & 0x0ff; 4499 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) 4500 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) 4501 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); 4502} 4503 4504#endif /* OBJ_AOUT or OBJ_BOUT */ 4505 4506#if defined (I386COFF) 4507 4508short 4509tc_coff_fix2rtype (fixP) 4510 fixS *fixP; 4511{ 4512 if (fixP->fx_r_type == R_IMAGEBASE) 4513 return R_IMAGEBASE; 4514 4515 return (fixP->fx_pcrel ? 4516 (fixP->fx_size == 1 ? R_PCRBYTE : 4517 fixP->fx_size == 2 ? R_PCRWORD : 4518 R_PCRLONG) : 4519 (fixP->fx_size == 1 ? R_RELBYTE : 4520 fixP->fx_size == 2 ? R_RELWORD : 4521 R_DIR32)); 4522} 4523 4524int 4525tc_coff_sizemachdep (frag) 4526 fragS *frag; 4527{ 4528 if (frag->fr_next) 4529 return (frag->fr_next->fr_address - frag->fr_address); 4530 else 4531 return 0; 4532} 4533 4534#endif /* I386COFF */ 4535 4536#endif /* ! BFD_ASSEMBLER */ 4537 4538/* end of tc-i386.c */ 4539