cap.c revision 250741
1/*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#ifndef lint 32static const char rcsid[] = 33 "$FreeBSD: head/usr.sbin/pciconf/cap.c 250741 2013-05-17 14:05:31Z kib $"; 34#endif /* not lint */ 35 36#include <sys/types.h> 37 38#include <err.h> 39#include <stdio.h> 40#include <sys/agpio.h> 41#include <sys/pciio.h> 42 43#include <dev/agp/agpreg.h> 44#include <dev/pci/pcireg.h> 45 46#include "pciconf.h" 47 48static void list_ecaps(int fd, struct pci_conf *p); 49 50static void 51cap_power(int fd, struct pci_conf *p, uint8_t ptr) 52{ 53 uint16_t cap, status; 54 55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 57 printf("powerspec %d supports D0%s%s D3 current D%d", 58 cap & PCIM_PCAP_SPEC, 59 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 60 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 61 status & PCIM_PSTAT_DMASK); 62} 63 64static void 65cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 66{ 67 uint32_t status, command; 68 69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 71 printf("AGP "); 72 if (AGP_MODE_GET_MODE_3(status)) { 73 printf("v3 "); 74 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 75 printf("8x "); 76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 77 printf("4x "); 78 } else { 79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 80 printf("4x "); 81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 82 printf("2x "); 83 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 84 printf("1x "); 85 } 86 if (AGP_MODE_GET_SBA(status)) 87 printf("SBA "); 88 if (AGP_MODE_GET_AGP(command)) { 89 printf("enabled at "); 90 if (AGP_MODE_GET_MODE_3(command)) { 91 printf("v3 "); 92 switch (AGP_MODE_GET_RATE(command)) { 93 case AGP_MODE_V3_RATE_8x: 94 printf("8x "); 95 break; 96 case AGP_MODE_V3_RATE_4x: 97 printf("4x "); 98 break; 99 } 100 } else 101 switch (AGP_MODE_GET_RATE(command)) { 102 case AGP_MODE_V2_RATE_4x: 103 printf("4x "); 104 break; 105 case AGP_MODE_V2_RATE_2x: 106 printf("2x "); 107 break; 108 case AGP_MODE_V2_RATE_1x: 109 printf("1x "); 110 break; 111 } 112 if (AGP_MODE_GET_SBA(command)) 113 printf("SBA "); 114 } else 115 printf("disabled"); 116} 117 118static void 119cap_vpd(int fd, struct pci_conf *p, uint8_t ptr) 120{ 121 122 printf("VPD"); 123} 124 125static void 126cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 127{ 128 uint16_t ctrl; 129 int msgnum; 130 131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 132 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 133 printf("MSI supports %d message%s%s%s ", msgnum, 134 (msgnum == 1) ? "" : "s", 135 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 136 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 137 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 138 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 139 printf("enabled with %d message%s", msgnum, 140 (msgnum == 1) ? "" : "s"); 141 } 142} 143 144static void 145cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 146{ 147 uint32_t status; 148 int comma, max_splits, max_burst_read; 149 150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 151 printf("PCI-X "); 152 if (status & PCIXM_STATUS_64BIT) 153 printf("64-bit "); 154 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 155 printf("bridge "); 156 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 157 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 158 printf("supports"); 159 comma = 0; 160 if (status & PCIXM_STATUS_133CAP) { 161 printf("%s 133MHz", comma ? "," : ""); 162 comma = 1; 163 } 164 if (status & PCIXM_STATUS_266CAP) { 165 printf("%s 266MHz", comma ? "," : ""); 166 comma = 1; 167 } 168 if (status & PCIXM_STATUS_533CAP) { 169 printf("%s 533MHz", comma ? "," : ""); 170 comma = 1; 171 } 172 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 173 return; 174 switch (status & PCIXM_STATUS_MAX_READ) { 175 case PCIXM_STATUS_MAX_READ_512: 176 max_burst_read = 512; 177 break; 178 case PCIXM_STATUS_MAX_READ_1024: 179 max_burst_read = 1024; 180 break; 181 case PCIXM_STATUS_MAX_READ_2048: 182 max_burst_read = 2048; 183 break; 184 case PCIXM_STATUS_MAX_READ_4096: 185 max_burst_read = 4096; 186 break; 187 } 188 switch (status & PCIXM_STATUS_MAX_SPLITS) { 189 case PCIXM_STATUS_MAX_SPLITS_1: 190 max_splits = 1; 191 break; 192 case PCIXM_STATUS_MAX_SPLITS_2: 193 max_splits = 2; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_3: 196 max_splits = 3; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_4: 199 max_splits = 4; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_8: 202 max_splits = 8; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_12: 205 max_splits = 12; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_16: 208 max_splits = 16; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_32: 211 max_splits = 32; 212 break; 213 } 214 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 215 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 216} 217 218static void 219cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 220{ 221 uint32_t reg; 222 uint16_t command; 223 224 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 225 printf("HT "); 226 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 227 printf("slave"); 228 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 229 printf("host"); 230 else 231 switch (command & PCIM_HTCMD_CAP_MASK) { 232 case PCIM_HTCAP_SWITCH: 233 printf("switch"); 234 break; 235 case PCIM_HTCAP_INTERRUPT: 236 printf("interrupt"); 237 break; 238 case PCIM_HTCAP_REVISION_ID: 239 printf("revision ID"); 240 break; 241 case PCIM_HTCAP_UNITID_CLUMPING: 242 printf("unit ID clumping"); 243 break; 244 case PCIM_HTCAP_EXT_CONFIG_SPACE: 245 printf("extended config space"); 246 break; 247 case PCIM_HTCAP_ADDRESS_MAPPING: 248 printf("address mapping"); 249 break; 250 case PCIM_HTCAP_MSI_MAPPING: 251 printf("MSI %saddress window %s at 0x", 252 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 253 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 254 "disabled"); 255 if (command & PCIM_HTCMD_MSI_FIXED) 256 printf("fee00000"); 257 else { 258 reg = read_config(fd, &p->pc_sel, 259 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 260 if (reg != 0) 261 printf("%08x", reg); 262 reg = read_config(fd, &p->pc_sel, 263 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 264 printf("%08x", reg); 265 } 266 break; 267 case PCIM_HTCAP_DIRECT_ROUTE: 268 printf("direct route"); 269 break; 270 case PCIM_HTCAP_VCSET: 271 printf("VC set"); 272 break; 273 case PCIM_HTCAP_RETRY_MODE: 274 printf("retry mode"); 275 break; 276 case PCIM_HTCAP_X86_ENCODING: 277 printf("X86 encoding"); 278 break; 279 case PCIM_HTCAP_GEN3: 280 printf("Gen3"); 281 break; 282 case PCIM_HTCAP_FLE: 283 printf("function-level extension"); 284 break; 285 case PCIM_HTCAP_PM: 286 printf("power management"); 287 break; 288 case PCIM_HTCAP_HIGH_NODE_COUNT: 289 printf("high node count"); 290 break; 291 default: 292 printf("unknown %02x", command); 293 break; 294 } 295} 296 297static void 298cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 299{ 300 uint8_t length; 301 302 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 303 printf("vendor (length %d)", length); 304 if (p->pc_vendor == 0x8086) { 305 /* Intel */ 306 uint8_t version; 307 308 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 309 1); 310 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 311 if (version >> 4 == 1 && length == 12) { 312 /* Feature Detection */ 313 uint32_t fvec; 314 int comma; 315 316 comma = 0; 317 fvec = read_config(fd, &p->pc_sel, ptr + 318 PCIR_VENDOR_DATA + 5, 4); 319 printf("\n\t\t features:"); 320 if (fvec & (1 << 0)) { 321 printf(" AMT"); 322 comma = 1; 323 } 324 fvec = read_config(fd, &p->pc_sel, ptr + 325 PCIR_VENDOR_DATA + 1, 4); 326 if (fvec & (1 << 21)) { 327 printf("%s Quick Resume", comma ? "," : ""); 328 comma = 1; 329 } 330 if (fvec & (1 << 18)) { 331 printf("%s SATA RAID-5", comma ? "," : ""); 332 comma = 1; 333 } 334 if (fvec & (1 << 9)) { 335 printf("%s Mobile", comma ? "," : ""); 336 comma = 1; 337 } 338 if (fvec & (1 << 7)) { 339 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 340 comma = 1; 341 } else { 342 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 343 comma = 1; 344 } 345 if (fvec & (1 << 5)) { 346 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 347 comma = 1; 348 } 349 if (fvec & (1 << 3)) { 350 printf("%s SATA AHCI", comma ? "," : ""); 351 comma = 1; 352 } 353 } 354 } 355} 356 357static void 358cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 359{ 360 uint16_t debug_port; 361 362 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 363 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 364 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 365} 366 367static void 368cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 369{ 370 uint32_t id; 371 372 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 373 printf("PCI Bridge card=0x%08x", id); 374} 375 376#define MAX_PAYLOAD(field) (128 << (field)) 377 378static const char * 379link_speed_string(uint8_t speed) 380{ 381 382 switch (speed) { 383 case 1: 384 return ("2.5"); 385 case 2: 386 return ("5.0"); 387 case 3: 388 return ("8.0"); 389 default: 390 return ("undef"); 391 } 392} 393 394static void 395cap_express(int fd, struct pci_conf *p, uint8_t ptr) 396{ 397 uint32_t val; 398 uint16_t flags; 399 400 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 401 printf("PCI-Express %d ", flags & PCIEM_FLAGS_VERSION); 402 switch (flags & PCIEM_FLAGS_TYPE) { 403 case PCIEM_TYPE_ENDPOINT: 404 printf("endpoint"); 405 break; 406 case PCIEM_TYPE_LEGACY_ENDPOINT: 407 printf("legacy endpoint"); 408 break; 409 case PCIEM_TYPE_ROOT_PORT: 410 printf("root port"); 411 break; 412 case PCIEM_TYPE_UPSTREAM_PORT: 413 printf("upstream port"); 414 break; 415 case PCIEM_TYPE_DOWNSTREAM_PORT: 416 printf("downstream port"); 417 break; 418 case PCIEM_TYPE_PCI_BRIDGE: 419 printf("PCI bridge"); 420 break; 421 case PCIEM_TYPE_PCIE_BRIDGE: 422 printf("PCI to PCIe bridge"); 423 break; 424 case PCIEM_TYPE_ROOT_INT_EP: 425 printf("root endpoint"); 426 break; 427 case PCIEM_TYPE_ROOT_EC: 428 printf("event collector"); 429 break; 430 default: 431 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 432 break; 433 } 434 if (flags & PCIEM_FLAGS_SLOT) 435 printf(" slot"); 436 if (flags & PCIEM_FLAGS_IRQ) 437 printf(" IRQ %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 438 val = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 439 flags = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 440 printf(" max data %d(%d)", 441 MAX_PAYLOAD((flags & PCIEM_CTL_MAX_PAYLOAD) >> 5), 442 MAX_PAYLOAD(val & PCIEM_CAP_MAX_PAYLOAD)); 443 if (val & PCIEM_CAP_FLR) 444 printf(" FLR"); 445 val = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 446 flags = read_config(fd, &p->pc_sel, ptr+ PCIER_LINK_STA, 2); 447 printf(" link x%d(x%d)", (flags & PCIEM_LINK_STA_WIDTH) >> 4, 448 (val & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 449 /* 450 * Only print link speed info if the link's max width is 451 * greater than 0. 452 */ 453 if ((val & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 454 printf("\n speed"); 455 printf(" %s(%s)", (flags & PCIEM_LINK_STA_WIDTH) == 0 ? 456 "0.0" : link_speed_string(flags & PCIEM_LINK_STA_SPEED), 457 link_speed_string(val & PCIEM_LINK_CAP_MAX_SPEED)); 458 } 459} 460 461static void 462cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 463{ 464 uint32_t pba_offset, table_offset, val; 465 int msgnum, pba_bar, table_bar; 466 uint16_t ctrl; 467 468 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 469 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 470 471 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 472 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 473 table_offset = val & ~PCIM_MSIX_BIR_MASK; 474 475 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 476 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 477 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 478 479 printf("MSI-X supports %d message%s%s\n", msgnum, 480 (msgnum == 1) ? "" : "s", 481 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 482 483 printf(" "); 484 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 485 table_bar, table_offset, pba_bar, pba_offset); 486} 487 488static void 489cap_sata(int fd, struct pci_conf *p, uint8_t ptr) 490{ 491 492 printf("SATA Index-Data Pair"); 493} 494 495static void 496cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 497{ 498 uint8_t cap; 499 500 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 501 printf("PCI Advanced Features:%s%s", 502 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 503 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 504} 505 506void 507list_caps(int fd, struct pci_conf *p) 508{ 509 int express; 510 uint16_t sta; 511 uint8_t ptr, cap; 512 513 /* Are capabilities present for this device? */ 514 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 515 if (!(sta & PCIM_STATUS_CAPPRESENT)) 516 return; 517 518 switch (p->pc_hdr & PCIM_HDRTYPE) { 519 case PCIM_HDRTYPE_NORMAL: 520 case PCIM_HDRTYPE_BRIDGE: 521 ptr = PCIR_CAP_PTR; 522 break; 523 case PCIM_HDRTYPE_CARDBUS: 524 ptr = PCIR_CAP_PTR_2; 525 break; 526 default: 527 errx(1, "list_caps: bad header type"); 528 } 529 530 /* Walk the capability list. */ 531 express = 0; 532 ptr = read_config(fd, &p->pc_sel, ptr, 1); 533 while (ptr != 0 && ptr != 0xff) { 534 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 535 printf(" cap %02x[%02x] = ", cap, ptr); 536 switch (cap) { 537 case PCIY_PMG: 538 cap_power(fd, p, ptr); 539 break; 540 case PCIY_AGP: 541 cap_agp(fd, p, ptr); 542 break; 543 case PCIY_VPD: 544 cap_vpd(fd, p, ptr); 545 break; 546 case PCIY_MSI: 547 cap_msi(fd, p, ptr); 548 break; 549 case PCIY_PCIX: 550 cap_pcix(fd, p, ptr); 551 break; 552 case PCIY_HT: 553 cap_ht(fd, p, ptr); 554 break; 555 case PCIY_VENDOR: 556 cap_vendor(fd, p, ptr); 557 break; 558 case PCIY_DEBUG: 559 cap_debug(fd, p, ptr); 560 break; 561 case PCIY_SUBVENDOR: 562 cap_subvendor(fd, p, ptr); 563 break; 564 case PCIY_EXPRESS: 565 express = 1; 566 cap_express(fd, p, ptr); 567 break; 568 case PCIY_MSIX: 569 cap_msix(fd, p, ptr); 570 break; 571 case PCIY_SATA: 572 cap_sata(fd, p, ptr); 573 break; 574 case PCIY_PCIAF: 575 cap_pciaf(fd, p, ptr); 576 break; 577 default: 578 printf("unknown"); 579 break; 580 } 581 printf("\n"); 582 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 583 } 584 585 if (express) 586 list_ecaps(fd, p); 587} 588 589/* From <sys/systm.h>. */ 590static __inline uint32_t 591bitcount32(uint32_t x) 592{ 593 594 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 595 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 596 x = (x + (x >> 4)) & 0x0f0f0f0f; 597 x = (x + (x >> 8)); 598 x = (x + (x >> 16)) & 0x000000ff; 599 return (x); 600} 601 602static void 603ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 604{ 605 uint32_t sta, mask; 606 607 printf("AER %d", ver); 608 if (ver < 1) 609 return; 610 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 611 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 612 printf(" %d fatal", bitcount32(sta & mask)); 613 printf(" %d non-fatal", bitcount32(sta & ~mask)); 614 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 615 printf(" %d corrected", bitcount32(sta)); 616} 617 618static void 619ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 620{ 621 uint32_t cap1; 622 623 printf("VC %d", ver); 624 if (ver < 1) 625 return; 626 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 627 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 628 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 629 printf(" lowpri VC0-VC%d", 630 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 631} 632 633static void 634ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 635{ 636 uint32_t high, low; 637 638 printf("Serial %d", ver); 639 if (ver < 1) 640 return; 641 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 642 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 643 printf(" %08x%08x", high, low); 644} 645 646static void 647ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 648{ 649 uint32_t val; 650 651 printf("Vendor %d", ver); 652 if (ver < 1) 653 return; 654 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 655 printf(" ID %d", val & 0xffff); 656} 657 658static void 659ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 660{ 661 uint32_t val; 662 663 printf("PCIe Sec %d", ver); 664 if (ver < 1) 665 return; 666 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 667 printf(" lane errors %#x", val); 668} 669 670struct { 671 uint16_t id; 672 const char *name; 673} ecap_names[] = { 674 { PCIZ_PWRBDGT, "Power Budgeting" }, 675 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 676 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 677 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 678 { PCIZ_MFVC, "MFVC" }, 679 { PCIZ_RCRB, "RCRB" }, 680 { PCIZ_ACS, "ACS" }, 681 { PCIZ_ARI, "ARI" }, 682 { PCIZ_ATS, "ATS" }, 683 { PCIZ_SRIOV, "SRIOV" }, 684 { PCIZ_MULTICAST, "Multicast" }, 685 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 686 { PCIZ_DPA, "DPA" }, 687 { PCIZ_TPH_REQ, "TPH Requester" }, 688 { PCIZ_LTR, "LTR" }, 689 { 0, NULL } 690}; 691 692static void 693list_ecaps(int fd, struct pci_conf *p) 694{ 695 const char *name; 696 uint32_t ecap; 697 uint16_t ptr; 698 int i; 699 700 ptr = PCIR_EXTCAP; 701 ecap = read_config(fd, &p->pc_sel, ptr, 4); 702 if (ecap == 0xffffffff || ecap == 0) 703 return; 704 for (;;) { 705 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 706 switch (PCI_EXTCAP_ID(ecap)) { 707 case PCIZ_AER: 708 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 709 break; 710 case PCIZ_VC: 711 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 712 break; 713 case PCIZ_SERNUM: 714 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 715 break; 716 case PCIZ_VENDOR: 717 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 718 break; 719 case PCIZ_SEC_PCIE: 720 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 721 break; 722 default: 723 name = "unknown"; 724 for (i = 0; ecap_names[i].name != NULL; i++) 725 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 726 name = ecap_names[i].name; 727 break; 728 } 729 printf("%s %d", name, PCI_EXTCAP_VER(ecap)); 730 break; 731 } 732 printf("\n"); 733 ptr = PCI_EXTCAP_NEXTPTR(ecap); 734 if (ptr == 0) 735 break; 736 ecap = read_config(fd, &p->pc_sel, ptr, 4); 737 } 738} 739 740/* Find offset of a specific capability. Returns 0 on failure. */ 741uint8_t 742pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 743{ 744 uint16_t sta; 745 uint8_t ptr, cap; 746 747 /* Are capabilities present for this device? */ 748 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 749 if (!(sta & PCIM_STATUS_CAPPRESENT)) 750 return (0); 751 752 switch (p->pc_hdr & PCIM_HDRTYPE) { 753 case PCIM_HDRTYPE_NORMAL: 754 case PCIM_HDRTYPE_BRIDGE: 755 ptr = PCIR_CAP_PTR; 756 break; 757 case PCIM_HDRTYPE_CARDBUS: 758 ptr = PCIR_CAP_PTR_2; 759 break; 760 default: 761 return (0); 762 } 763 764 ptr = read_config(fd, &p->pc_sel, ptr, 1); 765 while (ptr != 0 && ptr != 0xff) { 766 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 767 if (cap == id) 768 return (ptr); 769 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 770 } 771 return (0); 772} 773 774/* Find offset of a specific extended capability. Returns 0 on failure. */ 775uint16_t 776pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 777{ 778 uint32_t ecap; 779 uint16_t ptr; 780 781 ptr = PCIR_EXTCAP; 782 ecap = read_config(fd, &p->pc_sel, ptr, 4); 783 if (ecap == 0xffffffff || ecap == 0) 784 return (0); 785 for (;;) { 786 if (PCI_EXTCAP_ID(ecap) == id) 787 return (ptr); 788 ptr = PCI_EXTCAP_NEXTPTR(ecap); 789 if (ptr == 0) 790 break; 791 ecap = read_config(fd, &p->pc_sel, ptr, 4); 792 } 793 return (0); 794} 795