ahci.h revision 256056
1251607Sdim/*- 2251607Sdim * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3251607Sdim * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 4251607Sdim * All rights reserved. 5251607Sdim * 6251607Sdim * Redistribution and use in source and binary forms, with or without 7251607Sdim * modification, are permitted provided that the following conditions 8251607Sdim * are met: 9251607Sdim * 1. Redistributions of source code must retain the above copyright 10251607Sdim * notice, this list of conditions and the following disclaimer, 11251607Sdim * without modification, immediately at the beginning of the file. 12251607Sdim * 2. Redistributions in binary form must reproduce the above copyright 13251607Sdim * notice, this list of conditions and the following disclaimer in the 14251607Sdim * documentation and/or other materials provided with the distribution. 15251607Sdim * 16251607Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17251607Sdim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18251607Sdim * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19251607Sdim * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20276479Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21251607Sdim * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22251607Sdim * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23276479Sdim * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24276479Sdim * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25251607Sdim * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26251607Sdim * 27261991Sdim * $FreeBSD: head/usr.sbin/bhyve/ahci.h 256056 2013-10-04 18:31:38Z grehan $ 28251607Sdim */ 29251607Sdim 30251607Sdim#ifndef _AHCI_H_ 31251607Sdim#define _AHCI_H_ 32251607Sdim 33251607Sdim/* ATA register defines */ 34251607Sdim#define ATA_DATA 0 /* (RW) data */ 35251607Sdim 36251607Sdim#define ATA_FEATURE 1 /* (W) feature */ 37251607Sdim#define ATA_F_DMA 0x01 /* enable DMA */ 38251607Sdim#define ATA_F_OVL 0x02 /* enable overlap */ 39251607Sdim 40251607Sdim#define ATA_COUNT 2 /* (W) sector count */ 41251607Sdim 42251607Sdim#define ATA_SECTOR 3 /* (RW) sector # */ 43251607Sdim#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 44251607Sdim#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 45251607Sdim#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 46251607Sdim#define ATA_D_LBA 0x40 /* use LBA addressing */ 47251607Sdim#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 48251607Sdim 49251607Sdim#define ATA_COMMAND 7 /* (W) command */ 50251607Sdim 51276479Sdim#define ATA_ERROR 8 /* (R) error */ 52251607Sdim#define ATA_E_ILI 0x01 /* illegal length */ 53251607Sdim#define ATA_E_NM 0x02 /* no media */ 54251607Sdim#define ATA_E_ABORT 0x04 /* command aborted */ 55251607Sdim#define ATA_E_MCR 0x08 /* media change request */ 56251607Sdim#define ATA_E_IDNF 0x10 /* ID not found */ 57251607Sdim#define ATA_E_MC 0x20 /* media changed */ 58251607Sdim#define ATA_E_UNC 0x40 /* uncorrectable data */ 59251607Sdim#define ATA_E_ICRC 0x80 /* UDMA crc error */ 60251607Sdim#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 61251607Sdim 62251607Sdim#define ATA_IREASON 9 /* (R) interrupt reason */ 63251607Sdim#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 64251607Sdim#define ATA_I_IN 0x02 /* read (1) | write (0) */ 65251607Sdim#define ATA_I_RELEASE 0x04 /* released bus (1) */ 66251607Sdim#define ATA_I_TAGMASK 0xf8 /* tag mask */ 67251607Sdim 68251607Sdim#define ATA_STATUS 10 /* (R) status */ 69251607Sdim#define ATA_ALTSTAT 11 /* (R) alternate status */ 70251607Sdim#define ATA_S_ERROR 0x01 /* error */ 71251607Sdim#define ATA_S_INDEX 0x02 /* index */ 72251607Sdim#define ATA_S_CORR 0x04 /* data corrected */ 73251607Sdim#define ATA_S_DRQ 0x08 /* data request */ 74251607Sdim#define ATA_S_DSC 0x10 /* drive seek completed */ 75251607Sdim#define ATA_S_SERVICE 0x10 /* drive needs service */ 76251607Sdim#define ATA_S_DWF 0x20 /* drive write fault */ 77261991Sdim#define ATA_S_DMA 0x20 /* DMA ready */ 78261991Sdim#define ATA_S_READY 0x40 /* drive ready */ 79261991Sdim#define ATA_S_BUSY 0x80 /* busy */ 80261991Sdim 81261991Sdim#define ATA_CONTROL 12 /* (W) control */ 82261991Sdim#define ATA_A_IDS 0x02 /* disable interrupts */ 83261991Sdim#define ATA_A_RESET 0x04 /* RESET controller */ 84261991Sdim#define ATA_A_4BIT 0x08 /* 4 head bits */ 85288943Sdim#define ATA_A_HOB 0x80 /* High Order Byte enable */ 86288943Sdim 87288943Sdim/* SATA register defines */ 88261991Sdim#define ATA_SSTATUS 13 89261991Sdim#define ATA_SS_DET_MASK 0x0000000f 90261991Sdim#define ATA_SS_DET_NO_DEVICE 0x00000000 91261991Sdim#define ATA_SS_DET_DEV_PRESENT 0x00000001 92261991Sdim#define ATA_SS_DET_PHY_ONLINE 0x00000003 93261991Sdim#define ATA_SS_DET_PHY_OFFLINE 0x00000004 94261991Sdim 95261991Sdim#define ATA_SS_SPD_MASK 0x000000f0 96261991Sdim#define ATA_SS_SPD_NO_SPEED 0x00000000 97261991Sdim#define ATA_SS_SPD_GEN1 0x00000010 98261991Sdim#define ATA_SS_SPD_GEN2 0x00000020 99261991Sdim#define ATA_SS_SPD_GEN3 0x00000040 100261991Sdim 101261991Sdim#define ATA_SS_IPM_MASK 0x00000f00 102261991Sdim#define ATA_SS_IPM_NO_DEVICE 0x00000000 103261991Sdim#define ATA_SS_IPM_ACTIVE 0x00000100 104261991Sdim#define ATA_SS_IPM_PARTIAL 0x00000200 105261991Sdim#define ATA_SS_IPM_SLUMBER 0x00000600 106261991Sdim 107261991Sdim#define ATA_SERROR 14 108261991Sdim#define ATA_SE_DATA_CORRECTED 0x00000001 109261991Sdim#define ATA_SE_COMM_CORRECTED 0x00000002 110261991Sdim#define ATA_SE_DATA_ERR 0x00000100 111261991Sdim#define ATA_SE_COMM_ERR 0x00000200 112261991Sdim#define ATA_SE_PROT_ERR 0x00000400 113261991Sdim#define ATA_SE_HOST_ERR 0x00000800 114261991Sdim#define ATA_SE_PHY_CHANGED 0x00010000 115261991Sdim#define ATA_SE_PHY_IERROR 0x00020000 116261991Sdim#define ATA_SE_COMM_WAKE 0x00040000 117261991Sdim#define ATA_SE_DECODE_ERR 0x00080000 118261991Sdim#define ATA_SE_PARITY_ERR 0x00100000 119261991Sdim#define ATA_SE_CRC_ERR 0x00200000 120261991Sdim#define ATA_SE_HANDSHAKE_ERR 0x00400000 121261991Sdim#define ATA_SE_LINKSEQ_ERR 0x00800000 122261991Sdim#define ATA_SE_TRANSPORT_ERR 0x01000000 123261991Sdim#define ATA_SE_UNKNOWN_FIS 0x02000000 124261991Sdim#define ATA_SE_EXCHANGED 0x04000000 125261991Sdim 126261991Sdim#define ATA_SCONTROL 15 127261991Sdim#define ATA_SC_DET_MASK 0x0000000f 128251607Sdim#define ATA_SC_DET_IDLE 0x00000000 129261991Sdim#define ATA_SC_DET_RESET 0x00000001 130261991Sdim#define ATA_SC_DET_DISABLE 0x00000004 131276479Sdim 132261991Sdim#define ATA_SC_SPD_MASK 0x000000f0 133261991Sdim#define ATA_SC_SPD_NO_SPEED 0x00000000 134261991Sdim#define ATA_SC_SPD_SPEED_GEN1 0x00000010 135261991Sdim#define ATA_SC_SPD_SPEED_GEN2 0x00000020 136261991Sdim#define ATA_SC_SPD_SPEED_GEN3 0x00000040 137261991Sdim 138261991Sdim#define ATA_SC_IPM_MASK 0x00000f00 139261991Sdim#define ATA_SC_IPM_NONE 0x00000000 140261991Sdim#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 141288943Sdim#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 142261991Sdim 143261991Sdim#define ATA_SACTIVE 16 144261991Sdim 145261991Sdim#define AHCI_MAX_PORTS 32 146261991Sdim#define AHCI_MAX_SLOTS 32 147261991Sdim 148261991Sdim/* SATA AHCI v1.0 register defines */ 149261991Sdim#define AHCI_CAP 0x00 150261991Sdim#define AHCI_CAP_NPMASK 0x0000001f 151261991Sdim#define AHCI_CAP_SXS 0x00000020 152261991Sdim#define AHCI_CAP_EMS 0x00000040 153261991Sdim#define AHCI_CAP_CCCS 0x00000080 154261991Sdim#define AHCI_CAP_NCS 0x00001F00 155276479Sdim#define AHCI_CAP_NCS_SHIFT 8 156276479Sdim#define AHCI_CAP_PSC 0x00002000 157261991Sdim#define AHCI_CAP_SSC 0x00004000 158261991Sdim#define AHCI_CAP_PMD 0x00008000 159251607Sdim#define AHCI_CAP_FBSS 0x00010000 160251607Sdim#define AHCI_CAP_SPM 0x00020000 161261991Sdim#define AHCI_CAP_SAM 0x00080000 162261991Sdim#define AHCI_CAP_ISS 0x00F00000 163276479Sdim#define AHCI_CAP_ISS_SHIFT 20 164276479Sdim#define AHCI_CAP_SCLO 0x01000000 165276479Sdim#define AHCI_CAP_SAL 0x02000000 166261991Sdim#define AHCI_CAP_SALP 0x04000000 167261991Sdim#define AHCI_CAP_SSS 0x08000000 168261991Sdim#define AHCI_CAP_SMPS 0x10000000 169261991Sdim#define AHCI_CAP_SSNTF 0x20000000 170261991Sdim#define AHCI_CAP_SNCQ 0x40000000 171261991Sdim#define AHCI_CAP_64BIT 0x80000000 172261991Sdim 173261991Sdim#define AHCI_GHC 0x04 174261991Sdim#define AHCI_GHC_AE 0x80000000 175251607Sdim#define AHCI_GHC_MRSM 0x00000004 176251607Sdim#define AHCI_GHC_IE 0x00000002 177251607Sdim#define AHCI_GHC_HR 0x00000001 178251607Sdim 179251607Sdim#define AHCI_IS 0x08 180251607Sdim#define AHCI_PI 0x0c 181251607Sdim#define AHCI_VS 0x10 182251607Sdim 183251607Sdim#define AHCI_CCCC 0x14 184251607Sdim#define AHCI_CCCC_TV_MASK 0xffff0000 185251607Sdim#define AHCI_CCCC_TV_SHIFT 16 186251607Sdim#define AHCI_CCCC_CC_MASK 0x0000ff00 187261991Sdim#define AHCI_CCCC_CC_SHIFT 8 188251607Sdim#define AHCI_CCCC_INT_MASK 0x000000f8 189251607Sdim#define AHCI_CCCC_INT_SHIFT 3 190251607Sdim#define AHCI_CCCC_EN 0x00000001 191251607Sdim#define AHCI_CCCP 0x18 192251607Sdim 193276479Sdim#define AHCI_EM_LOC 0x1C 194261991Sdim#define AHCI_EM_CTL 0x20 195261991Sdim#define AHCI_EM_MR 0x00000001 196261991Sdim#define AHCI_EM_TM 0x00000100 197251607Sdim#define AHCI_EM_RST 0x00000200 198251607Sdim#define AHCI_EM_LED 0x00010000 199276479Sdim#define AHCI_EM_SAFTE 0x00020000 200276479Sdim#define AHCI_EM_SES2 0x00040000 201251607Sdim#define AHCI_EM_SGPIO 0x00080000 202251607Sdim#define AHCI_EM_SMB 0x01000000 203251607Sdim#define AHCI_EM_XMT 0x02000000 204251607Sdim#define AHCI_EM_ALHD 0x04000000 205276479Sdim#define AHCI_EM_PM 0x08000000 206251607Sdim 207251607Sdim#define AHCI_CAP2 0x24 208251607Sdim#define AHCI_CAP2_BOH 0x00000001 209251607Sdim#define AHCI_CAP2_NVMP 0x00000002 210251607Sdim#define AHCI_CAP2_APST 0x00000004 211251607Sdim 212288943Sdim#define AHCI_OFFSET 0x100 213251607Sdim#define AHCI_STEP 0x80 214251607Sdim 215251607Sdim#define AHCI_P_CLB 0x00 216288943Sdim#define AHCI_P_CLBU 0x04 217288943Sdim#define AHCI_P_FB 0x08 218251607Sdim#define AHCI_P_FBU 0x0c 219251607Sdim#define AHCI_P_IS 0x10 220251607Sdim#define AHCI_P_IE 0x14 221251607Sdim#define AHCI_P_IX_DHR 0x00000001 222251607Sdim#define AHCI_P_IX_PS 0x00000002 223251607Sdim#define AHCI_P_IX_DS 0x00000004 224251607Sdim#define AHCI_P_IX_SDB 0x00000008 225251607Sdim#define AHCI_P_IX_UF 0x00000010 226251607Sdim#define AHCI_P_IX_DP 0x00000020 227251607Sdim#define AHCI_P_IX_PC 0x00000040 228251607Sdim#define AHCI_P_IX_MP 0x00000080 229251607Sdim 230251607Sdim#define AHCI_P_IX_PRC 0x00400000 231296417Sdim#define AHCI_P_IX_IPM 0x00800000 232296417Sdim#define AHCI_P_IX_OF 0x01000000 233296417Sdim#define AHCI_P_IX_INF 0x04000000 234251607Sdim#define AHCI_P_IX_IF 0x08000000 235251607Sdim#define AHCI_P_IX_HBD 0x10000000 236251607Sdim#define AHCI_P_IX_HBF 0x20000000 237251607Sdim#define AHCI_P_IX_TFE 0x40000000 238251607Sdim#define AHCI_P_IX_CPD 0x80000000 239 240#define AHCI_P_CMD 0x18 241#define AHCI_P_CMD_ST 0x00000001 242#define AHCI_P_CMD_SUD 0x00000002 243#define AHCI_P_CMD_POD 0x00000004 244#define AHCI_P_CMD_CLO 0x00000008 245#define AHCI_P_CMD_FRE 0x00000010 246#define AHCI_P_CMD_CCS_MASK 0x00001f00 247#define AHCI_P_CMD_CCS_SHIFT 8 248#define AHCI_P_CMD_ISS 0x00002000 249#define AHCI_P_CMD_FR 0x00004000 250#define AHCI_P_CMD_CR 0x00008000 251#define AHCI_P_CMD_CPS 0x00010000 252#define AHCI_P_CMD_PMA 0x00020000 253#define AHCI_P_CMD_HPCP 0x00040000 254#define AHCI_P_CMD_MPSP 0x00080000 255#define AHCI_P_CMD_CPD 0x00100000 256#define AHCI_P_CMD_ESP 0x00200000 257#define AHCI_P_CMD_FBSCP 0x00400000 258#define AHCI_P_CMD_APSTE 0x00800000 259#define AHCI_P_CMD_ATAPI 0x01000000 260#define AHCI_P_CMD_DLAE 0x02000000 261#define AHCI_P_CMD_ALPE 0x04000000 262#define AHCI_P_CMD_ASP 0x08000000 263#define AHCI_P_CMD_ICC_MASK 0xf0000000 264#define AHCI_P_CMD_NOOP 0x00000000 265#define AHCI_P_CMD_ACTIVE 0x10000000 266#define AHCI_P_CMD_PARTIAL 0x20000000 267#define AHCI_P_CMD_SLUMBER 0x60000000 268 269#define AHCI_P_TFD 0x20 270#define AHCI_P_SIG 0x24 271#define AHCI_P_SSTS 0x28 272#define AHCI_P_SCTL 0x2c 273#define AHCI_P_SERR 0x30 274#define AHCI_P_SACT 0x34 275#define AHCI_P_CI 0x38 276#define AHCI_P_SNTF 0x3C 277#define AHCI_P_FBS 0x40 278#define AHCI_P_FBS_EN 0x00000001 279#define AHCI_P_FBS_DEC 0x00000002 280#define AHCI_P_FBS_SDE 0x00000004 281#define AHCI_P_FBS_DEV 0x00000f00 282#define AHCI_P_FBS_DEV_SHIFT 8 283#define AHCI_P_FBS_ADO 0x0000f000 284#define AHCI_P_FBS_ADO_SHIFT 12 285#define AHCI_P_FBS_DWE 0x000f0000 286#define AHCI_P_FBS_DWE_SHIFT 16 287 288/* Just to be sure, if building as module. */ 289#if MAXPHYS < 512 * 1024 290#undef MAXPHYS 291#define MAXPHYS 512 * 1024 292#endif 293/* Pessimistic prognosis on number of required S/G entries */ 294#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 295/* Command list. 32 commands. First, 1Kbyte aligned. */ 296#define AHCI_CL_OFFSET 0 297#define AHCI_CL_SIZE 32 298/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 299#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 300#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 301/* Total main work area. */ 302#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 303 304#endif /* _AHCI_H_ */ 305