1181624Skmacy/****************************************************************************** 2181624Skmacy * xen.h 3181624Skmacy * 4181624Skmacy * Guest OS interface to Xen. 5181624Skmacy * 6181624Skmacy * Permission is hereby granted, free of charge, to any person obtaining a copy 7181624Skmacy * of this software and associated documentation files (the "Software"), to 8181624Skmacy * deal in the Software without restriction, including without limitation the 9181624Skmacy * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10181624Skmacy * sell copies of the Software, and to permit persons to whom the Software is 11181624Skmacy * furnished to do so, subject to the following conditions: 12181624Skmacy * 13181624Skmacy * The above copyright notice and this permission notice shall be included in 14181624Skmacy * all copies or substantial portions of the Software. 15181624Skmacy * 16181624Skmacy * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17181624Skmacy * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18181624Skmacy * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19181624Skmacy * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20181624Skmacy * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21181624Skmacy * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22181624Skmacy * DEALINGS IN THE SOFTWARE. 23181624Skmacy * 24181624Skmacy * Copyright (c) 2004, K A Fraser 25181624Skmacy */ 26181624Skmacy 27181624Skmacy#ifndef __XEN_PUBLIC_XEN_H__ 28181624Skmacy#define __XEN_PUBLIC_XEN_H__ 29181624Skmacy 30183375Skmacy#include "xen-compat.h" 31181624Skmacy 32181624Skmacy#if defined(__i386__) || defined(__x86_64__) 33183375Skmacy#include "arch-x86/xen.h" 34181624Skmacy#elif defined(__ia64__) 35181624Skmacy#include "arch-ia64.h" 36251767Sgibbs#elif defined(__arm__) 37251767Sgibbs#include "arch-arm.h" 38181624Skmacy#else 39181624Skmacy#error "Unsupported architecture" 40181624Skmacy#endif 41181624Skmacy 42183375Skmacy#ifndef __ASSEMBLY__ 43183375Skmacy/* Guest handles for primitive C types. */ 44183375SkmacyDEFINE_XEN_GUEST_HANDLE(char); 45183375Skmacy__DEFINE_XEN_GUEST_HANDLE(uchar, unsigned char); 46183375SkmacyDEFINE_XEN_GUEST_HANDLE(int); 47183375Skmacy__DEFINE_XEN_GUEST_HANDLE(uint, unsigned int); 48183375SkmacyDEFINE_XEN_GUEST_HANDLE(long); 49183375Skmacy__DEFINE_XEN_GUEST_HANDLE(ulong, unsigned long); 50183375SkmacyDEFINE_XEN_GUEST_HANDLE(void); 51183375Skmacy 52251767SgibbsDEFINE_XEN_GUEST_HANDLE(uint64_t); 53183375SkmacyDEFINE_XEN_GUEST_HANDLE(xen_pfn_t); 54183375Skmacy#endif 55183375Skmacy 56181624Skmacy/* 57181624Skmacy * HYPERCALLS 58181624Skmacy */ 59181624Skmacy 60251767Sgibbs/* `incontents 100 hcalls List of hypercalls 61251767Sgibbs * ` enum hypercall_num { // __HYPERVISOR_* => HYPERVISOR_*() 62251767Sgibbs */ 63251767Sgibbs 64181624Skmacy#define __HYPERVISOR_set_trap_table 0 65181624Skmacy#define __HYPERVISOR_mmu_update 1 66181624Skmacy#define __HYPERVISOR_set_gdt 2 67181624Skmacy#define __HYPERVISOR_stack_switch 3 68181624Skmacy#define __HYPERVISOR_set_callbacks 4 69181624Skmacy#define __HYPERVISOR_fpu_taskswitch 5 70181624Skmacy#define __HYPERVISOR_sched_op_compat 6 /* compat since 0x00030101 */ 71181624Skmacy#define __HYPERVISOR_platform_op 7 72181624Skmacy#define __HYPERVISOR_set_debugreg 8 73181624Skmacy#define __HYPERVISOR_get_debugreg 9 74181624Skmacy#define __HYPERVISOR_update_descriptor 10 75181624Skmacy#define __HYPERVISOR_memory_op 12 76181624Skmacy#define __HYPERVISOR_multicall 13 77181624Skmacy#define __HYPERVISOR_update_va_mapping 14 78181624Skmacy#define __HYPERVISOR_set_timer_op 15 79181624Skmacy#define __HYPERVISOR_event_channel_op_compat 16 /* compat since 0x00030202 */ 80181624Skmacy#define __HYPERVISOR_xen_version 17 81181624Skmacy#define __HYPERVISOR_console_io 18 82181624Skmacy#define __HYPERVISOR_physdev_op_compat 19 /* compat since 0x00030202 */ 83181624Skmacy#define __HYPERVISOR_grant_table_op 20 84181624Skmacy#define __HYPERVISOR_vm_assist 21 85181624Skmacy#define __HYPERVISOR_update_va_mapping_otherdomain 22 86181624Skmacy#define __HYPERVISOR_iret 23 /* x86 only */ 87181624Skmacy#define __HYPERVISOR_vcpu_op 24 88181624Skmacy#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ 89181624Skmacy#define __HYPERVISOR_mmuext_op 26 90183375Skmacy#define __HYPERVISOR_xsm_op 27 91181624Skmacy#define __HYPERVISOR_nmi_op 28 92181624Skmacy#define __HYPERVISOR_sched_op 29 93181624Skmacy#define __HYPERVISOR_callback_op 30 94181624Skmacy#define __HYPERVISOR_xenoprof_op 31 95181624Skmacy#define __HYPERVISOR_event_channel_op 32 96181624Skmacy#define __HYPERVISOR_physdev_op 33 97181624Skmacy#define __HYPERVISOR_hvm_op 34 98181624Skmacy#define __HYPERVISOR_sysctl 35 99181624Skmacy#define __HYPERVISOR_domctl 36 100181624Skmacy#define __HYPERVISOR_kexec_op 37 101251767Sgibbs#define __HYPERVISOR_tmem_op 38 102251767Sgibbs#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ 103181624Skmacy 104181624Skmacy/* Architecture-specific hypercall definitions. */ 105181624Skmacy#define __HYPERVISOR_arch_0 48 106181624Skmacy#define __HYPERVISOR_arch_1 49 107181624Skmacy#define __HYPERVISOR_arch_2 50 108181624Skmacy#define __HYPERVISOR_arch_3 51 109181624Skmacy#define __HYPERVISOR_arch_4 52 110181624Skmacy#define __HYPERVISOR_arch_5 53 111181624Skmacy#define __HYPERVISOR_arch_6 54 112181624Skmacy#define __HYPERVISOR_arch_7 55 113181624Skmacy 114251767Sgibbs/* ` } */ 115251767Sgibbs 116181624Skmacy/* 117181624Skmacy * HYPERCALL COMPATIBILITY. 118181624Skmacy */ 119181624Skmacy 120181624Skmacy/* New sched_op hypercall introduced in 0x00030101. */ 121181624Skmacy#if __XEN_INTERFACE_VERSION__ < 0x00030101 122181624Skmacy#undef __HYPERVISOR_sched_op 123181624Skmacy#define __HYPERVISOR_sched_op __HYPERVISOR_sched_op_compat 124181624Skmacy#endif 125181624Skmacy 126181624Skmacy/* New event-channel and physdev hypercalls introduced in 0x00030202. */ 127181624Skmacy#if __XEN_INTERFACE_VERSION__ < 0x00030202 128181624Skmacy#undef __HYPERVISOR_event_channel_op 129181624Skmacy#define __HYPERVISOR_event_channel_op __HYPERVISOR_event_channel_op_compat 130181624Skmacy#undef __HYPERVISOR_physdev_op 131181624Skmacy#define __HYPERVISOR_physdev_op __HYPERVISOR_physdev_op_compat 132181624Skmacy#endif 133181624Skmacy 134181624Skmacy/* New platform_op hypercall introduced in 0x00030204. */ 135181624Skmacy#if __XEN_INTERFACE_VERSION__ < 0x00030204 136181624Skmacy#define __HYPERVISOR_dom0_op __HYPERVISOR_platform_op 137181624Skmacy#endif 138181624Skmacy 139181624Skmacy/* 140181624Skmacy * VIRTUAL INTERRUPTS 141181624Skmacy * 142181624Skmacy * Virtual interrupts that a guest OS may receive from Xen. 143181624Skmacy * 144181624Skmacy * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a 145181624Skmacy * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. 146181624Skmacy * The latter can be allocated only once per guest: they must initially be 147181624Skmacy * allocated to VCPU0 but can subsequently be re-bound. 148181624Skmacy */ 149251767Sgibbs/* ` enum virq { */ 150181624Skmacy#define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ 151181624Skmacy#define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ 152181624Skmacy#define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ 153181624Skmacy#define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ 154181624Skmacy#define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ 155181624Skmacy#define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ 156181624Skmacy#define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ 157181624Skmacy#define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ 158251767Sgibbs#define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ 159251767Sgibbs#define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ 160251767Sgibbs#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ 161251767Sgibbs#define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ 162181624Skmacy 163181624Skmacy/* Architecture-specific VIRQ definitions. */ 164181624Skmacy#define VIRQ_ARCH_0 16 165181624Skmacy#define VIRQ_ARCH_1 17 166181624Skmacy#define VIRQ_ARCH_2 18 167181624Skmacy#define VIRQ_ARCH_3 19 168181624Skmacy#define VIRQ_ARCH_4 20 169181624Skmacy#define VIRQ_ARCH_5 21 170181624Skmacy#define VIRQ_ARCH_6 22 171181624Skmacy#define VIRQ_ARCH_7 23 172251767Sgibbs/* ` } */ 173181624Skmacy 174181624Skmacy#define NR_VIRQS 24 175181624Skmacy 176181624Skmacy/* 177251767Sgibbs * ` enum neg_errnoval 178251767Sgibbs * ` HYPERVISOR_mmu_update(const struct mmu_update reqs[], 179251767Sgibbs * ` unsigned count, unsigned *done_out, 180251767Sgibbs * ` unsigned foreigndom) 181251767Sgibbs * ` 182251767Sgibbs * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). 183251767Sgibbs * @count is the length of the above array. 184251767Sgibbs * @pdone is an output parameter indicating number of completed operations 185251767Sgibbs * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this 186251767Sgibbs * hypercall invocation. Can be DOMID_SELF. 187251767Sgibbs * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced 188251767Sgibbs * in this hypercall invocation. The value of this field 189251767Sgibbs * (x) encodes the PFD as follows: 190251767Sgibbs * x == 0 => PFD == DOMID_SELF 191251767Sgibbs * x != 0 => PFD == x - 1 192181624Skmacy * 193251767Sgibbs * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. 194251767Sgibbs * ------------- 195181624Skmacy * ptr[1:0] == MMU_NORMAL_PT_UPDATE: 196251767Sgibbs * Updates an entry in a page table belonging to PFD. If updating an L1 table, 197251767Sgibbs * and the new table entry is valid/present, the mapped frame must belong to 198251767Sgibbs * FD. If attempting to map an I/O page then the caller assumes the privilege 199251767Sgibbs * of the FD. 200181624Skmacy * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. 201181624Skmacy * FD == DOMID_XEN: Map restricted areas of Xen's heap space. 202181624Skmacy * ptr[:2] -- Machine address of the page-table entry to modify. 203181624Skmacy * val -- Value to write. 204251767Sgibbs * 205251767Sgibbs * There also certain implicit requirements when using this hypercall. The 206251767Sgibbs * pages that make up a pagetable must be mapped read-only in the guest. 207251767Sgibbs * This prevents uncontrolled guest updates to the pagetable. Xen strictly 208251767Sgibbs * enforces this, and will disallow any pagetable update which will end up 209251767Sgibbs * mapping pagetable page RW, and will disallow using any writable page as a 210251767Sgibbs * pagetable. In practice it means that when constructing a page table for a 211251767Sgibbs * process, thread, etc, we MUST be very dilligient in following these rules: 212251767Sgibbs * 1). Start with top-level page (PGD or in Xen language: L4). Fill out 213251767Sgibbs * the entries. 214251767Sgibbs * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD 215251767Sgibbs * or L2). 216251767Sgibbs * 3). Start filling out the PTE table (L1) with the PTE entries. Once 217251767Sgibbs * done, make sure to set each of those entries to RO (so writeable bit 218251767Sgibbs * is unset). Once that has been completed, set the PMD (L2) for this 219251767Sgibbs * PTE table as RO. 220251767Sgibbs * 4). When completed with all of the PMD (L2) entries, and all of them have 221251767Sgibbs * been set to RO, make sure to set RO the PUD (L3). Do the same 222251767Sgibbs * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. 223251767Sgibbs * 5). Now before you can use those pages (so setting the cr3), you MUST also 224251767Sgibbs * pin them so that the hypervisor can verify the entries. This is done 225251767Sgibbs * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame 226251767Sgibbs * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( 227251767Sgibbs * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be 228251767Sgibbs * issued. 229251767Sgibbs * For 32-bit guests, the L4 is not used (as there is less pagetables), so 230251767Sgibbs * instead use L3. 231251767Sgibbs * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE 232251767Sgibbs * hypercall. Also if so desired the OS can also try to write to the PTE 233251767Sgibbs * and be trapped by the hypervisor (as the PTE entry is RO). 234251767Sgibbs * 235251767Sgibbs * To deallocate the pages, the operations are the reverse of the steps 236251767Sgibbs * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the 237251767Sgibbs * pagetable MUST not be in use (meaning that the cr3 is not set to it). 238181624Skmacy * 239181624Skmacy * ptr[1:0] == MMU_MACHPHYS_UPDATE: 240181624Skmacy * Updates an entry in the machine->pseudo-physical mapping table. 241181624Skmacy * ptr[:2] -- Machine address within the frame whose mapping to modify. 242181624Skmacy * The frame must belong to the FD, if one is specified. 243181624Skmacy * val -- Value to write into the mapping entry. 244183375Skmacy * 245183375Skmacy * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: 246183375Skmacy * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed 247183375Skmacy * with those in @val. 248251767Sgibbs * 249251767Sgibbs * @val is usually the machine frame number along with some attributes. 250251767Sgibbs * The attributes by default follow the architecture defined bits. Meaning that 251251767Sgibbs * if this is a X86_64 machine and four page table layout is used, the layout 252251767Sgibbs * of val is: 253251767Sgibbs * - 63 if set means No execute (NX) 254251767Sgibbs * - 46-13 the machine frame number 255251767Sgibbs * - 12 available for guest 256251767Sgibbs * - 11 available for guest 257251767Sgibbs * - 10 available for guest 258251767Sgibbs * - 9 available for guest 259251767Sgibbs * - 8 global 260251767Sgibbs * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) 261251767Sgibbs * - 6 dirty 262251767Sgibbs * - 5 accessed 263251767Sgibbs * - 4 page cached disabled 264251767Sgibbs * - 3 page write through 265251767Sgibbs * - 2 userspace accessible 266251767Sgibbs * - 1 writeable 267251767Sgibbs * - 0 present 268251767Sgibbs * 269251767Sgibbs * The one bits that does not fit with the default layout is the PAGE_PSE 270251767Sgibbs * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the 271251767Sgibbs * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB 272251767Sgibbs * (or 2MB) instead of using the PAGE_PSE bit. 273251767Sgibbs * 274251767Sgibbs * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen 275251767Sgibbs * using it as the Page Attribute Table (PAT) bit - for details on it please 276251767Sgibbs * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of 277251767Sgibbs * pages instead of using MTRRs. 278251767Sgibbs * 279251767Sgibbs * The PAT MSR is as follow (it is a 64-bit value, each entry is 8 bits): 280251767Sgibbs * PAT4 PAT0 281251767Sgibbs * +---+----+----+----+-----+----+----+ 282251767Sgibbs * WC | WC | WB | UC | UC- | WC | WB | <= Linux 283251767Sgibbs * +---+----+----+----+-----+----+----+ 284251767Sgibbs * WC | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) 285251767Sgibbs * +---+----+----+----+-----+----+----+ 286251767Sgibbs * WC | WP | WC | UC | UC- | WT | WB | <= Xen 287251767Sgibbs * +---+----+----+----+-----+----+----+ 288251767Sgibbs * 289251767Sgibbs * The lookup of this index table translates to looking up 290251767Sgibbs * Bit 7, Bit 4, and Bit 3 of val entry: 291251767Sgibbs * 292251767Sgibbs * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). 293251767Sgibbs * 294251767Sgibbs * If all bits are off, then we are using PAT0. If bit 3 turned on, 295251767Sgibbs * then we are using PAT1, if bit 3 and bit 4, then PAT2.. 296251767Sgibbs * 297251767Sgibbs * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means 298251767Sgibbs * that if a guest that follows Linux's PAT setup and would like to set Write 299251767Sgibbs * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is 300251767Sgibbs * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the 301251767Sgibbs * caching as: 302251767Sgibbs * 303251767Sgibbs * WB = none (so PAT0) 304251767Sgibbs * WC = PWT (bit 3 on) 305251767Sgibbs * UC = PWT | PCD (bit 3 and 4 are on). 306251767Sgibbs * 307251767Sgibbs * To make it work with Xen, it needs to translate the WC bit as so: 308251767Sgibbs * 309251767Sgibbs * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 310251767Sgibbs * 311251767Sgibbs * And to translate back it would: 312251767Sgibbs * 313251767Sgibbs * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. 314181624Skmacy */ 315183375Skmacy#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ 316183375Skmacy#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ 317183375Skmacy#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ 318181624Skmacy 319181624Skmacy/* 320181624Skmacy * MMU EXTENDED OPERATIONS 321181624Skmacy * 322181624Skmacy * HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. 323181624Skmacy * A foreigndom (FD) can be specified (or DOMID_SELF for none). 324181624Skmacy * Where the FD has some effect, it is described below. 325181624Skmacy * 326181624Skmacy * cmd: MMUEXT_(UN)PIN_*_TABLE 327181624Skmacy * mfn: Machine frame number to be (un)pinned as a p.t. page. 328181624Skmacy * The frame must belong to the FD, if one is specified. 329181624Skmacy * 330181624Skmacy * cmd: MMUEXT_NEW_BASEPTR 331181624Skmacy * mfn: Machine frame number of new page-table base to install in MMU. 332181624Skmacy * 333181624Skmacy * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] 334181624Skmacy * mfn: Machine frame number of new page-table base to install in MMU 335181624Skmacy * when in user space. 336181624Skmacy * 337181624Skmacy * cmd: MMUEXT_TLB_FLUSH_LOCAL 338181624Skmacy * No additional arguments. Flushes local TLB. 339181624Skmacy * 340181624Skmacy * cmd: MMUEXT_INVLPG_LOCAL 341181624Skmacy * linear_addr: Linear address to be flushed from the local TLB. 342181624Skmacy * 343181624Skmacy * cmd: MMUEXT_TLB_FLUSH_MULTI 344181624Skmacy * vcpumask: Pointer to bitmap of VCPUs to be flushed. 345181624Skmacy * 346181624Skmacy * cmd: MMUEXT_INVLPG_MULTI 347181624Skmacy * linear_addr: Linear address to be flushed. 348181624Skmacy * vcpumask: Pointer to bitmap of VCPUs to be flushed. 349181624Skmacy * 350181624Skmacy * cmd: MMUEXT_TLB_FLUSH_ALL 351181624Skmacy * No additional arguments. Flushes all VCPUs' TLBs. 352181624Skmacy * 353181624Skmacy * cmd: MMUEXT_INVLPG_ALL 354181624Skmacy * linear_addr: Linear address to be flushed from all VCPUs' TLBs. 355181624Skmacy * 356181624Skmacy * cmd: MMUEXT_FLUSH_CACHE 357181624Skmacy * No additional arguments. Writes back and flushes cache contents. 358251767Sgibbs * 359251767Sgibbs * cmd: MMUEXT_FLUSH_CACHE_GLOBAL 360251767Sgibbs * No additional arguments. Writes back and flushes cache contents 361251767Sgibbs * on all CPUs in the system. 362181624Skmacy * 363181624Skmacy * cmd: MMUEXT_SET_LDT 364181624Skmacy * linear_addr: Linear address of LDT base (NB. must be page-aligned). 365181624Skmacy * nr_ents: Number of entries in LDT. 366251767Sgibbs * 367251767Sgibbs * cmd: MMUEXT_CLEAR_PAGE 368251767Sgibbs * mfn: Machine frame number to be cleared. 369251767Sgibbs * 370251767Sgibbs * cmd: MMUEXT_COPY_PAGE 371251767Sgibbs * mfn: Machine frame number of the destination page. 372251767Sgibbs * src_mfn: Machine frame number of the source page. 373251767Sgibbs * 374251767Sgibbs * cmd: MMUEXT_[UN]MARK_SUPER 375251767Sgibbs * mfn: Machine frame number of head of superpage to be [un]marked. 376181624Skmacy */ 377181624Skmacy#define MMUEXT_PIN_L1_TABLE 0 378181624Skmacy#define MMUEXT_PIN_L2_TABLE 1 379181624Skmacy#define MMUEXT_PIN_L3_TABLE 2 380181624Skmacy#define MMUEXT_PIN_L4_TABLE 3 381181624Skmacy#define MMUEXT_UNPIN_TABLE 4 382181624Skmacy#define MMUEXT_NEW_BASEPTR 5 383181624Skmacy#define MMUEXT_TLB_FLUSH_LOCAL 6 384181624Skmacy#define MMUEXT_INVLPG_LOCAL 7 385181624Skmacy#define MMUEXT_TLB_FLUSH_MULTI 8 386181624Skmacy#define MMUEXT_INVLPG_MULTI 9 387181624Skmacy#define MMUEXT_TLB_FLUSH_ALL 10 388181624Skmacy#define MMUEXT_INVLPG_ALL 11 389181624Skmacy#define MMUEXT_FLUSH_CACHE 12 390181624Skmacy#define MMUEXT_SET_LDT 13 391181624Skmacy#define MMUEXT_NEW_USER_BASEPTR 15 392251767Sgibbs#define MMUEXT_CLEAR_PAGE 16 393251767Sgibbs#define MMUEXT_COPY_PAGE 17 394251767Sgibbs#define MMUEXT_FLUSH_CACHE_GLOBAL 18 395251767Sgibbs#define MMUEXT_MARK_SUPER 19 396251767Sgibbs#define MMUEXT_UNMARK_SUPER 20 397181624Skmacy 398181624Skmacy#ifndef __ASSEMBLY__ 399181624Skmacystruct mmuext_op { 400181624Skmacy unsigned int cmd; 401181624Skmacy union { 402251767Sgibbs /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR 403251767Sgibbs * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ 404181624Skmacy xen_pfn_t mfn; 405181624Skmacy /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ 406181624Skmacy unsigned long linear_addr; 407181624Skmacy } arg1; 408181624Skmacy union { 409181624Skmacy /* SET_LDT */ 410181624Skmacy unsigned int nr_ents; 411181624Skmacy /* TLB_FLUSH_MULTI, INVLPG_MULTI */ 412183375Skmacy#if __XEN_INTERFACE_VERSION__ >= 0x00030205 413251767Sgibbs XEN_GUEST_HANDLE(const_void) vcpumask; 414183375Skmacy#else 415251767Sgibbs const void *vcpumask; 416183375Skmacy#endif 417251767Sgibbs /* COPY_PAGE */ 418251767Sgibbs xen_pfn_t src_mfn; 419181624Skmacy } arg2; 420181624Skmacy}; 421181624Skmacytypedef struct mmuext_op mmuext_op_t; 422181624SkmacyDEFINE_XEN_GUEST_HANDLE(mmuext_op_t); 423181624Skmacy#endif 424181624Skmacy 425181624Skmacy/* These are passed as 'flags' to update_va_mapping. They can be ORed. */ 426181624Skmacy/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ 427181624Skmacy/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ 428181624Skmacy#define UVMF_NONE (0UL<<0) /* No flushing at all. */ 429181624Skmacy#define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ 430181624Skmacy#define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ 431181624Skmacy#define UVMF_FLUSHTYPE_MASK (3UL<<0) 432181624Skmacy#define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ 433181624Skmacy#define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ 434181624Skmacy#define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ 435181624Skmacy 436181624Skmacy/* 437181624Skmacy * Commands to HYPERVISOR_console_io(). 438181624Skmacy */ 439181624Skmacy#define CONSOLEIO_write 0 440181624Skmacy#define CONSOLEIO_read 1 441181624Skmacy 442181624Skmacy/* 443181624Skmacy * Commands to HYPERVISOR_vm_assist(). 444181624Skmacy */ 445181624Skmacy#define VMASST_CMD_enable 0 446181624Skmacy#define VMASST_CMD_disable 1 447181624Skmacy 448181624Skmacy/* x86/32 guests: simulate full 4GB segment limits. */ 449181624Skmacy#define VMASST_TYPE_4gb_segments 0 450181624Skmacy 451181624Skmacy/* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ 452181624Skmacy#define VMASST_TYPE_4gb_segments_notify 1 453181624Skmacy 454181624Skmacy/* 455181624Skmacy * x86 guests: support writes to bottom-level PTEs. 456181624Skmacy * NB1. Page-directory entries cannot be written. 457181624Skmacy * NB2. Guest must continue to remove all writable mappings of PTEs. 458181624Skmacy */ 459181624Skmacy#define VMASST_TYPE_writable_pagetables 2 460181624Skmacy 461181624Skmacy/* x86/PAE guests: support PDPTs above 4GB. */ 462181624Skmacy#define VMASST_TYPE_pae_extended_cr3 3 463181624Skmacy 464181624Skmacy#define MAX_VMASST_TYPE 3 465181624Skmacy 466181624Skmacy#ifndef __ASSEMBLY__ 467181624Skmacy 468181624Skmacytypedef uint16_t domid_t; 469181624Skmacy 470181624Skmacy/* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ 471181624Skmacy#define DOMID_FIRST_RESERVED (0x7FF0U) 472181624Skmacy 473181624Skmacy/* DOMID_SELF is used in certain contexts to refer to oneself. */ 474181624Skmacy#define DOMID_SELF (0x7FF0U) 475181624Skmacy 476181624Skmacy/* 477181624Skmacy * DOMID_IO is used to restrict page-table updates to mapping I/O memory. 478181624Skmacy * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO 479181624Skmacy * is useful to ensure that no mappings to the OS's own heap are accidentally 480181624Skmacy * installed. (e.g., in Linux this could cause havoc as reference counts 481181624Skmacy * aren't adjusted on the I/O-mapping code path). 482181624Skmacy * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can 483181624Skmacy * be specified by any calling domain. 484181624Skmacy */ 485181624Skmacy#define DOMID_IO (0x7FF1U) 486181624Skmacy 487181624Skmacy/* 488181624Skmacy * DOMID_XEN is used to allow privileged domains to map restricted parts of 489181624Skmacy * Xen's heap space (e.g., the machine_to_phys table). 490181624Skmacy * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if 491181624Skmacy * the caller is privileged. 492181624Skmacy */ 493181624Skmacy#define DOMID_XEN (0x7FF2U) 494181624Skmacy 495181624Skmacy/* 496251767Sgibbs * DOMID_COW is used as the owner of sharable pages */ 497251767Sgibbs#define DOMID_COW (0x7FF3U) 498251767Sgibbs 499251767Sgibbs/* DOMID_INVALID is used to identify pages with unknown owner. */ 500251767Sgibbs#define DOMID_INVALID (0x7FF4U) 501251767Sgibbs 502251767Sgibbs/* Idle domain. */ 503251767Sgibbs#define DOMID_IDLE (0x7FFFU) 504251767Sgibbs 505251767Sgibbs/* 506181624Skmacy * Send an array of these to HYPERVISOR_mmu_update(). 507181624Skmacy * NB. The fields are natural pointer/address size for this architecture. 508181624Skmacy */ 509181624Skmacystruct mmu_update { 510181624Skmacy uint64_t ptr; /* Machine address of PTE. */ 511181624Skmacy uint64_t val; /* New contents of PTE. */ 512181624Skmacy}; 513181624Skmacytypedef struct mmu_update mmu_update_t; 514181624SkmacyDEFINE_XEN_GUEST_HANDLE(mmu_update_t); 515181624Skmacy 516181624Skmacy/* 517181624Skmacy * Send an array of these to HYPERVISOR_multicall(). 518181624Skmacy * NB. The fields are natural register size for this architecture. 519181624Skmacy */ 520181624Skmacystruct multicall_entry { 521181624Skmacy unsigned long op, result; 522181624Skmacy unsigned long args[6]; 523181624Skmacy}; 524181624Skmacytypedef struct multicall_entry multicall_entry_t; 525181624SkmacyDEFINE_XEN_GUEST_HANDLE(multicall_entry_t); 526181624Skmacy 527181624Skmacy/* 528181624Skmacy * Event channel endpoints per domain: 529181624Skmacy * 1024 if a long is 32 bits; 4096 if a long is 64 bits. 530181624Skmacy */ 531181624Skmacy#define NR_EVENT_CHANNELS (sizeof(unsigned long) * sizeof(unsigned long) * 64) 532181624Skmacy 533181624Skmacystruct vcpu_time_info { 534181624Skmacy /* 535181624Skmacy * Updates to the following values are preceded and followed by an 536181624Skmacy * increment of 'version'. The guest can therefore detect updates by 537181624Skmacy * looking for changes to 'version'. If the least-significant bit of 538181624Skmacy * the version number is set then an update is in progress and the guest 539181624Skmacy * must wait to read a consistent set of values. 540181624Skmacy * The correct way to interact with the version number is similar to 541181624Skmacy * Linux's seqlock: see the implementations of read_seqbegin/read_seqretry. 542181624Skmacy */ 543181624Skmacy uint32_t version; 544181624Skmacy uint32_t pad0; 545181624Skmacy uint64_t tsc_timestamp; /* TSC at last update of time vals. */ 546181624Skmacy uint64_t system_time; /* Time, in nanosecs, since boot. */ 547181624Skmacy /* 548181624Skmacy * Current system time: 549181624Skmacy * system_time + 550181624Skmacy * ((((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul) >> 32) 551181624Skmacy * CPU frequency (Hz): 552181624Skmacy * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift 553181624Skmacy */ 554181624Skmacy uint32_t tsc_to_system_mul; 555181624Skmacy int8_t tsc_shift; 556181624Skmacy int8_t pad1[3]; 557181624Skmacy}; /* 32 bytes */ 558181624Skmacytypedef struct vcpu_time_info vcpu_time_info_t; 559181624Skmacy 560181624Skmacystruct vcpu_info { 561181624Skmacy /* 562181624Skmacy * 'evtchn_upcall_pending' is written non-zero by Xen to indicate 563181624Skmacy * a pending notification for a particular VCPU. It is then cleared 564181624Skmacy * by the guest OS /before/ checking for pending work, thus avoiding 565181624Skmacy * a set-and-check race. Note that the mask is only accessed by Xen 566181624Skmacy * on the CPU that is currently hosting the VCPU. This means that the 567181624Skmacy * pending and mask flags can be updated by the guest without special 568181624Skmacy * synchronisation (i.e., no need for the x86 LOCK prefix). 569181624Skmacy * This may seem suboptimal because if the pending flag is set by 570181624Skmacy * a different CPU then an IPI may be scheduled even when the mask 571181624Skmacy * is set. However, note: 572181624Skmacy * 1. The task of 'interrupt holdoff' is covered by the per-event- 573181624Skmacy * channel mask bits. A 'noisy' event that is continually being 574181624Skmacy * triggered can be masked at source at this very precise 575181624Skmacy * granularity. 576181624Skmacy * 2. The main purpose of the per-VCPU mask is therefore to restrict 577181624Skmacy * reentrant execution: whether for concurrency control, or to 578181624Skmacy * prevent unbounded stack usage. Whatever the purpose, we expect 579181624Skmacy * that the mask will be asserted only for short periods at a time, 580181624Skmacy * and so the likelihood of a 'spurious' IPI is suitably small. 581181624Skmacy * The mask is read before making an event upcall to the guest: a 582181624Skmacy * non-zero mask therefore guarantees that the VCPU will not receive 583181624Skmacy * an upcall activation. The mask is cleared when the VCPU requests 584181624Skmacy * to block: this avoids wakeup-waiting races. 585181624Skmacy */ 586181624Skmacy uint8_t evtchn_upcall_pending; 587181624Skmacy uint8_t evtchn_upcall_mask; 588181624Skmacy unsigned long evtchn_pending_sel; 589181624Skmacy struct arch_vcpu_info arch; 590181624Skmacy struct vcpu_time_info time; 591181624Skmacy}; /* 64 bytes (x86) */ 592181624Skmacy#ifndef __XEN__ 593181624Skmacytypedef struct vcpu_info vcpu_info_t; 594181624Skmacy#endif 595181624Skmacy 596181624Skmacy/* 597181624Skmacy * Xen/kernel shared data -- pointer provided in start_info. 598181624Skmacy * 599181624Skmacy * This structure is defined to be both smaller than a page, and the 600181624Skmacy * only data on the shared page, but may vary in actual size even within 601181624Skmacy * compatible Xen versions; guests should not rely on the size 602181624Skmacy * of this structure remaining constant. 603181624Skmacy */ 604181624Skmacystruct shared_info { 605251767Sgibbs struct vcpu_info vcpu_info[XEN_LEGACY_MAX_VCPUS]; 606181624Skmacy 607181624Skmacy /* 608181624Skmacy * A domain can create "event channels" on which it can send and receive 609181624Skmacy * asynchronous event notifications. There are three classes of event that 610181624Skmacy * are delivered by this mechanism: 611181624Skmacy * 1. Bi-directional inter- and intra-domain connections. Domains must 612181624Skmacy * arrange out-of-band to set up a connection (usually by allocating 613181624Skmacy * an unbound 'listener' port and avertising that via a storage service 614181624Skmacy * such as xenstore). 615181624Skmacy * 2. Physical interrupts. A domain with suitable hardware-access 616181624Skmacy * privileges can bind an event-channel port to a physical interrupt 617181624Skmacy * source. 618181624Skmacy * 3. Virtual interrupts ('events'). A domain can bind an event-channel 619181624Skmacy * port to a virtual interrupt source, such as the virtual-timer 620181624Skmacy * device or the emergency console. 621181624Skmacy * 622181624Skmacy * Event channels are addressed by a "port index". Each channel is 623181624Skmacy * associated with two bits of information: 624181624Skmacy * 1. PENDING -- notifies the domain that there is a pending notification 625181624Skmacy * to be processed. This bit is cleared by the guest. 626181624Skmacy * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING 627181624Skmacy * will cause an asynchronous upcall to be scheduled. This bit is only 628181624Skmacy * updated by the guest. It is read-only within Xen. If a channel 629181624Skmacy * becomes pending while the channel is masked then the 'edge' is lost 630181624Skmacy * (i.e., when the channel is unmasked, the guest must manually handle 631181624Skmacy * pending notifications as no upcall will be scheduled by Xen). 632181624Skmacy * 633181624Skmacy * To expedite scanning of pending notifications, any 0->1 pending 634181624Skmacy * transition on an unmasked channel causes a corresponding bit in a 635181624Skmacy * per-vcpu selector word to be set. Each bit in the selector covers a 636181624Skmacy * 'C long' in the PENDING bitfield array. 637181624Skmacy */ 638181624Skmacy unsigned long evtchn_pending[sizeof(unsigned long) * 8]; 639181624Skmacy unsigned long evtchn_mask[sizeof(unsigned long) * 8]; 640181624Skmacy 641181624Skmacy /* 642181624Skmacy * Wallclock time: updated only by control software. Guests should base 643181624Skmacy * their gettimeofday() syscall on this wallclock-base value. 644181624Skmacy */ 645181624Skmacy uint32_t wc_version; /* Version counter: see vcpu_time_info_t. */ 646181624Skmacy uint32_t wc_sec; /* Secs 00:00:00 UTC, Jan 1, 1970. */ 647181624Skmacy uint32_t wc_nsec; /* Nsecs 00:00:00 UTC, Jan 1, 1970. */ 648181624Skmacy 649181624Skmacy struct arch_shared_info arch; 650181624Skmacy 651181624Skmacy}; 652181624Skmacy#ifndef __XEN__ 653181624Skmacytypedef struct shared_info shared_info_t; 654181624Skmacy#endif 655181624Skmacy 656181624Skmacy/* 657181624Skmacy * Start-of-day memory layout: 658181624Skmacy * 1. The domain is started within contiguous virtual-memory region. 659181624Skmacy * 2. The contiguous region ends on an aligned 4MB boundary. 660181624Skmacy * 3. This the order of bootstrap elements in the initial virtual region: 661181624Skmacy * a. relocated kernel image 662181624Skmacy * b. initial ram disk [mod_start, mod_len] 663181624Skmacy * c. list of allocated page frames [mfn_list, nr_pages] 664251767Sgibbs * (unless relocated due to XEN_ELFNOTE_INIT_P2M) 665181624Skmacy * d. start_info_t structure [register ESI (x86)] 666181624Skmacy * e. bootstrap page tables [pt_base, CR3 (x86)] 667181624Skmacy * f. bootstrap stack [register ESP (x86)] 668181624Skmacy * 4. Bootstrap elements are packed together, but each is 4kB-aligned. 669181624Skmacy * 5. The initial ram disk may be omitted. 670181624Skmacy * 6. The list of page frames forms a contiguous 'pseudo-physical' memory 671181624Skmacy * layout for the domain. In particular, the bootstrap virtual-memory 672181624Skmacy * region is a 1:1 mapping to the first section of the pseudo-physical map. 673181624Skmacy * 7. All bootstrap elements are mapped read-writable for the guest OS. The 674181624Skmacy * only exception is the bootstrap page table, which is mapped read-only. 675181624Skmacy * 8. There is guaranteed to be at least 512kB padding after the final 676181624Skmacy * bootstrap element. If necessary, the bootstrap virtual region is 677181624Skmacy * extended by an extra 4MB to ensure this. 678181624Skmacy */ 679181624Skmacy 680181624Skmacy#define MAX_GUEST_CMDLINE 1024 681181624Skmacystruct start_info { 682181624Skmacy /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ 683181624Skmacy char magic[32]; /* "xen-<version>-<platform>". */ 684181624Skmacy unsigned long nr_pages; /* Total pages allocated to this domain. */ 685181624Skmacy unsigned long shared_info; /* MACHINE address of shared info struct. */ 686181624Skmacy uint32_t flags; /* SIF_xxx flags. */ 687181624Skmacy xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ 688181624Skmacy uint32_t store_evtchn; /* Event channel for store communication. */ 689181624Skmacy union { 690181624Skmacy struct { 691181624Skmacy xen_pfn_t mfn; /* MACHINE page number of console page. */ 692181624Skmacy uint32_t evtchn; /* Event channel for console page. */ 693181624Skmacy } domU; 694181624Skmacy struct { 695181624Skmacy uint32_t info_off; /* Offset of console_info struct. */ 696181624Skmacy uint32_t info_size; /* Size of console_info struct from start.*/ 697181624Skmacy } dom0; 698181624Skmacy } console; 699181624Skmacy /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ 700181624Skmacy unsigned long pt_base; /* VIRTUAL address of page directory. */ 701181624Skmacy unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ 702181624Skmacy unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ 703251767Sgibbs unsigned long mod_start; /* VIRTUAL address of pre-loaded module */ 704251767Sgibbs /* (PFN of pre-loaded module if */ 705251767Sgibbs /* SIF_MOD_START_PFN set in flags). */ 706181624Skmacy unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ 707181624Skmacy int8_t cmd_line[MAX_GUEST_CMDLINE]; 708251767Sgibbs /* The pfn range here covers both page table and p->m table frames. */ 709251767Sgibbs unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ 710251767Sgibbs unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ 711181624Skmacy}; 712181624Skmacytypedef struct start_info start_info_t; 713181624Skmacy 714181624Skmacy/* New console union for dom0 introduced in 0x00030203. */ 715181624Skmacy#if __XEN_INTERFACE_VERSION__ < 0x00030203 716181624Skmacy#define console_mfn console.domU.mfn 717181624Skmacy#define console_evtchn console.domU.evtchn 718181624Skmacy#endif 719181624Skmacy 720181624Skmacy/* These flags are passed in the 'flags' field of start_info_t. */ 721181624Skmacy#define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ 722181624Skmacy#define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ 723251767Sgibbs#define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ 724251767Sgibbs#define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ 725183375Skmacy#define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ 726181624Skmacy 727251767Sgibbs/* 728251767Sgibbs * A multiboot module is a package containing modules very similar to a 729251767Sgibbs * multiboot module array. The only differences are: 730251767Sgibbs * - the array of module descriptors is by convention simply at the beginning 731251767Sgibbs * of the multiboot module, 732251767Sgibbs * - addresses in the module descriptors are based on the beginning of the 733251767Sgibbs * multiboot module, 734251767Sgibbs * - the number of modules is determined by a termination descriptor that has 735251767Sgibbs * mod_start == 0. 736251767Sgibbs * 737251767Sgibbs * This permits to both build it statically and reference it in a configuration 738251767Sgibbs * file, and let the PV guest easily rebase the addresses to virtual addresses 739251767Sgibbs * and at the same time count the number of modules. 740251767Sgibbs */ 741251767Sgibbsstruct xen_multiboot_mod_list 742251767Sgibbs{ 743251767Sgibbs /* Address of first byte of the module */ 744251767Sgibbs uint32_t mod_start; 745251767Sgibbs /* Address of last byte of the module (inclusive) */ 746251767Sgibbs uint32_t mod_end; 747251767Sgibbs /* Address of zero-terminated command line */ 748251767Sgibbs uint32_t cmdline; 749251767Sgibbs /* Unused, must be zero */ 750251767Sgibbs uint32_t pad; 751251767Sgibbs}; 752251767Sgibbs 753181624Skmacytypedef struct dom0_vga_console_info { 754181624Skmacy uint8_t video_type; /* DOM0_VGA_CONSOLE_??? */ 755181624Skmacy#define XEN_VGATYPE_TEXT_MODE_3 0x03 756181624Skmacy#define XEN_VGATYPE_VESA_LFB 0x23 757251767Sgibbs#define XEN_VGATYPE_EFI_LFB 0x70 758181624Skmacy 759181624Skmacy union { 760181624Skmacy struct { 761181624Skmacy /* Font height, in pixels. */ 762181624Skmacy uint16_t font_height; 763181624Skmacy /* Cursor location (column, row). */ 764181624Skmacy uint16_t cursor_x, cursor_y; 765181624Skmacy /* Number of rows and columns (dimensions in characters). */ 766181624Skmacy uint16_t rows, columns; 767181624Skmacy } text_mode_3; 768181624Skmacy 769181624Skmacy struct { 770181624Skmacy /* Width and height, in pixels. */ 771181624Skmacy uint16_t width, height; 772181624Skmacy /* Bytes per scan line. */ 773181624Skmacy uint16_t bytes_per_line; 774181624Skmacy /* Bits per pixel. */ 775181624Skmacy uint16_t bits_per_pixel; 776181624Skmacy /* LFB physical address, and size (in units of 64kB). */ 777181624Skmacy uint32_t lfb_base; 778181624Skmacy uint32_t lfb_size; 779181624Skmacy /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ 780181624Skmacy uint8_t red_pos, red_size; 781181624Skmacy uint8_t green_pos, green_size; 782181624Skmacy uint8_t blue_pos, blue_size; 783181624Skmacy uint8_t rsvd_pos, rsvd_size; 784183375Skmacy#if __XEN_INTERFACE_VERSION__ >= 0x00030206 785183375Skmacy /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ 786183375Skmacy uint32_t gbl_caps; 787183375Skmacy /* Mode attributes (offset 0x0, VESA command 0x4f01). */ 788183375Skmacy uint16_t mode_attrs; 789183375Skmacy#endif 790181624Skmacy } vesa_lfb; 791181624Skmacy } u; 792181624Skmacy} dom0_vga_console_info_t; 793181624Skmacy#define xen_vga_console_info dom0_vga_console_info 794181624Skmacy#define xen_vga_console_info_t dom0_vga_console_info_t 795181624Skmacy 796181624Skmacytypedef uint8_t xen_domain_handle_t[16]; 797181624Skmacy 798181624Skmacy/* Turn a plain number into a C unsigned long constant. */ 799181624Skmacy#define __mk_unsigned_long(x) x ## UL 800181624Skmacy#define mk_unsigned_long(x) __mk_unsigned_long(x) 801181624Skmacy 802183375Skmacy__DEFINE_XEN_GUEST_HANDLE(uint8, uint8_t); 803183375Skmacy__DEFINE_XEN_GUEST_HANDLE(uint16, uint16_t); 804183375Skmacy__DEFINE_XEN_GUEST_HANDLE(uint32, uint32_t); 805183375Skmacy__DEFINE_XEN_GUEST_HANDLE(uint64, uint64_t); 806181624Skmacy 807181624Skmacy#else /* __ASSEMBLY__ */ 808181624Skmacy 809181624Skmacy/* In assembly code we cannot use C numeric constant suffixes. */ 810181624Skmacy#define mk_unsigned_long(x) x 811181624Skmacy 812181624Skmacy#endif /* !__ASSEMBLY__ */ 813181624Skmacy 814181624Skmacy/* Default definitions for macros used by domctl/sysctl. */ 815181624Skmacy#if defined(__XEN__) || defined(__XEN_TOOLS__) 816251767Sgibbs 817181624Skmacy#ifndef uint64_aligned_t 818181624Skmacy#define uint64_aligned_t uint64_t 819181624Skmacy#endif 820181624Skmacy#ifndef XEN_GUEST_HANDLE_64 821181624Skmacy#define XEN_GUEST_HANDLE_64(name) XEN_GUEST_HANDLE(name) 822181624Skmacy#endif 823251767Sgibbs 824251767Sgibbs#ifndef __ASSEMBLY__ 825251767Sgibbsstruct xenctl_cpumap { 826251767Sgibbs XEN_GUEST_HANDLE_64(uint8) bitmap; 827251767Sgibbs uint32_t nr_cpus; 828251767Sgibbs}; 829181624Skmacy#endif 830181624Skmacy 831251767Sgibbs#endif /* defined(__XEN__) || defined(__XEN_TOOLS__) */ 832251767Sgibbs 833181624Skmacy#endif /* __XEN_PUBLIC_XEN_H__ */ 834181624Skmacy 835181624Skmacy/* 836181624Skmacy * Local variables: 837181624Skmacy * mode: C 838181624Skmacy * c-set-style: "BSD" 839181624Skmacy * c-basic-offset: 4 840181624Skmacy * tab-width: 4 841181624Skmacy * indent-tabs-mode: nil 842181624Skmacy * End: 843181624Skmacy */ 844