local_apic.c revision 172144
1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/i386/i386/local_apic.c 172144 2007-09-11 22:54:09Z attilio $"); 36 37#include "opt_hwpmc_hooks.h" 38 39#include "opt_ddb.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/mutex.h> 47#include <sys/pcpu.h> 48#include <sys/smp.h> 49 50#include <vm/vm.h> 51#include <vm/pmap.h> 52 53#include <machine/apicreg.h> 54#include <machine/cpu.h> 55#include <machine/cputypes.h> 56#include <machine/frame.h> 57#include <machine/intr_machdep.h> 58#include <machine/apicvar.h> 59#include <machine/md_var.h> 60#include <machine/smp.h> 61#include <machine/specialreg.h> 62 63#ifdef DDB 64#include <sys/interrupt.h> 65#include <ddb/ddb.h> 66#endif 67 68/* Sanity checks on IDT vectors. */ 69CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 70CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 71CTASSERT(APIC_LOCAL_INTS == 240); 72CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 73 74#define LAPIC_TIMER_HZ_DIVIDER 2 75#define LAPIC_TIMER_STATHZ_DIVIDER 15 76#define LAPIC_TIMER_PROFHZ_DIVIDER 3 77 78/* Magic IRQ values for the timer and syscalls. */ 79#define IRQ_TIMER (NUM_IO_INTS + 1) 80#define IRQ_SYSCALL (NUM_IO_INTS + 2) 81 82/* 83 * Support for local APICs. Local APICs manage interrupts on each 84 * individual processor as opposed to I/O APICs which receive interrupts 85 * from I/O devices and then forward them on to the local APICs. 86 * 87 * Local APICs can also send interrupts to each other thus providing the 88 * mechanism for IPIs. 89 */ 90 91struct lvt { 92 u_int lvt_edgetrigger:1; 93 u_int lvt_activehi:1; 94 u_int lvt_masked:1; 95 u_int lvt_active:1; 96 u_int lvt_mode:16; 97 u_int lvt_vector:8; 98}; 99 100struct lapic { 101 struct lvt la_lvts[LVT_MAX + 1]; 102 u_int la_id:8; 103 u_int la_cluster:4; 104 u_int la_cluster_id:2; 105 u_int la_present:1; 106 u_long *la_timer_count; 107 u_long la_hard_ticks; 108 u_long la_stat_ticks; 109 u_long la_prof_ticks; 110} static lapics[MAX_APIC_ID + 1]; 111 112/* XXX: should thermal be an NMI? */ 113 114/* Global defaults for local APIC LVT entries. */ 115static struct lvt lvts[LVT_MAX + 1] = { 116 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 117 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 118 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 119 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 120 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 122}; 123 124static inthand_t *ioint_handlers[] = { 125 NULL, /* 0 - 31 */ 126 IDTVEC(apic_isr1), /* 32 - 63 */ 127 IDTVEC(apic_isr2), /* 64 - 95 */ 128 IDTVEC(apic_isr3), /* 96 - 127 */ 129 IDTVEC(apic_isr4), /* 128 - 159 */ 130 IDTVEC(apic_isr5), /* 160 - 191 */ 131 IDTVEC(apic_isr6), /* 192 - 223 */ 132 IDTVEC(apic_isr7), /* 224 - 255 */ 133}; 134 135/* Include IDT_SYSCALL to make indexing easier. */ 136static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 137 138static u_int32_t lapic_timer_divisors[] = { 139 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 140 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 141}; 142 143extern inthand_t IDTVEC(rsvd); 144 145volatile lapic_t *lapic; 146vm_paddr_t lapic_paddr; 147static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 148 149static void lapic_enable(void); 150static void lapic_resume(struct pic *pic); 151static void lapic_timer_enable_intr(void); 152static void lapic_timer_oneshot(u_int count); 153static void lapic_timer_periodic(u_int count); 154static void lapic_timer_set_divisor(u_int divisor); 155static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 156 157struct pic lapic_pic = { .pic_resume = lapic_resume }; 158 159static uint32_t 160lvt_mode(struct lapic *la, u_int pin, uint32_t value) 161{ 162 struct lvt *lvt; 163 164 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 165 if (la->la_lvts[pin].lvt_active) 166 lvt = &la->la_lvts[pin]; 167 else 168 lvt = &lvts[pin]; 169 170 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 171 APIC_LVT_VECTOR); 172 if (lvt->lvt_edgetrigger == 0) 173 value |= APIC_LVT_TM; 174 if (lvt->lvt_activehi == 0) 175 value |= APIC_LVT_IIPP_INTALO; 176 if (lvt->lvt_masked) 177 value |= APIC_LVT_M; 178 value |= lvt->lvt_mode; 179 switch (lvt->lvt_mode) { 180 case APIC_LVT_DM_NMI: 181 case APIC_LVT_DM_SMI: 182 case APIC_LVT_DM_INIT: 183 case APIC_LVT_DM_EXTINT: 184 if (!lvt->lvt_edgetrigger) { 185 printf("lapic%u: Forcing LINT%u to edge trigger\n", 186 la->la_id, pin); 187 value |= APIC_LVT_TM; 188 } 189 /* Use a vector of 0. */ 190 break; 191 case APIC_LVT_DM_FIXED: 192 value |= lvt->lvt_vector; 193 break; 194 default: 195 panic("bad APIC LVT delivery mode: %#x\n", value); 196 } 197 return (value); 198} 199 200/* 201 * Map the local APIC and setup necessary interrupt vectors. 202 */ 203void 204lapic_init(vm_paddr_t addr) 205{ 206 207 /* Map the local APIC and setup the spurious interrupt handler. */ 208 KASSERT(trunc_page(addr) == addr, 209 ("local APIC not aligned on a page boundary")); 210 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 211 lapic_paddr = addr; 212 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 213 GSEL(GCODE_SEL, SEL_KPL)); 214 215 /* Perform basic initialization of the BSP's local APIC. */ 216 lapic_enable(); 217 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 218 219 /* Set BSP's per-CPU local APIC ID. */ 220 PCPU_SET(apic_id, lapic_id()); 221 222 /* Local APIC timer interrupt. */ 223 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 224 GSEL(GCODE_SEL, SEL_KPL)); 225 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 226 227 /* XXX: error/thermal interrupts */ 228} 229 230/* 231 * Create a local APIC instance. 232 */ 233void 234lapic_create(u_int apic_id, int boot_cpu) 235{ 236 int i; 237 238 if (apic_id > MAX_APIC_ID) { 239 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 240 if (boot_cpu) 241 panic("Can't ignore BSP"); 242 return; 243 } 244 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 245 apic_id)); 246 247 /* 248 * Assume no local LVT overrides and a cluster of 0 and 249 * intra-cluster ID of 0. 250 */ 251 lapics[apic_id].la_present = 1; 252 lapics[apic_id].la_id = apic_id; 253 for (i = 0; i < LVT_MAX; i++) { 254 lapics[apic_id].la_lvts[i] = lvts[i]; 255 lapics[apic_id].la_lvts[i].lvt_active = 0; 256 } 257 258#ifdef SMP 259 cpu_add(apic_id, boot_cpu); 260#endif 261} 262 263/* 264 * Dump contents of local APIC registers 265 */ 266void 267lapic_dump(const char* str) 268{ 269 270 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 271 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 272 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 273 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 274 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 275 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 276 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 277 lapic->lvt_pcint); 278} 279 280void 281lapic_setup(int boot) 282{ 283 struct lapic *la; 284 u_int32_t maxlvt; 285 register_t eflags; 286 char buf[MAXCOMLEN + 1]; 287 288 la = &lapics[lapic_id()]; 289 KASSERT(la->la_present, ("missing APIC structure")); 290 eflags = intr_disable(); 291 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 292 293 /* Initialize the TPR to allow all interrupts. */ 294 lapic_set_tpr(0); 295 296 /* Setup spurious vector and enable the local APIC. */ 297 lapic_enable(); 298 299 /* Program LINT[01] LVT entries. */ 300 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 301 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 302#ifdef HWPMC_HOOKS 303 /* Program the PMC LVT entry if present. */ 304 if (maxlvt >= LVT_PMC) 305 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 306#endif 307 308 /* Program timer LVT and setup handler. */ 309 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 310 if (boot) { 311 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 312 intrcnt_add(buf, &la->la_timer_count); 313 } 314 315 /* We don't setup the timer during boot on the BSP until later. */ 316 if (!(boot && PCPU_GET(cpuid) == 0)) { 317 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 318 lapic_id())); 319 lapic_timer_set_divisor(lapic_timer_divisor); 320 lapic_timer_periodic(lapic_timer_period); 321 lapic_timer_enable_intr(); 322 } 323 324 /* XXX: Error and thermal LVTs */ 325 326 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 327 /* 328 * Detect the presence of C1E capability mostly on latest 329 * dual-cores (or future) k8 family. This feature renders 330 * the local APIC timer dead, so we disable it by reading 331 * the Interrupt Pending Message register and clearing both 332 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 333 * 334 * Reference: 335 * "BIOS and Kernel Developer's Guide for AMD NPT 336 * Family 0Fh Processors" 337 * #32559 revision 3.00 338 */ 339 if ((cpu_id & 0x00000f00) == 0x00000f00 && 340 (cpu_id & 0x0fff0000) >= 0x00040000) { 341 uint64_t msr; 342 343 msr = rdmsr(0xc0010055); 344 if (msr & 0x18000000) 345 wrmsr(0xc0010055, msr & ~0x18000000ULL); 346 } 347 } 348 349 intr_restore(eflags); 350} 351 352/* 353 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 354 * that it can drive hardclock, statclock, and profclock. This function 355 * returns true if it is able to use the local APIC timer to drive the 356 * clocks and false if it is not able. 357 */ 358int 359lapic_setup_clock(void) 360{ 361 u_long value; 362 363 /* Can't drive the timer without a local APIC. */ 364 if (lapic == NULL) 365 return (0); 366 367 /* Start off with a divisor of 2 (power on reset default). */ 368 lapic_timer_divisor = 2; 369 370 /* Try to calibrate the local APIC timer. */ 371 do { 372 lapic_timer_set_divisor(lapic_timer_divisor); 373 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 374 DELAY(2000000); 375 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 376 if (value != APIC_TIMER_MAX_COUNT) 377 break; 378 lapic_timer_divisor <<= 1; 379 } while (lapic_timer_divisor <= 128); 380 if (lapic_timer_divisor > 128) 381 panic("lapic: Divisor too big"); 382 value /= 2; 383 if (bootverbose) 384 printf("lapic: Divisor %lu, Frequency %lu hz\n", 385 lapic_timer_divisor, value); 386 387 /* 388 * We will drive the timer at a small multiple of hz and drive 389 * both of the other timers with similarly small but relatively 390 * prime divisors. 391 */ 392 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 393 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 394 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 395 lapic_timer_period = value / lapic_timer_hz; 396 397 /* 398 * Start up the timer on the BSP. The APs will kick off their 399 * timer during lapic_setup(). 400 */ 401 lapic_timer_periodic(lapic_timer_period); 402 lapic_timer_enable_intr(); 403 return (1); 404} 405 406void 407lapic_disable(void) 408{ 409 uint32_t value; 410 411 /* Software disable the local APIC. */ 412 value = lapic->svr; 413 value &= ~APIC_SVR_SWEN; 414 lapic->svr = value; 415} 416 417static void 418lapic_enable(void) 419{ 420 u_int32_t value; 421 422 /* Program the spurious vector to enable the local APIC. */ 423 value = lapic->svr; 424 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 425 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 426 lapic->svr = value; 427} 428 429/* Reset the local APIC on the BSP during resume. */ 430static void 431lapic_resume(struct pic *pic) 432{ 433 434 lapic_setup(0); 435} 436 437int 438lapic_id(void) 439{ 440 441 KASSERT(lapic != NULL, ("local APIC is not mapped")); 442 return (lapic->id >> APIC_ID_SHIFT); 443} 444 445int 446lapic_intr_pending(u_int vector) 447{ 448 volatile u_int32_t *irr; 449 450 /* 451 * The IRR registers are an array of 128-bit registers each of 452 * which only describes 32 interrupts in the low 32 bits.. Thus, 453 * we divide the vector by 32 to get the 128-bit index. We then 454 * multiply that index by 4 to get the equivalent index from 455 * treating the IRR as an array of 32-bit registers. Finally, we 456 * modulus the vector by 32 to determine the individual bit to 457 * test. 458 */ 459 irr = &lapic->irr0; 460 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 461} 462 463void 464lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 465{ 466 struct lapic *la; 467 468 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 469 __func__, apic_id)); 470 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 471 __func__, cluster)); 472 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 473 ("%s: intra cluster id %u too big", __func__, cluster_id)); 474 la = &lapics[apic_id]; 475 la->la_cluster = cluster; 476 la->la_cluster_id = cluster_id; 477} 478 479int 480lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 481{ 482 483 if (pin > LVT_MAX) 484 return (EINVAL); 485 if (apic_id == APIC_ID_ALL) { 486 lvts[pin].lvt_masked = masked; 487 if (bootverbose) 488 printf("lapic:"); 489 } else { 490 KASSERT(lapics[apic_id].la_present, 491 ("%s: missing APIC %u", __func__, apic_id)); 492 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 493 lapics[apic_id].la_lvts[pin].lvt_active = 1; 494 if (bootverbose) 495 printf("lapic%u:", apic_id); 496 } 497 if (bootverbose) 498 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 499 return (0); 500} 501 502int 503lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 504{ 505 struct lvt *lvt; 506 507 if (pin > LVT_MAX) 508 return (EINVAL); 509 if (apic_id == APIC_ID_ALL) { 510 lvt = &lvts[pin]; 511 if (bootverbose) 512 printf("lapic:"); 513 } else { 514 KASSERT(lapics[apic_id].la_present, 515 ("%s: missing APIC %u", __func__, apic_id)); 516 lvt = &lapics[apic_id].la_lvts[pin]; 517 lvt->lvt_active = 1; 518 if (bootverbose) 519 printf("lapic%u:", apic_id); 520 } 521 lvt->lvt_mode = mode; 522 switch (mode) { 523 case APIC_LVT_DM_NMI: 524 case APIC_LVT_DM_SMI: 525 case APIC_LVT_DM_INIT: 526 case APIC_LVT_DM_EXTINT: 527 lvt->lvt_edgetrigger = 1; 528 lvt->lvt_activehi = 1; 529 if (mode == APIC_LVT_DM_EXTINT) 530 lvt->lvt_masked = 1; 531 else 532 lvt->lvt_masked = 0; 533 break; 534 default: 535 panic("Unsupported delivery mode: 0x%x\n", mode); 536 } 537 if (bootverbose) { 538 printf(" Routing "); 539 switch (mode) { 540 case APIC_LVT_DM_NMI: 541 printf("NMI"); 542 break; 543 case APIC_LVT_DM_SMI: 544 printf("SMI"); 545 break; 546 case APIC_LVT_DM_INIT: 547 printf("INIT"); 548 break; 549 case APIC_LVT_DM_EXTINT: 550 printf("ExtINT"); 551 break; 552 } 553 printf(" -> LINT%u\n", pin); 554 } 555 return (0); 556} 557 558int 559lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 560{ 561 562 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 563 return (EINVAL); 564 if (apic_id == APIC_ID_ALL) { 565 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 566 if (bootverbose) 567 printf("lapic:"); 568 } else { 569 KASSERT(lapics[apic_id].la_present, 570 ("%s: missing APIC %u", __func__, apic_id)); 571 lapics[apic_id].la_lvts[pin].lvt_active = 1; 572 lapics[apic_id].la_lvts[pin].lvt_activehi = 573 (pol == INTR_POLARITY_HIGH); 574 if (bootverbose) 575 printf("lapic%u:", apic_id); 576 } 577 if (bootverbose) 578 printf(" LINT%u polarity: %s\n", pin, 579 pol == INTR_POLARITY_HIGH ? "high" : "low"); 580 return (0); 581} 582 583int 584lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 585{ 586 587 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 588 return (EINVAL); 589 if (apic_id == APIC_ID_ALL) { 590 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 591 if (bootverbose) 592 printf("lapic:"); 593 } else { 594 KASSERT(lapics[apic_id].la_present, 595 ("%s: missing APIC %u", __func__, apic_id)); 596 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 597 (trigger == INTR_TRIGGER_EDGE); 598 lapics[apic_id].la_lvts[pin].lvt_active = 1; 599 if (bootverbose) 600 printf("lapic%u:", apic_id); 601 } 602 if (bootverbose) 603 printf(" LINT%u trigger: %s\n", pin, 604 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 605 return (0); 606} 607 608/* 609 * Adjust the TPR of the current CPU so that it blocks all interrupts below 610 * the passed in vector. 611 */ 612void 613lapic_set_tpr(u_int vector) 614{ 615#ifdef CHEAP_TPR 616 lapic->tpr = vector; 617#else 618 u_int32_t tpr; 619 620 tpr = lapic->tpr & ~APIC_TPR_PRIO; 621 tpr |= vector; 622 lapic->tpr = tpr; 623#endif 624} 625 626void 627lapic_eoi(void) 628{ 629 630 lapic->eoi = 0; 631} 632 633void 634lapic_handle_intr(int vector, struct trapframe *frame) 635{ 636 struct intsrc *isrc; 637 638 if (vector == -1) 639 panic("Couldn't get vector from ISR!"); 640 isrc = intr_lookup_source(apic_idt_to_irq(vector)); 641 intr_execute_handlers(isrc, frame); 642} 643 644void 645lapic_handle_timer(struct trapframe *frame) 646{ 647 struct lapic *la; 648 649 /* Send EOI first thing. */ 650 lapic_eoi(); 651 652#if defined(SMP) && !defined(SCHED_ULE) 653 /* 654 * Don't do any accounting for the disabled HTT cores, since it 655 * will provide misleading numbers for the userland. 656 * 657 * No locking is necessary here, since even if we loose the race 658 * when hlt_cpus_mask changes it is not a big deal, really. 659 * 660 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 661 * and unlike other schedulers it actually schedules threads to 662 * those CPUs. 663 */ 664 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 665 return; 666#endif 667 668 /* Look up our local APIC structure for the tick counters. */ 669 la = &lapics[PCPU_GET(apic_id)]; 670 (*la->la_timer_count)++; 671 critical_enter(); 672 673 /* Fire hardclock at hz. */ 674 la->la_hard_ticks += hz; 675 if (la->la_hard_ticks >= lapic_timer_hz) { 676 la->la_hard_ticks -= lapic_timer_hz; 677 if (PCPU_GET(cpuid) == 0) 678 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 679 else 680 hardclock_cpu(TRAPF_USERMODE(frame)); 681 } 682 683 /* Fire statclock at stathz. */ 684 la->la_stat_ticks += stathz; 685 if (la->la_stat_ticks >= lapic_timer_hz) { 686 la->la_stat_ticks -= lapic_timer_hz; 687 statclock(TRAPF_USERMODE(frame)); 688 } 689 690 /* Fire profclock at profhz, but only when needed. */ 691 la->la_prof_ticks += profhz; 692 if (la->la_prof_ticks >= lapic_timer_hz) { 693 la->la_prof_ticks -= lapic_timer_hz; 694 if (profprocs != 0) 695 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 696 } 697 critical_exit(); 698} 699 700static void 701lapic_timer_set_divisor(u_int divisor) 702{ 703 704 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 705 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 706 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 707 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 708} 709 710static void 711lapic_timer_oneshot(u_int count) 712{ 713 u_int32_t value; 714 715 value = lapic->lvt_timer; 716 value &= ~APIC_LVTT_TM; 717 value |= APIC_LVTT_TM_ONE_SHOT; 718 lapic->lvt_timer = value; 719 lapic->icr_timer = count; 720} 721 722static void 723lapic_timer_periodic(u_int count) 724{ 725 u_int32_t value; 726 727 value = lapic->lvt_timer; 728 value &= ~APIC_LVTT_TM; 729 value |= APIC_LVTT_TM_PERIODIC; 730 lapic->lvt_timer = value; 731 lapic->icr_timer = count; 732} 733 734static void 735lapic_timer_enable_intr(void) 736{ 737 u_int32_t value; 738 739 value = lapic->lvt_timer; 740 value &= ~APIC_LVT_M; 741 lapic->lvt_timer = value; 742} 743 744/* Request a free IDT vector to be used by the specified IRQ. */ 745u_int 746apic_alloc_vector(u_int irq) 747{ 748 u_int vector; 749 750 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 751 752 /* 753 * Search for a free vector. Currently we just use a very simple 754 * algorithm to find the first free vector. 755 */ 756 mtx_lock_spin(&icu_lock); 757 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 758 if (ioint_irqs[vector] != 0) 759 continue; 760 ioint_irqs[vector] = irq; 761 mtx_unlock_spin(&icu_lock); 762 return (vector + APIC_IO_INTS); 763 } 764 mtx_unlock_spin(&icu_lock); 765 panic("Couldn't find an APIC vector for IRQ %u", irq); 766} 767 768/* 769 * Request 'count' free contiguous IDT vectors to be used by 'count' 770 * IRQs. 'count' must be a power of two and the vectors will be 771 * aligned on a boundary of 'align'. If the request cannot be 772 * satisfied, 0 is returned. 773 */ 774u_int 775apic_alloc_vectors(u_int *irqs, u_int count, u_int align) 776{ 777 u_int first, run, vector; 778 779 KASSERT(powerof2(count), ("bad count")); 780 KASSERT(powerof2(align), ("bad align")); 781 KASSERT(align >= count, ("align < count")); 782#ifdef INVARIANTS 783 for (run = 0; run < count; run++) 784 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 785 irqs[run], run)); 786#endif 787 788 /* 789 * Search for 'count' free vectors. As with apic_alloc_vector(), 790 * this just uses a simple first fit algorithm. 791 */ 792 run = 0; 793 first = 0; 794 mtx_lock_spin(&icu_lock); 795 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 796 797 /* Vector is in use, end run. */ 798 if (ioint_irqs[vector] != 0) { 799 run = 0; 800 first = 0; 801 continue; 802 } 803 804 /* Start a new run if run == 0 and vector is aligned. */ 805 if (run == 0) { 806 if ((vector & (align - 1)) != 0) 807 continue; 808 first = vector; 809 } 810 run++; 811 812 /* Keep looping if the run isn't long enough yet. */ 813 if (run < count) 814 continue; 815 816 /* Found a run, assign IRQs and return the first vector. */ 817 for (vector = 0; vector < count; vector++) 818 ioint_irqs[first + vector] = irqs[vector]; 819 mtx_unlock_spin(&icu_lock); 820 return (first + APIC_IO_INTS); 821 } 822 mtx_unlock_spin(&icu_lock); 823 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 824 return (0); 825} 826 827void 828apic_enable_vector(u_int vector) 829{ 830 831 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 832 KASSERT(ioint_handlers[vector / 32] != NULL, 833 ("No ISR handler for vector %u", vector)); 834 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 835 GSEL(GCODE_SEL, SEL_KPL)); 836} 837 838void 839apic_disable_vector(u_int vector) 840{ 841 842 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 843 KASSERT(ioint_handlers[vector / 32] != NULL, 844 ("No ISR handler for vector %u", vector)); 845 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL, 846 GSEL(GCODE_SEL, SEL_KPL)); 847} 848 849/* Release an APIC vector when it's no longer in use. */ 850void 851apic_free_vector(u_int vector, u_int irq) 852{ 853 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 854 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 855 ("Vector %u does not map to an IRQ line", vector)); 856 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 857 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 858 mtx_lock_spin(&icu_lock); 859 ioint_irqs[vector - APIC_IO_INTS] = 0; 860 mtx_unlock_spin(&icu_lock); 861} 862 863/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 864u_int 865apic_idt_to_irq(u_int vector) 866{ 867 868 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 869 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 870 ("Vector %u does not map to an IRQ line", vector)); 871 return (ioint_irqs[vector - APIC_IO_INTS]); 872} 873 874#ifdef DDB 875/* 876 * Dump data about APIC IDT vector mappings. 877 */ 878DB_SHOW_COMMAND(apic, db_show_apic) 879{ 880 struct intsrc *isrc; 881 int i, verbose; 882 u_int irq; 883 884 if (strcmp(modif, "vv") == 0) 885 verbose = 2; 886 else if (strcmp(modif, "v") == 0) 887 verbose = 1; 888 else 889 verbose = 0; 890 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 891 irq = ioint_irqs[i]; 892 if (irq != 0 && irq != IRQ_SYSCALL) { 893 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 894 if (irq == IRQ_TIMER) 895 db_printf("lapic timer\n"); 896 else if (irq < NUM_IO_INTS) { 897 isrc = intr_lookup_source(irq); 898 if (isrc == NULL || verbose == 0) 899 db_printf("IRQ %u\n", irq); 900 else 901 db_dump_intr_event(isrc->is_event, 902 verbose == 2); 903 } else 904 db_printf("IRQ %u ???\n", irq); 905 } 906 } 907} 908 909static void 910dump_mask(const char *prefix, uint32_t v, int base) 911{ 912 int i, first; 913 914 first = 1; 915 for (i = 0; i < 32; i++) 916 if (v & (1 << i)) { 917 if (first) { 918 db_printf("%s:", prefix); 919 first = 0; 920 } 921 db_printf(" %02x", base + i); 922 } 923 if (!first) 924 db_printf("\n"); 925} 926 927/* Show info from the lapic regs for this CPU. */ 928DB_SHOW_COMMAND(lapic, db_show_lapic) 929{ 930 uint32_t v; 931 932 db_printf("lapic ID = %d\n", lapic_id()); 933 v = lapic->version; 934 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 935 v & 0xf); 936 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 937 v = lapic->svr; 938 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 939 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 940 db_printf("TPR = %02x\n", lapic->tpr); 941 942#define dump_field(prefix, index) \ 943 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 944 index * 32) 945 946 db_printf("In-service Interrupts:\n"); 947 dump_field(isr, 0); 948 dump_field(isr, 1); 949 dump_field(isr, 2); 950 dump_field(isr, 3); 951 dump_field(isr, 4); 952 dump_field(isr, 5); 953 dump_field(isr, 6); 954 dump_field(isr, 7); 955 956 db_printf("TMR Interrupts:\n"); 957 dump_field(tmr, 0); 958 dump_field(tmr, 1); 959 dump_field(tmr, 2); 960 dump_field(tmr, 3); 961 dump_field(tmr, 4); 962 dump_field(tmr, 5); 963 dump_field(tmr, 6); 964 dump_field(tmr, 7); 965 966 db_printf("IRR Interrupts:\n"); 967 dump_field(irr, 0); 968 dump_field(irr, 1); 969 dump_field(irr, 2); 970 dump_field(irr, 3); 971 dump_field(irr, 4); 972 dump_field(irr, 5); 973 dump_field(irr, 6); 974 dump_field(irr, 7); 975 976#undef dump_field 977} 978#endif 979 980/* 981 * APIC probing support code. This includes code to manage enumerators. 982 */ 983 984static SLIST_HEAD(, apic_enumerator) enumerators = 985 SLIST_HEAD_INITIALIZER(enumerators); 986static struct apic_enumerator *best_enum; 987 988void 989apic_register_enumerator(struct apic_enumerator *enumerator) 990{ 991#ifdef INVARIANTS 992 struct apic_enumerator *apic_enum; 993 994 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 995 if (apic_enum == enumerator) 996 panic("%s: Duplicate register of %s", __func__, 997 enumerator->apic_name); 998 } 999#endif 1000 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1001} 1002 1003/* 1004 * Probe the APIC enumerators, enumerate CPUs, and initialize the 1005 * local APIC. 1006 */ 1007static void 1008apic_init(void *dummy __unused) 1009{ 1010 struct apic_enumerator *enumerator; 1011 uint64_t apic_base; 1012 int retval, best; 1013 1014 /* We only support built in local APICs. */ 1015 if (!(cpu_feature & CPUID_APIC)) 1016 return; 1017 1018 /* Don't probe if APIC mode is disabled. */ 1019 if (resource_disabled("apic", 0)) 1020 return; 1021 1022 /* First, probe all the enumerators to find the best match. */ 1023 best_enum = NULL; 1024 best = 0; 1025 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1026 retval = enumerator->apic_probe(); 1027 if (retval > 0) 1028 continue; 1029 if (best_enum == NULL || best < retval) { 1030 best_enum = enumerator; 1031 best = retval; 1032 } 1033 } 1034 if (best_enum == NULL) { 1035 if (bootverbose) 1036 printf("APIC: Could not find any APICs.\n"); 1037 return; 1038 } 1039 1040 if (bootverbose) 1041 printf("APIC: Using the %s enumerator.\n", 1042 best_enum->apic_name); 1043 1044 /* 1045 * To work around an errata, we disable the local APIC on some 1046 * CPUs during early startup. We need to turn the local APIC back 1047 * on on such CPUs now. 1048 */ 1049 if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 1050 (cpu_id & 0xff0) == 0x610) { 1051 apic_base = rdmsr(MSR_APICBASE); 1052 apic_base |= APICBASE_ENABLED; 1053 wrmsr(MSR_APICBASE, apic_base); 1054 } 1055 1056 /* Second, probe the CPU's in the system. */ 1057 retval = best_enum->apic_probe_cpus(); 1058 if (retval != 0) 1059 printf("%s: Failed to probe CPUs: returned %d\n", 1060 best_enum->apic_name, retval); 1061 1062 /* Third, initialize the local APIC. */ 1063 retval = best_enum->apic_setup_local(); 1064 if (retval != 0) 1065 printf("%s: Failed to setup the local APIC: returned %d\n", 1066 best_enum->apic_name, retval); 1067} 1068SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL) 1069 1070/* 1071 * Setup the I/O APICs. 1072 */ 1073static void 1074apic_setup_io(void *dummy __unused) 1075{ 1076 int retval; 1077 1078 if (best_enum == NULL) 1079 return; 1080 retval = best_enum->apic_setup_io(); 1081 if (retval != 0) 1082 printf("%s: Failed to setup I/O APICs: returned %d\n", 1083 best_enum->apic_name, retval); 1084 1085 /* 1086 * Finish setting up the local APIC on the BSP once we know how to 1087 * properly program the LINT pins. 1088 */ 1089 lapic_setup(1); 1090 intr_register_pic(&lapic_pic); 1091 if (bootverbose) 1092 lapic_dump("BSP"); 1093 1094 /* Enable the MSI "pic". */ 1095 msi_init(); 1096} 1097SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 1098 1099#ifdef SMP 1100/* 1101 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1102 * private to the sys/i386 code. The public interface for the rest of the 1103 * kernel is defined in mp_machdep.c. 1104 */ 1105int 1106lapic_ipi_wait(int delay) 1107{ 1108 int x, incr; 1109 1110 /* 1111 * Wait delay loops for IPI to be sent. This is highly bogus 1112 * since this is sensitive to CPU clock speed. If delay is 1113 * -1, we wait forever. 1114 */ 1115 if (delay == -1) { 1116 incr = 0; 1117 delay = 1; 1118 } else 1119 incr = 1; 1120 for (x = 0; x < delay; x += incr) { 1121 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1122 return (1); 1123 ia32_pause(); 1124 } 1125 return (0); 1126} 1127 1128void 1129lapic_ipi_raw(register_t icrlo, u_int dest) 1130{ 1131 register_t value, eflags; 1132 1133 /* XXX: Need more sanity checking of icrlo? */ 1134 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1135 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1136 ("%s: invalid dest field", __func__)); 1137 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1138 ("%s: reserved bits set in ICR LO register", __func__)); 1139 1140 /* Set destination in ICR HI register if it is being used. */ 1141 eflags = intr_disable(); 1142 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1143 value = lapic->icr_hi; 1144 value &= ~APIC_ID_MASK; 1145 value |= dest << APIC_ID_SHIFT; 1146 lapic->icr_hi = value; 1147 } 1148 1149 /* Program the contents of the IPI and dispatch it. */ 1150 value = lapic->icr_lo; 1151 value &= APIC_ICRLO_RESV_MASK; 1152 value |= icrlo; 1153 lapic->icr_lo = value; 1154 intr_restore(eflags); 1155} 1156 1157#define BEFORE_SPIN 1000000 1158#ifdef DETECT_DEADLOCK 1159#define AFTER_SPIN 1000 1160#endif 1161 1162void 1163lapic_ipi_vectored(u_int vector, int dest) 1164{ 1165 register_t icrlo, destfield; 1166 1167 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1168 ("%s: invalid vector %d", __func__, vector)); 1169 1170 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1171 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1172 destfield = 0; 1173 switch (dest) { 1174 case APIC_IPI_DEST_SELF: 1175 icrlo |= APIC_DEST_SELF; 1176 break; 1177 case APIC_IPI_DEST_ALL: 1178 icrlo |= APIC_DEST_ALLISELF; 1179 break; 1180 case APIC_IPI_DEST_OTHERS: 1181 icrlo |= APIC_DEST_ALLESELF; 1182 break; 1183 default: 1184 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1185 ("%s: invalid destination 0x%x", __func__, dest)); 1186 destfield = dest; 1187 } 1188 1189 /* Wait for an earlier IPI to finish. */ 1190 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1191 if (panicstr != NULL) 1192 return; 1193 else 1194 panic("APIC: Previous IPI is stuck"); 1195 } 1196 1197 lapic_ipi_raw(icrlo, destfield); 1198 1199#ifdef DETECT_DEADLOCK 1200 /* Wait for IPI to be delivered. */ 1201 if (!lapic_ipi_wait(AFTER_SPIN)) { 1202#ifdef needsattention 1203 /* 1204 * XXX FIXME: 1205 * 1206 * The above function waits for the message to actually be 1207 * delivered. It breaks out after an arbitrary timeout 1208 * since the message should eventually be delivered (at 1209 * least in theory) and that if it wasn't we would catch 1210 * the failure with the check above when the next IPI is 1211 * sent. 1212 * 1213 * We could skip this wait entirely, EXCEPT it probably 1214 * protects us from other routines that assume that the 1215 * message was delivered and acted upon when this function 1216 * returns. 1217 */ 1218 printf("APIC: IPI might be stuck\n"); 1219#else /* !needsattention */ 1220 /* Wait until mesage is sent without a timeout. */ 1221 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1222 ia32_pause(); 1223#endif /* needsattention */ 1224 } 1225#endif /* DETECT_DEADLOCK */ 1226} 1227#endif /* SMP */ 1228