specialreg.h revision 191648
1228753Smm/*- 2228753Smm * Copyright (c) 1991 The Regents of the University of California. 3228753Smm * All rights reserved. 4228753Smm * 5228753Smm * Redistribution and use in source and binary forms, with or without 6228753Smm * modification, are permitted provided that the following conditions 7228753Smm * are met: 8228753Smm * 1. Redistributions of source code must retain the above copyright 9228753Smm * notice, this list of conditions and the following disclaimer. 10228753Smm * 2. Redistributions in binary form must reproduce the above copyright 11228753Smm * notice, this list of conditions and the following disclaimer in the 12228753Smm * documentation and/or other materials provided with the distribution. 13228753Smm * 4. Neither the name of the University nor the names of its contributors 14228753Smm * may be used to endorse or promote products derived from this software 15228753Smm * without specific prior written permission. 16228753Smm * 17228753Smm * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18228753Smm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19228753Smm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20228753Smm * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21228753Smm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22228753Smm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23228753Smm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24228753Smm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25228753Smm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26228753Smm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27228753Smm * SUCH DAMAGE. 28228753Smm * 29228753Smm * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30228753Smm * $FreeBSD: head/sys/i386/include/specialreg.h 191648 2009-04-29 06:54:40Z jeff $ 31228753Smm */ 32228753Smm 33228753Smm#ifndef _MACHINE_SPECIALREG_H_ 34228753Smm#define _MACHINE_SPECIALREG_H_ 35228753Smm 36228753Smm/* 37228753Smm * Bits in 386 special registers: 38228753Smm */ 39228753Smm#define CR0_PE 0x00000001 /* Protected mode Enable */ 40228753Smm#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41228753Smm#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42228753Smm#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43228753Smm#define CR0_PG 0x80000000 /* PaGing enable */ 44228753Smm 45228753Smm/* 46228753Smm * Bits in 486 special registers: 47228753Smm */ 48228753Smm#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49228753Smm#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50228753Smm all modes) */ 51228753Smm#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52228753Smm#define CR0_NW 0x20000000 /* Not Write-through */ 53228753Smm#define CR0_CD 0x40000000 /* Cache Disable */ 54228753Smm 55228753Smm/* 56228753Smm * Bits in PPro special registers 57228753Smm */ 58228753Smm#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59228753Smm#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60228753Smm#define CR4_TSD 0x00000004 /* Time stamp disable */ 61228753Smm#define CR4_DE 0x00000008 /* Debugging extensions */ 62228753Smm#define CR4_PSE 0x00000010 /* Page size extensions */ 63228753Smm#define CR4_PAE 0x00000020 /* Physical address extension */ 64228753Smm#define CR4_MCE 0x00000040 /* Machine check enable */ 65228753Smm#define CR4_PGE 0x00000080 /* Page global enable */ 66228753Smm#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67228753Smm#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68228753Smm#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69228753Smm 70228753Smm/* 71228753Smm * Bits in AMD64 special registers. EFER is 64 bits wide. 72228753Smm */ 73228753Smm#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74228753Smm 75228753Smm/* 76228753Smm * CPUID instruction features register 77228753Smm */ 78228753Smm#define CPUID_FPU 0x00000001 79228753Smm#define CPUID_VME 0x00000002 80228753Smm#define CPUID_DE 0x00000004 81228753Smm#define CPUID_PSE 0x00000008 82228753Smm#define CPUID_TSC 0x00000010 83228753Smm#define CPUID_MSR 0x00000020 84228753Smm#define CPUID_PAE 0x00000040 85228753Smm#define CPUID_MCE 0x00000080 86228753Smm#define CPUID_CX8 0x00000100 87228753Smm#define CPUID_APIC 0x00000200 88228753Smm#define CPUID_B10 0x00000400 89228753Smm#define CPUID_SEP 0x00000800 90228753Smm#define CPUID_MTRR 0x00001000 91228753Smm#define CPUID_PGE 0x00002000 92228753Smm#define CPUID_MCA 0x00004000 93228753Smm#define CPUID_CMOV 0x00008000 94228753Smm#define CPUID_PAT 0x00010000 95228753Smm#define CPUID_PSE36 0x00020000 96228753Smm#define CPUID_PSN 0x00040000 97228753Smm#define CPUID_CLFSH 0x00080000 98228753Smm#define CPUID_B20 0x00100000 99228753Smm#define CPUID_DS 0x00200000 100228753Smm#define CPUID_ACPI 0x00400000 101228753Smm#define CPUID_MMX 0x00800000 102228753Smm#define CPUID_FXSR 0x01000000 103228753Smm#define CPUID_SSE 0x02000000 104228753Smm#define CPUID_XMM 0x02000000 105228753Smm#define CPUID_SSE2 0x04000000 106228753Smm#define CPUID_SS 0x08000000 107228753Smm#define CPUID_HTT 0x10000000 108228753Smm#define CPUID_TM 0x20000000 109228753Smm#define CPUID_IA64 0x40000000 110228753Smm#define CPUID_PBE 0x80000000 111228753Smm 112228753Smm#define CPUID2_SSE3 0x00000001 113228753Smm#define CPUID2_DTES64 0x00000004 114228753Smm#define CPUID2_MON 0x00000008 115228753Smm#define CPUID2_DS_CPL 0x00000010 116228753Smm#define CPUID2_VMX 0x00000020 117228753Smm#define CPUID2_SMX 0x00000040 118228753Smm#define CPUID2_EST 0x00000080 119228753Smm#define CPUID2_TM2 0x00000100 120228753Smm#define CPUID2_SSSE3 0x00000200 121228753Smm#define CPUID2_CNXTID 0x00000400 122228753Smm#define CPUID2_CX16 0x00002000 123228753Smm#define CPUID2_XTPR 0x00004000 124228753Smm#define CPUID2_PDCM 0x00008000 125228753Smm#define CPUID2_DCA 0x00040000 126228753Smm#define CPUID2_SSE41 0x00080000 127228753Smm#define CPUID2_SSE42 0x00100000 128228753Smm#define CPUID2_X2APIC 0x00200000 129228753Smm#define CPUID2_POPCNT 0x00800000 130228753Smm 131228753Smm/* 132228753Smm * Important bits in the AMD extended cpuid flags 133228753Smm */ 134228753Smm#define AMDID_SYSCALL 0x00000800 135228753Smm#define AMDID_MP 0x00080000 136228753Smm#define AMDID_NX 0x00100000 137228753Smm#define AMDID_EXT_MMX 0x00400000 138228753Smm#define AMDID_FFXSR 0x01000000 139228753Smm#define AMDID_PAGE1GB 0x04000000 140228753Smm#define AMDID_RDTSCP 0x08000000 141228753Smm#define AMDID_LM 0x20000000 142228753Smm#define AMDID_EXT_3DNOW 0x40000000 143228753Smm#define AMDID_3DNOW 0x80000000 144228753Smm 145#define AMDID2_LAHF 0x00000001 146#define AMDID2_CMP 0x00000002 147#define AMDID2_SVM 0x00000004 148#define AMDID2_EXT_APIC 0x00000008 149#define AMDID2_CR8 0x00000010 150#define AMDID2_ABM 0x00000020 151#define AMDID2_SSE4A 0x00000040 152#define AMDID2_MAS 0x00000080 153#define AMDID2_PREFETCH 0x00000100 154#define AMDID2_OSVW 0x00000200 155#define AMDID2_IBS 0x00000400 156#define AMDID2_SSE5 0x00000800 157#define AMDID2_SKINIT 0x00001000 158#define AMDID2_WDT 0x00002000 159 160/* 161 * CPUID instruction 1 eax info 162 */ 163#define CPUID_STEPPING 0x0000000f 164#define CPUID_MODEL 0x000000f0 165#define CPUID_FAMILY 0x00000f00 166#define CPUID_EXT_MODEL 0x000f0000 167#define CPUID_EXT_FAMILY 0x0ff00000 168#define I386_CPU_MODEL(id) \ 169 ((((id) & CPUID_MODEL) >> 4) | \ 170 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 171 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 172#define I386_CPU_FAMILY(id) \ 173 ((((id) & CPUID_FAMILY) >> 8) + \ 174 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 175 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 176 177/* 178 * CPUID instruction 1 ebx info 179 */ 180#define CPUID_BRAND_INDEX 0x000000ff 181#define CPUID_CLFUSH_SIZE 0x0000ff00 182#define CPUID_HTT_CORES 0x00ff0000 183#define CPUID_LOCAL_APIC_ID 0xff000000 184 185/* 186 * CPUID instruction 0xb ebx info. 187 */ 188#define CPUID_TYPE_INVAL 0 189#define CPUID_TYPE_SMT 1 190#define CPUID_TYPE_CORE 2 191 192/* 193 * AMD extended function 8000_0007h edx info 194 */ 195#define AMDPM_TS 0x00000001 196#define AMDPM_FID 0x00000002 197#define AMDPM_VID 0x00000004 198#define AMDPM_TTP 0x00000008 199#define AMDPM_TM 0x00000010 200#define AMDPM_STC 0x00000020 201#define AMDPM_100MHZ_STEPS 0x00000040 202#define AMDPM_HW_PSTATE 0x00000080 203#define AMDPM_TSC_INVARIANT 0x00000100 204 205/* 206 * AMD extended function 8000_0008h ecx info 207 */ 208#define AMDID_CMP_CORES 0x000000ff 209 210/* 211 * CPUID manufacturers identifiers 212 */ 213#define AMD_VENDOR_ID "AuthenticAMD" 214#define CENTAUR_VENDOR_ID "CentaurHauls" 215#define CYRIX_VENDOR_ID "CyrixInstead" 216#define INTEL_VENDOR_ID "GenuineIntel" 217#define NEXGEN_VENDOR_ID "NexGenDriven" 218#define NSC_VENDOR_ID "Geode by NSC" 219#define RISE_VENDOR_ID "RiseRiseRise" 220#define SIS_VENDOR_ID "SiS SiS SiS " 221#define TRANSMETA_VENDOR_ID "GenuineTMx86" 222#define UMC_VENDOR_ID "UMC UMC UMC " 223 224/* 225 * Model-specific registers for the i386 family 226 */ 227#define MSR_P5_MC_ADDR 0x000 228#define MSR_P5_MC_TYPE 0x001 229#define MSR_TSC 0x010 230#define MSR_P5_CESR 0x011 231#define MSR_P5_CTR0 0x012 232#define MSR_P5_CTR1 0x013 233#define MSR_IA32_PLATFORM_ID 0x017 234#define MSR_APICBASE 0x01b 235#define MSR_EBL_CR_POWERON 0x02a 236#define MSR_TEST_CTL 0x033 237#define MSR_BIOS_UPDT_TRIG 0x079 238#define MSR_BBL_CR_D0 0x088 239#define MSR_BBL_CR_D1 0x089 240#define MSR_BBL_CR_D2 0x08a 241#define MSR_BIOS_SIGN 0x08b 242#define MSR_PERFCTR0 0x0c1 243#define MSR_PERFCTR1 0x0c2 244#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 245#define MSR_MTRRcap 0x0fe 246#define MSR_BBL_CR_ADDR 0x116 247#define MSR_BBL_CR_DECC 0x118 248#define MSR_BBL_CR_CTL 0x119 249#define MSR_BBL_CR_TRIG 0x11a 250#define MSR_BBL_CR_BUSY 0x11b 251#define MSR_BBL_CR_CTL3 0x11e 252#define MSR_SYSENTER_CS_MSR 0x174 253#define MSR_SYSENTER_ESP_MSR 0x175 254#define MSR_SYSENTER_EIP_MSR 0x176 255#define MSR_MCG_CAP 0x179 256#define MSR_MCG_STATUS 0x17a 257#define MSR_MCG_CTL 0x17b 258#define MSR_EVNTSEL0 0x186 259#define MSR_EVNTSEL1 0x187 260#define MSR_THERM_CONTROL 0x19a 261#define MSR_THERM_INTERRUPT 0x19b 262#define MSR_THERM_STATUS 0x19c 263#define MSR_IA32_MISC_ENABLE 0x1a0 264#define MSR_DEBUGCTLMSR 0x1d9 265#define MSR_LASTBRANCHFROMIP 0x1db 266#define MSR_LASTBRANCHTOIP 0x1dc 267#define MSR_LASTINTFROMIP 0x1dd 268#define MSR_LASTINTTOIP 0x1de 269#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 270#define MSR_MTRRVarBase 0x200 271#define MSR_MTRR64kBase 0x250 272#define MSR_MTRR16kBase 0x258 273#define MSR_MTRR4kBase 0x268 274#define MSR_PAT 0x277 275#define MSR_MTRRdefType 0x2ff 276#define MSR_MC0_CTL 0x400 277#define MSR_MC0_STATUS 0x401 278#define MSR_MC0_ADDR 0x402 279#define MSR_MC0_MISC 0x403 280#define MSR_MC1_CTL 0x404 281#define MSR_MC1_STATUS 0x405 282#define MSR_MC1_ADDR 0x406 283#define MSR_MC1_MISC 0x407 284#define MSR_MC2_CTL 0x408 285#define MSR_MC2_STATUS 0x409 286#define MSR_MC2_ADDR 0x40a 287#define MSR_MC2_MISC 0x40b 288#define MSR_MC3_CTL 0x40c 289#define MSR_MC3_STATUS 0x40d 290#define MSR_MC3_ADDR 0x40e 291#define MSR_MC3_MISC 0x40f 292#define MSR_MC4_CTL 0x410 293#define MSR_MC4_STATUS 0x411 294#define MSR_MC4_ADDR 0x412 295#define MSR_MC4_MISC 0x413 296 297/* 298 * Constants related to MSR's. 299 */ 300#define APICBASE_RESERVED 0x000006ff 301#define APICBASE_BSP 0x00000100 302#define APICBASE_ENABLED 0x00000800 303#define APICBASE_ADDRESS 0xfffff000 304 305/* 306 * PAT modes. 307 */ 308#define PAT_UNCACHEABLE 0x00 309#define PAT_WRITE_COMBINING 0x01 310#define PAT_WRITE_THROUGH 0x04 311#define PAT_WRITE_PROTECTED 0x05 312#define PAT_WRITE_BACK 0x06 313#define PAT_UNCACHED 0x07 314#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 315#define PAT_MASK(i) PAT_VALUE(i, 0xff) 316 317/* 318 * Constants related to MTRRs 319 */ 320#define MTRR_UNCACHEABLE 0x00 321#define MTRR_WRITE_COMBINING 0x01 322#define MTRR_WRITE_THROUGH 0x04 323#define MTRR_WRITE_PROTECTED 0x05 324#define MTRR_WRITE_BACK 0x06 325#define MTRR_N64K 8 /* numbers of fixed-size entries */ 326#define MTRR_N16K 16 327#define MTRR_N4K 64 328#define MTRR_CAP_WC 0x0000000000000400ULL 329#define MTRR_CAP_FIXED 0x0000000000000100ULL 330#define MTRR_CAP_VCNT 0x00000000000000ffULL 331#define MTRR_DEF_ENABLE 0x0000000000000800ULL 332#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL 333#define MTRR_DEF_TYPE 0x00000000000000ffULL 334#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL 335#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL 336#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL 337#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL 338 339/* 340 * Cyrix configuration registers, accessible as IO ports. 341 */ 342#define CCR0 0xc0 /* Configuration control register 0 */ 343#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 344 non-cacheable */ 345#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 346#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 347#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 348#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 349#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 350 state */ 351#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 352 assoc */ 353#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 354 355#define CCR1 0xc1 /* Configuration control register 1 */ 356#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 357#define CCR1_SMI 0x02 /* Enables SMM pins */ 358#define CCR1_SMAC 0x04 /* System management memory access */ 359#define CCR1_MMAC 0x08 /* Main memory access */ 360#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 361#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 362 363#define CCR2 0xc2 364#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 365#define CCR2_SADS 0x02 /* Slow ADS */ 366#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 367#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 368#define CCR2_WT1 0x10 /* WT region 1 */ 369#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 370#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 371 hold state. */ 372#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 373#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 374 375#define CCR3 0xc3 376#define CCR3_SMILOCK 0x01 /* SMM register lock */ 377#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 378#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 379#define CCR3_SMMMODE 0x08 /* SMM Mode */ 380#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 381#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 382#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 383#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 384 385#define CCR4 0xe8 386#define CCR4_IOMASK 0x07 387#define CCR4_MEM 0x08 /* Enables momory bypassing */ 388#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 389#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 390#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 391 392#define CCR5 0xe9 393#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 394#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 395#define CCR5_LBR1 0x10 /* Local bus region 1 */ 396#define CCR5_ARREN 0x20 /* Enables ARR region */ 397 398#define CCR6 0xea 399 400#define CCR7 0xeb 401 402/* Performance Control Register (5x86 only). */ 403#define PCR0 0x20 404#define PCR0_RSTK 0x01 /* Enables return stack */ 405#define PCR0_BTB 0x02 /* Enables branch target buffer */ 406#define PCR0_LOOP 0x04 /* Enables loop */ 407#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 408 serialize pipe. */ 409#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 410#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 411#define PCR0_LSSER 0x80 /* Disable reorder */ 412 413/* Device Identification Registers */ 414#define DIR0 0xfe 415#define DIR1 0xff 416 417/* 418 * The following four 3-byte registers control the non-cacheable regions. 419 * These registers must be written as three separate bytes. 420 * 421 * NCRx+0: A31-A24 of starting address 422 * NCRx+1: A23-A16 of starting address 423 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 424 * 425 * The non-cacheable region's starting address must be aligned to the 426 * size indicated by the NCR_SIZE_xx field. 427 */ 428#define NCR1 0xc4 429#define NCR2 0xc7 430#define NCR3 0xca 431#define NCR4 0xcd 432 433#define NCR_SIZE_0K 0 434#define NCR_SIZE_4K 1 435#define NCR_SIZE_8K 2 436#define NCR_SIZE_16K 3 437#define NCR_SIZE_32K 4 438#define NCR_SIZE_64K 5 439#define NCR_SIZE_128K 6 440#define NCR_SIZE_256K 7 441#define NCR_SIZE_512K 8 442#define NCR_SIZE_1M 9 443#define NCR_SIZE_2M 10 444#define NCR_SIZE_4M 11 445#define NCR_SIZE_8M 12 446#define NCR_SIZE_16M 13 447#define NCR_SIZE_32M 14 448#define NCR_SIZE_4G 15 449 450/* 451 * The address region registers are used to specify the location and 452 * size for the eight address regions. 453 * 454 * ARRx + 0: A31-A24 of start address 455 * ARRx + 1: A23-A16 of start address 456 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 457 */ 458#define ARR0 0xc4 459#define ARR1 0xc7 460#define ARR2 0xca 461#define ARR3 0xcd 462#define ARR4 0xd0 463#define ARR5 0xd3 464#define ARR6 0xd6 465#define ARR7 0xd9 466 467#define ARR_SIZE_0K 0 468#define ARR_SIZE_4K 1 469#define ARR_SIZE_8K 2 470#define ARR_SIZE_16K 3 471#define ARR_SIZE_32K 4 472#define ARR_SIZE_64K 5 473#define ARR_SIZE_128K 6 474#define ARR_SIZE_256K 7 475#define ARR_SIZE_512K 8 476#define ARR_SIZE_1M 9 477#define ARR_SIZE_2M 10 478#define ARR_SIZE_4M 11 479#define ARR_SIZE_8M 12 480#define ARR_SIZE_16M 13 481#define ARR_SIZE_32M 14 482#define ARR_SIZE_4G 15 483 484/* 485 * The region control registers specify the attributes associated with 486 * the ARRx addres regions. 487 */ 488#define RCR0 0xdc 489#define RCR1 0xdd 490#define RCR2 0xde 491#define RCR3 0xdf 492#define RCR4 0xe0 493#define RCR5 0xe1 494#define RCR6 0xe2 495#define RCR7 0xe3 496 497#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 498#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 499#define RCR_WWO 0x02 /* Weak write ordering. */ 500#define RCR_WL 0x04 /* Weak locking. */ 501#define RCR_WG 0x08 /* Write gathering. */ 502#define RCR_WT 0x10 /* Write-through. */ 503#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 504 505/* AMD Write Allocate Top-Of-Memory and Control Register */ 506#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 507#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 508#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 509 510/* AMD64 MSR's */ 511#define MSR_EFER 0xc0000080 /* extended features */ 512#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 513 514/* VIA ACE crypto featureset: for via_feature_rng */ 515#define VIA_HAS_RNG 1 /* cpu has RNG */ 516 517/* VIA ACE crypto featureset: for via_feature_xcrypt */ 518#define VIA_HAS_AES 1 /* cpu has AES */ 519#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 520#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 521#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 522 523/* Centaur Extended Feature flags */ 524#define VIA_CPUID_HAS_RNG 0x000004 525#define VIA_CPUID_DO_RNG 0x000008 526#define VIA_CPUID_HAS_ACE 0x000040 527#define VIA_CPUID_DO_ACE 0x000080 528#define VIA_CPUID_HAS_ACE2 0x000100 529#define VIA_CPUID_DO_ACE2 0x000200 530#define VIA_CPUID_HAS_PHE 0x000400 531#define VIA_CPUID_DO_PHE 0x000800 532#define VIA_CPUID_HAS_PMM 0x001000 533#define VIA_CPUID_DO_PMM 0x002000 534 535/* VIA ACE xcrypt-* instruction context control options */ 536#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 537#define VIA_CRYPT_CWLO_ALG_M 0x00000070 538#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 539#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 540#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 541#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 542#define VIA_CRYPT_CWLO_NORMAL 0x00000000 543#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 544#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 545#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 546#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 547#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 548#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 549 550#ifndef LOCORE 551static __inline u_char 552read_cyrix_reg(u_char reg) 553{ 554 outb(0x22, reg); 555 return inb(0x23); 556} 557 558static __inline void 559write_cyrix_reg(u_char reg, u_char data) 560{ 561 outb(0x22, reg); 562 outb(0x23, data); 563} 564#endif 565 566#endif /* !_MACHINE_SPECIALREG_H_ */ 567