specialreg.h revision 197070
14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 4. Neither the name of the University nor the names of its contributors 144Srgrimes * may be used to endorse or promote products derived from this software 154Srgrimes * without specific prior written permission. 164Srgrimes * 174Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 184Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 194Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 204Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 214Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 224Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 234Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 244Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 254Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 264Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 274Srgrimes * SUCH DAMAGE. 284Srgrimes * 29621Srgrimes * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD: head/sys/i386/include/specialreg.h 197070 2009-09-10 17:27:36Z jkim $ 314Srgrimes */ 324Srgrimes 33719Swollman#ifndef _MACHINE_SPECIALREG_H_ 345594Sbde#define _MACHINE_SPECIALREG_H_ 35719Swollman 364Srgrimes/* 374Srgrimes * Bits in 386 special registers: 384Srgrimes */ 394Srgrimes#define CR0_PE 0x00000001 /* Protected mode Enable */ 40160329Sjkim#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41160329Sjkim#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 424Srgrimes#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 434Srgrimes#define CR0_PG 0x80000000 /* PaGing enable */ 444Srgrimes 454Srgrimes/* 464Srgrimes * Bits in 486 special registers: 474Srgrimes */ 4824112Skato#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 4924112Skato#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 5024112Skato all modes) */ 5124112Skato#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 5224112Skato#define CR0_NW 0x20000000 /* Not Write-through */ 5324112Skato#define CR0_CD 0x40000000 /* Cache Disable */ 542495Spst 552495Spst/* 5619621Sdyson * Bits in PPro special registers 5719621Sdyson */ 5819621Sdyson#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 5919621Sdyson#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 6019621Sdyson#define CR4_TSD 0x00000004 /* Time stamp disable */ 6119621Sdyson#define CR4_DE 0x00000008 /* Debugging extensions */ 6219621Sdyson#define CR4_PSE 0x00000010 /* Page size extensions */ 6319621Sdyson#define CR4_PAE 0x00000020 /* Physical address extension */ 6419621Sdyson#define CR4_MCE 0x00000040 /* Machine check enable */ 6519621Sdyson#define CR4_PGE 0x00000080 /* Page global enable */ 6619621Sdyson#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 6751127Speter#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 6851127Speter#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 6919621Sdyson 7019621Sdyson/* 71168439Sru * Bits in AMD64 special registers. EFER is 64 bits wide. 72168439Sru */ 73168439Sru#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74168439Sru 75168439Sru/* 7619621Sdyson * CPUID instruction features register 7719621Sdyson */ 7898650Smp#define CPUID_FPU 0x00000001 7998650Smp#define CPUID_VME 0x00000002 8098650Smp#define CPUID_DE 0x00000004 8198650Smp#define CPUID_PSE 0x00000008 8298650Smp#define CPUID_TSC 0x00000010 8398650Smp#define CPUID_MSR 0x00000020 8498650Smp#define CPUID_PAE 0x00000040 8598650Smp#define CPUID_MCE 0x00000080 8698650Smp#define CPUID_CX8 0x00000100 8798650Smp#define CPUID_APIC 0x00000200 8898650Smp#define CPUID_B10 0x00000400 8998650Smp#define CPUID_SEP 0x00000800 9098650Smp#define CPUID_MTRR 0x00001000 9198650Smp#define CPUID_PGE 0x00002000 9298650Smp#define CPUID_MCA 0x00004000 9398650Smp#define CPUID_CMOV 0x00008000 9498650Smp#define CPUID_PAT 0x00010000 9598650Smp#define CPUID_PSE36 0x00020000 9698650Smp#define CPUID_PSN 0x00040000 9798650Smp#define CPUID_CLFSH 0x00080000 9898650Smp#define CPUID_B20 0x00100000 9998650Smp#define CPUID_DS 0x00200000 10098650Smp#define CPUID_ACPI 0x00400000 10198650Smp#define CPUID_MMX 0x00800000 10298650Smp#define CPUID_FXSR 0x01000000 10398650Smp#define CPUID_SSE 0x02000000 10498650Smp#define CPUID_XMM 0x02000000 10598650Smp#define CPUID_SSE2 0x04000000 10698650Smp#define CPUID_SS 0x08000000 107108909Sjhb#define CPUID_HTT 0x10000000 10898650Smp#define CPUID_TM 0x20000000 109114376Speter#define CPUID_IA64 0x40000000 11098650Smp#define CPUID_PBE 0x80000000 11119621Sdyson 112167493Sjkim#define CPUID2_SSE3 0x00000001 113183128Sjhb#define CPUID2_DTES64 0x00000004 114167493Sjkim#define CPUID2_MON 0x00000008 115167493Sjkim#define CPUID2_DS_CPL 0x00000010 116167493Sjkim#define CPUID2_VMX 0x00000020 117167744Sjkim#define CPUID2_SMX 0x00000040 118167493Sjkim#define CPUID2_EST 0x00000080 119167493Sjkim#define CPUID2_TM2 0x00000100 120167493Sjkim#define CPUID2_SSSE3 0x00000200 121167493Sjkim#define CPUID2_CNXTID 0x00000400 122167493Sjkim#define CPUID2_CX16 0x00002000 123167493Sjkim#define CPUID2_XTPR 0x00004000 124170150Sdes#define CPUID2_PDCM 0x00008000 125167744Sjkim#define CPUID2_DCA 0x00040000 126183128Sjhb#define CPUID2_SSE41 0x00080000 127183128Sjhb#define CPUID2_SSE42 0x00100000 128183128Sjhb#define CPUID2_X2APIC 0x00200000 129183128Sjhb#define CPUID2_POPCNT 0x00800000 130160329Sjkim 13119621Sdyson/* 132151348Sjkim * Important bits in the AMD extended cpuid flags 133151348Sjkim */ 134167493Sjkim#define AMDID_SYSCALL 0x00000800 135167493Sjkim#define AMDID_MP 0x00080000 136167493Sjkim#define AMDID_NX 0x00100000 137167493Sjkim#define AMDID_EXT_MMX 0x00400000 138167493Sjkim#define AMDID_FFXSR 0x01000000 139183128Sjhb#define AMDID_PAGE1GB 0x04000000 140167493Sjkim#define AMDID_RDTSCP 0x08000000 141167493Sjkim#define AMDID_LM 0x20000000 142167493Sjkim#define AMDID_EXT_3DNOW 0x40000000 143167493Sjkim#define AMDID_3DNOW 0x80000000 144151348Sjkim 145167493Sjkim#define AMDID2_LAHF 0x00000001 146167493Sjkim#define AMDID2_CMP 0x00000002 147167493Sjkim#define AMDID2_SVM 0x00000004 148167493Sjkim#define AMDID2_EXT_APIC 0x00000008 149167493Sjkim#define AMDID2_CR8 0x00000010 150186009Sjkim#define AMDID2_ABM 0x00000020 151186009Sjkim#define AMDID2_SSE4A 0x00000040 152186009Sjkim#define AMDID2_MAS 0x00000080 153167493Sjkim#define AMDID2_PREFETCH 0x00000100 154186009Sjkim#define AMDID2_OSVW 0x00000200 155186009Sjkim#define AMDID2_IBS 0x00000400 156186009Sjkim#define AMDID2_SSE5 0x00000800 157186009Sjkim#define AMDID2_SKINIT 0x00001000 158186009Sjkim#define AMDID2_WDT 0x00002000 159151348Sjkim 160151348Sjkim/* 161184146Sjkim * CPUID instruction 1 eax info 162184146Sjkim */ 163184146Sjkim#define CPUID_STEPPING 0x0000000f 164184146Sjkim#define CPUID_MODEL 0x000000f0 165184146Sjkim#define CPUID_FAMILY 0x00000f00 166184146Sjkim#define CPUID_EXT_MODEL 0x000f0000 167184146Sjkim#define CPUID_EXT_FAMILY 0x0ff00000 168197070Sjkim#define CPUID_TO_MODEL(id) \ 169184146Sjkim ((((id) & CPUID_MODEL) >> 4) | \ 170184146Sjkim ((((id) & CPUID_FAMILY) >= 0x600) ? \ 171184146Sjkim (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 172197070Sjkim#define CPUID_TO_FAMILY(id) \ 173184146Sjkim ((((id) & CPUID_FAMILY) >> 8) + \ 174184146Sjkim ((((id) & CPUID_FAMILY) == 0xf00) ? \ 175184146Sjkim (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 176184146Sjkim 177184146Sjkim/* 178109691Sjhb * CPUID instruction 1 ebx info 179108909Sjhb */ 180108909Sjhb#define CPUID_BRAND_INDEX 0x000000ff 181108909Sjhb#define CPUID_CLFUSH_SIZE 0x0000ff00 182108909Sjhb#define CPUID_HTT_CORES 0x00ff0000 183108909Sjhb#define CPUID_LOCAL_APIC_ID 0xff000000 184108909Sjhb 185191648Sjeff/* 186191648Sjeff * CPUID instruction 0xb ebx info. 187191648Sjeff */ 188191648Sjeff#define CPUID_TYPE_INVAL 0 189191648Sjeff#define CPUID_TYPE_SMT 1 190191648Sjeff#define CPUID_TYPE_CORE 2 191191648Sjeff 192108909Sjhb/* 193184101Sjkim * AMD extended function 8000_0007h edx info 194184101Sjkim */ 195184101Sjkim#define AMDPM_TS 0x00000001 196184101Sjkim#define AMDPM_FID 0x00000002 197184101Sjkim#define AMDPM_VID 0x00000004 198184101Sjkim#define AMDPM_TTP 0x00000008 199184101Sjkim#define AMDPM_TM 0x00000010 200184101Sjkim#define AMDPM_STC 0x00000020 201184101Sjkim#define AMDPM_100MHZ_STEPS 0x00000040 202184101Sjkim#define AMDPM_HW_PSTATE 0x00000080 203184101Sjkim#define AMDPM_TSC_INVARIANT 0x00000100 204184101Sjkim 205184101Sjkim/* 206151348Sjkim * AMD extended function 8000_0008h ecx info 207151348Sjkim */ 208167493Sjkim#define AMDID_CMP_CORES 0x000000ff 209151348Sjkim 210151348Sjkim/* 211181430Sstas * CPUID manufacturers identifiers 212181430Sstas */ 213185341Sjkim#define AMD_VENDOR_ID "AuthenticAMD" 214185341Sjkim#define CENTAUR_VENDOR_ID "CentaurHauls" 215185341Sjkim#define CYRIX_VENDOR_ID "CyrixInstead" 216185341Sjkim#define INTEL_VENDOR_ID "GenuineIntel" 217185341Sjkim#define NEXGEN_VENDOR_ID "NexGenDriven" 218185341Sjkim#define NSC_VENDOR_ID "Geode by NSC" 219185341Sjkim#define RISE_VENDOR_ID "RiseRiseRise" 220185341Sjkim#define SIS_VENDOR_ID "SiS SiS SiS " 221185341Sjkim#define TRANSMETA_VENDOR_ID "GenuineTMx86" 222185341Sjkim#define UMC_VENDOR_ID "UMC UMC UMC " 223181430Sstas 224181430Sstas/* 22545406Smsmith * Model-specific registers for the i386 family 22645406Smsmith */ 227167493Sjkim#define MSR_P5_MC_ADDR 0x000 228167493Sjkim#define MSR_P5_MC_TYPE 0x001 229167493Sjkim#define MSR_TSC 0x010 230118954Sjhb#define MSR_P5_CESR 0x011 231118954Sjhb#define MSR_P5_CTR0 0x012 232118954Sjhb#define MSR_P5_CTR1 0x013 233118954Sjhb#define MSR_IA32_PLATFORM_ID 0x017 234167493Sjkim#define MSR_APICBASE 0x01b 235167493Sjkim#define MSR_EBL_CR_POWERON 0x02a 236118954Sjhb#define MSR_TEST_CTL 0x033 237167493Sjkim#define MSR_BIOS_UPDT_TRIG 0x079 238118954Sjhb#define MSR_BBL_CR_D0 0x088 239118954Sjhb#define MSR_BBL_CR_D1 0x089 240118954Sjhb#define MSR_BBL_CR_D2 0x08a 241167493Sjkim#define MSR_BIOS_SIGN 0x08b 242167493Sjkim#define MSR_PERFCTR0 0x0c1 243167493Sjkim#define MSR_PERFCTR1 0x0c2 244171854Sdes#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 245167493Sjkim#define MSR_MTRRcap 0x0fe 246118954Sjhb#define MSR_BBL_CR_ADDR 0x116 247118954Sjhb#define MSR_BBL_CR_DECC 0x118 248118954Sjhb#define MSR_BBL_CR_CTL 0x119 249118954Sjhb#define MSR_BBL_CR_TRIG 0x11a 250118954Sjhb#define MSR_BBL_CR_BUSY 0x11b 251118954Sjhb#define MSR_BBL_CR_CTL3 0x11e 252118954Sjhb#define MSR_SYSENTER_CS_MSR 0x174 253118954Sjhb#define MSR_SYSENTER_ESP_MSR 0x175 254118954Sjhb#define MSR_SYSENTER_EIP_MSR 0x176 255167493Sjkim#define MSR_MCG_CAP 0x179 256167493Sjkim#define MSR_MCG_STATUS 0x17a 257167493Sjkim#define MSR_MCG_CTL 0x17b 258167493Sjkim#define MSR_EVNTSEL0 0x186 259167493Sjkim#define MSR_EVNTSEL1 0x187 260167493Sjkim#define MSR_THERM_CONTROL 0x19a 261167493Sjkim#define MSR_THERM_INTERRUPT 0x19b 262167493Sjkim#define MSR_THERM_STATUS 0x19c 263159768Sdavidxu#define MSR_IA32_MISC_ENABLE 0x1a0 264167493Sjkim#define MSR_DEBUGCTLMSR 0x1d9 265167493Sjkim#define MSR_LASTBRANCHFROMIP 0x1db 266167493Sjkim#define MSR_LASTBRANCHTOIP 0x1dc 267167493Sjkim#define MSR_LASTINTFROMIP 0x1dd 268167493Sjkim#define MSR_LASTINTTOIP 0x1de 269167493Sjkim#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 270167493Sjkim#define MSR_MTRRVarBase 0x200 271167493Sjkim#define MSR_MTRR64kBase 0x250 272167493Sjkim#define MSR_MTRR16kBase 0x258 273167493Sjkim#define MSR_MTRR4kBase 0x268 274167493Sjkim#define MSR_PAT 0x277 275167493Sjkim#define MSR_MTRRdefType 0x2ff 276167493Sjkim#define MSR_MC0_CTL 0x400 277167493Sjkim#define MSR_MC0_STATUS 0x401 278167493Sjkim#define MSR_MC0_ADDR 0x402 279167493Sjkim#define MSR_MC0_MISC 0x403 280167493Sjkim#define MSR_MC1_CTL 0x404 281167493Sjkim#define MSR_MC1_STATUS 0x405 282167493Sjkim#define MSR_MC1_ADDR 0x406 283167493Sjkim#define MSR_MC1_MISC 0x407 284167493Sjkim#define MSR_MC2_CTL 0x408 285167493Sjkim#define MSR_MC2_STATUS 0x409 286167493Sjkim#define MSR_MC2_ADDR 0x40a 287167493Sjkim#define MSR_MC2_MISC 0x40b 288167493Sjkim#define MSR_MC3_CTL 0x40c 289167493Sjkim#define MSR_MC3_STATUS 0x40d 290167493Sjkim#define MSR_MC3_ADDR 0x40e 291167493Sjkim#define MSR_MC3_MISC 0x40f 292167493Sjkim#define MSR_MC4_CTL 0x410 293167493Sjkim#define MSR_MC4_STATUS 0x411 294167493Sjkim#define MSR_MC4_ADDR 0x412 295167493Sjkim#define MSR_MC4_MISC 0x413 29645406Smsmith 29745406Smsmith/* 298118954Sjhb * Constants related to MSR's. 299118954Sjhb */ 300118954Sjhb#define APICBASE_RESERVED 0x000006ff 301118954Sjhb#define APICBASE_BSP 0x00000100 302118954Sjhb#define APICBASE_ENABLED 0x00000800 303118954Sjhb#define APICBASE_ADDRESS 0xfffff000 304118954Sjhb 305118954Sjhb/* 306158238Sjhb * PAT modes. 307158238Sjhb */ 308158238Sjhb#define PAT_UNCACHEABLE 0x00 309158238Sjhb#define PAT_WRITE_COMBINING 0x01 310158238Sjhb#define PAT_WRITE_THROUGH 0x04 311158238Sjhb#define PAT_WRITE_PROTECTED 0x05 312158238Sjhb#define PAT_WRITE_BACK 0x06 313158238Sjhb#define PAT_UNCACHED 0x07 314158238Sjhb#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 315158238Sjhb#define PAT_MASK(i) PAT_VALUE(i, 0xff) 316158238Sjhb 317158238Sjhb/* 31845406Smsmith * Constants related to MTRRs 31945406Smsmith */ 320177069Sjhb#define MTRR_UNCACHEABLE 0x00 321177069Sjhb#define MTRR_WRITE_COMBINING 0x01 322177069Sjhb#define MTRR_WRITE_THROUGH 0x04 323177069Sjhb#define MTRR_WRITE_PROTECTED 0x05 324177069Sjhb#define MTRR_WRITE_BACK 0x06 325167493Sjkim#define MTRR_N64K 8 /* numbers of fixed-size entries */ 326167493Sjkim#define MTRR_N16K 16 327167493Sjkim#define MTRR_N4K 64 328177069Sjhb#define MTRR_CAP_WC 0x0000000000000400ULL 329177069Sjhb#define MTRR_CAP_FIXED 0x0000000000000100ULL 330177069Sjhb#define MTRR_CAP_VCNT 0x00000000000000ffULL 331177069Sjhb#define MTRR_DEF_ENABLE 0x0000000000000800ULL 332177069Sjhb#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL 333177069Sjhb#define MTRR_DEF_TYPE 0x00000000000000ffULL 334177125Sjhb#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL 335177069Sjhb#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL 336177125Sjhb#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL 337177069Sjhb#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL 33845406Smsmith 33945406Smsmith/* 34024112Skato * Cyrix configuration registers, accessible as IO ports. 3412495Spst */ 34224112Skato#define CCR0 0xc0 /* Configuration control register 0 */ 34324112Skato#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 34424112Skato non-cacheable */ 34524112Skato#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 34624112Skato#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 34724112Skato#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 34824112Skato#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 34924112Skato#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 35024112Skato state */ 35124112Skato#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 35224112Skato assoc */ 35324112Skato#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 3542495Spst 35524112Skato#define CCR1 0xc1 /* Configuration control register 1 */ 35624112Skato#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 35724112Skato#define CCR1_SMI 0x02 /* Enables SMM pins */ 35824112Skato#define CCR1_SMAC 0x04 /* System management memory access */ 35924112Skato#define CCR1_MMAC 0x08 /* Main memory access */ 36024112Skato#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 36124112Skato#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 3622495Spst 36324112Skato#define CCR2 0xc2 36424112Skato#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 36524112Skato#define CCR2_SADS 0x02 /* Slow ADS */ 36624112Skato#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 36724112Skato#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 36824112Skato#define CCR2_WT1 0x10 /* WT region 1 */ 36924112Skato#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 370167493Sjkim#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 37124112Skato hold state. */ 37224112Skato#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 37324112Skato#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 37424112Skato 37524112Skato#define CCR3 0xc3 37624112Skato#define CCR3_SMILOCK 0x01 /* SMM register lock */ 37724112Skato#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 37824112Skato#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 37924112Skato#define CCR3_SMMMODE 0x08 /* SMM Mode */ 38024112Skato#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 38124112Skato#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 38224112Skato#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 38324112Skato#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 38424112Skato 38524112Skato#define CCR4 0xe8 38624112Skato#define CCR4_IOMASK 0x07 38724112Skato#define CCR4_MEM 0x08 /* Enables momory bypassing */ 38824112Skato#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 38924112Skato#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 39024112Skato#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 39124112Skato 39224112Skato#define CCR5 0xe9 39324112Skato#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 39424112Skato#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 39524112Skato#define CCR5_LBR1 0x10 /* Local bus region 1 */ 39624112Skato#define CCR5_ARREN 0x20 /* Enables ARR region */ 39724112Skato 39834031Skato#define CCR6 0xea 39934031Skato 40034031Skato#define CCR7 0xeb 40134031Skato 40224112Skato/* Performance Control Register (5x86 only). */ 40324112Skato#define PCR0 0x20 40424112Skato#define PCR0_RSTK 0x01 /* Enables return stack */ 40524112Skato#define PCR0_BTB 0x02 /* Enables branch target buffer */ 40624112Skato#define PCR0_LOOP 0x04 /* Enables loop */ 40724112Skato#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 40824112Skato serialize pipe. */ 40924112Skato#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 41024112Skato#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 41124112Skato#define PCR0_LSSER 0x80 /* Disable reorder */ 41224112Skato 41324112Skato/* Device Identification Registers */ 41424112Skato#define DIR0 0xfe 41524112Skato#define DIR1 0xff 41624112Skato 4172495Spst/* 418192050Sjhb * Machine Check register constants. 419192050Sjhb */ 420192050Sjhb#define MCG_CAP_COUNT 0x000000ff 421192050Sjhb#define MCG_CAP_CTL_P 0x00000100 422192050Sjhb#define MCG_CAP_EXT_P 0x00000200 423192050Sjhb#define MCG_CAP_TES_P 0x00000800 424192050Sjhb#define MCG_CAP_EXT_CNT 0x00ff0000 425192050Sjhb#define MCG_STATUS_RIPV 0x00000001 426192050Sjhb#define MCG_STATUS_EIPV 0x00000002 427192050Sjhb#define MCG_STATUS_MCIP 0x00000004 428192050Sjhb#define MCG_CTL_ENABLE 0xffffffffffffffffUL 429192050Sjhb#define MCG_CTL_DISABLE 0x0000000000000000UL 430192050Sjhb#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 431192050Sjhb#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 432192050Sjhb#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 433192050Sjhb#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 434192050Sjhb#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL 435192050Sjhb#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL 436192050Sjhb#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL 437192050Sjhb#define MC_STATUS_PCC 0x0200000000000000UL 438192050Sjhb#define MC_STATUS_ADDRV 0x0400000000000000UL 439192050Sjhb#define MC_STATUS_MISCV 0x0800000000000000UL 440192050Sjhb#define MC_STATUS_EN 0x1000000000000000UL 441192050Sjhb#define MC_STATUS_UC 0x2000000000000000UL 442192050Sjhb#define MC_STATUS_OVER 0x4000000000000000UL 443192050Sjhb#define MC_STATUS_VAL 0x8000000000000000UL 444192050Sjhb 445192050Sjhb/* 44624112Skato * The following four 3-byte registers control the non-cacheable regions. 44713765Smpp * These registers must be written as three separate bytes. 4482495Spst * 4492495Spst * NCRx+0: A31-A24 of starting address 4502495Spst * NCRx+1: A23-A16 of starting address 4512495Spst * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 4528876Srgrimes * 4532495Spst * The non-cacheable region's starting address must be aligned to the 4542495Spst * size indicated by the NCR_SIZE_xx field. 4552495Spst */ 45624112Skato#define NCR1 0xc4 45724112Skato#define NCR2 0xc7 45824112Skato#define NCR3 0xca 45924112Skato#define NCR4 0xcd 4602495Spst 46124112Skato#define NCR_SIZE_0K 0 46224112Skato#define NCR_SIZE_4K 1 46324112Skato#define NCR_SIZE_8K 2 46424112Skato#define NCR_SIZE_16K 3 46524112Skato#define NCR_SIZE_32K 4 46624112Skato#define NCR_SIZE_64K 5 46724112Skato#define NCR_SIZE_128K 6 46824112Skato#define NCR_SIZE_256K 7 46924112Skato#define NCR_SIZE_512K 8 47024112Skato#define NCR_SIZE_1M 9 47124112Skato#define NCR_SIZE_2M 10 47224112Skato#define NCR_SIZE_4M 11 47324112Skato#define NCR_SIZE_8M 12 47424112Skato#define NCR_SIZE_16M 13 47524112Skato#define NCR_SIZE_32M 14 47624112Skato#define NCR_SIZE_4G 15 4772495Spst 47824112Skato/* 47924112Skato * The address region registers are used to specify the location and 48024112Skato * size for the eight address regions. 48124112Skato * 48224112Skato * ARRx + 0: A31-A24 of start address 48324112Skato * ARRx + 1: A23-A16 of start address 48424112Skato * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 48524112Skato */ 48624112Skato#define ARR0 0xc4 48724112Skato#define ARR1 0xc7 48824112Skato#define ARR2 0xca 48924112Skato#define ARR3 0xcd 49024112Skato#define ARR4 0xd0 49124112Skato#define ARR5 0xd3 49224112Skato#define ARR6 0xd6 49324112Skato#define ARR7 0xd9 49424112Skato 49524112Skato#define ARR_SIZE_0K 0 49624112Skato#define ARR_SIZE_4K 1 49724112Skato#define ARR_SIZE_8K 2 49824112Skato#define ARR_SIZE_16K 3 49924112Skato#define ARR_SIZE_32K 4 50024112Skato#define ARR_SIZE_64K 5 50124112Skato#define ARR_SIZE_128K 6 50224112Skato#define ARR_SIZE_256K 7 50324112Skato#define ARR_SIZE_512K 8 50424112Skato#define ARR_SIZE_1M 9 50524112Skato#define ARR_SIZE_2M 10 50624112Skato#define ARR_SIZE_4M 11 50724112Skato#define ARR_SIZE_8M 12 50824112Skato#define ARR_SIZE_16M 13 50924112Skato#define ARR_SIZE_32M 14 51024112Skato#define ARR_SIZE_4G 15 51124112Skato 51224112Skato/* 51324112Skato * The region control registers specify the attributes associated with 51424112Skato * the ARRx addres regions. 51524112Skato */ 51624112Skato#define RCR0 0xdc 51724112Skato#define RCR1 0xdd 51824112Skato#define RCR2 0xde 51924112Skato#define RCR3 0xdf 52024112Skato#define RCR4 0xe0 52124112Skato#define RCR5 0xe1 52224112Skato#define RCR6 0xe2 52324112Skato#define RCR7 0xe3 52424112Skato 525167493Sjkim#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 526167493Sjkim#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 527167493Sjkim#define RCR_WWO 0x02 /* Weak write ordering. */ 52824112Skato#define RCR_WL 0x04 /* Weak locking. */ 529167493Sjkim#define RCR_WG 0x08 /* Write gathering. */ 53024112Skato#define RCR_WT 0x10 /* Write-through. */ 53124112Skato#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 53224112Skato 53340003Skato/* AMD Write Allocate Top-Of-Memory and Control Register */ 53440003Skato#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 53540003Skato#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 53640003Skato#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 53724112Skato 538168439Sru/* AMD64 MSR's */ 539168439Sru#define MSR_EFER 0xc0000080 /* extended features */ 540181430Sstas#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 541168439Sru 542160305Smr/* VIA ACE crypto featureset: for via_feature_rng */ 543167493Sjkim#define VIA_HAS_RNG 1 /* cpu has RNG */ 544160305Smr 545160305Smr/* VIA ACE crypto featureset: for via_feature_xcrypt */ 546167493Sjkim#define VIA_HAS_AES 1 /* cpu has AES */ 547167493Sjkim#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 548167493Sjkim#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 549167493Sjkim#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 55040003Skato 551160298Smr/* Centaur Extended Feature flags */ 552167493Sjkim#define VIA_CPUID_HAS_RNG 0x000004 553167493Sjkim#define VIA_CPUID_DO_RNG 0x000008 554167493Sjkim#define VIA_CPUID_HAS_ACE 0x000040 555167493Sjkim#define VIA_CPUID_DO_ACE 0x000080 556167493Sjkim#define VIA_CPUID_HAS_ACE2 0x000100 557167493Sjkim#define VIA_CPUID_DO_ACE2 0x000200 558167493Sjkim#define VIA_CPUID_HAS_PHE 0x000400 559167493Sjkim#define VIA_CPUID_DO_PHE 0x000800 560167493Sjkim#define VIA_CPUID_HAS_PMM 0x001000 561167493Sjkim#define VIA_CPUID_DO_PMM 0x002000 562160298Smr 563160298Smr/* VIA ACE xcrypt-* instruction context control options */ 564167493Sjkim#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 565167493Sjkim#define VIA_CRYPT_CWLO_ALG_M 0x00000070 566167493Sjkim#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 567167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 568167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 569167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 570167493Sjkim#define VIA_CRYPT_CWLO_NORMAL 0x00000000 571167493Sjkim#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 572167493Sjkim#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 573167493Sjkim#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 574167493Sjkim#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 575167493Sjkim#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 576167493Sjkim#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 577160298Smr 5785594Sbde#endif /* !_MACHINE_SPECIALREG_H_ */ 579