14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 4. Neither the name of the University nor the names of its contributors 144Srgrimes * may be used to endorse or promote products derived from this software 154Srgrimes * without specific prior written permission. 164Srgrimes * 174Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 184Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 194Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 204Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 214Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 224Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 234Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 244Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 254Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 264Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 274Srgrimes * SUCH DAMAGE. 284Srgrimes * 29621Srgrimes * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD$ 314Srgrimes */ 324Srgrimes 33719Swollman#ifndef _MACHINE_SPECIALREG_H_ 345594Sbde#define _MACHINE_SPECIALREG_H_ 35719Swollman 364Srgrimes/* 374Srgrimes * Bits in 386 special registers: 384Srgrimes */ 394Srgrimes#define CR0_PE 0x00000001 /* Protected mode Enable */ 40160329Sjkim#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41160329Sjkim#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 424Srgrimes#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 434Srgrimes#define CR0_PG 0x80000000 /* PaGing enable */ 444Srgrimes 454Srgrimes/* 464Srgrimes * Bits in 486 special registers: 474Srgrimes */ 4824112Skato#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 4924112Skato#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 5024112Skato all modes) */ 5124112Skato#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 5224112Skato#define CR0_NW 0x20000000 /* Not Write-through */ 5324112Skato#define CR0_CD 0x40000000 /* Cache Disable */ 542495Spst 55242432Skib#define CR3_PCID_SAVE 0x8000000000000000 56242432Skib 572495Spst/* 5819621Sdyson * Bits in PPro special registers 5919621Sdyson */ 6019621Sdyson#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 6119621Sdyson#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 6219621Sdyson#define CR4_TSD 0x00000004 /* Time stamp disable */ 6319621Sdyson#define CR4_DE 0x00000008 /* Debugging extensions */ 6419621Sdyson#define CR4_PSE 0x00000010 /* Page size extensions */ 6519621Sdyson#define CR4_PAE 0x00000020 /* Physical address extension */ 6619621Sdyson#define CR4_MCE 0x00000040 /* Machine check enable */ 6719621Sdyson#define CR4_PGE 0x00000080 /* Page global enable */ 6819621Sdyson#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 6951127Speter#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 7051127Speter#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 71245055Sneel#define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 72242432Skib#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 73242432Skib#define CR4_PCIDE 0x00020000 /* Enable Context ID */ 74230261Skib#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 75242432Skib#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 7619621Sdyson 7719621Sdyson/* 78168439Sru * Bits in AMD64 special registers. EFER is 64 bits wide. 79168439Sru */ 80233207Stijl#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 81233207Stijl#define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 82233207Stijl#define EFER_LMA 0x000000400 /* Long mode active (R) */ 83168439Sru#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 84168439Sru 85168439Sru/* 86233207Stijl * Intel Extended Features registers 87233207Stijl */ 88233207Stijl#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 89233207Stijl 90233207Stijl#define XFEATURE_ENABLED_X87 0x00000001 91233207Stijl#define XFEATURE_ENABLED_SSE 0x00000002 92233207Stijl#define XFEATURE_ENABLED_AVX 0x00000004 93233207Stijl 94233207Stijl#define XFEATURE_AVX \ 95233207Stijl (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 96233207Stijl 97233207Stijl/* 9819621Sdyson * CPUID instruction features register 9919621Sdyson */ 10098650Smp#define CPUID_FPU 0x00000001 10198650Smp#define CPUID_VME 0x00000002 10298650Smp#define CPUID_DE 0x00000004 10398650Smp#define CPUID_PSE 0x00000008 10498650Smp#define CPUID_TSC 0x00000010 10598650Smp#define CPUID_MSR 0x00000020 10698650Smp#define CPUID_PAE 0x00000040 10798650Smp#define CPUID_MCE 0x00000080 10898650Smp#define CPUID_CX8 0x00000100 10998650Smp#define CPUID_APIC 0x00000200 11098650Smp#define CPUID_B10 0x00000400 11198650Smp#define CPUID_SEP 0x00000800 11298650Smp#define CPUID_MTRR 0x00001000 11398650Smp#define CPUID_PGE 0x00002000 11498650Smp#define CPUID_MCA 0x00004000 11598650Smp#define CPUID_CMOV 0x00008000 11698650Smp#define CPUID_PAT 0x00010000 11798650Smp#define CPUID_PSE36 0x00020000 11898650Smp#define CPUID_PSN 0x00040000 11998650Smp#define CPUID_CLFSH 0x00080000 12098650Smp#define CPUID_B20 0x00100000 12198650Smp#define CPUID_DS 0x00200000 12298650Smp#define CPUID_ACPI 0x00400000 12398650Smp#define CPUID_MMX 0x00800000 12498650Smp#define CPUID_FXSR 0x01000000 12598650Smp#define CPUID_SSE 0x02000000 12698650Smp#define CPUID_XMM 0x02000000 12798650Smp#define CPUID_SSE2 0x04000000 12898650Smp#define CPUID_SS 0x08000000 129108909Sjhb#define CPUID_HTT 0x10000000 13098650Smp#define CPUID_TM 0x20000000 131114376Speter#define CPUID_IA64 0x40000000 13298650Smp#define CPUID_PBE 0x80000000 13319621Sdyson 134167493Sjkim#define CPUID2_SSE3 0x00000001 135207676Skib#define CPUID2_PCLMULQDQ 0x00000002 136183128Sjhb#define CPUID2_DTES64 0x00000004 137167493Sjkim#define CPUID2_MON 0x00000008 138167493Sjkim#define CPUID2_DS_CPL 0x00000010 139167493Sjkim#define CPUID2_VMX 0x00000020 140167744Sjkim#define CPUID2_SMX 0x00000040 141167493Sjkim#define CPUID2_EST 0x00000080 142167493Sjkim#define CPUID2_TM2 0x00000100 143167493Sjkim#define CPUID2_SSSE3 0x00000200 144167493Sjkim#define CPUID2_CNXTID 0x00000400 145222043Sjkim#define CPUID2_FMA 0x00001000 146167493Sjkim#define CPUID2_CX16 0x00002000 147167493Sjkim#define CPUID2_XTPR 0x00004000 148170150Sdes#define CPUID2_PDCM 0x00008000 149213452Skib#define CPUID2_PCID 0x00020000 150167744Sjkim#define CPUID2_DCA 0x00040000 151183128Sjhb#define CPUID2_SSE41 0x00080000 152183128Sjhb#define CPUID2_SSE42 0x00100000 153183128Sjhb#define CPUID2_X2APIC 0x00200000 154199968Savg#define CPUID2_MOVBE 0x00400000 155183128Sjhb#define CPUID2_POPCNT 0x00800000 156222043Sjkim#define CPUID2_TSCDLT 0x01000000 157207676Skib#define CPUID2_AESNI 0x02000000 158222043Sjkim#define CPUID2_XSAVE 0x04000000 159222043Sjkim#define CPUID2_OSXSAVE 0x08000000 160222043Sjkim#define CPUID2_AVX 0x10000000 161222043Sjkim#define CPUID2_F16C 0x20000000 162234059Sjhb#define CPUID2_RDRAND 0x40000000 163221188Sjkim#define CPUID2_HV 0x80000000 164160329Sjkim 16519621Sdyson/* 166215748Savg * Important bits in the Thermal and Power Management flags 167215748Savg * CPUID.6 EAX and ECX. 168215748Savg */ 169215748Savg#define CPUTPM1_SENSOR 0x00000001 170215748Savg#define CPUTPM1_TURBO 0x00000002 171215748Savg#define CPUTPM1_ARAT 0x00000004 172215748Savg#define CPUTPM2_EFFREQ 0x00000001 173215748Savg 174215748Savg/* 175151348Sjkim * Important bits in the AMD extended cpuid flags 176151348Sjkim */ 177167493Sjkim#define AMDID_SYSCALL 0x00000800 178167493Sjkim#define AMDID_MP 0x00080000 179167493Sjkim#define AMDID_NX 0x00100000 180167493Sjkim#define AMDID_EXT_MMX 0x00400000 181167493Sjkim#define AMDID_FFXSR 0x01000000 182183128Sjhb#define AMDID_PAGE1GB 0x04000000 183167493Sjkim#define AMDID_RDTSCP 0x08000000 184167493Sjkim#define AMDID_LM 0x20000000 185167493Sjkim#define AMDID_EXT_3DNOW 0x40000000 186167493Sjkim#define AMDID_3DNOW 0x80000000 187151348Sjkim 188167493Sjkim#define AMDID2_LAHF 0x00000001 189167493Sjkim#define AMDID2_CMP 0x00000002 190167493Sjkim#define AMDID2_SVM 0x00000004 191167493Sjkim#define AMDID2_EXT_APIC 0x00000008 192167493Sjkim#define AMDID2_CR8 0x00000010 193186009Sjkim#define AMDID2_ABM 0x00000020 194186009Sjkim#define AMDID2_SSE4A 0x00000040 195186009Sjkim#define AMDID2_MAS 0x00000080 196167493Sjkim#define AMDID2_PREFETCH 0x00000100 197186009Sjkim#define AMDID2_OSVW 0x00000200 198186009Sjkim#define AMDID2_IBS 0x00000400 199222043Sjkim#define AMDID2_XOP 0x00000800 200186009Sjkim#define AMDID2_SKINIT 0x00001000 201186009Sjkim#define AMDID2_WDT 0x00002000 202222043Sjkim#define AMDID2_LWP 0x00008000 203222043Sjkim#define AMDID2_FMA4 0x00010000 204258159Skib#define AMDID2_TCE 0x00020000 205222043Sjkim#define AMDID2_NODE_ID 0x00080000 206222043Sjkim#define AMDID2_TBM 0x00200000 207222043Sjkim#define AMDID2_TOPOLOGY 0x00400000 208258159Skib#define AMDID2_PCXC 0x00800000 209258159Skib#define AMDID2_PNXC 0x01000000 210258159Skib#define AMDID2_DBE 0x04000000 211258159Skib#define AMDID2_PTSC 0x08000000 212258159Skib#define AMDID2_PTSCEL2I 0x10000000 213151348Sjkim 214151348Sjkim/* 215184146Sjkim * CPUID instruction 1 eax info 216184146Sjkim */ 217184146Sjkim#define CPUID_STEPPING 0x0000000f 218184146Sjkim#define CPUID_MODEL 0x000000f0 219184146Sjkim#define CPUID_FAMILY 0x00000f00 220184146Sjkim#define CPUID_EXT_MODEL 0x000f0000 221184146Sjkim#define CPUID_EXT_FAMILY 0x0ff00000 222233207Stijl#ifdef __i386__ 223197070Sjkim#define CPUID_TO_MODEL(id) \ 224184146Sjkim ((((id) & CPUID_MODEL) >> 4) | \ 225184146Sjkim ((((id) & CPUID_FAMILY) >= 0x600) ? \ 226184146Sjkim (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 227197070Sjkim#define CPUID_TO_FAMILY(id) \ 228184146Sjkim ((((id) & CPUID_FAMILY) >> 8) + \ 229184146Sjkim ((((id) & CPUID_FAMILY) == 0xf00) ? \ 230184146Sjkim (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 231233207Stijl#else 232233207Stijl#define CPUID_TO_MODEL(id) \ 233233207Stijl ((((id) & CPUID_MODEL) >> 4) | \ 234233207Stijl (((id) & CPUID_EXT_MODEL) >> 12)) 235233207Stijl#define CPUID_TO_FAMILY(id) \ 236233207Stijl ((((id) & CPUID_FAMILY) >> 8) + \ 237233207Stijl (((id) & CPUID_EXT_FAMILY) >> 20)) 238233207Stijl#endif 239184146Sjkim 240184146Sjkim/* 241109691Sjhb * CPUID instruction 1 ebx info 242108909Sjhb */ 243108909Sjhb#define CPUID_BRAND_INDEX 0x000000ff 244108909Sjhb#define CPUID_CLFUSH_SIZE 0x0000ff00 245108909Sjhb#define CPUID_HTT_CORES 0x00ff0000 246108909Sjhb#define CPUID_LOCAL_APIC_ID 0xff000000 247108909Sjhb 248220578Sjkim/* 249253747Savg * CPUID instruction 5 info 250253747Savg */ 251253747Savg#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 252253747Savg#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 253253747Savg#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 254253747Savg#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 255253747Savg 256253747Savg/* 257253747Savg * MWAIT cpu power states. Lower 4 bits are sub-states. 258253747Savg */ 259253747Savg#define MWAIT_C0 0xf0 260253747Savg#define MWAIT_C1 0x00 261253747Savg#define MWAIT_C2 0x10 262253747Savg#define MWAIT_C3 0x20 263253747Savg#define MWAIT_C4 0x30 264253747Savg 265253747Savg/* 266253747Savg * MWAIT extensions. 267253747Savg */ 268253747Savg/* Interrupt breaks MWAIT even when masked. */ 269253747Savg#define MWAIT_INTRBREAK 0x00000001 270253747Savg 271253747Savg/* 272220578Sjkim * CPUID instruction 6 ecx info 273220578Sjkim */ 274220578Sjkim#define CPUID_PERF_STAT 0x00000001 275220578Sjkim#define CPUID_PERF_BIAS 0x00000008 276220578Sjkim 277191648Sjeff/* 278191648Sjeff * CPUID instruction 0xb ebx info. 279191648Sjeff */ 280191648Sjeff#define CPUID_TYPE_INVAL 0 281191648Sjeff#define CPUID_TYPE_SMT 1 282191648Sjeff#define CPUID_TYPE_CORE 2 283191648Sjeff 284108909Sjhb/* 285238450Skib * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 286238450Skib */ 287238450Skib#define CPUID_EXTSTATE_XSAVEOPT 0x00000001 288238450Skib 289238450Skib/* 290184101Sjkim * AMD extended function 8000_0007h edx info 291184101Sjkim */ 292184101Sjkim#define AMDPM_TS 0x00000001 293184101Sjkim#define AMDPM_FID 0x00000002 294184101Sjkim#define AMDPM_VID 0x00000004 295184101Sjkim#define AMDPM_TTP 0x00000008 296184101Sjkim#define AMDPM_TM 0x00000010 297184101Sjkim#define AMDPM_STC 0x00000020 298184101Sjkim#define AMDPM_100MHZ_STEPS 0x00000040 299184101Sjkim#define AMDPM_HW_PSTATE 0x00000080 300184101Sjkim#define AMDPM_TSC_INVARIANT 0x00000100 301215522Savg#define AMDPM_CPB 0x00000200 302184101Sjkim 303184101Sjkim/* 304151348Sjkim * AMD extended function 8000_0008h ecx info 305151348Sjkim */ 306167493Sjkim#define AMDID_CMP_CORES 0x000000ff 307221527Savg#define AMDID_COREID_SIZE 0x0000f000 308221527Savg#define AMDID_COREID_SIZE_SHIFT 12 309151348Sjkim 310249608Srpaulo/* 311249608Srpaulo * Structured Extended Features 312249608Srpaulo */ 313242432Skib#define CPUID_STDEXT_FSGSBASE 0x00000001 314242432Skib#define CPUID_STDEXT_TSC_ADJUST 0x00000002 315249608Srpaulo#define CPUID_STDEXT_BMI1 0x00000008 316249608Srpaulo#define CPUID_STDEXT_HLE 0x00000010 317249608Srpaulo#define CPUID_STDEXT_AVX2 0x00000020 318242432Skib#define CPUID_STDEXT_SMEP 0x00000080 319249608Srpaulo#define CPUID_STDEXT_BMI2 0x00000100 320242432Skib#define CPUID_STDEXT_ENH_MOVSB 0x00000200 321249608Srpaulo#define CPUID_STDEXT_RTM 0x00000800 322242432Skib#define CPUID_STDEXT_INVPCID 0x00000400 323249608Srpaulo#define CPUID_STDEXT_RDSEED 0x00040000 324249608Srpaulo#define CPUID_STDEXT_ADX 0x00080000 325249608Srpaulo#define CPUID_STDEXT_SMAP 0x00100000 326242432Skib 327151348Sjkim/* 328181430Sstas * CPUID manufacturers identifiers 329181430Sstas */ 330185341Sjkim#define AMD_VENDOR_ID "AuthenticAMD" 331185341Sjkim#define CENTAUR_VENDOR_ID "CentaurHauls" 332185341Sjkim#define CYRIX_VENDOR_ID "CyrixInstead" 333185341Sjkim#define INTEL_VENDOR_ID "GenuineIntel" 334185341Sjkim#define NEXGEN_VENDOR_ID "NexGenDriven" 335185341Sjkim#define NSC_VENDOR_ID "Geode by NSC" 336185341Sjkim#define RISE_VENDOR_ID "RiseRiseRise" 337185341Sjkim#define SIS_VENDOR_ID "SiS SiS SiS " 338185341Sjkim#define TRANSMETA_VENDOR_ID "GenuineTMx86" 339185341Sjkim#define UMC_VENDOR_ID "UMC UMC UMC " 340181430Sstas 341181430Sstas/* 34245406Smsmith * Model-specific registers for the i386 family 34345406Smsmith */ 344167493Sjkim#define MSR_P5_MC_ADDR 0x000 345167493Sjkim#define MSR_P5_MC_TYPE 0x001 346167493Sjkim#define MSR_TSC 0x010 347118954Sjhb#define MSR_P5_CESR 0x011 348118954Sjhb#define MSR_P5_CTR0 0x012 349118954Sjhb#define MSR_P5_CTR1 0x013 350118954Sjhb#define MSR_IA32_PLATFORM_ID 0x017 351167493Sjkim#define MSR_APICBASE 0x01b 352167493Sjkim#define MSR_EBL_CR_POWERON 0x02a 353118954Sjhb#define MSR_TEST_CTL 0x033 354245055Sneel#define MSR_IA32_FEATURE_CONTROL 0x03a 355167493Sjkim#define MSR_BIOS_UPDT_TRIG 0x079 356118954Sjhb#define MSR_BBL_CR_D0 0x088 357118954Sjhb#define MSR_BBL_CR_D1 0x089 358118954Sjhb#define MSR_BBL_CR_D2 0x08a 359167493Sjkim#define MSR_BIOS_SIGN 0x08b 360167493Sjkim#define MSR_PERFCTR0 0x0c1 361167493Sjkim#define MSR_PERFCTR1 0x0c2 362215524Savg#define MSR_MPERF 0x0e7 363215524Savg#define MSR_APERF 0x0e8 364171854Sdes#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 365167493Sjkim#define MSR_MTRRcap 0x0fe 366118954Sjhb#define MSR_BBL_CR_ADDR 0x116 367118954Sjhb#define MSR_BBL_CR_DECC 0x118 368118954Sjhb#define MSR_BBL_CR_CTL 0x119 369118954Sjhb#define MSR_BBL_CR_TRIG 0x11a 370118954Sjhb#define MSR_BBL_CR_BUSY 0x11b 371118954Sjhb#define MSR_BBL_CR_CTL3 0x11e 372118954Sjhb#define MSR_SYSENTER_CS_MSR 0x174 373118954Sjhb#define MSR_SYSENTER_ESP_MSR 0x175 374118954Sjhb#define MSR_SYSENTER_EIP_MSR 0x176 375167493Sjkim#define MSR_MCG_CAP 0x179 376167493Sjkim#define MSR_MCG_STATUS 0x17a 377167493Sjkim#define MSR_MCG_CTL 0x17b 378167493Sjkim#define MSR_EVNTSEL0 0x186 379167493Sjkim#define MSR_EVNTSEL1 0x187 380167493Sjkim#define MSR_THERM_CONTROL 0x19a 381167493Sjkim#define MSR_THERM_INTERRUPT 0x19b 382167493Sjkim#define MSR_THERM_STATUS 0x19c 383159768Sdavidxu#define MSR_IA32_MISC_ENABLE 0x1a0 384210624Sdelphij#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 385167493Sjkim#define MSR_DEBUGCTLMSR 0x1d9 386167493Sjkim#define MSR_LASTBRANCHFROMIP 0x1db 387167493Sjkim#define MSR_LASTBRANCHTOIP 0x1dc 388167493Sjkim#define MSR_LASTINTFROMIP 0x1dd 389167493Sjkim#define MSR_LASTINTTOIP 0x1de 390167493Sjkim#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 391167493Sjkim#define MSR_MTRRVarBase 0x200 392167493Sjkim#define MSR_MTRR64kBase 0x250 393167493Sjkim#define MSR_MTRR16kBase 0x258 394167493Sjkim#define MSR_MTRR4kBase 0x268 395167493Sjkim#define MSR_PAT 0x277 396205214Sjhb#define MSR_MC0_CTL2 0x280 397167493Sjkim#define MSR_MTRRdefType 0x2ff 398167493Sjkim#define MSR_MC0_CTL 0x400 399167493Sjkim#define MSR_MC0_STATUS 0x401 400167493Sjkim#define MSR_MC0_ADDR 0x402 401167493Sjkim#define MSR_MC0_MISC 0x403 402167493Sjkim#define MSR_MC1_CTL 0x404 403167493Sjkim#define MSR_MC1_STATUS 0x405 404167493Sjkim#define MSR_MC1_ADDR 0x406 405167493Sjkim#define MSR_MC1_MISC 0x407 406167493Sjkim#define MSR_MC2_CTL 0x408 407167493Sjkim#define MSR_MC2_STATUS 0x409 408167493Sjkim#define MSR_MC2_ADDR 0x40a 409167493Sjkim#define MSR_MC2_MISC 0x40b 410167493Sjkim#define MSR_MC3_CTL 0x40c 411167493Sjkim#define MSR_MC3_STATUS 0x40d 412167493Sjkim#define MSR_MC3_ADDR 0x40e 413167493Sjkim#define MSR_MC3_MISC 0x40f 414167493Sjkim#define MSR_MC4_CTL 0x410 415167493Sjkim#define MSR_MC4_STATUS 0x411 416167493Sjkim#define MSR_MC4_ADDR 0x412 417167493Sjkim#define MSR_MC4_MISC 0x413 41845406Smsmith 41945406Smsmith/* 420234364Sgrehan * X2APIC MSRs 421234364Sgrehan */ 422234364Sgrehan#define MSR_APIC_ID 0x802 423234364Sgrehan#define MSR_APIC_VERSION 0x803 424234364Sgrehan#define MSR_APIC_TPR 0x808 425234364Sgrehan#define MSR_APIC_EOI 0x80b 426234364Sgrehan#define MSR_APIC_LDR 0x80d 427234364Sgrehan#define MSR_APIC_SVR 0x80f 428234364Sgrehan#define MSR_APIC_ISR0 0x810 429234364Sgrehan#define MSR_APIC_ISR1 0x811 430234364Sgrehan#define MSR_APIC_ISR2 0x812 431234364Sgrehan#define MSR_APIC_ISR3 0x813 432234364Sgrehan#define MSR_APIC_ISR4 0x814 433234364Sgrehan#define MSR_APIC_ISR5 0x815 434234364Sgrehan#define MSR_APIC_ISR6 0x816 435234364Sgrehan#define MSR_APIC_ISR7 0x817 436234364Sgrehan#define MSR_APIC_TMR0 0x818 437234364Sgrehan#define MSR_APIC_IRR0 0x820 438234364Sgrehan#define MSR_APIC_ESR 0x828 439234364Sgrehan#define MSR_APIC_LVT_CMCI 0x82F 440234364Sgrehan#define MSR_APIC_ICR 0x830 441234364Sgrehan#define MSR_APIC_LVT_TIMER 0x832 442234364Sgrehan#define MSR_APIC_LVT_THERMAL 0x833 443234364Sgrehan#define MSR_APIC_LVT_PCINT 0x834 444234364Sgrehan#define MSR_APIC_LVT_LINT0 0x835 445234364Sgrehan#define MSR_APIC_LVT_LINT1 0x836 446234364Sgrehan#define MSR_APIC_LVT_ERROR 0x837 447234364Sgrehan#define MSR_APIC_ICR_TIMER 0x838 448234364Sgrehan#define MSR_APIC_CCR_TIMER 0x839 449234364Sgrehan#define MSR_APIC_DCR_TIMER 0x83e 450234364Sgrehan#define MSR_APIC_SELF_IPI 0x83f 451234364Sgrehan 452234364Sgrehan/* 453118954Sjhb * Constants related to MSR's. 454118954Sjhb */ 455234364Sgrehan#define APICBASE_RESERVED 0x000002ff 456118954Sjhb#define APICBASE_BSP 0x00000100 457234364Sgrehan#define APICBASE_X2APIC 0x00000400 458118954Sjhb#define APICBASE_ENABLED 0x00000800 459118954Sjhb#define APICBASE_ADDRESS 0xfffff000 460118954Sjhb 461249351Sneel/* MSR_IA32_FEATURE_CONTROL related */ 462249351Sneel#define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 463249351Sneel#define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 464249351Sneel#define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 465249351Sneel 466118954Sjhb/* 467158238Sjhb * PAT modes. 468158238Sjhb */ 469158238Sjhb#define PAT_UNCACHEABLE 0x00 470158238Sjhb#define PAT_WRITE_COMBINING 0x01 471158238Sjhb#define PAT_WRITE_THROUGH 0x04 472158238Sjhb#define PAT_WRITE_PROTECTED 0x05 473158238Sjhb#define PAT_WRITE_BACK 0x06 474158238Sjhb#define PAT_UNCACHED 0x07 475158238Sjhb#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 476158238Sjhb#define PAT_MASK(i) PAT_VALUE(i, 0xff) 477158238Sjhb 478158238Sjhb/* 47945406Smsmith * Constants related to MTRRs 48045406Smsmith */ 481177069Sjhb#define MTRR_UNCACHEABLE 0x00 482177069Sjhb#define MTRR_WRITE_COMBINING 0x01 483177069Sjhb#define MTRR_WRITE_THROUGH 0x04 484177069Sjhb#define MTRR_WRITE_PROTECTED 0x05 485177069Sjhb#define MTRR_WRITE_BACK 0x06 486167493Sjkim#define MTRR_N64K 8 /* numbers of fixed-size entries */ 487167493Sjkim#define MTRR_N16K 16 488167493Sjkim#define MTRR_N4K 64 489205448Sjhb#define MTRR_CAP_WC 0x0000000000000400 490205448Sjhb#define MTRR_CAP_FIXED 0x0000000000000100 491205448Sjhb#define MTRR_CAP_VCNT 0x00000000000000ff 492205448Sjhb#define MTRR_DEF_ENABLE 0x0000000000000800 493205448Sjhb#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 494205448Sjhb#define MTRR_DEF_TYPE 0x00000000000000ff 495205448Sjhb#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 496205448Sjhb#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 497205448Sjhb#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 498205448Sjhb#define MTRR_PHYSMASK_VALID 0x0000000000000800 49945406Smsmith 50045406Smsmith/* 50124112Skato * Cyrix configuration registers, accessible as IO ports. 5022495Spst */ 50324112Skato#define CCR0 0xc0 /* Configuration control register 0 */ 50424112Skato#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 50524112Skato non-cacheable */ 50624112Skato#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 50724112Skato#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 50824112Skato#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 50924112Skato#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 51024112Skato#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 51124112Skato state */ 51224112Skato#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 51324112Skato assoc */ 51424112Skato#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 5152495Spst 51624112Skato#define CCR1 0xc1 /* Configuration control register 1 */ 51724112Skato#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 51824112Skato#define CCR1_SMI 0x02 /* Enables SMM pins */ 51924112Skato#define CCR1_SMAC 0x04 /* System management memory access */ 52024112Skato#define CCR1_MMAC 0x08 /* Main memory access */ 52124112Skato#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 52224112Skato#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 5232495Spst 52424112Skato#define CCR2 0xc2 52524112Skato#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 52624112Skato#define CCR2_SADS 0x02 /* Slow ADS */ 52724112Skato#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 52824112Skato#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 52924112Skato#define CCR2_WT1 0x10 /* WT region 1 */ 53024112Skato#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 531167493Sjkim#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 53224112Skato hold state. */ 53324112Skato#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 53424112Skato#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 53524112Skato 53624112Skato#define CCR3 0xc3 53724112Skato#define CCR3_SMILOCK 0x01 /* SMM register lock */ 53824112Skato#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 53924112Skato#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 54024112Skato#define CCR3_SMMMODE 0x08 /* SMM Mode */ 54124112Skato#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 54224112Skato#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 54324112Skato#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 54424112Skato#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 54524112Skato 54624112Skato#define CCR4 0xe8 54724112Skato#define CCR4_IOMASK 0x07 54824112Skato#define CCR4_MEM 0x08 /* Enables momory bypassing */ 54924112Skato#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 55024112Skato#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 55124112Skato#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 55224112Skato 55324112Skato#define CCR5 0xe9 55424112Skato#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 55524112Skato#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 55624112Skato#define CCR5_LBR1 0x10 /* Local bus region 1 */ 55724112Skato#define CCR5_ARREN 0x20 /* Enables ARR region */ 55824112Skato 55934031Skato#define CCR6 0xea 56034031Skato 56134031Skato#define CCR7 0xeb 56234031Skato 56324112Skato/* Performance Control Register (5x86 only). */ 56424112Skato#define PCR0 0x20 56524112Skato#define PCR0_RSTK 0x01 /* Enables return stack */ 56624112Skato#define PCR0_BTB 0x02 /* Enables branch target buffer */ 56724112Skato#define PCR0_LOOP 0x04 /* Enables loop */ 56824112Skato#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 56924112Skato serialize pipe. */ 57024112Skato#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 57124112Skato#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 57224112Skato#define PCR0_LSSER 0x80 /* Disable reorder */ 57324112Skato 57424112Skato/* Device Identification Registers */ 57524112Skato#define DIR0 0xfe 57624112Skato#define DIR1 0xff 57724112Skato 5782495Spst/* 579192050Sjhb * Machine Check register constants. 580192050Sjhb */ 581192050Sjhb#define MCG_CAP_COUNT 0x000000ff 582192050Sjhb#define MCG_CAP_CTL_P 0x00000100 583192050Sjhb#define MCG_CAP_EXT_P 0x00000200 584205214Sjhb#define MCG_CAP_CMCI_P 0x00000400 585192050Sjhb#define MCG_CAP_TES_P 0x00000800 586192050Sjhb#define MCG_CAP_EXT_CNT 0x00ff0000 587205214Sjhb#define MCG_CAP_SER_P 0x01000000 588192050Sjhb#define MCG_STATUS_RIPV 0x00000001 589192050Sjhb#define MCG_STATUS_EIPV 0x00000002 590192050Sjhb#define MCG_STATUS_MCIP 0x00000004 591205448Sjhb#define MCG_CTL_ENABLE 0xffffffffffffffff 592205448Sjhb#define MCG_CTL_DISABLE 0x0000000000000000 593192050Sjhb#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 594192050Sjhb#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 595192050Sjhb#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 596192050Sjhb#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 597205214Sjhb#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 598205448Sjhb#define MC_STATUS_MCA_ERROR 0x000000000000ffff 599205448Sjhb#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 600205448Sjhb#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 601210577Sjhb#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 602205448Sjhb#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 603210577Sjhb#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 604210577Sjhb#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 605205448Sjhb#define MC_STATUS_PCC 0x0200000000000000 606205448Sjhb#define MC_STATUS_ADDRV 0x0400000000000000 607205448Sjhb#define MC_STATUS_MISCV 0x0800000000000000 608205448Sjhb#define MC_STATUS_EN 0x1000000000000000 609205448Sjhb#define MC_STATUS_UC 0x2000000000000000 610205448Sjhb#define MC_STATUS_OVER 0x4000000000000000 611205448Sjhb#define MC_STATUS_VAL 0x8000000000000000 612205448Sjhb#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 613205448Sjhb#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 614208507Sjhb#define MC_CTL2_THRESHOLD 0x0000000000007fff 615205448Sjhb#define MC_CTL2_CMCI_EN 0x0000000040000000 616192050Sjhb 617192050Sjhb/* 61824112Skato * The following four 3-byte registers control the non-cacheable regions. 61913765Smpp * These registers must be written as three separate bytes. 6202495Spst * 6212495Spst * NCRx+0: A31-A24 of starting address 6222495Spst * NCRx+1: A23-A16 of starting address 6232495Spst * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 6248876Srgrimes * 6252495Spst * The non-cacheable region's starting address must be aligned to the 6262495Spst * size indicated by the NCR_SIZE_xx field. 6272495Spst */ 62824112Skato#define NCR1 0xc4 62924112Skato#define NCR2 0xc7 63024112Skato#define NCR3 0xca 63124112Skato#define NCR4 0xcd 6322495Spst 63324112Skato#define NCR_SIZE_0K 0 63424112Skato#define NCR_SIZE_4K 1 63524112Skato#define NCR_SIZE_8K 2 63624112Skato#define NCR_SIZE_16K 3 63724112Skato#define NCR_SIZE_32K 4 63824112Skato#define NCR_SIZE_64K 5 63924112Skato#define NCR_SIZE_128K 6 64024112Skato#define NCR_SIZE_256K 7 64124112Skato#define NCR_SIZE_512K 8 64224112Skato#define NCR_SIZE_1M 9 64324112Skato#define NCR_SIZE_2M 10 64424112Skato#define NCR_SIZE_4M 11 64524112Skato#define NCR_SIZE_8M 12 64624112Skato#define NCR_SIZE_16M 13 64724112Skato#define NCR_SIZE_32M 14 64824112Skato#define NCR_SIZE_4G 15 6492495Spst 65024112Skato/* 65124112Skato * The address region registers are used to specify the location and 65224112Skato * size for the eight address regions. 65324112Skato * 65424112Skato * ARRx + 0: A31-A24 of start address 65524112Skato * ARRx + 1: A23-A16 of start address 65624112Skato * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 65724112Skato */ 65824112Skato#define ARR0 0xc4 65924112Skato#define ARR1 0xc7 66024112Skato#define ARR2 0xca 66124112Skato#define ARR3 0xcd 66224112Skato#define ARR4 0xd0 66324112Skato#define ARR5 0xd3 66424112Skato#define ARR6 0xd6 66524112Skato#define ARR7 0xd9 66624112Skato 66724112Skato#define ARR_SIZE_0K 0 66824112Skato#define ARR_SIZE_4K 1 66924112Skato#define ARR_SIZE_8K 2 67024112Skato#define ARR_SIZE_16K 3 67124112Skato#define ARR_SIZE_32K 4 67224112Skato#define ARR_SIZE_64K 5 67324112Skato#define ARR_SIZE_128K 6 67424112Skato#define ARR_SIZE_256K 7 67524112Skato#define ARR_SIZE_512K 8 67624112Skato#define ARR_SIZE_1M 9 67724112Skato#define ARR_SIZE_2M 10 67824112Skato#define ARR_SIZE_4M 11 67924112Skato#define ARR_SIZE_8M 12 68024112Skato#define ARR_SIZE_16M 13 68124112Skato#define ARR_SIZE_32M 14 68224112Skato#define ARR_SIZE_4G 15 68324112Skato 68424112Skato/* 68524112Skato * The region control registers specify the attributes associated with 68624112Skato * the ARRx addres regions. 68724112Skato */ 68824112Skato#define RCR0 0xdc 68924112Skato#define RCR1 0xdd 69024112Skato#define RCR2 0xde 69124112Skato#define RCR3 0xdf 69224112Skato#define RCR4 0xe0 69324112Skato#define RCR5 0xe1 69424112Skato#define RCR6 0xe2 69524112Skato#define RCR7 0xe3 69624112Skato 697167493Sjkim#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 698167493Sjkim#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 699167493Sjkim#define RCR_WWO 0x02 /* Weak write ordering. */ 70024112Skato#define RCR_WL 0x04 /* Weak locking. */ 701167493Sjkim#define RCR_WG 0x08 /* Write gathering. */ 70224112Skato#define RCR_WT 0x10 /* Write-through. */ 70324112Skato#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 70424112Skato 70540003Skato/* AMD Write Allocate Top-Of-Memory and Control Register */ 70640003Skato#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 70740003Skato#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 70840003Skato#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 70924112Skato 710168439Sru/* AMD64 MSR's */ 711233207Stijl#define MSR_EFER 0xc0000080 /* extended features */ 712233207Stijl#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 713233207Stijl#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 714233207Stijl#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 715233207Stijl#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 716233207Stijl#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 717233207Stijl#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 718233207Stijl#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 719233207Stijl#define MSR_PERFEVSEL0 0xc0010000 720233207Stijl#define MSR_PERFEVSEL1 0xc0010001 721233207Stijl#define MSR_PERFEVSEL2 0xc0010002 722233207Stijl#define MSR_PERFEVSEL3 0xc0010003 723233207Stijl#undef MSR_PERFCTR0 724233207Stijl#undef MSR_PERFCTR1 725233207Stijl#define MSR_PERFCTR0 0xc0010004 726233207Stijl#define MSR_PERFCTR1 0xc0010005 727233207Stijl#define MSR_PERFCTR2 0xc0010006 728233207Stijl#define MSR_PERFCTR3 0xc0010007 729233207Stijl#define MSR_SYSCFG 0xc0010010 730233207Stijl#define MSR_HWCR 0xc0010015 731233207Stijl#define MSR_IORRBASE0 0xc0010016 732233207Stijl#define MSR_IORRMASK0 0xc0010017 733233207Stijl#define MSR_IORRBASE1 0xc0010018 734233207Stijl#define MSR_IORRMASK1 0xc0010019 735233207Stijl#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 736233207Stijl#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 737181430Sstas#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 738205573Salc#define MSR_MC0_CTL_MASK 0xc0010044 739168439Sru 740160305Smr/* VIA ACE crypto featureset: for via_feature_rng */ 741167493Sjkim#define VIA_HAS_RNG 1 /* cpu has RNG */ 742160305Smr 743160305Smr/* VIA ACE crypto featureset: for via_feature_xcrypt */ 744167493Sjkim#define VIA_HAS_AES 1 /* cpu has AES */ 745167493Sjkim#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 746167493Sjkim#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 747167493Sjkim#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 74840003Skato 749160298Smr/* Centaur Extended Feature flags */ 750167493Sjkim#define VIA_CPUID_HAS_RNG 0x000004 751167493Sjkim#define VIA_CPUID_DO_RNG 0x000008 752167493Sjkim#define VIA_CPUID_HAS_ACE 0x000040 753167493Sjkim#define VIA_CPUID_DO_ACE 0x000080 754167493Sjkim#define VIA_CPUID_HAS_ACE2 0x000100 755167493Sjkim#define VIA_CPUID_DO_ACE2 0x000200 756167493Sjkim#define VIA_CPUID_HAS_PHE 0x000400 757167493Sjkim#define VIA_CPUID_DO_PHE 0x000800 758167493Sjkim#define VIA_CPUID_HAS_PMM 0x001000 759167493Sjkim#define VIA_CPUID_DO_PMM 0x002000 760160298Smr 761160298Smr/* VIA ACE xcrypt-* instruction context control options */ 762167493Sjkim#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 763167493Sjkim#define VIA_CRYPT_CWLO_ALG_M 0x00000070 764167493Sjkim#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 765167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 766167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 767167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 768167493Sjkim#define VIA_CRYPT_CWLO_NORMAL 0x00000000 769167493Sjkim#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 770167493Sjkim#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 771167493Sjkim#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 772167493Sjkim#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 773167493Sjkim#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 774167493Sjkim#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 775160298Smr 7765594Sbde#endif /* !_MACHINE_SPECIALREG_H_ */ 777