apicreg.h revision 27778
1169691Skan/* 2169691Skan * Copyright (c) 1996, by Peter Wemm and Steve Passe 3169691Skan * All rights reserved. 4169691Skan * 5169691Skan * Redistribution and use in source and binary forms, with or without 6169691Skan * modification, are permitted provided that the following conditions 7169691Skan * are met: 8169691Skan * 1. Redistributions of source code must retain the above copyright 9169691Skan * notice, this list of conditions and the following disclaimer. 10169691Skan * 2. The name of the developer may NOT be used to endorse or promote products 11169691Skan * derived from this software without specific prior written permission. 12169691Skan * 13169691Skan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14169691Skan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15169691Skan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16169691Skan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17169691Skan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18169691Skan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19169691Skan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20169691Skan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21169691Skan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22169691Skan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23169691Skan * SUCH DAMAGE. 24169691Skan * 25169691Skan * $Id: apic.h,v 1.6 1997/07/30 22:44:20 smp Exp smp $ 26169691Skan */ 27169691Skan 28169691Skan#ifndef _MACHINE_APIC_H_ 29169691Skan#define _MACHINE_APIC_H_ 30169691Skan 31169691Skan/* 32169691Skan * Local && I/O APIC definitions. 33169691Skan */ 34169691Skan 35169691Skan/* 36169691Skan * Pentium P54C+ Build-in APIC 37169691Skan * (Advanced programmable Interrupt Controller) 38169691Skan * 39169691Skan * Base Address of Build-in APIC in memory location 40169691Skan * is 0xfee00000. 41169691Skan * 42169691Skan * Map of APIC REgisters: 43169691Skan * 44169691Skan * Offset (hex) Description Read/Write state 45169691Skan * 000 Reserved 46169691Skan * 010 Reserved 47169691Skan * 020 ID Local APIC ID R/W 48169691Skan * 030 VER Local APIC Version R 49169691Skan * 040 Reserved 50169691Skan * 050 Reserved 51169691Skan * 060 Reserved 52169691Skan * 070 Reserved 53169691Skan * 080 Task Priority Register R/W 54169691Skan * 090 Arbitration Priority Register R 55169691Skan * 0A0 Processor Priority Register R 56169691Skan * 0B0 EOI Register W 57169691Skan * 0C0 RRR Remote read R 58169691Skan * 0D0 Logical Destination R/W 59169691Skan * 0E0 Destination Format Register 0..27 R; 28..31 R/W 60169691Skan * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W 61169691Skan * 100 ISR 000-031 R 62169691Skan * 110 ISR 032-063 R 63169691Skan * 120 ISR 064-095 R 64169691Skan * 130 ISR 095-128 R 65169691Skan * 140 ISR 128-159 R 66169691Skan * 150 ISR 160-191 R 67169691Skan * 160 ISR 192-223 R 68169691Skan * 170 ISR 224-255 R 69169691Skan * 180 TMR 000-031 R 70169691Skan * 190 TMR 032-063 R 71169691Skan * 1A0 TMR 064-095 R 72169691Skan * 1B0 TMR 095-128 R 73169691Skan * 1C0 TMR 128-159 R 74169691Skan * 1D0 TMR 160-191 R 75169691Skan * 1E0 TMR 192-223 R 76169691Skan * 1F0 TMR 224-255 R 77169691Skan * 200 IRR 000-031 R 78169691Skan * 210 IRR 032-063 R 79169691Skan * 220 IRR 064-095 R 80169691Skan * 230 IRR 095-128 R 81169691Skan * 240 IRR 128-159 R 82169691Skan * 250 IRR 160-191 R 83169691Skan * 260 IRR 192-223 R 84169691Skan * 270 IRR 224-255 R 85169691Skan * 280 Error Status Register R 86169691Skan * 290 Reserved 87169691Skan * 2A0 Reserved 88169691Skan * 2B0 Reserved 89169691Skan * 2C0 Reserved 90169691Skan * 2D0 Reserved 91169691Skan * 2E0 Reserved 92169691Skan * 2F0 Reserved 93169691Skan * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W 94169691Skan * 310 ICR_HI Interrupt Command Reg. (32-63) R/W 95169691Skan * 320 Local Vector Table (Timer) R/W 96169691Skan * 330 Reserved 97169691Skan * 340 Reserved 98169691Skan * 350 LVT1 Local Vector Table (LINT0) R/W 99169691Skan * 360 LVT2 Local Vector Table (LINT1) R/W 100169691Skan * 370 LVT3 Local Vector Table (ERROR) R/W 101169691Skan * 380 Initial Count Reg. for Timer R/W 102169691Skan * 390 Current Count of Timer R 103169691Skan * 3A0 Reserved 104169691Skan * 3B0 Reserved 105169691Skan * 3C0 Reserved 106169691Skan * 3D0 Reserved 107169691Skan * 3E0 Timer Divide Configuration Reg. R/W 108169691Skan * 3F0 Reserved 109169691Skan */ 110169691Skan 111169691Skan 112169691Skan/****************************************************************************** 113169691Skan * global defines, etc. 114169691Skan */ 115169691Skan 116169691Skan/** 117169691Skan * this enables code concerned with handling more than one IO APIC. 118169691Skan * Note: this is NOT READY for use! 119169691Skan * 120169691Skan#define MULTIPLE_IOAPICS 121169691Skan */ 122169691Skan 123169691Skan/****************************************************************************** 124169691Skan * LOCAL APIC structure 125169691Skan */ 126169691Skan 127169691Skan#ifndef LOCORE 128169691Skan#include <sys/types.h> 129169691Skan 130169691Skan#define PAD3 int : 32; int : 32; int : 32 131169691Skan#define PAD4 int : 32; int : 32; int : 32; int : 32 132169691Skan 133169691Skanstruct LAPIC { 134169691Skan /* reserved */ PAD4; 135169691Skan /* reserved */ PAD4; 136169691Skan u_int32_t id; PAD3; 137169691Skan u_int32_t version; PAD3; 138169691Skan /* reserved */ PAD4; 139169691Skan /* reserved */ PAD4; 140169691Skan /* reserved */ PAD4; 141169691Skan /* reserved */ PAD4; 142169691Skan u_int32_t tpr; PAD3; 143169691Skan u_int32_t apr; PAD3; 144169691Skan u_int32_t ppr; PAD3; 145169691Skan u_int32_t eoi; PAD3; 146169691Skan /* reserved */ PAD4; 147169691Skan u_int32_t ldr; PAD3; 148169691Skan u_int32_t dfr; PAD3; 149169691Skan u_int32_t svr; PAD3; 150169691Skan u_int32_t isr0; PAD3; 151169691Skan u_int32_t isr1; PAD3; 152169691Skan u_int32_t isr2; PAD3; 153169691Skan u_int32_t isr3; PAD3; 154169691Skan u_int32_t isr4; PAD3; 155169691Skan u_int32_t isr5; PAD3; 156169691Skan u_int32_t isr6; PAD3; 157169691Skan u_int32_t isr7; PAD3; 158169691Skan u_int32_t tmr0; PAD3; 159169691Skan u_int32_t tmr1; PAD3; 160169691Skan u_int32_t tmr2; PAD3; 161169691Skan u_int32_t tmr3; PAD3; 162169691Skan u_int32_t tmr4; PAD3; 163169691Skan u_int32_t tmr5; PAD3; 164169691Skan u_int32_t tmr6; PAD3; 165169691Skan u_int32_t tmr7; PAD3; 166169691Skan u_int32_t irr0; PAD3; 167169691Skan u_int32_t irr1; PAD3; 168169691Skan u_int32_t irr2; PAD3; 169169691Skan u_int32_t irr3; PAD3; 170169691Skan u_int32_t irr4; PAD3; 171169691Skan u_int32_t irr5; PAD3; 172169691Skan u_int32_t irr6; PAD3; 173169691Skan u_int32_t irr7; PAD3; 174169691Skan u_int32_t esr; PAD3; 175169691Skan /* reserved */ PAD4; 176169691Skan /* reserved */ PAD4; 177169691Skan /* reserved */ PAD4; 178169691Skan /* reserved */ PAD4; 179169691Skan /* reserved */ PAD4; 180169691Skan /* reserved */ PAD4; 181169691Skan /* reserved */ PAD4; 182169691Skan u_int32_t icr_lo; PAD3; 183169691Skan u_int32_t icr_hi; PAD3; 184169691Skan u_int32_t lvt_timer; PAD3; 185169691Skan /* reserved */ PAD4; 186169691Skan u_int32_t lvt_pcint; PAD3; 187169691Skan u_int32_t lvt_lint0; PAD3; 188169691Skan u_int32_t lvt_lint1; PAD3; 189169691Skan u_int32_t lvt_error; PAD3; 190169691Skan u_int32_t icr_timer; PAD3; 191169691Skan u_int32_t ccr_timer; PAD3; 192169691Skan /* reserved */ PAD4; 193169691Skan /* reserved */ PAD4; 194169691Skan /* reserved */ PAD4; 195169691Skan /* reserved */ PAD4; 196169691Skan u_int32_t dcr_timer; PAD3; 197169691Skan /* reserved */ PAD4; 198169691Skan}; 199169691Skan 200169691Skantypedef struct LAPIC lapic_t; 201169691Skan 202169691Skan/****************************************************************************** 203169691Skan * I/O APIC structure 204169691Skan */ 205169691Skan 206169691Skanstruct IOAPIC { 207169691Skan u_int32_t ioregsel; PAD3; 208169691Skan u_int32_t iowin; PAD3; 209169691Skan}; 210169691Skan 211169691Skantypedef struct IOAPIC ioapic_t; 212169691Skan 213169691Skan#undef PAD4 214169691Skan#undef PAD3 215169691Skan 216169691Skan#endif /* !LOCORE */ 217169691Skan 218169691Skan 219169691Skan/****************************************************************************** 220169691Skan * various code 'logical' values 221169691Skan */ 222169691Skan 223169691Skan/* default level for TPR */ 224169691Skan#define LOPRIO_LEVEL 0x00000010 /* TPR of CPUs accepting INT */ 225169691Skan 226169691Skan/* XXX these 2 don't really belong here... */ 227#define COUNT_FIELD 0x00ffffff /* count portion of the lock */ 228#define FREE_LOCK 0xffffffff /* value of lock when free */ 229 230/* 231 * XXX This code assummes that the reserved field of the 232 * local APIC TPR can be written with all 0s. 233 * This saves quite a few memory accesses. 234 * If the silicon ever changes then things will break! 235 * It affects mplock.s, swtch.s, and possibly other files. 236 */ 237#define CHEAP_TPR 238 239 240/****************************************************************************** 241 * LOCAL APIC defines 242 */ 243 244/* default physical locations of LOCAL (CPU) APICs */ 245#define DEFAULT_APIC_BASE 0xfee00000 246 247/* fields in VER */ 248#define APIC_VER_VERSION 0x000000ff 249#define APIC_VER_MAXLVT 0x00ff0000 250#define MAXLVTSHIFT 16 251 252/* fields in SVR */ 253#define APIC_SVR_VECTOR 0x000000ff 254#define APIC_SVR_VEC_PROG 0x000000f0 255#define APIC_SVR_VEC_FIX 0x0000000f 256#define APIC_SVR_ENABLE 0x00000100 257# define APIC_SVR_SWDIS 0x00000000 258# define APIC_SVR_SWEN 0x00000100 259#define APIC_SVR_FOCUS 0x00000200 260# define APIC_SVR_FEN 0x00000000 261# define APIC_SVR_FDIS 0x00000200 262 263/* fields in TPR */ 264#define APIC_TPR_PRIO 0x000000ff 265# define APIC_TPR_INT 0x000000f0 266# define APIC_TPR_SUB 0x0000000f 267 268 269/* fields in ICR_LOW */ 270#define APIC_VECTOR_MASK 0x000000ff 271 272#define APIC_DELMODE_MASK 0x00000700 273# define APIC_DELMODE_FIXED 0x00000000 274# define APIC_DELMODE_LOWPRIO 0x00000100 275# define APIC_DELMODE_SMI 0x00000200 276# define APIC_DELMODE_RR 0x00000300 277# define APIC_DELMODE_NMI 0x00000400 278# define APIC_DELMODE_INIT 0x00000500 279# define APIC_DELMODE_STARTUP 0x00000600 280# define APIC_DELMODE_RESV 0x00000700 281 282#define APIC_DESTMODE_MASK 0x00000800 283# define APIC_DESTMODE_PHY 0x00000000 284# define APIC_DESTMODE_LOG 0x00000800 285 286#define APIC_DELSTAT_MASK 0x00001000 287# define APIC_DELSTAT_IDLE 0x00000000 288# define APIC_DELSTAT_PEND 0x00001000 289 290#define APIC_RESV1_MASK 0x00002000 291 292#define APIC_LEVEL_MASK 0x00004000 293# define APIC_LEVEL_DEASSERT 0x00000000 294# define APIC_LEVEL_ASSERT 0x00004000 295 296#define APIC_TRIGMOD_MASK 0x00008000 297# define APIC_TRIGMOD_EDGE 0x00000000 298# define APIC_TRIGMOD_LEVEL 0x00008000 299 300#define APIC_RRSTAT_MASK 0x00030000 301# define APIC_RRSTAT_INVALID 0x00000000 302# define APIC_RRSTAT_INPROG 0x00010000 303# define APIC_RRSTAT_VALID 0x00020000 304# define APIC_RRSTAT_RESV 0x00030000 305 306#define APIC_DEST_MASK 0x000c0000 307# define APIC_DEST_DESTFLD 0x00000000 308# define APIC_DEST_SELF 0x00040000 309# define APIC_DEST_ALLISELF 0x00080000 310# define APIC_DEST_ALLESELF 0x000c0000 311 312#define APIC_RESV2_MASK 0xfff00000 313 314 315/* fields in ICR_HIGH */ 316#define APIC_ID_MASK 0x0f000000 317 318 319/* fields in LVT1/2 */ 320#define APIC_LVT_VECTOR 0x000000ff 321#define APIC_LVT_DM 0x00000700 322# define APIC_LVT_DM_FIXED 0x00000000 323# define APIC_LVT_DM_NMI 0x00000400 324# define APIC_LVT_DM_EXTINT 0x00000700 325#define APIC_LVT_DS 0x00001000 326#define APIC_LVT_IIPP 0x00002000 327#define APIC_LVT_IIPP_INTALO 0x00002000 328#define APIC_LVT_IIPP_INTAHI 0x00000000 329#define APIC_LVT_RIRR 0x00004000 330#define APIC_LVT_TM 0x00008000 331#define APIC_LVT_M 0x00010000 332 333 334/* fields in LVT Timer */ 335#define APIC_LVTT_VECTOR 0x000000ff 336#define APIC_LVTT_DS 0x00001000 337#define APIC_LVTT_M 0x00010000 338#define APIC_LVTT_TM 0x00020000 339 340 341/* fields in TDCR */ 342#define APIC_TDCR_2 0x00 343#define APIC_TDCR_4 0x01 344#define APIC_TDCR_8 0x02 345#define APIC_TDCR_16 0x03 346#define APIC_TDCR_32 0x08 347#define APIC_TDCR_64 0x09 348#define APIC_TDCR_128 0x0a 349#define APIC_TDCR_1 0x0b 350 351 352/* 353 * fields in IRR 354 * ISA INTerrupts are in bits 16-31 of the 1st IRR register. 355 * these masks DON'T EQUAL the isa IRQs of the same name. 356 */ 357#define APIC_IRQ0 0x00000001 358#define APIC_IRQ1 0x00000002 359#define APIC_IRQ2 0x00000004 360#define APIC_IRQ3 0x00000008 361#define APIC_IRQ4 0x00000010 362#define APIC_IRQ5 0x00000020 363#define APIC_IRQ6 0x00000040 364#define APIC_IRQ7 0x00000080 365#define APIC_IRQ8 0x00000100 366#define APIC_IRQ9 0x00000200 367#define APIC_IRQ10 0x00000400 368#define APIC_IRQ11 0x00000800 369#define APIC_IRQ12 0x00001000 370#define APIC_IRQ13 0x00002000 371#define APIC_IRQ14 0x00004000 372#define APIC_IRQ15 0x00008000 373#define APIC_IRQ16 0x00010000 374#define APIC_IRQ17 0x00020000 375#define APIC_IRQ18 0x00040000 376#define APIC_IRQ19 0x00080000 377#define APIC_IRQ20 0x00100000 378#define APIC_IRQ21 0x00200000 379#define APIC_IRQ22 0x00400000 380#define APIC_IRQ23 0x00800000 381 382 383/****************************************************************************** 384 * I/O APIC defines 385 */ 386 387/* default physical locations of an IO APIC */ 388#define DEFAULT_IO_APIC_BASE 0xfec00000 389 390/* window register offset */ 391#define IOAPIC_WINDOW 0x10 392 393/* indexes into IO APIC */ 394#define IOAPIC_ID 0x00 395#define IOAPIC_VER 0x01 396#define IOAPIC_ARB 0x02 397#define IOAPIC_REDTBL 0x10 398#define IOAPIC_REDTBL0 IOAPIC_REDTBL 399#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) 400#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) 401#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) 402#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) 403#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) 404#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) 405#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) 406#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) 407#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) 408#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) 409#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) 410#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) 411#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) 412#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) 413#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) 414#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) 415#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) 416#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) 417#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) 418#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) 419#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) 420#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) 421#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) 422 423/* fields in VER */ 424#define IOART_VER_VERSION 0x000000ff 425#define IOART_VER_MAXREDIR 0x00ff0000 426#define MAXREDIRSHIFT 16 427 428/* 429 * fields in the IO APIC's redirection table entries 430 */ 431#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ 432 433#define IOART_RESV 0x00fe0000 /* reserved */ 434 435#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ 436# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ 437# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ 438 439#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ 440# define IOART_TRGREDG 0x00000000 /* edge */ 441# define IOART_TRGRLVL 0x00008000 /* level */ 442 443#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ 444 445#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ 446# define IOART_INTAHI 0x00000000 /* active high */ 447# define IOART_INTALO 0x00002000 /* active low */ 448 449#define IOART_DELIVS 0x00001000 /* RO: delivery status */ 450 451#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ 452# define IOART_DESTPHY 0x00000000 /* physical */ 453# define IOART_DESTLOG 0x00000800 /* logical */ 454 455#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ 456# define IOART_DELFIXED 0x00000000 /* fixed */ 457# define IOART_DELLOPRI 0x00000100 /* lowest priority */ 458# define IOART_DELSMI 0x00000200 /* System Management INT */ 459# define IOART_DELRSV1 0x00000300 /* reserved */ 460# define IOART_DELNMI 0x00000400 /* NMI signal */ 461# define IOART_DELINIT 0x00000500 /* INIT signal */ 462# define IOART_DELRSV2 0x00000600 /* reserved */ 463# define IOART_DELEXINT 0x00000700 /* External INTerrupt */ 464 465#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ 466 467#endif /* _MACHINE_APIC_H_ */ 468