apicreg.h revision 27000
1/* 2 * Copyright (c) 1996, by Peter Wemm and Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: apic.h,v 1.4 1997/06/22 16:03:46 peter Exp $ 26 */ 27 28#ifndef _MACHINE_APIC_H_ 29#define _MACHINE_APIC_H_ 30 31/* 32 * Local && I/O APIC definitions. 33 */ 34 35/* 36 * Pentium P54C+ Build-in APIC 37 * (Advanced programmable Interrupt Controller) 38 * 39 * Base Address of Build-in APIC in memory location 40 * is 0xfee00000. 41 * 42 * Map of APIC REgisters: 43 * 44 * Offset (hex) Description Read/Write state 45 * 000 Reserved 46 * 010 Reserved 47 * 020 ID Local APIC ID R/W 48 * 030 VER Local APIC Version R 49 * 040 Reserved 50 * 050 Reserved 51 * 060 Reserved 52 * 070 Reserved 53 * 080 Task Priority Register R/W 54 * 090 Arbitration Priority Register R 55 * 0A0 Processor Priority Register R 56 * 0B0 EOI Register W 57 * 0C0 RRR Remote read R 58 * 0D0 Logical Destination R/W 59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W 60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W 61 * 100 ISR 000-031 R 62 * 110 ISR 032-063 R 63 * 120 ISR 064-095 R 64 * 130 ISR 095-128 R 65 * 140 ISR 128-159 R 66 * 150 ISR 160-191 R 67 * 160 ISR 192-223 R 68 * 170 ISR 224-255 R 69 * 180 TMR 000-031 R 70 * 190 TMR 032-063 R 71 * 1A0 TMR 064-095 R 72 * 1B0 TMR 095-128 R 73 * 1C0 TMR 128-159 R 74 * 1D0 TMR 160-191 R 75 * 1E0 TMR 192-223 R 76 * 1F0 TMR 224-255 R 77 * 200 IRR 000-031 R 78 * 210 IRR 032-063 R 79 * 220 IRR 064-095 R 80 * 230 IRR 095-128 R 81 * 240 IRR 128-159 R 82 * 250 IRR 160-191 R 83 * 260 IRR 192-223 R 84 * 270 IRR 224-255 R 85 * 280 Error Status Register R 86 * 290 Reserved 87 * 2A0 Reserved 88 * 2B0 Reserved 89 * 2C0 Reserved 90 * 2D0 Reserved 91 * 2E0 Reserved 92 * 2F0 Reserved 93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W 94 * 310 ICR_HI Interrupt Command Reg. (32-63) R/W 95 * 320 Local Vector Table (Timer) R/W 96 * 330 Reserved 97 * 340 Reserved 98 * 350 LVT1 Local Vector Table (LINT0) R/W 99 * 360 LVT2 Local Vector Table (LINT1) R/W 100 * 370 LVT3 Local Vector Table (ERROR) R/W 101 * 380 Initial Count Reg. for Timer R/W 102 * 390 Current Count of Timer R 103 * 3A0 Reserved 104 * 3B0 Reserved 105 * 3C0 Reserved 106 * 3D0 Reserved 107 * 3E0 Timer Divide Configuration Reg. R/W 108 * 3F0 Reserved 109 */ 110 111 112/****************************************************************************** 113 * global defines, etc. 114 */ 115 116/** 117 * this enables code concerned with handling more than one IO APIC. 118 * Note: this is NOT READY for use! 119 * 120#define MULTIPLE_IOAPICS 121 */ 122 123/****************************************************************************** 124 * LOCAL APIC structure 125 */ 126 127#ifndef LOCORE 128#include <sys/types.h> 129 130#define PAD3 int : 32; int : 32; int : 32 131#define PAD4 int : 32; int : 32; int : 32; int : 32 132 133struct LAPIC { 134 /* reserved */ PAD4; 135 /* reserved */ PAD4; 136 u_int32_t id; PAD3; 137 u_int32_t version; PAD3; 138 /* reserved */ PAD4; 139 /* reserved */ PAD4; 140 /* reserved */ PAD4; 141 /* reserved */ PAD4; 142 u_int32_t tpr; PAD3; 143 u_int32_t apr; PAD3; 144 u_int32_t ppr; PAD3; 145 u_int32_t eoi; PAD3; 146 /* reserved */ PAD4; 147 u_int32_t ldr; PAD3; 148 u_int32_t dfr; PAD3; 149 u_int32_t svr; PAD3; 150 u_int32_t isr0; PAD3; 151 u_int32_t isr1; PAD3; 152 u_int32_t isr2; PAD3; 153 u_int32_t isr3; PAD3; 154 u_int32_t isr4; PAD3; 155 u_int32_t isr5; PAD3; 156 u_int32_t isr6; PAD3; 157 u_int32_t isr7; PAD3; 158 u_int32_t tmr0; PAD3; 159 u_int32_t tmr1; PAD3; 160 u_int32_t tmr2; PAD3; 161 u_int32_t tmr3; PAD3; 162 u_int32_t tmr4; PAD3; 163 u_int32_t tmr5; PAD3; 164 u_int32_t tmr6; PAD3; 165 u_int32_t tmr7; PAD3; 166 u_int32_t irr0; PAD3; 167 u_int32_t irr1; PAD3; 168 u_int32_t irr2; PAD3; 169 u_int32_t irr3; PAD3; 170 u_int32_t irr4; PAD3; 171 u_int32_t irr5; PAD3; 172 u_int32_t irr6; PAD3; 173 u_int32_t irr7; PAD3; 174 u_int32_t esr; PAD3; 175 /* reserved */ PAD4; 176 /* reserved */ PAD4; 177 /* reserved */ PAD4; 178 /* reserved */ PAD4; 179 /* reserved */ PAD4; 180 /* reserved */ PAD4; 181 /* reserved */ PAD4; 182 u_int32_t icr_lo; PAD3; 183 u_int32_t icr_hi; PAD3; 184 u_int32_t lvt_timer; PAD3; 185 /* reserved */ PAD4; 186 u_int32_t lvt_pcint; PAD3; 187 u_int32_t lvt_lint0; PAD3; 188 u_int32_t lvt_lint1; PAD3; 189 u_int32_t lvt_error; PAD3; 190 u_int32_t icr_timer; PAD3; 191 u_int32_t ccr_timer; PAD3; 192 /* reserved */ PAD4; 193 /* reserved */ PAD4; 194 /* reserved */ PAD4; 195 /* reserved */ PAD4; 196 u_int32_t dcr_timer; PAD3; 197 /* reserved */ PAD4; 198}; 199 200typedef struct LAPIC lapic_t; 201 202/****************************************************************************** 203 * I/O APIC structure 204 */ 205 206struct IOAPIC { 207 u_int32_t ioregsel; PAD3; 208 u_int32_t iowin; PAD3; 209}; 210 211typedef struct IOAPIC ioapic_t; 212 213#undef PAD4 214#undef PAD3 215 216#endif /* LOCORE */ 217 218 219/****************************************************************************** 220 * LOCAL APIC defines 221 */ 222 223/* default physical locations of LOCAL (CPU) APICs */ 224#define DEFAULT_APIC_BASE 0xfee00000 225 226/* fields in VER */ 227#define APIC_VER_VERSION 0x000000ff 228#define APIC_VER_MAXLVT 0x00ff0000 229#define MAXLVTSHIFT 16 230 231/* fields in SVR */ 232#define APIC_SVR_ENABLE 0x00000100 233# define APIC_SVR_SWDIS 0x00000000 234# define APIC_SVR_SWEN 0x00000100 235#define APIC_SVR_FOCUS 0x00000200 236# define APIC_SVR_FEN 0x00000000 237# define APIC_SVR_FDIS 0x00000200 238#define APIC_TPR_PRIO 0x000000ff 239# define APIC_TPR_INT 0x000000f0 240# define APIC_TPR_SUB 0x0000000f 241 242 243/* fields in ICR_LOW */ 244#define APIC_VECTOR_MASK 0x000000ff 245 246#define APIC_DELMODE_MASK 0x00000700 247# define APIC_DELMODE_FIXED 0x00000000 248# define APIC_DELMODE_LOWPRIO 0x00000100 249# define APIC_DELMODE_SMI 0x00000200 250# define APIC_DELMODE_RR 0x00000300 251# define APIC_DELMODE_NMI 0x00000400 252# define APIC_DELMODE_INIT 0x00000500 253# define APIC_DELMODE_STARTUP 0x00000600 254# define APIC_DELMODE_RESV 0x00000700 255 256#define APIC_DESTMODE_MASK 0x00000800 257# define APIC_DESTMODE_PHY 0x00000000 258# define APIC_DESTMODE_LOG 0x00000800 259 260#define APIC_DELSTAT_MASK 0x00001000 261# define APIC_DELSTAT_IDLE 0x00000000 262# define APIC_DELSTAT_PEND 0x00001000 263 264#define APIC_RESV1_MASK 0x00002000 265 266#define APIC_LEVEL_MASK 0x00004000 267# define APIC_LEVEL_DEASSERT 0x00000000 268# define APIC_LEVEL_ASSERT 0x00004000 269 270#define APIC_TRIGMOD_MASK 0x00008000 271# define APIC_TRIGMOD_EDGE 0x00000000 272# define APIC_TRIGMOD_LEVEL 0x00008000 273 274#define APIC_RRSTAT_MASK 0x00030000 275# define APIC_RRSTAT_INVALID 0x00000000 276# define APIC_RRSTAT_INPROG 0x00010000 277# define APIC_RRSTAT_VALID 0x00020000 278# define APIC_RRSTAT_RESV 0x00030000 279 280#define APIC_DEST_MASK 0x000c0000 281# define APIC_DEST_DESTFLD 0x00000000 282# define APIC_DEST_SELF 0x00040000 283# define APIC_DEST_ALLISELF 0x00080000 284# define APIC_DEST_ALLESELF 0x000c0000 285 286#define APIC_RESV2_MASK 0xfff00000 287 288 289/* fields in ICR_HIGH */ 290#define APIC_ID_MASK 0x0f000000 291 292 293/* fields in LVT1/2 */ 294#define APIC_LVT_VECTOR 0x000000ff 295#define APIC_LVT_DM 0x00000700 296# define APIC_LVT_DM_FIXED 0x00000000 297# define APIC_LVT_DM_NMI 0x00000400 298# define APIC_LVT_DM_EXTINT 0x00000700 299#define APIC_LVT_DS 0x00001000 300#define APIC_LVT_IIPP 0x00002000 301#define APIC_LVT_IIPP_INTALO 0x00002000 302#define APIC_LVT_IIPP_INTAHI 0x00000000 303#define APIC_LVT_RIRR 0x00004000 304#define APIC_LVT_TM 0x00008000 305#define APIC_LVT_M 0x00010000 306 307 308/* fields in LVT Timer */ 309#define APIC_LVTT_VECTOR 0x000000ff 310#define APIC_LVTT_DS 0x00001000 311#define APIC_LVTT_M 0x00010000 312#define APIC_LVTT_TM 0x00020000 313 314 315/* fields in TDCR */ 316#define APIC_TDCR_2 0x00 317#define APIC_TDCR_4 0x01 318#define APIC_TDCR_8 0x02 319#define APIC_TDCR_16 0x03 320#define APIC_TDCR_32 0x08 321#define APIC_TDCR_64 0x09 322#define APIC_TDCR_128 0x0a 323#define APIC_TDCR_1 0x0b 324 325 326/* 327 * fields in IRR 328 * ISA INTerrupts are in bits 16-31 of the 1st IRR register. 329 * these masks DON'T EQUAL the isa IRQs of the same name. 330 * FIXME: how do we make this portable for MP table configurations??? 331 * look for "HARD_VECTORXXX" marking places with this problem. 332 */ 333#define APIC_IRQ0 0x00000001 334#define APIC_IRQ1 0x00000002 335#define APIC_IRQ2 0x00000004 336#define APIC_IRQ3 0x00000008 337#define APIC_IRQ4 0x00000010 338#define APIC_IRQ5 0x00000020 339#define APIC_IRQ6 0x00000040 340#define APIC_IRQ7 0x00000080 341#define APIC_IRQ8 0x00000100 342#define APIC_IRQ9 0x00000200 343#define APIC_IRQ10 0x00000400 344#define APIC_IRQ11 0x00000800 345#define APIC_IRQ12 0x00001000 346#define APIC_IRQ13 0x00002000 347#define APIC_IRQ14 0x00004000 348#define APIC_IRQ15 0x00008000 349#define APIC_IRQ16 0x00010000 350#define APIC_IRQ17 0x00020000 351#define APIC_IRQ18 0x00040000 352#define APIC_IRQ19 0x00080000 353#define APIC_IRQ20 0x00100000 354#define APIC_IRQ21 0x00200000 355#define APIC_IRQ22 0x00400000 356#define APIC_IRQ23 0x00800000 357 358 359/****************************************************************************** 360 * I/O APIC defines 361 */ 362 363/* default physical locations of an IO APIC */ 364#define DEFAULT_IO_APIC_BASE 0xfec00000 365 366/* window register offset */ 367#define IOAPIC_WINDOW 0x10 368 369/* indexes into IO APIC */ 370#define IOAPIC_ID 0x00 371#define IOAPIC_VER 0x01 372#define IOAPIC_ARB 0x02 373#define IOAPIC_REDTBL 0x10 374#define IOAPIC_REDTBL0 IOAPIC_REDTBL 375#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) 376#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) 377#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) 378#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) 379#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) 380#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) 381#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) 382#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) 383#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) 384#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) 385#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) 386#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) 387#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) 388#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) 389#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) 390#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) 391#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) 392#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) 393#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) 394#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) 395#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) 396#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) 397#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) 398 399/* fields in VER */ 400#define IOART_VER_VERSION 0x000000ff 401#define IOART_VER_MAXREDIR 0x00ff0000 402#define MAXREDIRSHIFT 16 403 404/* 405 * fields in the IO APIC's redirection table entries 406 */ 407#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ 408 409#define IOART_RESV 0x00fe0000 /* reserved */ 410 411#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ 412# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ 413# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ 414 415#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ 416# define IOART_TRGREDG 0x00000000 /* edge */ 417# define IOART_TRGRLVL 0x00008000 /* level */ 418 419#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ 420 421#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ 422# define IOART_INTAHI 0x00000000 /* active high */ 423# define IOART_INTALO 0x00002000 /* active low */ 424 425#define IOART_DELIVS 0x00001000 /* RO: delivery status */ 426 427#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ 428# define IOART_DESTPHY 0x00000000 /* physical */ 429# define IOART_DESTLOG 0x00000800 /* logical */ 430 431#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ 432# define IOART_DELFIXED 0x00000000 /* fixed */ 433# define IOART_DELLOPRI 0x00000100 /* lowest priority */ 434# define IOART_DELSMI 0x00000200 /* System Management INT */ 435# define IOART_DELRSV1 0x00000300 /* reserved */ 436# define IOART_DELNMI 0x00000400 /* NMI signal */ 437# define IOART_DELINIT 0x00000500 /* INIT signal */ 438# define IOART_DELRSV2 0x00000600 /* reserved */ 439# define IOART_DELEXINT 0x00000700 /* External INTerrupt */ 440 441#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ 442 443#endif /* _MACHINE_APIC_H_ */ 444