apicreg.h revision 26269
1/* 2 * Copyright (c) 1996, by Peter Wemm and Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: apic.h,v 1.1 1997/05/28 19:43:45 smp Exp smp $ 26 */ 27 28#ifndef _MACHINE_APIC_H_ 29#define _MACHINE_APIC_H_ 30 31/* 32 * Local && I/O APIC definitions. 33 */ 34 35/* 36 * Pentium P54C+ Build-in APIC 37 * (Advanced programmable Interrupt Controller) 38 * 39 * Base Address of Build-in APIC in memory location 40 * is 0xfee00000. 41 * 42 * Map of APIC REgisters: 43 * 44 * Offset (hex) Description Read/Write state 45 * 000 Reserved 46 * 010 Reserved 47 * 020 ID Local APIC ID R/W 48 * 030 VER Local APIC Version R 49 * 040 Reserved 50 * 050 Reserved 51 * 060 Reserved 52 * 070 Reserved 53 * 080 Task Priority Register R/W 54 * 090 Arbitration Priority Register R 55 * 0A0 Processor Priority Register R 56 * 0B0 EOI Register W 57 * 0C0 RRR Remote read R 58 * 0D0 Logical Destination R/W 59 * 0E0 Destination Format Register 0..27 R; 28..31 R/W 60 * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W 61 * 100 ISR 000-031 R 62 * 110 ISR 032-063 R 63 * 120 ISR 064-095 R 64 * 130 ISR 095-128 R 65 * 140 ISR 128-159 R 66 * 150 ISR 160-191 R 67 * 160 ISR 192-223 R 68 * 170 ISR 224-255 R 69 * 180 TMR 000-031 R 70 * 190 TMR 032-063 R 71 * 1A0 TMR 064-095 R 72 * 1B0 TMR 095-128 R 73 * 1C0 TMR 128-159 R 74 * 1D0 TMR 160-191 R 75 * 1E0 TMR 192-223 R 76 * 1F0 TMR 224-255 R 77 * 200 IRR 000-031 R 78 * 210 IRR 032-063 R 79 * 220 IRR 064-095 R 80 * 230 IRR 095-128 R 81 * 240 IRR 128-159 R 82 * 250 IRR 160-191 R 83 * 260 IRR 192-223 R 84 * 270 IRR 224-255 R 85 * 280 Error Status Register R 86 * 290 Reserved 87 * 2A0 Reserved 88 * 2B0 Reserved 89 * 2C0 Reserved 90 * 2D0 Reserved 91 * 2E0 Reserved 92 * 2F0 Reserved 93 * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W 94 * 310 ICR_HI Interrupt Command Reg. (32-63) R/W 95 * 320 Local Vector Table (Timer) R/W 96 * 330 Reserved 97 * 340 Reserved 98 * 350 LVT1 Local Vector Table (LINT0) R/W 99 * 360 LVT2 Local Vector Table (LINT1) R/W 100 * 370 LVT3 Local Vector Table (ERROR) R/W 101 * 380 Initial Count Reg. for Timer R/W 102 * 390 Current Count of Timer R 103 * 3A0 Reserved 104 * 3B0 Reserved 105 * 3C0 Reserved 106 * 3D0 Reserved 107 * 3E0 Timer Divide Configuration Reg. R/W 108 * 3F0 Reserved 109 */ 110 111 112/****************************************************************************** 113 * global defines, etc. 114 */ 115 116/** 117 * this enables code concerned with handling more than one IO APIC. 118 * Note: this is NOT READY for use! 119 * 120#define MULTIPLE_IOAPICS 121 */ 122 123/****************************************************************************** 124 * LOCAL APIC structure 125 */ 126 127#ifndef LOCORE 128#include <sys/types.h> 129 130#define PAD3 int : 32; int : 32; int : 32 131#define PAD4 int : 32; int : 32; int : 32; int : 32 132 133struct LAPIC { 134 /* reserved */ PAD4; 135 /* reserved */ PAD4; 136 u_int32_t id; PAD3; 137 u_int32_t version; PAD3; 138 /* reserved */ PAD4; 139 /* reserved */ PAD4; 140 /* reserved */ PAD4; 141 /* reserved */ PAD4; 142 u_int32_t tpr; PAD3; 143 u_int32_t apr; PAD3; 144 u_int32_t ppr; PAD3; 145 u_int32_t eoi; PAD3; 146 /* reserved */ PAD4; 147 u_int32_t ldr; PAD3; 148 u_int32_t dfr; PAD3; 149 u_int32_t svr; PAD3; 150 u_int32_t isr0; PAD3; 151 u_int32_t isr1; PAD3; 152 u_int32_t isr2; PAD3; 153 u_int32_t isr3; PAD3; 154 u_int32_t isr4; PAD3; 155 u_int32_t isr5; PAD3; 156 u_int32_t isr6; PAD3; 157 u_int32_t isr7; PAD3; 158 u_int32_t tmr0; PAD3; 159 u_int32_t tmr1; PAD3; 160 u_int32_t tmr2; PAD3; 161 u_int32_t tmr3; PAD3; 162 u_int32_t tmr4; PAD3; 163 u_int32_t tmr5; PAD3; 164 u_int32_t tmr6; PAD3; 165 u_int32_t tmr7; PAD3; 166 u_int32_t irr0; PAD3; 167 u_int32_t irr1; PAD3; 168 u_int32_t irr2; PAD3; 169 u_int32_t irr3; PAD3; 170 u_int32_t irr4; PAD3; 171 u_int32_t irr5; PAD3; 172 u_int32_t irr6; PAD3; 173 u_int32_t irr7; PAD3; 174 u_int32_t esr; PAD3; 175 /* reserved */ PAD4; 176 /* reserved */ PAD4; 177 /* reserved */ PAD4; 178 /* reserved */ PAD4; 179 /* reserved */ PAD4; 180 /* reserved */ PAD4; 181 /* reserved */ PAD4; 182 u_int32_t icr_lo; PAD3; 183 u_int32_t icr_hi; PAD3; 184 u_int32_t lvt_timer; PAD3; 185 /* reserved */ PAD4; 186 u_int32_t lvt_pcint; PAD3; 187 u_int32_t lvt_lint0; PAD3; 188 u_int32_t lvt_lint1; PAD3; 189 u_int32_t lvt_error; PAD3; 190 u_int32_t icr_timer; PAD3; 191 u_int32_t ccr_timer; PAD3; 192 /* reserved */ PAD4; 193 /* reserved */ PAD4; 194 /* reserved */ PAD4; 195 /* reserved */ PAD4; 196 u_int32_t dcr_timer; PAD3; 197 /* reserved */ PAD4; 198}; 199 200typedef struct LAPIC lapic_t; 201 202/****************************************************************************** 203 * I/O APIC structure 204 */ 205 206struct IOAPIC { 207 u_int32_t ioregsel; PAD3; 208 u_int32_t iowin; PAD3; 209}; 210 211typedef struct IOAPIC ioapic_t; 212 213#undef PAD4 214#undef PAD3 215 216#endif /* LOCORE */ 217 218 219/****************************************************************************** 220 * LOCAL APIC defines 221 */ 222 223/* default physical locations of LOCAL (CPU) APICs */ 224#define DEFAULT_APIC_BASE 0xfee00000 225 226# if defined(LOCORE) 227 228#define APIC_ID 0x020 229#define APIC_VER 0x030 230#define APIC_TPR 0x080 231#define APIC_APR 0x090 232#define APIC_PPR 0x0a0 233#define APIC_EOI 0x0b0 234#define APIC_RR 0x0c0 235#define APIC_LDR 0x0d0 236#define APIC_DFR 0x0e0 237#define APIC_SVR 0x0f0 238#define APIC_ISR 0x100 239#define APIC_ISR0 0x100 240#define APIC_ISR1 0x110 241#define APIC_ISR2 0x120 242#define APIC_TMR 0x180 243#define APIC_IRR 0x200 244#define APIC_IRR0 0x200 245#define APIC_IRR1 0x210 246#define APIC_IRR2 0x220 247#define APIC_ESR 0x280 248#define APIC_ICR_LOW 0x300 249#define APIC_ICR_HI 0x310 250#define APIC_LVTT 0x320 251#define APIC_LVT1 0x350 252#define APIC_LVT2 0x360 253#define APIC_LVT3 0x370 254#define APIC_TICR 0x380 255#define APIC_TCCR 0x390 256#define APIC_TDCR 0x3e0 257 258# else /* !LOCORE */ 259 260#if 0 /** XXX APIC_STRUCT */ 261/* offsets in apic_base[] */ 262#define APIC_ID (0x020/4) 263#define APIC_VER (0x030/4) 264#define APIC_TPR (0x080/4) 265#define APIC_APR (0x090/4) 266#define APIC_PPR (0x0a0/4) 267#define APIC_EOI (0x0b0/4) 268#define APIC_RR (0x0c0/4) 269#define APIC_LDR (0x0d0/4) 270#define APIC_DFR (0x0e0/4) 271#define APIC_SVR (0x0f0/4) 272#define APIC_ISR (0x100/4) 273#define APIC_ISR0 (0x100/4) 274#define APIC_ISR1 (0x110/4) 275#define APIC_ISR2 (0x120/4) 276#define APIC_TMR (0x180/4) 277#define APIC_IRR (0x200/4) 278#define APIC_IRR0 (0x200/4) 279#define APIC_IRR1 (0x210/4) 280#define APIC_IRR2 (0x220/4) 281#define APIC_ESR (0x280/4) 282#define APIC_ICR_LOW (0x300/4) 283#define APIC_ICR_HI (0x310/4) 284#define APIC_LVTT (0x320/4) 285#define APIC_LVT1 (0x350/4) 286#define APIC_LVT2 (0x360/4) 287#define APIC_LVT3 (0x370/4) 288#define APIC_TICR (0x380/4) 289#define APIC_TCCR (0x390/4) 290#define APIC_TDCR (0x3e0/4) 291#endif /** XXX APIC_STRUCT */ 292 293# endif /* LOCORE */ 294 295 296/* fields in VER */ 297#define APIC_VER_VERSION 0x000000ff 298#define APIC_VER_MAXLVT 0x00ff0000 299#define MAXLVTSHIFT 16 300 301/* fields in SVR */ 302#define APIC_SVR_ENABLE 0x00000100 303# define APIC_SVR_SWDIS 0x00000000 304# define APIC_SVR_SWEN 0x00000100 305#define APIC_SVR_FOCUS 0x00000200 306# define APIC_SVR_FEN 0x00000000 307# define APIC_SVR_FDIS 0x00000200 308#define APIC_TPR_PRIO 0x000000ff 309# define APIC_TPR_INT 0x000000f0 310# define APIC_TPR_SUB 0x0000000f 311 312 313/* fields in ICR_LOW */ 314#define APIC_VECTOR_MASK 0x000000ff 315 316#define APIC_DELMODE_MASK 0x00000700 317# define APIC_DELMODE_FIXED 0x00000000 318# define APIC_DELMODE_LOWPRIO 0x00000100 319# define APIC_DELMODE_SMI 0x00000200 320# define APIC_DELMODE_RR 0x00000300 321# define APIC_DELMODE_NMI 0x00000400 322# define APIC_DELMODE_INIT 0x00000500 323# define APIC_DELMODE_STARTUP 0x00000600 324# define APIC_DELMODE_RESV 0x00000700 325 326#define APIC_DESTMODE_MASK 0x00000800 327# define APIC_DESTMODE_PHY 0x00000000 328# define APIC_DESTMODE_LOG 0x00000800 329 330#define APIC_DELSTAT_MASK 0x00001000 331# define APIC_DELSTAT_IDLE 0x00000000 332# define APIC_DELSTAT_PEND 0x00001000 333 334#define APIC_RESV1_MASK 0x00002000 335 336#define APIC_LEVEL_MASK 0x00004000 337# define APIC_LEVEL_DEASSERT 0x00000000 338# define APIC_LEVEL_ASSERT 0x00004000 339 340#define APIC_TRIGMOD_MASK 0x00008000 341# define APIC_TRIGMOD_EDGE 0x00000000 342# define APIC_TRIGMOD_LEVEL 0x00008000 343 344#define APIC_RRSTAT_MASK 0x00030000 345# define APIC_RRSTAT_INVALID 0x00000000 346# define APIC_RRSTAT_INPROG 0x00010000 347# define APIC_RRSTAT_VALID 0x00020000 348# define APIC_RRSTAT_RESV 0x00030000 349 350#define APIC_DEST_MASK 0x000c0000 351# define APIC_DEST_DESTFLD 0x00000000 352# define APIC_DEST_SELF 0x00040000 353# define APIC_DEST_ALLISELF 0x00080000 354# define APIC_DEST_ALLESELF 0x000c0000 355 356#define APIC_RESV2_MASK 0xfff00000 357 358 359/* fields in ICR_HIGH */ 360#define APIC_ID_MASK 0x0f000000 361 362 363/* fields in LVT1/2 */ 364#define APIC_LVT_VECTOR 0x000000ff 365#define APIC_LVT_DS 0x00001000 366#define APIC_LVT_M 0x00010000 367 368 369/* fields in LVT Timer */ 370#define APIC_LVTT_VECTOR 0x000000ff 371#define APIC_LVTT_DS 0x00001000 372#define APIC_LVTT_M 0x00010000 373#define APIC_LVTT_TM 0x00020000 374 375 376/* fields in TDCR */ 377#define APIC_TDCR_2 0x00 378#define APIC_TDCR_4 0x01 379#define APIC_TDCR_8 0x02 380#define APIC_TDCR_16 0x03 381#define APIC_TDCR_32 0x08 382#define APIC_TDCR_64 0x09 383#define APIC_TDCR_128 0x0a 384#define APIC_TDCR_1 0x0b 385 386 387/* 388 * fields in IRR 389 * ISA INTerrupts are in bits 16-31 of the 1st IRR register. 390 * these masks DON'T EQUAL the isa IRQs of the same name. 391 * FIXME: how do we make this portable for MP table configurations??? 392 * look for "HARD_VECTORXXX" marking places with this problem. 393 */ 394#define APIC_IRQ0 0x00000001 395#define APIC_IRQ1 0x00000002 396#define APIC_IRQ2 0x00000004 397#define APIC_IRQ3 0x00000008 398#define APIC_IRQ4 0x00000010 399#define APIC_IRQ5 0x00000020 400#define APIC_IRQ6 0x00000040 401#define APIC_IRQ7 0x00000080 402#define APIC_IRQ8 0x00000100 403#define APIC_IRQ9 0x00000200 404#define APIC_IRQ10 0x00000400 405#define APIC_IRQ11 0x00000800 406#define APIC_IRQ12 0x00001000 407#define APIC_IRQ13 0x00002000 408#define APIC_IRQ14 0x00004000 409#define APIC_IRQ15 0x00008000 410#define APIC_IRQ16 0x00010000 411#define APIC_IRQ17 0x00020000 412#define APIC_IRQ18 0x00040000 413#define APIC_IRQ19 0x00080000 414#define APIC_IRQ20 0x00100000 415#define APIC_IRQ21 0x00200000 416#define APIC_IRQ22 0x00400000 417#define APIC_IRQ23 0x00800000 418 419 420/****************************************************************************** 421 * I/O APIC defines 422 */ 423 424/* default physical locations of an IO APIC */ 425#define DEFAULT_IO_APIC_BASE 0xfec00000 426 427/* window register offset */ 428#define IOAPIC_WINDOW 0x10 429 430/* indexes into IO APIC */ 431#define IOAPIC_ID 0x00 432#define IOAPIC_VER 0x01 433#define IOAPIC_ARB 0x02 434#define IOAPIC_REDTBL 0x10 435#define IOAPIC_REDTBL0 IOAPIC_REDTBL 436#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) 437#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) 438#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) 439#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) 440#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) 441#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) 442#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) 443#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) 444#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) 445#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) 446#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) 447#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) 448#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) 449#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) 450#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) 451#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) 452#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) 453#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) 454#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) 455#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) 456#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) 457#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) 458#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) 459 460/* fields in VER */ 461#define IOART_VER_VERSION 0x000000ff 462#define IOART_VER_MAXREDIR 0x00ff0000 463#define MAXREDIRSHIFT 16 464 465/* 466 * fields in the IO APIC's redirection table entries 467 */ 468#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ 469 470#define IOART_RESV 0x00fe0000 /* reserved */ 471 472#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ 473# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ 474# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ 475 476#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ 477# define IOART_TRGREDG 0x00000000 /* edge */ 478# define IOART_TRGRLVL 0x00008000 /* level */ 479 480#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ 481 482#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ 483# define IOART_INTAHI 0x00000000 /* active high */ 484# define IOART_INTALO 0x00002000 /* active low */ 485 486#define IOART_DELIVS 0x00001000 /* RO: delivery status */ 487 488#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ 489# define IOART_DESTPHY 0x00000000 /* physical */ 490# define IOART_DESTLOG 0x00000800 /* logical */ 491 492#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ 493# define IOART_DELFIXED 0x00000000 /* fixed */ 494# define IOART_DELLOPRI 0x00000100 /* lowest priority */ 495# define IOART_DELSMI 0x00000200 /* System Management INT */ 496# define IOART_DELRSV1 0x00000300 /* reserved */ 497# define IOART_DELNMI 0x00000400 /* NMI signal */ 498# define IOART_DELINIT 0x00000500 /* INIT signal */ 499# define IOART_DELRSV2 0x00000600 /* reserved */ 500# define IOART_DELEXINT 0x00000700 /* External INTerrupt */ 501 502#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ 503 504/** 505 * XXX FIXME: temproary defines till we get private pages... 506 */ 507#if 1 /** XXX APIC_STRUCT */ 508 509/* XXX when automatically mapped to a virtual page */ 510#define lapic__id lapic->id 511#define lapic__version lapic->version 512#define lapic__eoi lapic->eoi 513#define lapic__irr1 lapic->irr1 514#define lapic__lvt_lint0 lapic->lvt_lint0 515#define lapic__lvt_lint1 lapic->lvt_lint1 516#define lapic__tpr lapic->tpr 517#define lapic__svr lapic->svr 518#define lapic__icr_lo lapic->icr_lo 519#define lapic__icr_hi lapic->icr_hi 520#define lapic__dcr_timer lapic->dcr_timer 521#define lapic__lvt_timer lapic->lvt_timer 522#define lapic__icr_timer lapic->icr_timer 523#define lapic__ccr_timer lapic->ccr_timer 524 525#else 526 527/* XXX when mapped to a known virtual address */ 528#define lapic__id lapic.id 529#define lapic__version lapic.version 530#define lapic__eoi lapic.eoi 531#define lapic__irr1 lapic.irr1 532#define lapic__lvt_lint0 lapic.lvt_lint0 533#define lapic__lvt_lint1 lapic.lvt_lint1 534#define lapic__tpr lapic.tpr 535#define lapic__svr lapic.svr 536#define lapic__icr_lo lapic.icr_lo 537#define lapic__icr_hi lapic.icr_hi 538#define lapic__dcr_timer lapic.dcr_timer 539#define lapic__lvt_timer lapic.lvt_timer 540#define lapic__icr_timer lapic.icr_timer 541#define lapic__ccr_timer lapic.ccr_timer 542 543#endif /** XXX APIC_STRUCT */ 544 545#endif /* _MACHINE_APIC_H_ */ 546