1112399Sjake/*- 2112399Sjake * Copyright (c) 2003 Jake Burkholder. 3223719Smarius * Copyright (c) 2005 - 2011 Marius Strobl <marius@FreeBSD.org> 4112399Sjake * All rights reserved. 5112399Sjake * 6112399Sjake * Redistribution and use in source and binary forms, with or without 7112399Sjake * modification, are permitted provided that the following conditions 8112399Sjake * are met: 9112399Sjake * 1. Redistributions of source code must retain the above copyright 10112399Sjake * notice, this list of conditions and the following disclaimer. 11112399Sjake * 2. Redistributions in binary form must reproduce the above copyright 12112399Sjake * notice, this list of conditions and the following disclaimer in the 13112399Sjake * documentation and/or other materials provided with the distribution. 14112399Sjake * 15112399Sjake * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16112399Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17112399Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18112399Sjake * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19112399Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20112399Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21112399Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22112399Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23112399Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24112399Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25112399Sjake * SUCH DAMAGE. 26112399Sjake */ 27112399Sjake 28176994Smarius#include <sys/cdefs.h> 29176994Smarius__FBSDID("$FreeBSD$"); 30176994Smarius 31112399Sjake#include <sys/param.h> 32181701Smarius#include <sys/systm.h> 33112399Sjake#include <sys/lock.h> 34112399Sjake#include <sys/mutex.h> 35112399Sjake#include <sys/smp.h> 36112399Sjake 37112399Sjake#include <vm/vm.h> 38112399Sjake#include <vm/pmap.h> 39112399Sjake 40207537Smarius#include <machine/asi.h> 41112399Sjake#include <machine/cache.h> 42182768Smarius#include <machine/cpu.h> 43112399Sjake#include <machine/cpufunc.h> 44182768Smarius#include <machine/dcr.h> 45182768Smarius#include <machine/lsu.h> 46112399Sjake#include <machine/smp.h> 47113453Sjake#include <machine/tlb.h> 48182768Smarius#include <machine/ver.h> 49182768Smarius#include <machine/vmparam.h> 50112399Sjake 51182768Smarius#define CHEETAH_ICACHE_TAG_LOWER 0x30 52223719Smarius#define CHEETAH_T16_ENTRIES 16 53223719Smarius#define CHEETAH_DT512_ENTRIES 512 54223719Smarius#define CHEETAH_IT128_ENTRIES 128 55223719Smarius#define CHEETAH_IT512_ENTRIES 512 56182768Smarius 57112399Sjake/* 58223719Smarius * CPU-specific initialization for Sun Cheetah and later CPUs 59182768Smarius */ 60182768Smariusvoid 61204152Smariuscheetah_init(u_int cpu_impl) 62182768Smarius{ 63205269Smarius u_long val; 64182768Smarius 65182768Smarius /* Ensure the TSB Extension Registers hold 0 as TSB_Base. */ 66182768Smarius 67182768Smarius stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0); 68182768Smarius stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0); 69182768Smarius membar(Sync); 70182768Smarius 71182768Smarius stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0); 72182768Smarius /* 73182768Smarius * NB: the secondary context was removed from the iMMU. 74182768Smarius */ 75182768Smarius membar(Sync); 76182768Smarius 77182768Smarius stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0); 78182768Smarius stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0); 79182768Smarius membar(Sync); 80182768Smarius 81182878Smarius /* 82205269Smarius * Configure the first large dTLB to hold 4MB pages (e.g. for direct 83205269Smarius * mappings) for all three contexts and ensure the second one is set 84205269Smarius * up to hold 8k pages for them. Note that this is constraint by 85205269Smarius * US-IV+, whose large dTLBs can only hold entries of certain page 86205269Smarius * sizes each. 87205269Smarius * For US-IV+, additionally ensure that the large iTLB is set up to 88205269Smarius * hold 8k pages for nucleus and primary context (still no secondary 89205269Smarius * iMMU context. 90205269Smarius * NB: according to documentation, changing the page size of the same 91205269Smarius * context requires a context demap before changing the corresponding 92205269Smarius * page size, but we hardly can flush our locked pages here, so we use 93205269Smarius * a demap all instead. 94182878Smarius */ 95182878Smarius stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0); 96182878Smarius membar(Sync); 97205269Smarius val = (TS_4M << TLB_PCXR_N_PGSZ0_SHIFT) | 98205269Smarius (TS_8K << TLB_PCXR_N_PGSZ1_SHIFT) | 99205269Smarius (TS_4M << TLB_PCXR_P_PGSZ0_SHIFT) | 100205269Smarius (TS_8K << TLB_PCXR_P_PGSZ1_SHIFT); 101205269Smarius if (cpu_impl == CPU_IMPL_ULTRASPARCIVp) 102205269Smarius val |= (TS_8K << TLB_PCXR_N_PGSZ_I_SHIFT) | 103205269Smarius (TS_8K << TLB_PCXR_P_PGSZ_I_SHIFT); 104205269Smarius stxa(AA_DMMU_PCXR, ASI_DMMU, val); 105205269Smarius val = (TS_4M << TLB_SCXR_S_PGSZ0_SHIFT) | 106205269Smarius (TS_8K << TLB_SCXR_S_PGSZ1_SHIFT); 107205269Smarius stxa(AA_DMMU_SCXR, ASI_DMMU, val); 108182878Smarius flush(KERNBASE); 109182878Smarius 110205269Smarius /* 111205269Smarius * Ensure DCR_IFPOE is disabled as long as we haven't implemented 112205269Smarius * support for it (if ever) as most if not all firmware versions 113205269Smarius * apparently turn it on. Not making use of DCR_IFPOE should also 114205269Smarius * avoid Cheetah erratum #109. 115205269Smarius */ 116205269Smarius val = rd(asr18) & ~DCR_IFPOE; 117205269Smarius if (cpu_impl == CPU_IMPL_ULTRASPARCIVp) { 118205269Smarius /* 119205269Smarius * Ensure the branch prediction mode is set to PC indexing 120205269Smarius * in order to work around US-IV+ erratum #2. 121205269Smarius */ 122205269Smarius val = (val & ~DCR_BPM_MASK) | DCR_BPM_PC; 123205269Smarius /* 124205269Smarius * XXX disable dTLB parity error reporting as otherwise we 125205269Smarius * get seemingly false positives when copying in the user 126205269Smarius * window by simulating a fill trap on return to usermode in 127205269Smarius * case single issue is disabled, which thus appears to be 128205269Smarius * a CPU bug. 129205269Smarius */ 130205269Smarius val &= ~DCR_DTPE; 131205269Smarius } 132205269Smarius wr(asr18, val, 0); 133182768Smarius} 134182768Smarius 135182768Smarius/* 136122464Sjake * Enable level 1 caches. 137122464Sjake */ 138122464Sjakevoid 139204152Smariuscheetah_cache_enable(u_int cpu_impl) 140122464Sjake{ 141182768Smarius u_long lsu; 142176994Smarius 143182768Smarius lsu = ldxa(0, ASI_LSU_CTL_REG); 144182768Smarius if (cpu_impl == CPU_IMPL_ULTRASPARCIII) { 145205269Smarius /* Disable P$ due to US-III erratum #18. */ 146182768Smarius lsu &= ~LSU_PE; 147182768Smarius } 148182768Smarius stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC); 149205269Smarius flush(KERNBASE); 150122464Sjake} 151122464Sjake 152122464Sjake/* 153122464Sjake * Flush all lines from the level 1 caches. 154122464Sjake */ 155122464Sjakevoid 156122464Sjakecheetah_cache_flush(void) 157122464Sjake{ 158182768Smarius u_long addr, lsu; 159205269Smarius register_t s; 160176994Smarius 161205269Smarius s = intr_disable(); 162182768Smarius for (addr = 0; addr < PCPU_GET(cache.dc_size); 163182768Smarius addr += PCPU_GET(cache.dc_linesize)) 164205269Smarius /* 165205269Smarius * Note that US-IV+ additionally require a membar #Sync before 166205269Smarius * a load or store to ASI_DCACHE_TAG. 167205269Smarius */ 168205269Smarius __asm __volatile( 169205269Smarius "membar #Sync;" 170205269Smarius "stxa %%g0, [%0] %1;" 171205269Smarius "membar #Sync" 172205269Smarius : : "r" (addr), "n" (ASI_DCACHE_TAG)); 173182768Smarius 174182768Smarius /* The I$ must be disabled when flushing it so ensure it's off. */ 175182768Smarius lsu = ldxa(0, ASI_LSU_CTL_REG); 176182768Smarius stxa(0, ASI_LSU_CTL_REG, lsu & ~(LSU_IC)); 177205269Smarius flush(KERNBASE); 178182768Smarius for (addr = CHEETAH_ICACHE_TAG_LOWER; 179182768Smarius addr < PCPU_GET(cache.ic_size) * 2; 180182768Smarius addr += PCPU_GET(cache.ic_linesize) * 2) 181205269Smarius __asm __volatile( 182205269Smarius "stxa %%g0, [%0] %1;" 183205269Smarius "membar #Sync" 184205269Smarius : : "r" (addr), "n" (ASI_ICACHE_TAG)); 185182768Smarius stxa(0, ASI_LSU_CTL_REG, lsu); 186205269Smarius flush(KERNBASE); 187205269Smarius intr_restore(s); 188122464Sjake} 189122464Sjake 190122464Sjake/* 191112399Sjake * Flush a physical page from the data cache. 192112399Sjake */ 193112399Sjakevoid 194113238Sjakecheetah_dcache_page_inval(vm_paddr_t spa) 195112399Sjake{ 196113238Sjake vm_paddr_t pa; 197112399Sjake void *cookie; 198112399Sjake 199205269Smarius KASSERT((spa & PAGE_MASK) == 0, 200205269Smarius ("%s: pa not page aligned", __func__)); 201112399Sjake cookie = ipi_dcache_page_inval(tl_ipi_cheetah_dcache_page_inval, spa); 202205269Smarius for (pa = spa; pa < spa + PAGE_SIZE; 203205269Smarius pa += PCPU_GET(cache.dc_linesize)) 204112399Sjake stxa_sync(pa, ASI_DCACHE_INVALIDATE, 0); 205112399Sjake ipi_wait(cookie); 206112399Sjake} 207112399Sjake 208112399Sjake/* 209112399Sjake * Flush a physical page from the intsruction cache. Instruction cache 210112399Sjake * consistency is maintained by hardware. 211112399Sjake */ 212112399Sjakevoid 213207537Smariuscheetah_icache_page_inval(vm_paddr_t pa __unused) 214112399Sjake{ 215176994Smarius 216112399Sjake} 217113453Sjake 218176994Smarius/* 219223719Smarius * Flush all non-locked mappings from the TLBs. 220176994Smarius */ 221113453Sjakevoid 222176994Smariuscheetah_tlb_flush_nonlocked(void) 223176994Smarius{ 224176994Smarius 225223719Smarius stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0); 226223719Smarius stxa(TLB_DEMAP_ALL, ASI_IMMU_DEMAP, 0); 227223719Smarius flush(KERNBASE); 228176994Smarius} 229176994Smarius 230176994Smarius/* 231223719Smarius * Flush all user mappings from the TLBs. 232176994Smarius */ 233176994Smariusvoid 234223719Smariuscheetah_tlb_flush_user(void) 235113453Sjake{ 236223719Smarius u_long data, tag; 237223719Smarius register_t s; 238223719Smarius u_int i, slot; 239176994Smarius 240182768Smarius /* 241223719Smarius * We read ASI_{D,I}TLB_DATA_ACCESS_REG twice back-to-back in order 242223719Smarius * to work around errata of USIII and beyond. 243182768Smarius */ 244223719Smarius for (i = 0; i < CHEETAH_T16_ENTRIES; i++) { 245223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_T16, i); 246223719Smarius s = intr_disable(); 247223719Smarius (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 248223719Smarius data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 249223719Smarius intr_restore(s); 250223719Smarius tag = ldxa(slot, ASI_DTLB_TAG_READ_REG); 251223719Smarius if ((data & TD_V) != 0 && (data & TD_L) == 0 && 252223719Smarius TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 253223719Smarius stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 254223719Smarius s = intr_disable(); 255223719Smarius (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 256223719Smarius data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 257223719Smarius intr_restore(s); 258223719Smarius tag = ldxa(slot, ASI_ITLB_TAG_READ_REG); 259223719Smarius if ((data & TD_V) != 0 && (data & TD_L) == 0 && 260223719Smarius TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 261223719Smarius stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 262223719Smarius } 263223719Smarius for (i = 0; i < CHEETAH_DT512_ENTRIES; i++) { 264223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_DT512_0, i); 265223719Smarius s = intr_disable(); 266223719Smarius (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 267223719Smarius data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 268223719Smarius intr_restore(s); 269223719Smarius tag = ldxa(slot, ASI_DTLB_TAG_READ_REG); 270223719Smarius if ((data & TD_V) != 0 && TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 271223719Smarius stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 272223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_DT512_1, i); 273223719Smarius s = intr_disable(); 274223719Smarius (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 275223719Smarius data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 276223719Smarius intr_restore(s); 277223719Smarius tag = ldxa(slot, ASI_DTLB_TAG_READ_REG); 278223719Smarius if ((data & TD_V) != 0 && TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 279223719Smarius stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 280223719Smarius } 281223719Smarius if (PCPU_GET(impl) == CPU_IMPL_ULTRASPARCIVp) { 282223719Smarius for (i = 0; i < CHEETAH_IT512_ENTRIES; i++) { 283223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_IT512, i); 284223719Smarius s = intr_disable(); 285223719Smarius (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 286223719Smarius data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 287223719Smarius intr_restore(s); 288223719Smarius tag = ldxa(slot, ASI_ITLB_TAG_READ_REG); 289223719Smarius if ((data & TD_V) != 0 && 290223719Smarius TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 291223719Smarius stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 292223719Smarius } 293223719Smarius } else { 294223719Smarius for (i = 0; i < CHEETAH_IT128_ENTRIES; i++) { 295223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_IT128, i); 296223719Smarius s = intr_disable(); 297223719Smarius (void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 298223719Smarius data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 299223719Smarius tag = ldxa(slot, ASI_ITLB_TAG_READ_REG); 300223719Smarius intr_restore(s); 301223719Smarius if ((data & TD_V) != 0 && 302223719Smarius TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 303223719Smarius stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 304223719Smarius } 305223719Smarius } 306113453Sjake} 307