schizoreg.h revision 208097
1/*- 2 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 3 * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp 28 * $FreeBSD: head/sys/sparc64/pci/schizoreg.h 208097 2010-05-14 20:00:21Z marius $ 29 */ 30 31#ifndef _SPARC64_PCI_SCHIZOREG_H_ 32#define _SPARC64_PCI_SCHIZOREG_H_ 33 34#define STX_NINTR 5 /* 4 via OFW + 1 CDMA */ 35#define STX_NRANGE 4 36#define SCZ_NREG 3 37#define TOM_NREG 4 38 39#define STX_PCI 0 40#define STX_CTRL 1 41#define STX_PCICFG 2 42#define STX_ICON 3 43 44/* PCI configuration and status registers */ 45#define SX_PCI_CFG_ICD 0x00110 46#define STX_PCI_IOMMU 0x00200 47#define STX_PCI_IOMMU_CTXFLUSH 0x00218 48#define STX_PCI_IMAP_BASE 0x01000 49#define STX_PCI_ICLR_BASE 0x01400 50#define STX_PCI_INTR_RETRY_TIM 0x01a00 51#define SCZ_PCI_DMA_SYNC 0x01a08 52#define TOM_PCI_DMA_SYNC_COMP 0x01a10 53#define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18 54#define STX_PCI_CTRL 0x02000 55#define STX_PCI_AFSR 0x02010 56#define STX_PCI_AFAR 0x02018 57#define STX_PCI_DIAG 0x02020 58#define TOM_PCI_IOC_CSR 0x02248 59#define TOM_PCI_IOC_TAG 0x02290 60#define TOM_PCI_IOC_DATA 0x02290 61#define STX_PCI_STRBUF 0x02800 62#define STX_PCI_STRBUF_CTXFLUSH 0x02818 63#define STX_PCI_IOMMU_SVADIAG 0x0a400 64#define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408 65#define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500 66#define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580 67#define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600 68#define STX_PCI_IOBIO_DIAG 0x0a808 69#define STX_PCI_STRBUF_CTXMATCH 0x10000 70 71/* PCI configuration/idle check diagnostic registers */ 72#define SX_PCI_CFG_ICD_PCI_2_0_COMPAT 0x0000000000008000ULL 73#define SX_PCI_CFG_ICD_DMAW_PERR_IEN 0x0000000000004000ULL 74#define SX_PCI_CFG_ICD_IFC_NOT_IDLE 0x0000000000000010ULL 75#define SX_PCI_CFG_ICD_MDU_NOT_IDLE 0x0000000000000008ULL 76#define SX_PCI_CFG_ICD_MMU_NOT_IDLE 0x0000000000000004ULL 77#define SX_PCI_CFG_ICD_PBM_NOT_IDLE 0x0000000000000002ULL 78#define SX_PCI_CFG_ICD_STC_NOT_IDLE 0x0000000000000001ULL 79 80/* PCI IOMMU control registers */ 81#define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL 82#define TOM_PCI_IOMMU_ERR_ILLTSBTBW 0x0000000008000000ULL 83#define TOM_PCI_IOMMU_ECC_ERR 0x0000000006000000ULL 84#define TOM_PCI_IOMMU_TIMEOUT_ERR 0x0000000004000000ULL 85#define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL 86#define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL 87#define TOM_PCI_IOMMU_ERRMASK \ 88 (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \ 89 TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR) 90#define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL 91 92/* PCI control/status register */ 93#define SCZ_PCI_CTRL_BUS_UNUS 0x8000000000000000ULL 94#define TOM_PCI_CTRL_DTO_ERR 0x4000000000000000ULL 95#define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL 96#define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL 97#define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL 98#define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL 99#define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL 100#define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL 101#define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL 102#define STX_PCI_CTRL_SERR 0x0000000400000000ULL 103#define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL 104#define TOM_PCI_CTRL_PRM 0x0000000040000000ULL 105#define TOM_PCI_CTRL_PRO 0x0000000020000000ULL 106#define TOM_PCI_CTRL_PRL 0x0000000010000000ULL 107#define STX_PCI_CTRL_PTO 0x0000000003000000ULL 108#define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL 109#define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL 110#define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL 111#define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL 112#define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL 113#define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL 114 115/* PCI asynchronous fault status register */ 116#define STX_PCI_AFSR_P_MA 0x8000000000000000ULL 117#define STX_PCI_AFSR_P_TA 0x4000000000000000ULL 118#define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL 119#define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL 120#define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL 121#define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL 122#define STX_PCI_AFSR_S_MA 0x0200000000000000ULL 123#define STX_PCI_AFSR_S_TA 0x0100000000000000ULL 124#define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL 125#define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL 126#define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL 127#define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL 128#define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL 129#define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL 130#define STX_PCI_AFSR_BLK 0x0000000080000000ULL 131#define STX_PCI_AFSR_CFG 0x0000000040000000ULL 132#define STX_PCI_AFSR_MEM 0x0000000020000000ULL 133#define STX_PCI_AFSR_IO 0x0000000010000000ULL 134 135/* PCI diagnostic register */ 136#define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL 137#define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL 138#define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL 139#define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL 140#define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL 141#define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL 142#define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL 143#define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL 144#define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL 145 146/* Tomatillo I/O cache register */ 147#define TOM_PCI_IOC_PW 0x0000000000080000ULL 148#define TOM_PCI_IOC_PRM 0x0000000000040000ULL 149#define TOM_PCI_IOC_PRO 0x0000000000020000ULL 150#define TOM_PCI_IOC_PRL 0x0000000000010000ULL 151#define TOM_PCI_IOC_PRM_LEN 0x000000000000c000ULL 152#define TOM_PCI_IOC_PRM_LEN_SHIFT 14 153#define TOM_PCI_IOC_PRO_LEN 0x0000000000003000ULL 154#define TOM_PCI_IOC_PRO_LEN_SHIFT 12 155#define TOM_PCI_IOC_PRL_LEN 0x0000000000000c00ULL 156#define TOM_PCI_IOC_PRL_LEN_SHIFT 10 157#define TOM_PCI_IOC_PREF_OFF 0x0000000000000038ULL 158#define TOM_PCI_IOC_PREF_OFF_SHIFT 3 159#define TOM_PCI_IOC_CPRM 0x0000000000000004ULL 160#define TOM_PCI_IOC_CPRO 0x0000000000000002ULL 161#define TOM_PCI_IOC_CPRL 0x0000000000000001ULL 162 163/* Controller configuration and status registers */ 164/* Note that these are shared on Schizo but per-PBM on Tomatillo. */ 165#define STX_CTRL_BUS_ERRLOG 0x00018 166#define STX_CTRL_ECCCTRL 0x00020 167#define STX_CTRL_UE_AFSR 0x00030 168#define STX_CTRL_UE_AFAR 0x00038 169#define STX_CTRL_CE_AFSR 0x00040 170#define STX_CTRL_CE_AFAR 0x00048 171#define STX_CTRL_PERF 0x07000 172#define STX_CTRL_PERF_CNT 0x07008 173 174/* Safari/JBus error log register */ 175#define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL 176#define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL 177#define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL 178#define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL 179#define SCZ_CTRL_BUS_ERRLOG_BADMC 0x0400000000000000ULL 180#define TOM_CTRL_BUS_ERRLOG_SNOOP_GR 0x0000000000200000ULL 181#define TOM_CTRL_BUS_ERRLOG_SNOOP_PCI 0x0000000000100000ULL 182#define TOM_CTRL_BUS_ERRLOG_SNOOP_RD 0x0000000000080000ULL 183#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDS 0x0000000000020000ULL 184#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA 0x0000000000010000ULL 185#define TOM_CTRL_BUS_ERRLOG_SNOOP_OWN 0x0000000000008000ULL 186#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDO 0x0000000000004000ULL 187#define SCZ_CTRL_BUS_ERRLOG_CPU1PS 0x0000000000002000ULL 188#define TOM_CTRL_BUS_ERRLOG_WDATA_PERR 0x0000000000002000ULL 189#define SCZ_CTRL_BUS_ERRLOG_CPU1PB 0x0000000000001000ULL 190#define TOM_CTRL_BUS_ERRLOG_CTRL_PERR 0x0000000000001000ULL 191#define SCZ_CTRL_BUS_ERRLOG_CPU0PS 0x0000000000000800ULL 192#define TOM_CTRL_BUS_ERRLOG_SNOOP_ERR 0x0000000000000800ULL 193#define SCZ_CTRL_BUS_ERRLOG_CPU0PB 0x0000000000000400ULL 194#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B 0x0000000000000400ULL 195#define SCZ_CTRL_BUS_ERRLOG_CIQTO 0x0000000000000200ULL 196#define SCZ_CTRL_BUS_ERRLOG_LPQTO 0x0000000000000100ULL 197#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C 0x0000000000000100ULL 198#define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL 199#define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL 200#define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL 201#define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL 202#define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL 203#define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL 204#define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL 205#define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL 206 207/* ECC control register */ 208#define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL 209#define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL 210#define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL 211 212/* Uncorrectable error asynchronous fault status register */ 213#define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL 214#define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL 215#define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL 216#define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL 217#define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL 218#define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL 219#define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL 220#define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL 221#define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL 222#define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL 223#define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL 224#define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL 225#define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL 226#define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL 227#define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL 228 229/* Correctable error asynchronous fault status register */ 230#define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL 231#define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL 232#define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL 233#define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL 234#define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL 235#define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL 236#define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL 237#define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL 238#define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL 239#define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL 240#define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL 241#define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL 242#define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL 243#define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL 244#define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL 245 246/* 247 * Safari/JBus performance control register 248 * NB: for Tomatillo only events 0x00 through 0x08 are documented as 249 * implemented. 250 */ 251#define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL 252#define SCZ_CTRL_PERF_ZDATA_IN 0x0000000000000015ULL 253#define SCZ_CTRL_PERF_ORQFULL 0x0000000000000014ULL 254#define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL 255#define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL 256#define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL 257#define STX_CTRL_PERF_PCI_B 0x000000000000000fULL 258#define STX_CTRL_PERF_PCI_A 0x000000000000000eULL 259#define STX_CTRL_PERF_UPA 0x000000000000000dULL 260#define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL 261#define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL 262#define STX_CTRL_PERF_INTRS 0x000000000000000aULL 263#define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL 264#define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL 265#define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL 266#define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL 267#define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL 268#define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL 269#define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL 270#define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL 271#define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL 272#define STX_CTRL_PERF_DIS 0x0000000000000000ULL 273#define STX_CTRL_PERF_CNT1_SHIFT 11 274#define STX_CTRL_PERF_CNT0_SHIFT 4 275 276/* Safari/JBus performance counter register */ 277#define STX_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL 278#define STX_CTRL_PERF_CNT_CNT1_SHIFT 32 279#define STX_CTRL_PERF_CNT_CNT0_SHIFT 0 280 281/* INO defines */ 282#define STX_FB0_INO 0x2a /* FB0 int. shared w/ UPA64s */ 283#define STX_FB1_INO 0x2b /* FB1 int. shared w/ UPA64s */ 284#define STX_UE_INO 0x30 /* uncorrectable error */ 285#define STX_CE_INO 0x31 /* correctable error */ 286#define STX_PCIERR_A_INO 0x32 /* PCI bus A error */ 287#define STX_PCIERR_B_INO 0x33 /* PCI bus B error */ 288#define STX_BUS_INO 0x34 /* Safari/JBus error */ 289#define STX_CDMA_A_INO 0x35 /* PCI bus A CDMA */ 290#define STX_CDMA_B_INO 0x36 /* PCI bus B CDMA */ 291#define STX_MAX_INO 0x37 292 293/* Device space defines */ 294#define STX_CONF_SIZE 0x1000000 295#define STX_CONF_BUS_SHIFT 16 296#define STX_CONF_DEV_SHIFT 11 297#define STX_CONF_FUNC_SHIFT 8 298#define STX_CONF_REG_SHIFT 0 299#define STX_IO_SIZE 0x1000000 300#define STX_MEM_SIZE 0x100000000 301 302#define STX_CONF_OFF(bus, slot, func, reg) \ 303 (((bus) << STX_CONF_BUS_SHIFT) | \ 304 ((slot) << STX_CONF_DEV_SHIFT) | \ 305 ((func) << STX_CONF_FUNC_SHIFT) | \ 306 ((reg) << STX_CONF_REG_SHIFT)) 307 308/* Definitions for the Schizo/Tomatillo configuration space */ 309#define STX_CS_DEVICE 0 /* bridge CS device number */ 310#define STX_CS_FUNC 0 /* brdige CS function number */ 311 312/* Non-Standard registers in the configration space */ 313/* 314 * NB: for Tomatillo the secondary and subordinate bus number registers 315 * apparently are read-only although documented otherwise; writing to 316 * them just triggers a PCI bus error interrupt or has no effect at best. 317 */ 318#define STX_CSR_SECBUS 0x40 /* secondary bus number */ 319#define STX_CSR_SUBBUS 0x41 /* subordinate bus number */ 320 321/* Width of the physical addresses the IOMMU translates to */ 322#define STX_IOMMU_BITS 43 323 324#endif /* !_SPARC64_PCI_SCHIZOREG_H_ */ 325