instr.h revision 88663
1234353Sdim/* 2193323Sed * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3193323Sed * Copyright (c) 1995 Paul Kranenburg 4193323Sed * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5193323Sed * All rights reserved. 6193323Sed * 7193323Sed * Redistribution and use in source and binary forms, with or without 8193323Sed * modification, are permitted provided that the following conditions 9193323Sed * are met: 10193323Sed * 1. Redistributions of source code must retain the above copyright 11193323Sed * notice, this list of conditions and the following disclaimer. 12193323Sed * 2. Redistributions in binary form must reproduce the above copyright 13193323Sed * notice, this list of conditions and the following disclaimer in the 14193323Sed * documentation and/or other materials provided with the distribution. 15193323Sed * 3. All advertising materials mentioning features or use of this software 16193323Sed * must display the following acknowledgement: 17193323Sed * This product includes software developed by David Miller. 18193323Sed * 4. The name of the author may not be used to endorse or promote products 19193323Sed * derived from this software without specific prior written permission 20193323Sed * 21193323Sed * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22193323Sed * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23193323Sed * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24228379Sdim * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25228379Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26228379Sdim * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27228379Sdim * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28228379Sdim * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29228379Sdim * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30228379Sdim * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31228379Sdim * 32228379Sdim * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33228379Sdim * 34228379Sdim * $FreeBSD: head/sys/sparc64/include/instr.h 88663 2001-12-29 08:55:56Z jake $ 35228379Sdim */ 36228379Sdim 37228379Sdim#ifndef _MACHINE_INSTR_H_ 38228379Sdim#define _MACHINE_INSTR_H_ 39193323Sed 40221345Sdim/* 41228379Sdim * Definitions for all instruction formats 42193323Sed */ 43193323Sed#define IF_OP_SHIFT 30 44228379Sdim#define IF_OP_BITS 2 45193323Sed#define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 46193323Sed 47193323Sed/* 48234982Sdim * Definitions for format 2 49234982Sdim */ 50228379Sdim#define IF_F2_RD_SHIFT 25 51193323Sed#define IF_F2_RD_BITS 5 52228379Sdim#define IF_F2_A_SHIFT 29 53228379Sdim#define IF_F2_A_BITS 1 54221345Sdim#define IF_F2_COND_SHIFT 25 55228379Sdim#define IF_F2_COND_BITS 4 56228379Sdim#define IF_F2_RCOND_SHIFT 25 57193323Sed#define IF_F2_RCOND_BITS 3 58193323Sed#define IF_F2_OP2_SHIFT 22 59193323Sed#define IF_F2_OP2_BITS 3 60193323Sed#define IF_F2_CC1_SHIFT 21 61228379Sdim#define IF_F2_CC1_BITS 1 62228379Sdim#define IF_F2_CC0_SHIFT 20 63228379Sdim#define IF_F2_CC0_BITS 1 64228379Sdim#define IF_F2_D16HI_SHIFT 20 65228379Sdim#define IF_F2_D16HI_BITS 2 66228379Sdim#define IF_F2_P_SHIFT 19 67228379Sdim#define IF_F2_P_BITS 1 68228379Sdim#define IF_F2_RS1_SHIFT 14 69234982Sdim#define IF_F2_RS1_BITS 5 70234982Sdim 71234982Sdim/* 72234982Sdim * Definitions for format 3 73193323Sed */ 74193323Sed#define IF_F3_OP3_SHIFT 19 75193323Sed#define IF_F3_OP3_BITS 6 76193323Sed#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 77228379Sdim#define IF_F3_RD_BITS IF_F2_RD_BITS 78228379Sdim#define IF_F3_FCN_SHIFT 25 79226633Sdim#define IF_F3_FCN_BITS 5 80226633Sdim#define IF_F3_CC1_SHIFT 26 81193323Sed#define IF_F3_CC1_BITS 1 82193323Sed#define IF_F3_CC0_SHIFT 25 83193323Sed#define IF_F3_CC0_BITS 1 84193323Sed#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 85193323Sed#define IF_F3_RS1_BITS IF_F2_RS1_BITS 86193323Sed#define IF_F3_I_SHIFT 13 87193323Sed#define IF_F3_I_BITS 1 88228379Sdim#define IF_F3_X_SHIFT 12 89193323Sed#define IF_F3_X_BITS 1 90193323Sed#define IF_F3_RCOND_SHIFT 10 91193323Sed#define IF_F3_RCOND_BITS 3 92193323Sed#define IF_F3_IMM_ASI_SHIFT 5 93193323Sed#define IF_F3_IMM_ASI_BITS 8 94193323Sed#define IF_F3_OPF_SHIFT 5 95193323Sed#define IF_F3_OPF_BITS 9 96228379Sdim#define IF_F3_CMASK_SHIFT 4 97193323Sed#define IF_F3_CMASK_BITS 3 98193323Sed#define IF_F3_RS2_SHIFT 0 99193323Sed#define IF_F3_RS2_BITS 5 100221345Sdim#define IF_F3_SHCNT32_SHIFT 0 101193323Sed#define IF_F3_SHCNT32_BITS 5 102193323Sed#define IF_F3_SHCNT64_SHIFT 0 103193323Sed#define IF_F3_SHCNT64_BITS 6 104193323Sed 105193323Sed/* 106193323Sed * Definitions for format 4 107193323Sed */ 108193323Sed#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 109193323Sed#define IF_F4_OP3_BITS IF_F3_OP3_BITS 110193323Sed#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 111228379Sdim#define IF_F4_RD_BITS IF_F2_RD_BITS 112193323Sed#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 113193323Sed#define IF_F4_RS1_BITS IF_F2_RS1_BITS 114193323Sed#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 115193323Sed#define IF_F4_TCOND_BITS IF_F2_COND_BITS 116193323Sed#define IF_F4_CC2_SHIFT 18 117228379Sdim#define IF_F4_CC2_BITS 1 118193323Sed#define IF_F4_COND_SHIFT 14 119193323Sed#define IF_F4_COND_BITS 4 120221345Sdim#define IF_F4_I_SHIFT IF_F3_I_SHIFT 121193323Sed#define IF_F4_I_BITS IF_F3_I_BITS 122193323Sed#define IF_F4_OPF_CC_SHIFT 11 123193323Sed#define IF_F4_OPF_CC_BITS 3 124234353Sdim#define IF_F4_CC1_SHIFT 12 125226633Sdim#define IF_F4_CC1_BITS 1 126228379Sdim#define IF_F4_CC0_SHIFT 11 127226633Sdim#define IF_F4_CC0_BITS 1 128226633Sdim#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 129226633Sdim#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 130226633Sdim#define IF_F4_OPF_LOW_SHIFT 5 131226633Sdim#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 132228379Sdim#define IF_F4_RS2_BITS IF_F3_RS2_BITS 133226633Sdim#define IF_F4_SW_TRAP_SHIFT 0 134226633Sdim#define IF_F4_SW_TRAP_BITS 7 135226633Sdim 136226633Sdim/* 137226633Sdim * Macros to decode instructions 138226633Sdim */ 139193323Sed/* Extract a field */ 140193323Sed#define IF_MASK(s, w) (((1 << (w)) - 1) << (s)) 141193323Sed#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s)) 142193323Sed#define IF_DECODE(x, f) \ 143193323Sed IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 144228379Sdim 145193323Sed/* Sign-extend a field of width W */ 146193323Sed#define IF_SEXT(x, w) \ 147193323Sed (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x)) 148228379Sdim 149221345Sdim#if 0 150193323Sed/* 151193323Sed * The following C variant is from db_disassemble.c, and surely faster, but it 152193323Sed * relies on behaviour that is undefined by the C standard (>> in conjunction 153193323Sed * with signed negative arguments). 154193323Sed */ 155193323Sed#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 156193323Sed/* Assembler version of the above */ 157193323Sed#define IF_SEXT(v, w) \ 158193323Sed { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 159193323Sed "=r" (t) : "r" (v) : "i" (64 - w)); t)} 160193323Sed#endif 161193323Sed 162193323Sed/* All instruction formats */ 163193323Sed#define IF_OP(i) IF_DECODE(i, OP) 164193323Sed 165193323Sed/* Instruction format 2 */ 166193323Sed#define IF_F2_RD(i) IF_DECODE((i), F2_RD) 167193323Sed#define IF_F2_A(i) IF_DECODE((i), F2_A) 168193323Sed#define IF_F2_COND(i) IF_DECODE((i), F2_COND) 169193323Sed#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 170221345Sdim#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 171221345Sdim#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 172228379Sdim#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 173193323Sed#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 174193323Sed#define IF_F2_P(i) IF_DECODE((i), F2_P) 175193323Sed#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 176193323Sed 177193323Sed/* Instruction format 3 */ 178193323Sed#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 179193323Sed#define IF_F3_RD(i) IF_F2_RD((i)) 180228379Sdim#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 181193323Sed#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 182193323Sed#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 183193323Sed#define IF_F3_RS1(i) IF_F2_RS1((i)) 184193323Sed#define IF_F3_I(i) IF_DECODE((i), F3_I) 185221345Sdim#define IF_F3_X(i) IF_DECODE((i), F3_X) 186193323Sed#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 187193323Sed#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 188193323Sed#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 189193323Sed#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 190193323Sed#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 191193323Sed#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 192193323Sed#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 193193323Sed 194193323Sed/* Instruction format 4 */ 195221345Sdim#define IF_F4_OP3(i) IF_F3_OP3((i)) 196228379Sdim#define IF_F4_RD(i) IF_F3_RD((i)) 197193323Sed#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 198193323Sed#define IF_F4_RS1(i) IF_F3_RS1((i)) 199193323Sed#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 200193323Sed#define IF_F4_COND(i) IF_DECODE((i), F4_COND) 201193323Sed#define IF_F4_I(i) IF_F3_I((i)) 202228379Sdim#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 203193323Sed#define IF_F4_RCOND(i) IF_F3_RCOND((i)) 204193323Sed#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 205221345Sdim#define IF_F4_RS2(i) IF_F3_RS2((i)) 206193323Sed#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 207193323Sed 208193323Sed/* Extract an immediate from an instruction, with an without sign extension */ 209193323Sed#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 210193323Sed#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 211193323Sed 212193323Sed/* 213221345Sdim * Macros to encode instructions 214228379Sdim */ 215193323Sed#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 216193323Sed#define IF_ENCODE(x, f) \ 217193323Sed IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 218193323Sed 219193323Sed/* All instruction formats */ 220193323Sed#define EIF_OP(x) IF_ENCODE((x), OP) 221228379Sdim 222193323Sed/* Instruction format 2 */ 223193323Sed#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 224193323Sed#define EIF_F2_A(x) IF_ENCODE((x), F2_A) 225221345Sdim#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 226193323Sed#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 227193323Sed#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 228193323Sed#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 229193323Sed#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 230193323Sed#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 231221345Sdim#define EIF_F2_P(x) IF_ENCODE((x), F2_P) 232221345Sdim#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 233221345Sdim 234221345Sdim/* Instruction format 3 */ 235228379Sdim#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 236221345Sdim#define EIF_F3_RD(x) EIF_F2_RD((x)) 237221345Sdim#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 238221345Sdim#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 239228379Sdim#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 240221345Sdim#define EIF_F3_RS1(x) EIF_F2_RS1((x)) 241221345Sdim#define EIF_F3_I(x) IF_ENCODE((x), F3_I) 242228379Sdim#define EIF_F3_X(x) IF_ENCODE((x), F3_X) 243221345Sdim#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 244221345Sdim#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 245221345Sdim#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 246228379Sdim#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 247221345Sdim#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 248221345Sdim#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 249221345Sdim#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 250221345Sdim 251221345Sdim/* Instruction format 4 */ 252221345Sdim#define EIF_F4_OP3(x) EIF_F3_OP3((x)) 253221345Sdim#define EIF_F4_RD(x) EIF_F2_RD((x)) 254221345Sdim#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 255221345Sdim#define EIF_F4_RS1(x) EIF_F2_RS1((x)) 256228379Sdim#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 257221345Sdim#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 258221345Sdim#define EIF_F4_I(x) EIF_F3_I((x)) 259221345Sdim#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 260228379Sdim#define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 261221345Sdim#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 262221345Sdim#define EIF_F4_RS2(x) EIF_F3_RS2((x)) 263221345Sdim#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 264228379Sdim 265221345Sdim/* Immediates */ 266221345Sdim#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 267221345Sdim#define EIF_SIMM(x, w) IF_EIMM((x), (w)) 268221345Sdim 269228379Sdim/* 270221345Sdim * OP field values (specifying the instruction format) 271221345Sdim */ 272221345Sdim#define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 273221345Sdim#define IOP_CALL 0x01 /* Format 1: call */ 274221345Sdim#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 275226633Sdim#define IOP_LDST 0x03 /* Format 4: loads and stores */ 276226633Sdim 277226633Sdim/* 278226633Sdim * OP2/OP3 values (specifying the actual instruction) 279226633Sdim */ 280226633Sdim/* OP2 values for format 2 (OP = 0) */ 281226633Sdim#define INS0_ILLTRAP 0x00 282226633Sdim#define INS0_BPcc 0x01 283226633Sdim#define INS0_Bicc 0x02 284226633Sdim#define INS0_BPr 0x03 285226633Sdim#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 286226633Sdim#define INS0_FBPfcc 0x05 287226633Sdim#define INS0_FBfcc 0x06 288226633Sdim/* undefined 0x07 */ 289226633Sdim 290226633Sdim/* OP3 values for Format 3 and 4 (OP = 2) */ 291226633Sdim#define INS2_ADD 0x00 292226633Sdim#define INS2_AND 0x01 293226633Sdim#define INS2_OR 0x02 294226633Sdim#define INS2_XOR 0x03 295226633Sdim#define INS2_SUB 0x04 296226633Sdim#define INS2_ANDN 0x05 297226633Sdim#define INS2_ORN 0x06 298226633Sdim#define INS2_XNOR 0x07 299234353Sdim#define INS2_ADDC 0x08 300234353Sdim#define INS2_MULX 0x09 301234353Sdim#define INS2_UMUL 0x0a 302234353Sdim#define INS2_SMUL 0x0b 303234353Sdim#define INS2_SUBC 0x0c 304234353Sdim#define INS2_UDIVX 0x0d 305234353Sdim#define INS2_UDIV 0x0e 306234353Sdim#define INS2_SDIV 0x0f 307234353Sdim#define INS2_ADDcc 0x10 308234353Sdim#define INS2_ANDcc 0x11 309234353Sdim#define INS2_ORcc 0x12 310234353Sdim#define INS2_XORcc 0x13 311234353Sdim#define INS2_SUBcc 0x14 312234353Sdim#define INS2_ANDNcc 0x15 313234353Sdim#define INS2_ORNcc 0x16 314234353Sdim#define INS2_XNORcc 0x17 315234353Sdim#define INS2_ADDCcc 0x18 316234353Sdim/* undefined 0x19 */ 317234353Sdim#define INS2_UMULcc 0x1a 318234353Sdim#define INS2_SMULcc 0x1b 319234353Sdim#define INS2_SUBCcc 0x1c 320234353Sdim/* undefined 0x1d */ 321234353Sdim#define INS2_UDIVcc 0x1e 322234353Sdim#define INS2_SDIVcc 0x1f 323234353Sdim#define INS2_TADDcc 0x20 324234353Sdim#define INS2_TSUBcc 0x21 325234353Sdim#define INS2_TADDccTV 0x22 326234353Sdim#define INS2_TSUBccTV 0x23 327234353Sdim#define INS2_MULScc 0x24 328234353Sdim#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 329234353Sdim#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 330234353Sdim#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 331234353Sdim#define INS2_RD 0x28 /* and MEMBAR, STBAR */ 332234353Sdim/* undefined 0x29 */ 333234353Sdim#define INS2_RDPR 0x2a 334234353Sdim#define INS2_FLUSHW 0x2b 335234353Sdim#define INS2_MOVcc 0x2c 336#define INS2_SDIVX 0x2d 337#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 338#define INS2_MOVr 0x2f 339#define INS2_WR 0x30 /* and SIR */ 340#define INS2_SV_RSTR 0x31 /* saved, restored */ 341#define INS2_WRPR 0x32 342/* undefined 0x33 */ 343#define INS2_FPop1 0x34 /* further encoded in opf field */ 344#define INS2_FPop2 0x35 /* further encoded in opf field */ 345#define INS2_IMPLDEP1 0x36 346#define INS2_IMPLDEP2 0x37 347#define INS2_JMPL 0x38 348#define INS2_RETURN 0x39 349#define INS2_Tcc 0x3a 350#define INS2_FLUSH 0x3b 351#define INS2_SAVE 0x3c 352#define INS2_RESTORE 0x3d 353#define INS2_DONE_RETR 0x3e /* done, retry */ 354/* undefined 0x3f */ 355 356/* OP3 values for format 3 (OP = 3) */ 357#define INS3_LDUW 0x00 358#define INS3_LDUB 0x01 359#define INS3_LDUH 0x02 360#define INS3_LDD 0x03 361#define INS3_STW 0x04 362#define INS3_STB 0x05 363#define INS3_STH 0x06 364#define INS3_STD 0x07 365#define INS3_LDSW 0x08 366#define INS3_LDSB 0x09 367#define INS3_LDSH 0x0a 368#define INS3_LDX 0x0b 369/* undefined 0x0c */ 370#define INS3_LDSTUB 0x0d 371#define INS3_STX 0x0e 372#define INS3_SWAP 0x0f 373#define INS3_LDUWA 0x10 374#define INS3_LDUBA 0x11 375#define INS3_LDUHA 0x12 376#define INS3_LDDA 0x13 377#define INS3_STWA 0x14 378#define INS3_STBA 0x15 379#define INS3_STHA 0x16 380#define INS3_STDA 0x17 381#define INS3_LDSWA 0x18 382#define INS3_LDSBA 0x19 383#define INS3_LDSHA 0x1a 384#define INS3_LDXA 0x1b 385/* undefined 0x1c */ 386#define INS3_LDSTUBA 0x1d 387#define INS3_STXA 0x1e 388#define INS3_SWAPA 0x1f 389#define INS3_LDF 0x20 390#define INS3_LDFSR 0x21 /* and LDXFSR */ 391#define INS3_LDQF 0x22 392#define INS3_LDDF 0x23 393#define INS3_STF 0x24 394#define INS3_STFSR 0x25 /* and STXFSR */ 395#define INS3_STQF 0x26 396#define INS3_STDF 0x27 397/* undefined 0x28 - 0x2c */ 398#define INS3_PREFETCH 0x2d 399/* undefined 0x2e - 0x2f */ 400#define INS3_LDFA 0x30 401/* undefined 0x31 */ 402#define INS3_LDQFA 0x32 403#define INS3_LDDFA 0x33 404#define INS3_STFA 0x34 405/* undefined 0x35 */ 406#define INS3_STQFA 0x36 407#define INS3_STDFA 0x37 408/* undefined 0x38 - 0x3b */ 409#define INS3_CASA 0x39 410#define INS3_PREFETCHA 0x3a 411#define INS3_CASXA 0x3b 412 413/* 414 * OPF values (floating point instructions, IMPLDEP) 415 */ 416/* 417 * These values are or'ed to the FPop values to get the instructions. 418 * They describe the operand type(s). 419 */ 420#define INSFP_i 0x000 /* 32-bit int */ 421#define INSFP_s 0x001 /* 32-bit single */ 422#define INSFP_d 0x002 /* 64-bit double */ 423#define INSFP_q 0x003 /* 128-bit quad */ 424/* FPop1. The comments give the types for which this instruction is defined. */ 425#define INSFP1_FMOV 0x000 /* s, d, q */ 426#define INSFP1_FNEG 0x004 /* s, d, q */ 427#define INSFP1_FABS 0x008 /* s, d, q */ 428#define INSFP1_FSQRT 0x028 /* s, d, q */ 429#define INSFP1_FADD 0x040 /* s, d, q */ 430#define INSFP1_FSUB 0x044 /* s, d, q */ 431#define INSFP1_FMUL 0x048 /* s, d, q */ 432#define INSFP1_FDIV 0x04c /* s, d, q */ 433#define INSFP1_FsMULd 0x068 /* s */ 434#define INSFP1_FdMULq 0x06c /* d */ 435#define INSFP1_FTOx 0x080 /* s, d, q */ 436#define INSFP1_FxTOs 0x084 /* special: i only */ 437#define INSFP1_FxTOd 0x088 /* special: i only */ 438#define INSFP1_FxTOq 0x08c /* special: i only */ 439#define INSFP1_FTOs 0x0c4 /* i, d, q */ 440#define INSFP1_FTOd 0x0c8 /* i, s, q */ 441#define INSFP1_FTOq 0x0cc /* i, s, d */ 442#define INSFP1_FTOi 0x0d0 /* i, s, d */ 443 444/* FPop2 */ 445#define INSFP2_FMOV_CCMUL 0x40 446#define INSFP2_FMOV_CCOFFS 0x00 447/* Use the IFCC_* constants for cc. Operand types: s, d, q */ 448#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 449#define INSFP2_FMOV_RCMUL 0x20 450#define INSFP2_FMOV_RCOFFS 0x04 451/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 452#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 453#define INSFP2_FCMP 0x050 /* s, d, q */ 454#define INSFP2_FCMPE 0x054 /* s, d, q */ 455 456/* IMPLDEP1 for Sun UltraSparc */ 457#define IIDP1_EDGE8 0x00 458#define IIDP1_EDGE8L 0x02 459#define IIDP1_EDGE16 0x04 460#define IIDP1_EDGE16L 0x06 461#define IIDP1_EDGE32 0x08 462#define IIDP1_EDGE32L 0x0a 463#define IIDP1_ARRAY8 0x10 464#define IIDP1_ARRAY16 0x12 465#define IIDP1_ARRAY32 0x14 466#define IIDP1_ALIGNADDRESS 0x18 467#define IIDP1_ALIGNADDRESS_L 0x1a 468#define IIDP1_FCMPLE16 0x20 469#define IIDP1_FCMPNE16 0x22 470#define IIDP1_FCMPLE32 0x24 471#define IIDP1_FCMPNE32 0x26 472#define IIDP1_FCMPGT16 0x28 473#define IIDP1_FCMPEQ16 0x2a 474#define IIDP1_FCMPGT32 0x2c 475#define IIDP1_FCMPEQ32 0x2e 476#define IIDP1_FMUL8x16 0x31 477#define IIDP1_FMUL8x16AU 0x33 478#define IIDP1_FMUL8X16AL 0x35 479#define IIDP1_FMUL8SUx16 0x36 480#define IIDP1_FMUL8ULx16 0x37 481#define IIDP1_FMULD8SUx16 0x38 482#define IIDP1_FMULD8ULx16 0x39 483#define IIDP1_FPACK32 0x3a 484#define IIDP1_FPACK16 0x3b 485#define IIDP1_FPACKFIX 0x3d 486#define IIDP1_PDIST 0x3e 487#define IIDP1_FALIGNDATA 0x48 488#define IIDP1_FPMERGE 0x4b 489#define IIDP1_FEXPAND 0x4d 490#define IIDP1_FPADD16 0x50 491#define IIDP1_FPADD16S 0x51 492#define IIDP1_FPADD32 0x52 493#define IIDP1_FPADD32S 0x53 494#define IIDP1_SUB16 0x54 495#define IIDP1_SUB16S 0x55 496#define IIDP1_SUB32 0x56 497#define IIDP1_SUB32S 0x57 498#define IIDP1_FZERO 0x60 499#define IIDP1_FZEROS 0x61 500#define IIDP1_FNOR 0x62 501#define IIDP1_FNORS 0x63 502#define IIDP1_FANDNOT2 0x64 503#define IIDP1_FANDNOT2S 0x65 504#define IIDP1_NOT2 0x66 505#define IIDP1_NOT2S 0x67 506#define IIDP1_FANDNOT1 0x68 507#define IIDP1_FANDNOT1S 0x69 508#define IIDP1_FNOT1 0x6a 509#define IIDP1_FNOT1S 0x6b 510#define IIDP1_FXOR 0x6c 511#define IIDP1_FXORS 0x6d 512#define IIDP1_FNAND 0x6e 513#define IIDP1_FNANDS 0x6f 514#define IIDP1_FAND 0x70 515#define IIDP1_FANDS 0x71 516#define IIDP1_FXNOR 0x72 517#define IIDP1_FXNORS 0x73 518#define IIDP1_FSRC1 0x74 519#define IIDP1_FSRC1S 0x75 520#define IIDP1_FORNOT2 0x76 521#define IIDP1_FORNOT2S 0x77 522#define IIDP1_FSRC2 0x78 523#define IIDP1_FSRC2S 0x79 524#define IIDP1_FORNOT1 0x7a 525#define IIDP1_FORNOT1S 0x7b 526#define IIDP1_FOR 0x7c 527#define IIDP1_FORS 0x7d 528#define IIDP1_FONE 0x7e 529#define IIDP1_FONES 0x7f 530#define IIDP1_SHUTDOWN 0x80 531 532/* 533 * Instruction modifiers 534 */ 535/* cond values for integer ccr's */ 536#define IICOND_N 0x00 537#define IICOND_E 0x01 538#define IICOND_LE 0x02 539#define IICOND_L 0x03 540#define IICOND_LEU 0x04 541#define IICOND_CS 0x05 542#define IICOND_NEG 0x06 543#define IICOND_VS 0x07 544#define IICOND_A 0x08 545#define IICOND_NE 0x09 546#define IICOND_G 0x0a 547#define IICOND_GE 0x0b 548#define IICOND_GU 0x0c 549#define IICOND_CC 0x0d 550#define IICOND_POS 0x0e 551#define IICOND_VC 0x0f 552 553/* cond values for fp ccr's */ 554#define IFCOND_N 0x00 555#define IFCOND_NE 0x01 556#define IFCOND_LG 0x02 557#define IFCOND_UL 0x03 558#define IFCOND_L 0x04 559#define IFCOND_UG 0x05 560#define IFCOND_G 0x06 561#define IFCOND_U 0x07 562#define IFCOND_A 0x08 563#define IFCOND_E 0x09 564#define IFCOND_UE 0x0a 565#define IFCOND_GE 0x0b 566#define IFCOND_UGE 0x0c 567#define IFCOND_LE 0x0d 568#define IFCOND_ULE 0x0e 569#define IFCOND_O 0x0f 570 571/* rcond values for BPr, MOVr, FMOVr */ 572#define IRCOND_Z 0x01 573#define IRCOND_LEZ 0x02 574#define IRCOND_LZ 0x03 575#define IRCOND_NZ 0x05 576#define IRCOND_GZ 0x06 577#define IRCOND_GEZ 0x07 578 579/* cc values for MOVcc and FMOVcc */ 580#define IFCC_ICC 0x04 581#define IFCC_XCC 0x06 582/* if true, the lower 2 bits are the fcc number */ 583#define IFCC_FCC(c) ((c) & 3) 584#define IFCC_GET_FCC(c) ((c) & 3) 585#define IFCC_ISFCC(c) (((c) & 4) == 0) 586 587/* cc values for BPc and Tcc */ 588#define IBCC_ICC 0x00 589#define IBCC_XCC 0x02 590 591/* 592 * Integer registers 593 */ 594#define IREG_G0 0x00 595#define IREG_O0 0x08 596#define IREG_L0 0x10 597#define IREQ_I0 0x18 598 599#endif /* !_MACHINE_INSTR_H_ */ 600