instr.h revision 86146
186146Stmm/* 286146Stmm * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 386146Stmm * Copyright (c) 1995 Paul Kranenburg 486146Stmm * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 586146Stmm * All rights reserved. 686146Stmm * 786146Stmm * Redistribution and use in source and binary forms, with or without 886146Stmm * modification, are permitted provided that the following conditions 986146Stmm * are met: 1086146Stmm * 1. Redistributions of source code must retain the above copyright 1186146Stmm * notice, this list of conditions and the following disclaimer. 1286146Stmm * 2. Redistributions in binary form must reproduce the above copyright 1386146Stmm * notice, this list of conditions and the following disclaimer in the 1486146Stmm * documentation and/or other materials provided with the distribution. 1586146Stmm * 3. All advertising materials mentioning features or use of this software 1686146Stmm * must display the following acknowledgement: 1786146Stmm * This product includes software developed by David Miller. 1886146Stmm * 4. The name of the author may not be used to endorse or promote products 1986146Stmm * derived from this software without specific prior written permission 2086146Stmm * 2186146Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2286146Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2386146Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2486146Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2586146Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2686146Stmm * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2786146Stmm * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2886146Stmm * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2986146Stmm * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3086146Stmm * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3186146Stmm * 3286146Stmm * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 3386146Stmm * 3486146Stmm * $FreeBSD: head/sys/sparc64/include/instr.h 86146 2001-11-06 20:13:44Z tmm $ 3586146Stmm */ 3686146Stmm 3786146Stmm#ifndef _MACHINE_INSTR_H_ 3886146Stmm#define _MACHINE_INSTR_H_ 3986146Stmm 4086146Stmm/* 4186146Stmm * Definitions for all instruction formats 4286146Stmm */ 4386146Stmm#define IF_OP_SHIFT 30 4486146Stmm#define IF_OP_BITS 2 4586146Stmm#define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 4686146Stmm 4786146Stmm/* 4886146Stmm * Definitions for format 2 4986146Stmm */ 5086146Stmm#define IF_F2_RD_SHIFT 25 5186146Stmm#define IF_F2_RD_BITS 5 5286146Stmm#define IF_F2_A_SHIFT 29 5386146Stmm#define IF_F2_A_BITS 1 5486146Stmm#define IF_F2_COND_SHIFT 25 5586146Stmm#define IF_F2_COND_BITS 4 5686146Stmm#define IF_F2_RCOND_SHIFT 25 5786146Stmm#define IF_F2_RCOND_BITS 3 5886146Stmm#define IF_F2_OP2_SHIFT 22 5986146Stmm#define IF_F2_OP2_BITS 3 6086146Stmm#define IF_F2_CC1_SHIFT 21 6186146Stmm#define IF_F2_CC1_BITS 1 6286146Stmm#define IF_F2_CC0_SHIFT 20 6386146Stmm#define IF_F2_CC0_BITS 1 6486146Stmm#define IF_F2_D16HI_SHIFT 20 6586146Stmm#define IF_F2_D16HI_BITS 2 6686146Stmm#define IF_F2_P_SHIFT 19 6786146Stmm#define IF_F2_P_BITS 1 6886146Stmm#define IF_F2_RS1_SHIFT 14 6986146Stmm#define IF_F2_RS1_BITS 5 7086146Stmm 7186146Stmm/* 7286146Stmm * Definitions for format 3 7386146Stmm */ 7486146Stmm#define IF_F3_OP3_SHIFT 19 7586146Stmm#define IF_F3_OP3_BITS 6 7686146Stmm#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 7786146Stmm#define IF_F3_RD_BITS IF_F2_RD_BITS 7886146Stmm#define IF_F3_FCN_SHIFT 25 7986146Stmm#define IF_F3_FCN_BITS 5 8086146Stmm#define IF_F3_CC1_SHIFT 26 8186146Stmm#define IF_F3_CC1_BITS 1 8286146Stmm#define IF_F3_CC0_SHIFT 25 8386146Stmm#define IF_F3_CC0_BITS 1 8486146Stmm#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 8586146Stmm#define IF_F3_RS1_BITS IF_F2_RS1_BITS 8686146Stmm#define IF_F3_I_SHIFT 13 8786146Stmm#define IF_F3_I_BITS 1 8886146Stmm#define IF_F3_X_SHIFT 12 8986146Stmm#define IF_F3_X_BITS 1 9086146Stmm#define IF_F3_RCOND_SHIFT 10 9186146Stmm#define IF_F3_RCOND_BITS 3 9286146Stmm#define IF_F3_IMM_ASI_SHIFT 5 9386146Stmm#define IF_F3_IMM_ASI_BITS 8 9486146Stmm#define IF_F3_OPF_SHIFT 5 9586146Stmm#define IF_F3_OPF_BITS 9 9686146Stmm#define IF_F3_CMASK_SHIFT 4 9786146Stmm#define IF_F3_CMASK_BITS 3 9886146Stmm#define IF_F3_RS2_SHIFT 0 9986146Stmm#define IF_F3_RS2_BITS 5 10086146Stmm#define IF_F3_SHCNT32_SHIFT 0 10186146Stmm#define IF_F3_SHCNT32_BITS 5 10286146Stmm#define IF_F3_SHCNT64_SHIFT 0 10386146Stmm#define IF_F3_SHCNT64_BITS 6 10486146Stmm 10586146Stmm/* 10686146Stmm * Definitions for format 4 10786146Stmm */ 10886146Stmm#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 10986146Stmm#define IF_F4_OP3_BITS IF_F3_OP3_BITS 11086146Stmm#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 11186146Stmm#define IF_F4_RD_BITS IF_F2_RD_BITS 11286146Stmm#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 11386146Stmm#define IF_F4_RS1_BITS IF_F2_RS1_BITS 11486146Stmm#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 11586146Stmm#define IF_F4_TCOND_BITS IF_F2_COND_BITS 11686146Stmm#define IF_F4_CC2_SHIFT 18 11786146Stmm#define IF_F4_CC2_BITS 1 11886146Stmm#define IF_F4_COND_SHIFT 14 11986146Stmm#define IF_F4_COND_BITS 4 12086146Stmm#define IF_F4_I_SHIFT IF_F3_I_SHIFT 12186146Stmm#define IF_F4_I_BITS IF_F3_I_BITS 12286146Stmm#define IF_F4_OPF_CC_SHIFT 11 12386146Stmm#define IF_F4_OPF_CC_BITS 3 12486146Stmm#define IF_F4_CC1_SHIFT 12 12586146Stmm#define IF_F4_CC1_BITS 1 12686146Stmm#define IF_F4_CC0_SHIFT 11 12786146Stmm#define IF_F4_CC0_BITS 1 12886146Stmm#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 12986146Stmm#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 13086146Stmm#define IF_F4_OPF_LOW_SHIFT 5 13186146Stmm#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 13286146Stmm#define IF_F4_RS2_BITS IF_F3_RS2_BITS 13386146Stmm#define IF_F4_SW_TRAP_SHIFT 0 13486146Stmm#define IF_F4_SW_TRAP_BITS 7 13586146Stmm 13686146Stmm/* 13786146Stmm * Macros to decode instructions 13886146Stmm */ 13986146Stmm/* Extract a field */ 14086146Stmm#define IF_EXTRACT(x, s, w) (((x) >> (s)) & ((1 << (w)) - 1)) 14186146Stmm#define IF_DECODE(x, f) \ 14286146Stmm IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 14386146Stmm 14486146Stmm/* Sign-extend a field of width W */ 14586146Stmm#define IF_SEXT(x, w) \ 14686146Stmm (((x) & (1 << ((w) - 1))) != 0 ? (-1L - ((x) ^ ((1 << (w)) - 1))) : (x)) 14786146Stmm 14886146Stmm#if 0 14986146Stmm/* 15086146Stmm * The following C variant is from db_disassemble.c, and surely faster, but it 15186146Stmm * relies on behaviour that is undefined by the C standard (>> in conjunction 15286146Stmm * with signed negative arguments). 15386146Stmm */ 15486146Stmm#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 15586146Stmm/* Assembler version of the above */ 15686146Stmm#define IF_SEXT(v, w) \ 15786146Stmm { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 15886146Stmm "=r" (t) : "r" (v) : "i" (64 - w)); t)} 15986146Stmm#endif 16086146Stmm 16186146Stmm/* All instruction formats */ 16286146Stmm#define IF_OP(i) IF_DECODE(i, OP) 16386146Stmm 16486146Stmm/* Instruction format 2 */ 16586146Stmm#define IF_F2_RD(i) IF_DECODE((i), F2_RD) 16686146Stmm#define IF_F2_A(i) IF_DECODE((i), F2_A) 16786146Stmm#define IF_F2_COND(i) IF_DECODE((i), F2_COND) 16886146Stmm#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 16986146Stmm#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 17086146Stmm#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 17186146Stmm#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 17286146Stmm#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 17386146Stmm#define IF_F2_P(i) IF_DECODE((i), F2_P) 17486146Stmm#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 17586146Stmm 17686146Stmm/* Instruction format 3 */ 17786146Stmm#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 17886146Stmm#define IF_F3_RD(i) IF_F2_RD((i)) 17986146Stmm#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 18086146Stmm#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 18186146Stmm#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 18286146Stmm#define IF_F3_RS1(i) IF_F2_RS1((i)) 18386146Stmm#define IF_F3_I(i) IF_DECODE((i), F3_I) 18486146Stmm#define IF_F3_X(i) IF_DECODE((i), F3_X) 18586146Stmm#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 18686146Stmm#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 18786146Stmm#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 18886146Stmm#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 18986146Stmm#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 19086146Stmm#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 19186146Stmm#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 19286146Stmm 19386146Stmm/* Instruction format 4 */ 19486146Stmm#define IF_F4_OP3(i) IF_F3_OP3((i)) 19586146Stmm#define IF_F4_RD(i) IF_F3_RD((i)) 19686146Stmm#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 19786146Stmm#define IF_F4_RS1(i) IF_F3_RS1((i)) 19886146Stmm#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 19986146Stmm#define IF_F4_COND(i) IF_DECODE((i), F4_COND) 20086146Stmm#define IF_F4_I(i) IF_F3_I((i)) 20186146Stmm#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 20286146Stmm#define IF_F4_RCOND(i) IF_F3_RCOND((i)) 20386146Stmm#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 20486146Stmm#define IF_F4_RS2(i) IF_F3_RS2((i)) 20586146Stmm#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 20686146Stmm 20786146Stmm/* Extract an immediate from an instruction, with an without sign extension */ 20886146Stmm#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 20986146Stmm#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 21086146Stmm 21186146Stmm/* 21286146Stmm * Macros to encode instructions 21386146Stmm */ 21486146Stmm#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 21586146Stmm#define IF_ENCODE(x, f) \ 21686146Stmm IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 21786146Stmm 21886146Stmm/* All instruction formats */ 21986146Stmm#define EIF_OP(x) IF_ENCODE((x), OP) 22086146Stmm 22186146Stmm/* Instruction format 2 */ 22286146Stmm#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 22386146Stmm#define EIF_F2_A(x) IF_ENCODE((x), F2_A) 22486146Stmm#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 22586146Stmm#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 22686146Stmm#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 22786146Stmm#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 22886146Stmm#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 22986146Stmm#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 23086146Stmm#define EIF_F2_P(x) IF_ENCODE((x), F2_P) 23186146Stmm#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 23286146Stmm 23386146Stmm/* Instruction format 3 */ 23486146Stmm#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 23586146Stmm#define EIF_F3_RD(x) EIF_F2_RD((x)) 23686146Stmm#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 23786146Stmm#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 23886146Stmm#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 23986146Stmm#define EIF_F3_RS1(x) EIF_F2_RS1((x)) 24086146Stmm#define EIF_F3_I(x) IF_ENCODE((x), F3_I) 24186146Stmm#define EIF_F3_X(x) IF_ENCODE((x), F3_X) 24286146Stmm#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 24386146Stmm#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 24486146Stmm#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 24586146Stmm#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 24686146Stmm#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 24786146Stmm#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 24886146Stmm#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 24986146Stmm 25086146Stmm/* Instruction format 4 */ 25186146Stmm#define EIF_F4_OP3(x) EIF_F3_OP3((x)) 25286146Stmm#define EIF_F4_RD(x) EIF_F2_RD((x)) 25386146Stmm#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 25486146Stmm#define EIF_F4_RS1(x) EIF_F2_RS1((x)) 25586146Stmm#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 25686146Stmm#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 25786146Stmm#define EIF_F4_I(x) EIF_F3_I((x)) 25886146Stmm#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 25986146Stmm#define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 26086146Stmm#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 26186146Stmm#define EIF_F4_RS2(x) EIF_F3_RS2((x)) 26286146Stmm#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 26386146Stmm 26486146Stmm/* Immediates */ 26586146Stmm#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 26686146Stmm#define EIF_SIMM(x, w) IF_EIMM((x), (w)) 26786146Stmm 26886146Stmm/* 26986146Stmm * OP field values (specifying the instruction format) 27086146Stmm */ 27186146Stmm#define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 27286146Stmm#define IOP_CALL 0x01 /* Format 1: call */ 27386146Stmm#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 27486146Stmm#define IOP_LDST 0x03 /* Format 4: loads and stores */ 27586146Stmm 27686146Stmm/* 27786146Stmm * OP2/OP3 values (specifying the actual instruction) 27886146Stmm */ 27986146Stmm/* OP2 values for format 2 (OP = 0) */ 28086146Stmm#define INS0_ILLTRAP 0x00 28186146Stmm#define INS0_BPcc 0x01 28286146Stmm#define INS0_Bicc 0x02 28386146Stmm#define INS0_BPr 0x03 28486146Stmm#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 28586146Stmm#define INS0_FBPfcc 0x05 28686146Stmm#define INS0_FBfcc 0x06 28786146Stmm/* undefined 0x07 */ 28886146Stmm 28986146Stmm/* OP3 values for Format 3 and 4 (OP = 2) */ 29086146Stmm#define INS2_ADD 0x00 29186146Stmm#define INS2_AND 0x01 29286146Stmm#define INS2_OR 0x02 29386146Stmm#define INS2_XOR 0x03 29486146Stmm#define INS2_SUB 0x04 29586146Stmm#define INS2_ANDN 0x05 29686146Stmm#define INS2_ORN 0x06 29786146Stmm#define INS2_XNOR 0x07 29886146Stmm#define INS2_ADDC 0x08 29986146Stmm#define INS2_MULX 0x09 30086146Stmm#define INS2_UMUL 0x0a 30186146Stmm#define INS2_SMUL 0x0b 30286146Stmm#define INS2_SUBC 0x0c 30386146Stmm#define INS2_UDIVX 0x0d 30486146Stmm#define INS2_UDIV 0x0e 30586146Stmm#define INS2_SDIV 0x0f 30686146Stmm#define INS2_ADDcc 0x10 30786146Stmm#define INS2_ANDcc 0x11 30886146Stmm#define INS2_ORcc 0x12 30986146Stmm#define INS2_XORcc 0x13 31086146Stmm#define INS2_SUBcc 0x14 31186146Stmm#define INS2_ANDNcc 0x15 31286146Stmm#define INS2_ORNcc 0x16 31386146Stmm#define INS2_XNORcc 0x17 31486146Stmm#define INS2_ADDCcc 0x18 31586146Stmm/* undefined 0x19 */ 31686146Stmm#define INS2_UMULcc 0x1a 31786146Stmm#define INS2_SMULcc 0x1b 31886146Stmm#define INS2_SUBCcc 0x1c 31986146Stmm/* undefined 0x1d */ 32086146Stmm#define INS2_UDIVcc 0x1e 32186146Stmm#define INS2_SDIVcc 0x1f 32286146Stmm#define INS2_TADDcc 0x20 32386146Stmm#define INS2_TSUBcc 0x21 32486146Stmm#define INS2_TADDccTV 0x22 32586146Stmm#define INS2_TSUBccTV 0x23 32686146Stmm#define INS2_MULScc 0x24 32786146Stmm#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 32886146Stmm#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 32986146Stmm#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 33086146Stmm#define INS2_RD 0x28 /* and MEMBAR, STBAR */ 33186146Stmm/* undefined 0x29 */ 33286146Stmm#define INS2_RDPR 0x2a 33386146Stmm#define INS2_FLUSHW 0x2b 33486146Stmm#define INS2_MOVcc 0x2c 33586146Stmm#define INS2_SDIVX 0x2d 33686146Stmm#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 33786146Stmm#define INS2_MOVr 0x2f 33886146Stmm#define INS2_WR 0x30 /* and SIR */ 33986146Stmm#define INS2_SV_RSTR 0x31 /* saved, restored */ 34086146Stmm#define INS2_WRPR 0x32 34186146Stmm/* undefined 0x33 */ 34286146Stmm#define INS2_FPop1 0x34 /* further encoded in opf field */ 34386146Stmm#define INS2_FPop2 0x35 /* further encoded in opf field */ 34486146Stmm#define INS2_IMPLDEP1 0x36 34586146Stmm#define INS2_IMPLDEP2 0x37 34686146Stmm#define INS2_JMPL 0x38 34786146Stmm#define INS2_RETURN 0x39 34886146Stmm#define INS2_Tcc 0x3a 34986146Stmm#define INS2_FLUSH 0x3b 35086146Stmm#define INS2_SAVE 0x3c 35186146Stmm#define INS2_RESTORE 0x3d 35286146Stmm#define INS2_DONE_RETR 0x3e /* done, retry */ 35386146Stmm/* undefined 0x3f */ 35486146Stmm 35586146Stmm/* OP3 values for format 3 (OP = 3) */ 35686146Stmm#define INS3_LDUW 0x00 35786146Stmm#define INS3_LDUB 0x01 35886146Stmm#define INS3_LDUH 0x02 35986146Stmm#define INS3_LDD 0x03 36086146Stmm#define INS3_STW 0x04 36186146Stmm#define INS3_STB 0x05 36286146Stmm#define INS3_STH 0x06 36386146Stmm#define INS3_STD 0x07 36486146Stmm#define INS3_LDSW 0x08 36586146Stmm#define INS3_LDSB 0x09 36686146Stmm#define INS3_LDSH 0x0a 36786146Stmm#define INS3_LDX 0x0b 36886146Stmm/* undefined 0x0c */ 36986146Stmm#define INS3_LDSTUB 0x0d 37086146Stmm#define INS3_STX 0x0e 37186146Stmm#define INS3_SWAP 0x0f 37286146Stmm#define INS3_LDUWA 0x10 37386146Stmm#define INS3_LDUBA 0x11 37486146Stmm#define INS3_LDUHA 0x12 37586146Stmm#define INS3_LDDA 0x13 37686146Stmm#define INS3_STWA 0x14 37786146Stmm#define INS3_STBA 0x15 37886146Stmm#define INS3_STHA 0x16 37986146Stmm#define INS3_STDA 0x17 38086146Stmm#define INS3_LDSWA 0x18 38186146Stmm#define INS3_LDSBA 0x19 38286146Stmm#define INS3_LDSHA 0x1a 38386146Stmm#define INS3_LDXA 0x1b 38486146Stmm/* undefined 0x1c */ 38586146Stmm#define INS3_LDSTUBA 0x1d 38686146Stmm#define INS3_STXA 0x1e 38786146Stmm#define INS3_SWAPA 0x1f 38886146Stmm#define INS3_LDF 0x20 38986146Stmm#define INS3_LDFSR 0x21 /* and LDXFSR */ 39086146Stmm#define INS3_LDQF 0x22 39186146Stmm#define INS3_LDDF 0x23 39286146Stmm#define INS3_STF 0x24 39386146Stmm#define INS3_STFSR 0x25 /* and STXFSR */ 39486146Stmm#define INS3_STQF 0x26 39586146Stmm#define INS3_STDF 0x27 39686146Stmm/* undefined 0x28 - 0x2c */ 39786146Stmm#define INS3_PREFETCH 0x2d 39886146Stmm/* undefined 0x2e - 0x2f */ 39986146Stmm#define INS3_LDFA 0x30 40086146Stmm/* undefined 0x31 */ 40186146Stmm#define INS3_LDQFA 0x32 40286146Stmm#define INS3_LDDFA 0x33 40386146Stmm#define INS3_STFA 0x34 40486146Stmm/* undefined 0x35 */ 40586146Stmm#define INS3_STQFA 0x36 40686146Stmm#define INS3_STDFA 0x37 40786146Stmm/* undefined 0x38 - 0x3b */ 40886146Stmm#define INS3_CASA 0x39 40986146Stmm#define INS3_PREFETCHA 0x3a 41086146Stmm#define INS3_CASXA 0x3b 41186146Stmm 41286146Stmm/* 41386146Stmm * OPF values (floating point instructions, IMPLDEP) 41486146Stmm */ 41586146Stmm/* FPop1 */ 41686146Stmm#define INSFP1_FMOVs 0x001 41786146Stmm#define INSFP1_FMOVd 0x002 41886146Stmm#define INSFP1_FMOVq 0x003 41986146Stmm#define INSFP1_FNEGs 0x005 42086146Stmm#define INSFP1_FNEGd 0x006 42186146Stmm#define INSFP1_FNEGq 0x007 42286146Stmm#define INSFP1_FABSs 0x009 42386146Stmm#define INSFP1_FABSd 0x00a 42486146Stmm#define INSFP1_FABSq 0x00b 42586146Stmm#define INSFP1_FSQRTs 0x029 42686146Stmm#define INSFP1_FSQRTd 0x02a 42786146Stmm#define INSFP1_FSQRTq 0x02b 42886146Stmm#define INSFP1_FADDs 0x041 42986146Stmm#define INSFP1_FADDd 0x042 43086146Stmm#define INSFP1_FADDq 0x043 43186146Stmm#define INSFP1_FSUBs 0x045 43286146Stmm#define INSFP1_FSUBd 0x046 43386146Stmm#define INSFP1_FSUBq 0x047 43486146Stmm#define INSFP1_FMULs 0x049 43586146Stmm#define INSFP1_FMULd 0x04a 43686146Stmm#define INSFP1_FMULq 0x04b 43786146Stmm#define INSFP1_FDIVs 0x04d 43886146Stmm#define INSFP1_FDIVd 0x04e 43986146Stmm#define INSFP1_FDIVq 0x04f 44086146Stmm#define INSFP1_FsMULd 0x069 44186146Stmm#define INSFP1_FdMULq 0x06e 44286146Stmm#define INSFP1_FsTOx 0x081 44386146Stmm#define INSFP1_FdTOx 0x082 44486146Stmm#define INSFP1_FqTOx 0x083 44586146Stmm#define INSFP1_FxTOs 0x084 44686146Stmm#define INSFP1_FxTOd 0x088 44786146Stmm#define INSFP1_FxTOq 0x08c 44886146Stmm#define INSFP1_FiTOs 0x0c4 44986146Stmm#define INSFP1_FdTOs 0x0c6 45086146Stmm#define INSFP1_FqTOs 0x0c7 45186146Stmm#define INSFP1_FiTOd 0x0c8 45286146Stmm#define INSFP1_FsTOd 0x0c9 45386146Stmm#define INSFP1_FqTOd 0x0cb 45486146Stmm#define INSFP1_FiTOq 0x0cc 45586146Stmm#define INSFP1_FsTOq 0x0cd 45686146Stmm#define INSFP1_FdTOq 0x0ce 45786146Stmm 45886146Stmm/* FPop2 */ 45986146Stmm#define INSFP2_FMOV_CCMUL 0x40 46086146Stmm/* use the IFCC_* constants for cc */ 46186146Stmm#define INSFP2_FMOV_CC(i, cc) (i + (cc) * INSFP2_FMOV_CCMUL) 46286146Stmm#define INSFP2_FMOVs(cc) INSFP2_FMOV_CC(0x01, (cc)) 46386146Stmm#define INSFP2_FMOVd(cc) INSFP2_FMOV_CC(0x02, (cc)) 46486146Stmm#define INSFP2_FMOVq(cc) INSFP2_FMOV_CC(0x03, (cc)) 46586146Stmm 46686146Stmm/* use the IRCOND_* constants for rc */ 46786146Stmm#define INSFP2_FMOV_RCMUL 0x20 46886146Stmm#define INSFP2_FMOV_RC(i, rc) (i + (rc) * INSFP2_FMOV_RCMUL) 46986146Stmm#define INSFP2_FMOVRsZ(rc) INSFP2_FMOV_RC(0x05, (rc)) 47086146Stmm#define INSFP2_FMOVRdZ(rc) INSFP2_FMOV_RC(0x06, (rc)) 47186146Stmm#define INSFP2_FMOVRqZ(rc) INSFP2_FMOV_RC(0x07, (rc)) 47286146Stmm#define INSFP2_FCMPs 0x051 47386146Stmm#define INSFP2_FCMPd 0x052 47486146Stmm#define INSFP2_FCMPq 0x053 47586146Stmm#define INSFP2_FCMPEs 0x055 47686146Stmm#define INSFP2_FCMPEd 0x056 47786146Stmm#define INSFP2_FCMPEq 0x057 47886146Stmm 47986146Stmm/* IMPLDEP1 for Sun UltraSparc */ 48086146Stmm#define IIDP1_EDGE8 0x00 48186146Stmm#define IIDP1_EDGE8L 0x02 48286146Stmm#define IIDP1_EDGE16 0x04 48386146Stmm#define IIDP1_EDGE16L 0x06 48486146Stmm#define IIDP1_EDGE32 0x08 48586146Stmm#define IIDP1_EDGE32L 0x0a 48686146Stmm#define IIDP1_ARRAY8 0x10 48786146Stmm#define IIDP1_ARRAY16 0x12 48886146Stmm#define IIDP1_ARRAY32 0x14 48986146Stmm#define IIDP1_ALIGNADDRESS 0x18 49086146Stmm#define IIDP1_ALIGNADDRESS_L 0x1a 49186146Stmm#define IIDP1_FCMPLE16 0x20 49286146Stmm#define IIDP1_FCMPNE16 0x22 49386146Stmm#define IIDP1_FCMPLE32 0x24 49486146Stmm#define IIDP1_FCMPNE32 0x26 49586146Stmm#define IIDP1_FCMPGT16 0x28 49686146Stmm#define IIDP1_FCMPEQ16 0x2a 49786146Stmm#define IIDP1_FCMPGT32 0x2c 49886146Stmm#define IIDP1_FCMPEQ32 0x2e 49986146Stmm#define IIDP1_FMUL8x16 0x31 50086146Stmm#define IIDP1_FMUL8x16AU 0x33 50186146Stmm#define IIDP1_FMUL8X16AL 0x35 50286146Stmm#define IIDP1_FMUL8SUx16 0x36 50386146Stmm#define IIDP1_FMUL8ULx16 0x37 50486146Stmm#define IIDP1_FMULD8SUx16 0x38 50586146Stmm#define IIDP1_FMULD8ULx16 0x39 50686146Stmm#define IIDP1_FPACK32 0x3a 50786146Stmm#define IIDP1_FPACK16 0x3b 50886146Stmm#define IIDP1_FPACKFIX 0x3d 50986146Stmm#define IIDP1_PDIST 0x3e 51086146Stmm#define IIDP1_FALIGNDATA 0x48 51186146Stmm#define IIDP1_FPMERGE 0x4b 51286146Stmm#define IIDP1_FEXPAND 0x4d 51386146Stmm#define IIDP1_FPADD16 0x50 51486146Stmm#define IIDP1_FPADD16S 0x51 51586146Stmm#define IIDP1_FPADD32 0x52 51686146Stmm#define IIDP1_FPADD32S 0x53 51786146Stmm#define IIDP1_SUB16 0x54 51886146Stmm#define IIDP1_SUB16S 0x55 51986146Stmm#define IIDP1_SUB32 0x56 52086146Stmm#define IIDP1_SUB32S 0x57 52186146Stmm#define IIDP1_FZERO 0x60 52286146Stmm#define IIDP1_FZEROS 0x61 52386146Stmm#define IIDP1_FNOR 0x62 52486146Stmm#define IIDP1_FNORS 0x63 52586146Stmm#define IIDP1_FANDNOT2 0x64 52686146Stmm#define IIDP1_FANDNOT2S 0x65 52786146Stmm#define IIDP1_NOT2 0x66 52886146Stmm#define IIDP1_NOT2S 0x67 52986146Stmm#define IIDP1_FANDNOT1 0x68 53086146Stmm#define IIDP1_FANDNOT1S 0x69 53186146Stmm#define IIDP1_FNOT1 0x6a 53286146Stmm#define IIDP1_FNOT1S 0x6b 53386146Stmm#define IIDP1_FXOR 0x6c 53486146Stmm#define IIDP1_FXORS 0x6d 53586146Stmm#define IIDP1_FNAND 0x6e 53686146Stmm#define IIDP1_FNANDS 0x6f 53786146Stmm#define IIDP1_FAND 0x70 53886146Stmm#define IIDP1_FANDS 0x71 53986146Stmm#define IIDP1_FXNOR 0x72 54086146Stmm#define IIDP1_FXNORS 0x73 54186146Stmm#define IIDP1_FSRC1 0x74 54286146Stmm#define IIDP1_FSRC1S 0x75 54386146Stmm#define IIDP1_FORNOT2 0x76 54486146Stmm#define IIDP1_FORNOT2S 0x77 54586146Stmm#define IIDP1_FSRC2 0x78 54686146Stmm#define IIDP1_FSRC2S 0x79 54786146Stmm#define IIDP1_FORNOT1 0x7a 54886146Stmm#define IIDP1_FORNOT1S 0x7b 54986146Stmm#define IIDP1_FOR 0x7c 55086146Stmm#define IIDP1_FORS 0x7d 55186146Stmm#define IIDP1_FONE 0x7e 55286146Stmm#define IIDP1_FONES 0x7f 55386146Stmm#define IIDP1_SHUTDOWN 0x80 55486146Stmm 55586146Stmm/* 55686146Stmm * Instruction modifiers 55786146Stmm */ 55886146Stmm/* cond values for integer ccr's */ 55986146Stmm#define IICOND_N 0x00 56086146Stmm#define IICOND_E 0x01 56186146Stmm#define IICOND_LE 0x02 56286146Stmm#define IICOND_L 0x03 56386146Stmm#define IICOND_LEU 0x04 56486146Stmm#define IICOND_CS 0x05 56586146Stmm#define IICOND_NEG 0x06 56686146Stmm#define IICOND_VS 0x07 56786146Stmm#define IICOND_A 0x08 56886146Stmm#define IICOND_NE 0x09 56986146Stmm#define IICOND_G 0x0a 57086146Stmm#define IICOND_GE 0x0b 57186146Stmm#define IICOND_GU 0x0c 57286146Stmm#define IICOND_CC 0x0d 57386146Stmm#define IICOND_POS 0x0e 57486146Stmm#define IICOND_VC 0x0f 57586146Stmm 57686146Stmm/* cond values for fp ccr's */ 57786146Stmm#define IFCOND_N 0x00 57886146Stmm#define IFCOND_NE 0x01 57986146Stmm#define IFCOND_LG 0x02 58086146Stmm#define IFCOND_UL 0x03 58186146Stmm#define IFCOND_L 0x04 58286146Stmm#define IFCOND_UG 0x05 58386146Stmm#define IFCOND_G 0x06 58486146Stmm#define IFCOND_U 0x07 58586146Stmm#define IFCOND_A 0x08 58686146Stmm#define IFCOND_E 0x09 58786146Stmm#define IFCOND_UE 0x0a 58886146Stmm#define IFCOND_GE 0x0b 58986146Stmm#define IFCOND_UGE 0x0c 59086146Stmm#define IFCOND_LE 0x0d 59186146Stmm#define IFCOND_ULE 0x0e 59286146Stmm#define IFCOND_O 0x0f 59386146Stmm 59486146Stmm/* rcond values for BPr, MOVr, FMOVr */ 59586146Stmm#define IRCOND_RZ 0x01 59686146Stmm#define IRCOND_LEZ 0x02 59786146Stmm#define IRCOND_LZ 0x03 59886146Stmm#define IRCOND_NZ 0x05 59986146Stmm#define IRCOND_GZ 0x06 60086146Stmm#define IRCOND_GEZ 0x07 60186146Stmm 60286146Stmm/* cc values for MOVcc and FMOVcc */ 60386146Stmm#define IFCC_ICC 0x04 60486146Stmm#define IFCC_XCC 0x06 60586146Stmm/* if true, the lower 2 bits are the fcc number */ 60686146Stmm#define IFCC_FCC(c) (((c) & 4) == 0) 60786146Stmm 60886146Stmm/* cc values for BPc and Tcc */ 60986146Stmm#define IBCC_ICC 0x00 61086146Stmm#define IBCC_XCC 0x02 61186146Stmm 61286146Stmm/* 61386146Stmm * Integer registers 61486146Stmm */ 61586146Stmm#define IREG_G0 0x00 61686146Stmm#define IREG_O0 0x08 61786146Stmm#define IREG_L0 0x10 61886146Stmm#define IREQ_I0 0x18 61986146Stmm 62086146Stmm#endif /* !_MACHINE_INSTR_H_ */ 621