1139825Simp/*- 286146Stmm * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 386146Stmm * Copyright (c) 1995 Paul Kranenburg 486146Stmm * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 586146Stmm * All rights reserved. 686146Stmm * 786146Stmm * Redistribution and use in source and binary forms, with or without 886146Stmm * modification, are permitted provided that the following conditions 986146Stmm * are met: 1086146Stmm * 1. Redistributions of source code must retain the above copyright 1186146Stmm * notice, this list of conditions and the following disclaimer. 1286146Stmm * 2. Redistributions in binary form must reproduce the above copyright 1386146Stmm * notice, this list of conditions and the following disclaimer in the 1486146Stmm * documentation and/or other materials provided with the distribution. 1586146Stmm * 3. All advertising materials mentioning features or use of this software 1686146Stmm * must display the following acknowledgement: 1786146Stmm * This product includes software developed by David Miller. 1886146Stmm * 4. The name of the author may not be used to endorse or promote products 1986146Stmm * derived from this software without specific prior written permission 2086146Stmm * 2186146Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2286146Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2386146Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2486146Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2586146Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2686146Stmm * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2786146Stmm * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2886146Stmm * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2986146Stmm * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3086146Stmm * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3186146Stmm * 3286146Stmm * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 3386146Stmm * 3486146Stmm * $FreeBSD$ 3586146Stmm */ 3686146Stmm 3786146Stmm#ifndef _MACHINE_INSTR_H_ 3886146Stmm#define _MACHINE_INSTR_H_ 3986146Stmm 4086146Stmm/* 4186146Stmm * Definitions for all instruction formats 4286146Stmm */ 4386146Stmm#define IF_OP_SHIFT 30 4486146Stmm#define IF_OP_BITS 2 4586146Stmm#define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 4686146Stmm 4786146Stmm/* 4886146Stmm * Definitions for format 2 4986146Stmm */ 5086146Stmm#define IF_F2_RD_SHIFT 25 5186146Stmm#define IF_F2_RD_BITS 5 5286146Stmm#define IF_F2_A_SHIFT 29 5386146Stmm#define IF_F2_A_BITS 1 5486146Stmm#define IF_F2_COND_SHIFT 25 5586146Stmm#define IF_F2_COND_BITS 4 5686146Stmm#define IF_F2_RCOND_SHIFT 25 5786146Stmm#define IF_F2_RCOND_BITS 3 5886146Stmm#define IF_F2_OP2_SHIFT 22 5986146Stmm#define IF_F2_OP2_BITS 3 6086146Stmm#define IF_F2_CC1_SHIFT 21 6186146Stmm#define IF_F2_CC1_BITS 1 6286146Stmm#define IF_F2_CC0_SHIFT 20 6386146Stmm#define IF_F2_CC0_BITS 1 6492050Stmm#define IF_F2_CC_SHIFT 20 /* CC0 and CC1 combined. */ 6592050Stmm#define IF_F2_CC_BITS 2 6686146Stmm#define IF_F2_D16HI_SHIFT 20 6786146Stmm#define IF_F2_D16HI_BITS 2 6886146Stmm#define IF_F2_P_SHIFT 19 6986146Stmm#define IF_F2_P_BITS 1 7086146Stmm#define IF_F2_RS1_SHIFT 14 7186146Stmm#define IF_F2_RS1_BITS 5 7286146Stmm 7386146Stmm/* 7486146Stmm * Definitions for format 3 7586146Stmm */ 7686146Stmm#define IF_F3_OP3_SHIFT 19 7786146Stmm#define IF_F3_OP3_BITS 6 7886146Stmm#define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 7986146Stmm#define IF_F3_RD_BITS IF_F2_RD_BITS 8086146Stmm#define IF_F3_FCN_SHIFT 25 8186146Stmm#define IF_F3_FCN_BITS 5 8286146Stmm#define IF_F3_CC1_SHIFT 26 8386146Stmm#define IF_F3_CC1_BITS 1 8486146Stmm#define IF_F3_CC0_SHIFT 25 8586146Stmm#define IF_F3_CC0_BITS 1 8692050Stmm#define IF_F3_CC_SHIFT 25 /* CC0 and CC1 combined. */ 8792050Stmm#define IF_F3_CC_BITS 2 8886146Stmm#define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 8986146Stmm#define IF_F3_RS1_BITS IF_F2_RS1_BITS 9086146Stmm#define IF_F3_I_SHIFT 13 9186146Stmm#define IF_F3_I_BITS 1 9286146Stmm#define IF_F3_X_SHIFT 12 9386146Stmm#define IF_F3_X_BITS 1 9486146Stmm#define IF_F3_RCOND_SHIFT 10 9586146Stmm#define IF_F3_RCOND_BITS 3 9686146Stmm#define IF_F3_IMM_ASI_SHIFT 5 9786146Stmm#define IF_F3_IMM_ASI_BITS 8 9886146Stmm#define IF_F3_OPF_SHIFT 5 9986146Stmm#define IF_F3_OPF_BITS 9 10086146Stmm#define IF_F3_CMASK_SHIFT 4 10186146Stmm#define IF_F3_CMASK_BITS 3 10286146Stmm#define IF_F3_RS2_SHIFT 0 10386146Stmm#define IF_F3_RS2_BITS 5 10486146Stmm#define IF_F3_SHCNT32_SHIFT 0 10586146Stmm#define IF_F3_SHCNT32_BITS 5 10686146Stmm#define IF_F3_SHCNT64_SHIFT 0 10786146Stmm#define IF_F3_SHCNT64_BITS 6 10886146Stmm 10986146Stmm/* 11086146Stmm * Definitions for format 4 11186146Stmm */ 11286146Stmm#define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 11386146Stmm#define IF_F4_OP3_BITS IF_F3_OP3_BITS 11486146Stmm#define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 11586146Stmm#define IF_F4_RD_BITS IF_F2_RD_BITS 11686146Stmm#define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 11786146Stmm#define IF_F4_RS1_BITS IF_F2_RS1_BITS 11886146Stmm#define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 11986146Stmm#define IF_F4_TCOND_BITS IF_F2_COND_BITS 12086146Stmm#define IF_F4_CC2_SHIFT 18 12186146Stmm#define IF_F4_CC2_BITS 1 12286146Stmm#define IF_F4_COND_SHIFT 14 12386146Stmm#define IF_F4_COND_BITS 4 12486146Stmm#define IF_F4_I_SHIFT IF_F3_I_SHIFT 12586146Stmm#define IF_F4_I_BITS IF_F3_I_BITS 12686146Stmm#define IF_F4_OPF_CC_SHIFT 11 12786146Stmm#define IF_F4_OPF_CC_BITS 3 12886146Stmm#define IF_F4_CC1_SHIFT 12 12986146Stmm#define IF_F4_CC1_BITS 1 13086146Stmm#define IF_F4_CC0_SHIFT 11 13186146Stmm#define IF_F4_CC0_BITS 1 13286146Stmm#define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 13386146Stmm#define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 13486146Stmm#define IF_F4_OPF_LOW_SHIFT 5 13586146Stmm#define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 13686146Stmm#define IF_F4_RS2_BITS IF_F3_RS2_BITS 13786146Stmm#define IF_F4_SW_TRAP_SHIFT 0 13886146Stmm#define IF_F4_SW_TRAP_BITS 7 13986146Stmm 14086146Stmm/* 14186146Stmm * Macros to decode instructions 14286146Stmm */ 14386146Stmm/* Extract a field */ 14488663Sjake#define IF_MASK(s, w) (((1 << (w)) - 1) << (s)) 14588663Sjake#define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s)) 14686146Stmm#define IF_DECODE(x, f) \ 14786146Stmm IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 14886146Stmm 14986146Stmm/* Sign-extend a field of width W */ 15086146Stmm#define IF_SEXT(x, w) \ 15196491Sjake (((x) & (1L << ((w) - 1))) != 0 ? \ 15296491Sjake (-1L - ((x) ^ ((1L << (w)) - 1))) : (x)) 15386146Stmm 15486146Stmm#if 0 15586146Stmm/* 15686146Stmm * The following C variant is from db_disassemble.c, and surely faster, but it 15786146Stmm * relies on behaviour that is undefined by the C standard (>> in conjunction 15886146Stmm * with signed negative arguments). 15986146Stmm */ 16086146Stmm#define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 16186146Stmm/* Assembler version of the above */ 16286146Stmm#define IF_SEXT(v, w) \ 16386146Stmm { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 16486146Stmm "=r" (t) : "r" (v) : "i" (64 - w)); t)} 16586146Stmm#endif 16686146Stmm 16786146Stmm/* All instruction formats */ 16886146Stmm#define IF_OP(i) IF_DECODE(i, OP) 16986146Stmm 17086146Stmm/* Instruction format 2 */ 17186146Stmm#define IF_F2_RD(i) IF_DECODE((i), F2_RD) 17286146Stmm#define IF_F2_A(i) IF_DECODE((i), F2_A) 17386146Stmm#define IF_F2_COND(i) IF_DECODE((i), F2_COND) 17486146Stmm#define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 17586146Stmm#define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 17686146Stmm#define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 17786146Stmm#define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 17892050Stmm#define IF_F2_CC(i) IF_DECODE((i), F2_CC) 17986146Stmm#define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 18086146Stmm#define IF_F2_P(i) IF_DECODE((i), F2_P) 18186146Stmm#define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 18286146Stmm 18386146Stmm/* Instruction format 3 */ 18486146Stmm#define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 18586146Stmm#define IF_F3_RD(i) IF_F2_RD((i)) 18686146Stmm#define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 18786146Stmm#define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 18886146Stmm#define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 18992050Stmm#define IF_F3_CC(i) IF_DECODE((i), F3_CC) 19086146Stmm#define IF_F3_RS1(i) IF_F2_RS1((i)) 19186146Stmm#define IF_F3_I(i) IF_DECODE((i), F3_I) 19286146Stmm#define IF_F3_X(i) IF_DECODE((i), F3_X) 19386146Stmm#define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 19486146Stmm#define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 19586146Stmm#define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 19686146Stmm#define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 19786146Stmm#define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 19886146Stmm#define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 19986146Stmm#define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 20086146Stmm 20186146Stmm/* Instruction format 4 */ 20286146Stmm#define IF_F4_OP3(i) IF_F3_OP3((i)) 20386146Stmm#define IF_F4_RD(i) IF_F3_RD((i)) 20486146Stmm#define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 20586146Stmm#define IF_F4_RS1(i) IF_F3_RS1((i)) 20686146Stmm#define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 20786146Stmm#define IF_F4_COND(i) IF_DECODE((i), F4_COND) 20886146Stmm#define IF_F4_I(i) IF_F3_I((i)) 20986146Stmm#define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 21086146Stmm#define IF_F4_RCOND(i) IF_F3_RCOND((i)) 21186146Stmm#define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 21286146Stmm#define IF_F4_RS2(i) IF_F3_RS2((i)) 21386146Stmm#define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 21486146Stmm 21586146Stmm/* Extract an immediate from an instruction, with an without sign extension */ 21686146Stmm#define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 21786146Stmm#define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 21886146Stmm 21986146Stmm/* 22086146Stmm * Macros to encode instructions 22186146Stmm */ 22286146Stmm#define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 22386146Stmm#define IF_ENCODE(x, f) \ 22486146Stmm IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 22586146Stmm 22686146Stmm/* All instruction formats */ 22786146Stmm#define EIF_OP(x) IF_ENCODE((x), OP) 22886146Stmm 22986146Stmm/* Instruction format 2 */ 23086146Stmm#define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 23186146Stmm#define EIF_F2_A(x) IF_ENCODE((x), F2_A) 23286146Stmm#define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 23386146Stmm#define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 23486146Stmm#define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 23586146Stmm#define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 23686146Stmm#define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 23786146Stmm#define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 23886146Stmm#define EIF_F2_P(x) IF_ENCODE((x), F2_P) 23986146Stmm#define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 24086146Stmm 24186146Stmm/* Instruction format 3 */ 24286146Stmm#define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 24386146Stmm#define EIF_F3_RD(x) EIF_F2_RD((x)) 24486146Stmm#define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 24586146Stmm#define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 24686146Stmm#define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 24786146Stmm#define EIF_F3_RS1(x) EIF_F2_RS1((x)) 24886146Stmm#define EIF_F3_I(x) IF_ENCODE((x), F3_I) 24986146Stmm#define EIF_F3_X(x) IF_ENCODE((x), F3_X) 25086146Stmm#define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 25186146Stmm#define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 25286146Stmm#define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 25386146Stmm#define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 25486146Stmm#define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 25586146Stmm#define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 25686146Stmm#define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 25786146Stmm 25886146Stmm/* Instruction format 4 */ 25986146Stmm#define EIF_F4_OP3(x) EIF_F3_OP3((x)) 26086146Stmm#define EIF_F4_RD(x) EIF_F2_RD((x)) 26186146Stmm#define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 26286146Stmm#define EIF_F4_RS1(x) EIF_F2_RS1((x)) 26386146Stmm#define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 26486146Stmm#define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 26586146Stmm#define EIF_F4_I(x) EIF_F3_I((x)) 26686146Stmm#define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 26786146Stmm#define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 26886146Stmm#define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 26986146Stmm#define EIF_F4_RS2(x) EIF_F3_RS2((x)) 27086146Stmm#define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 27186146Stmm 27286146Stmm/* Immediates */ 27386146Stmm#define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 27486146Stmm#define EIF_SIMM(x, w) IF_EIMM((x), (w)) 27586146Stmm 27686146Stmm/* 27786146Stmm * OP field values (specifying the instruction format) 27886146Stmm */ 27986146Stmm#define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 28086146Stmm#define IOP_CALL 0x01 /* Format 1: call */ 28186146Stmm#define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 28286146Stmm#define IOP_LDST 0x03 /* Format 4: loads and stores */ 28386146Stmm 28486146Stmm/* 28586146Stmm * OP2/OP3 values (specifying the actual instruction) 28686146Stmm */ 28786146Stmm/* OP2 values for format 2 (OP = 0) */ 28886146Stmm#define INS0_ILLTRAP 0x00 28986146Stmm#define INS0_BPcc 0x01 29086146Stmm#define INS0_Bicc 0x02 29186146Stmm#define INS0_BPr 0x03 29286146Stmm#define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 29386146Stmm#define INS0_FBPfcc 0x05 29486146Stmm#define INS0_FBfcc 0x06 29586146Stmm/* undefined 0x07 */ 29686146Stmm 29786146Stmm/* OP3 values for Format 3 and 4 (OP = 2) */ 29886146Stmm#define INS2_ADD 0x00 29986146Stmm#define INS2_AND 0x01 30086146Stmm#define INS2_OR 0x02 30186146Stmm#define INS2_XOR 0x03 30286146Stmm#define INS2_SUB 0x04 30386146Stmm#define INS2_ANDN 0x05 30486146Stmm#define INS2_ORN 0x06 30586146Stmm#define INS2_XNOR 0x07 30686146Stmm#define INS2_ADDC 0x08 30786146Stmm#define INS2_MULX 0x09 30886146Stmm#define INS2_UMUL 0x0a 30986146Stmm#define INS2_SMUL 0x0b 31086146Stmm#define INS2_SUBC 0x0c 31186146Stmm#define INS2_UDIVX 0x0d 31286146Stmm#define INS2_UDIV 0x0e 31386146Stmm#define INS2_SDIV 0x0f 31486146Stmm#define INS2_ADDcc 0x10 31586146Stmm#define INS2_ANDcc 0x11 31686146Stmm#define INS2_ORcc 0x12 31786146Stmm#define INS2_XORcc 0x13 31886146Stmm#define INS2_SUBcc 0x14 31986146Stmm#define INS2_ANDNcc 0x15 32086146Stmm#define INS2_ORNcc 0x16 32186146Stmm#define INS2_XNORcc 0x17 32286146Stmm#define INS2_ADDCcc 0x18 32386146Stmm/* undefined 0x19 */ 32486146Stmm#define INS2_UMULcc 0x1a 32586146Stmm#define INS2_SMULcc 0x1b 32686146Stmm#define INS2_SUBCcc 0x1c 32786146Stmm/* undefined 0x1d */ 32886146Stmm#define INS2_UDIVcc 0x1e 32986146Stmm#define INS2_SDIVcc 0x1f 33086146Stmm#define INS2_TADDcc 0x20 33186146Stmm#define INS2_TSUBcc 0x21 33286146Stmm#define INS2_TADDccTV 0x22 33386146Stmm#define INS2_TSUBccTV 0x23 33486146Stmm#define INS2_MULScc 0x24 33586146Stmm#define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 33686146Stmm#define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 33786146Stmm#define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 33886146Stmm#define INS2_RD 0x28 /* and MEMBAR, STBAR */ 33986146Stmm/* undefined 0x29 */ 34086146Stmm#define INS2_RDPR 0x2a 34186146Stmm#define INS2_FLUSHW 0x2b 34286146Stmm#define INS2_MOVcc 0x2c 34386146Stmm#define INS2_SDIVX 0x2d 34486146Stmm#define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 34586146Stmm#define INS2_MOVr 0x2f 34686146Stmm#define INS2_WR 0x30 /* and SIR */ 34786146Stmm#define INS2_SV_RSTR 0x31 /* saved, restored */ 34886146Stmm#define INS2_WRPR 0x32 34986146Stmm/* undefined 0x33 */ 35086146Stmm#define INS2_FPop1 0x34 /* further encoded in opf field */ 35186146Stmm#define INS2_FPop2 0x35 /* further encoded in opf field */ 35286146Stmm#define INS2_IMPLDEP1 0x36 35386146Stmm#define INS2_IMPLDEP2 0x37 35486146Stmm#define INS2_JMPL 0x38 35586146Stmm#define INS2_RETURN 0x39 35686146Stmm#define INS2_Tcc 0x3a 35786146Stmm#define INS2_FLUSH 0x3b 35886146Stmm#define INS2_SAVE 0x3c 35986146Stmm#define INS2_RESTORE 0x3d 36086146Stmm#define INS2_DONE_RETR 0x3e /* done, retry */ 36186146Stmm/* undefined 0x3f */ 36286146Stmm 36386146Stmm/* OP3 values for format 3 (OP = 3) */ 36486146Stmm#define INS3_LDUW 0x00 36586146Stmm#define INS3_LDUB 0x01 36686146Stmm#define INS3_LDUH 0x02 36786146Stmm#define INS3_LDD 0x03 36886146Stmm#define INS3_STW 0x04 36986146Stmm#define INS3_STB 0x05 37086146Stmm#define INS3_STH 0x06 37186146Stmm#define INS3_STD 0x07 37286146Stmm#define INS3_LDSW 0x08 37386146Stmm#define INS3_LDSB 0x09 37486146Stmm#define INS3_LDSH 0x0a 37586146Stmm#define INS3_LDX 0x0b 37686146Stmm/* undefined 0x0c */ 37786146Stmm#define INS3_LDSTUB 0x0d 37886146Stmm#define INS3_STX 0x0e 37986146Stmm#define INS3_SWAP 0x0f 38086146Stmm#define INS3_LDUWA 0x10 38186146Stmm#define INS3_LDUBA 0x11 38286146Stmm#define INS3_LDUHA 0x12 38386146Stmm#define INS3_LDDA 0x13 38486146Stmm#define INS3_STWA 0x14 38586146Stmm#define INS3_STBA 0x15 38686146Stmm#define INS3_STHA 0x16 38786146Stmm#define INS3_STDA 0x17 38886146Stmm#define INS3_LDSWA 0x18 38986146Stmm#define INS3_LDSBA 0x19 39086146Stmm#define INS3_LDSHA 0x1a 39186146Stmm#define INS3_LDXA 0x1b 39286146Stmm/* undefined 0x1c */ 39386146Stmm#define INS3_LDSTUBA 0x1d 39486146Stmm#define INS3_STXA 0x1e 39586146Stmm#define INS3_SWAPA 0x1f 39686146Stmm#define INS3_LDF 0x20 39786146Stmm#define INS3_LDFSR 0x21 /* and LDXFSR */ 39886146Stmm#define INS3_LDQF 0x22 39986146Stmm#define INS3_LDDF 0x23 40086146Stmm#define INS3_STF 0x24 40186146Stmm#define INS3_STFSR 0x25 /* and STXFSR */ 40286146Stmm#define INS3_STQF 0x26 40386146Stmm#define INS3_STDF 0x27 40486146Stmm/* undefined 0x28 - 0x2c */ 40586146Stmm#define INS3_PREFETCH 0x2d 40686146Stmm/* undefined 0x2e - 0x2f */ 40786146Stmm#define INS3_LDFA 0x30 40886146Stmm/* undefined 0x31 */ 40986146Stmm#define INS3_LDQFA 0x32 41086146Stmm#define INS3_LDDFA 0x33 41186146Stmm#define INS3_STFA 0x34 41286146Stmm/* undefined 0x35 */ 41386146Stmm#define INS3_STQFA 0x36 41486146Stmm#define INS3_STDFA 0x37 41586146Stmm/* undefined 0x38 - 0x3b */ 41686146Stmm#define INS3_CASA 0x39 41786146Stmm#define INS3_PREFETCHA 0x3a 41886146Stmm#define INS3_CASXA 0x3b 41986146Stmm 42086146Stmm/* 42186146Stmm * OPF values (floating point instructions, IMPLDEP) 42286146Stmm */ 42388663Sjake/* 42488663Sjake * These values are or'ed to the FPop values to get the instructions. 42588663Sjake * They describe the operand type(s). 42688663Sjake */ 42788663Sjake#define INSFP_i 0x000 /* 32-bit int */ 42888663Sjake#define INSFP_s 0x001 /* 32-bit single */ 42988663Sjake#define INSFP_d 0x002 /* 64-bit double */ 43088663Sjake#define INSFP_q 0x003 /* 128-bit quad */ 43188663Sjake/* FPop1. The comments give the types for which this instruction is defined. */ 43288663Sjake#define INSFP1_FMOV 0x000 /* s, d, q */ 43388663Sjake#define INSFP1_FNEG 0x004 /* s, d, q */ 43488663Sjake#define INSFP1_FABS 0x008 /* s, d, q */ 43588663Sjake#define INSFP1_FSQRT 0x028 /* s, d, q */ 43688663Sjake#define INSFP1_FADD 0x040 /* s, d, q */ 43788663Sjake#define INSFP1_FSUB 0x044 /* s, d, q */ 43888663Sjake#define INSFP1_FMUL 0x048 /* s, d, q */ 43988663Sjake#define INSFP1_FDIV 0x04c /* s, d, q */ 44088663Sjake#define INSFP1_FsMULd 0x068 /* s */ 44188663Sjake#define INSFP1_FdMULq 0x06c /* d */ 44288663Sjake#define INSFP1_FTOx 0x080 /* s, d, q */ 44388663Sjake#define INSFP1_FxTOs 0x084 /* special: i only */ 44488663Sjake#define INSFP1_FxTOd 0x088 /* special: i only */ 44588663Sjake#define INSFP1_FxTOq 0x08c /* special: i only */ 44688663Sjake#define INSFP1_FTOs 0x0c4 /* i, d, q */ 44788663Sjake#define INSFP1_FTOd 0x0c8 /* i, s, q */ 44888663Sjake#define INSFP1_FTOq 0x0cc /* i, s, d */ 44988663Sjake#define INSFP1_FTOi 0x0d0 /* i, s, d */ 45086146Stmm 45186146Stmm/* FPop2 */ 45286146Stmm#define INSFP2_FMOV_CCMUL 0x40 45388663Sjake#define INSFP2_FMOV_CCOFFS 0x00 45488663Sjake/* Use the IFCC_* constants for cc. Operand types: s, d, q */ 45588663Sjake#define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 45686146Stmm#define INSFP2_FMOV_RCMUL 0x20 45788663Sjake#define INSFP2_FMOV_RCOFFS 0x04 45888663Sjake/* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 45988663Sjake#define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 46088663Sjake#define INSFP2_FCMP 0x050 /* s, d, q */ 46188663Sjake#define INSFP2_FCMPE 0x054 /* s, d, q */ 46286146Stmm 46396422Sjake/* Decode 5-bit register field into 6-bit number (for doubles and quads). */ 46496422Sjake#define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5)) 46596422Sjake 46686146Stmm/* IMPLDEP1 for Sun UltraSparc */ 46786146Stmm#define IIDP1_EDGE8 0x00 468100185Stmm#define IIDP1_EDGE8N 0x01 /* US-III */ 46986146Stmm#define IIDP1_EDGE8L 0x02 470100185Stmm#define IIDP1_EDGE8LN 0x03 /* US-III */ 47186146Stmm#define IIDP1_EDGE16 0x04 472100185Stmm#define IIDP1_EDGE16N 0x05 /* US-III */ 47386146Stmm#define IIDP1_EDGE16L 0x06 474100185Stmm#define IIDP1_EDGE16LN 0x07 /* US-III */ 47586146Stmm#define IIDP1_EDGE32 0x08 476100185Stmm#define IIDP1_EDGE32N 0x09 /* US-III */ 47786146Stmm#define IIDP1_EDGE32L 0x0a 478100185Stmm#define IIDP1_EDGE32LN 0x0b /* US-III */ 47986146Stmm#define IIDP1_ARRAY8 0x10 48086146Stmm#define IIDP1_ARRAY16 0x12 48186146Stmm#define IIDP1_ARRAY32 0x14 48286146Stmm#define IIDP1_ALIGNADDRESS 0x18 483100185Stmm#define IIDP1_BMASK 0x19 /* US-III */ 48486146Stmm#define IIDP1_ALIGNADDRESS_L 0x1a 48586146Stmm#define IIDP1_FCMPLE16 0x20 48686146Stmm#define IIDP1_FCMPNE16 0x22 48786146Stmm#define IIDP1_FCMPLE32 0x24 48886146Stmm#define IIDP1_FCMPNE32 0x26 48986146Stmm#define IIDP1_FCMPGT16 0x28 49086146Stmm#define IIDP1_FCMPEQ16 0x2a 49186146Stmm#define IIDP1_FCMPGT32 0x2c 49286146Stmm#define IIDP1_FCMPEQ32 0x2e 49386146Stmm#define IIDP1_FMUL8x16 0x31 49486146Stmm#define IIDP1_FMUL8x16AU 0x33 49586146Stmm#define IIDP1_FMUL8X16AL 0x35 49686146Stmm#define IIDP1_FMUL8SUx16 0x36 49786146Stmm#define IIDP1_FMUL8ULx16 0x37 49886146Stmm#define IIDP1_FMULD8SUx16 0x38 49986146Stmm#define IIDP1_FMULD8ULx16 0x39 50086146Stmm#define IIDP1_FPACK32 0x3a 50186146Stmm#define IIDP1_FPACK16 0x3b 50286146Stmm#define IIDP1_FPACKFIX 0x3d 50386146Stmm#define IIDP1_PDIST 0x3e 50486146Stmm#define IIDP1_FALIGNDATA 0x48 50586146Stmm#define IIDP1_FPMERGE 0x4b 506100185Stmm#define IIDP1_BSHUFFLE 0x4c /* US-III */ 50786146Stmm#define IIDP1_FEXPAND 0x4d 50886146Stmm#define IIDP1_FPADD16 0x50 50986146Stmm#define IIDP1_FPADD16S 0x51 51086146Stmm#define IIDP1_FPADD32 0x52 51186146Stmm#define IIDP1_FPADD32S 0x53 51286146Stmm#define IIDP1_SUB16 0x54 51386146Stmm#define IIDP1_SUB16S 0x55 51486146Stmm#define IIDP1_SUB32 0x56 51586146Stmm#define IIDP1_SUB32S 0x57 51686146Stmm#define IIDP1_FZERO 0x60 51786146Stmm#define IIDP1_FZEROS 0x61 51886146Stmm#define IIDP1_FNOR 0x62 51986146Stmm#define IIDP1_FNORS 0x63 52086146Stmm#define IIDP1_FANDNOT2 0x64 52186146Stmm#define IIDP1_FANDNOT2S 0x65 52286146Stmm#define IIDP1_NOT2 0x66 52386146Stmm#define IIDP1_NOT2S 0x67 52486146Stmm#define IIDP1_FANDNOT1 0x68 52586146Stmm#define IIDP1_FANDNOT1S 0x69 52686146Stmm#define IIDP1_FNOT1 0x6a 52786146Stmm#define IIDP1_FNOT1S 0x6b 52886146Stmm#define IIDP1_FXOR 0x6c 52986146Stmm#define IIDP1_FXORS 0x6d 53086146Stmm#define IIDP1_FNAND 0x6e 53186146Stmm#define IIDP1_FNANDS 0x6f 53286146Stmm#define IIDP1_FAND 0x70 53386146Stmm#define IIDP1_FANDS 0x71 53486146Stmm#define IIDP1_FXNOR 0x72 53586146Stmm#define IIDP1_FXNORS 0x73 53686146Stmm#define IIDP1_FSRC1 0x74 53786146Stmm#define IIDP1_FSRC1S 0x75 53886146Stmm#define IIDP1_FORNOT2 0x76 53986146Stmm#define IIDP1_FORNOT2S 0x77 54086146Stmm#define IIDP1_FSRC2 0x78 54186146Stmm#define IIDP1_FSRC2S 0x79 54286146Stmm#define IIDP1_FORNOT1 0x7a 54386146Stmm#define IIDP1_FORNOT1S 0x7b 54486146Stmm#define IIDP1_FOR 0x7c 54586146Stmm#define IIDP1_FORS 0x7d 54686146Stmm#define IIDP1_FONE 0x7e 54786146Stmm#define IIDP1_FONES 0x7f 54886146Stmm#define IIDP1_SHUTDOWN 0x80 549100185Stmm#define IIDP1_SIAM 0x81 /* US-III */ 55086146Stmm 55186146Stmm/* 55286146Stmm * Instruction modifiers 55386146Stmm */ 55486146Stmm/* cond values for integer ccr's */ 55586146Stmm#define IICOND_N 0x00 55686146Stmm#define IICOND_E 0x01 55786146Stmm#define IICOND_LE 0x02 55886146Stmm#define IICOND_L 0x03 55986146Stmm#define IICOND_LEU 0x04 56086146Stmm#define IICOND_CS 0x05 56186146Stmm#define IICOND_NEG 0x06 56286146Stmm#define IICOND_VS 0x07 56386146Stmm#define IICOND_A 0x08 56486146Stmm#define IICOND_NE 0x09 56586146Stmm#define IICOND_G 0x0a 56686146Stmm#define IICOND_GE 0x0b 56786146Stmm#define IICOND_GU 0x0c 56886146Stmm#define IICOND_CC 0x0d 56986146Stmm#define IICOND_POS 0x0e 57086146Stmm#define IICOND_VC 0x0f 57186146Stmm 57286146Stmm/* cond values for fp ccr's */ 57386146Stmm#define IFCOND_N 0x00 57486146Stmm#define IFCOND_NE 0x01 57586146Stmm#define IFCOND_LG 0x02 57686146Stmm#define IFCOND_UL 0x03 57786146Stmm#define IFCOND_L 0x04 57886146Stmm#define IFCOND_UG 0x05 57986146Stmm#define IFCOND_G 0x06 58086146Stmm#define IFCOND_U 0x07 58186146Stmm#define IFCOND_A 0x08 58286146Stmm#define IFCOND_E 0x09 58386146Stmm#define IFCOND_UE 0x0a 58486146Stmm#define IFCOND_GE 0x0b 58586146Stmm#define IFCOND_UGE 0x0c 58686146Stmm#define IFCOND_LE 0x0d 58786146Stmm#define IFCOND_ULE 0x0e 58886146Stmm#define IFCOND_O 0x0f 58986146Stmm 59086146Stmm/* rcond values for BPr, MOVr, FMOVr */ 59188663Sjake#define IRCOND_Z 0x01 59286146Stmm#define IRCOND_LEZ 0x02 59386146Stmm#define IRCOND_LZ 0x03 59486146Stmm#define IRCOND_NZ 0x05 59586146Stmm#define IRCOND_GZ 0x06 59686146Stmm#define IRCOND_GEZ 0x07 59786146Stmm 59886146Stmm/* cc values for MOVcc and FMOVcc */ 59986146Stmm#define IFCC_ICC 0x04 60086146Stmm#define IFCC_XCC 0x06 60186146Stmm/* if true, the lower 2 bits are the fcc number */ 60288663Sjake#define IFCC_FCC(c) ((c) & 3) 60388663Sjake#define IFCC_GET_FCC(c) ((c) & 3) 60488663Sjake#define IFCC_ISFCC(c) (((c) & 4) == 0) 60586146Stmm 60686146Stmm/* cc values for BPc and Tcc */ 60786146Stmm#define IBCC_ICC 0x00 60886146Stmm#define IBCC_XCC 0x02 60986146Stmm 61086146Stmm/* 61186146Stmm * Integer registers 61286146Stmm */ 61386146Stmm#define IREG_G0 0x00 61486146Stmm#define IREG_O0 0x08 61586146Stmm#define IREG_L0 0x10 61686146Stmm#define IREQ_I0 0x18 61786146Stmm 61886146Stmm#endif /* !_MACHINE_INSTR_H_ */ 619