asi.h revision 100180
180709Sjake/*- 282894Sjake * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved. 380709Sjake * 480709Sjake * Redistribution and use in source and binary forms, with or without 580709Sjake * modification, are permitted provided that the following conditions 680709Sjake * are met: 780709Sjake * 1. Redistributions of source code must retain the above copyright 880709Sjake * notice, this list of conditions and the following disclaimer. 980709Sjake * 2. Redistributions in binary form must reproduce the above copyright 1080709Sjake * notice, this list of conditions and the following disclaimer in the 1180709Sjake * documentation and/or other materials provided with the distribution. 1282894Sjake * 3. Berkeley Software Design Inc's name may not be used to endorse or 1382894Sjake * promote products derived from this software without specific prior 1482894Sjake * written permission. 1580709Sjake * 1682894Sjake * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND 1780709Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1880709Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1982894Sjake * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE 2080709Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2180709Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2280709Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2380709Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2480709Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2580709Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2680709Sjake * SUCH DAMAGE. 2780709Sjake * 2882894Sjake * from: BSDI: asi.h,v 1.3 1997/08/08 14:31:42 torek 2980709Sjake * $FreeBSD: head/sys/sparc64/include/asi.h 100180 2002-07-16 16:22:25Z tmm $ 3080709Sjake */ 3180709Sjake 3280709Sjake#ifndef _MACHINE_ASI_H_ 3380709Sjake#define _MACHINE_ASI_H_ 3480709Sjake 3580709Sjake/* 3680709Sjake * Standard v9 asis 3780709Sjake */ 3880709Sjake#define ASI_N 0x4 3980709Sjake#define ASI_NL 0xc 4080709Sjake#define ASI_AIUP 0x10 4180709Sjake#define ASI_AIUS 0x11 42100180Stmm#define ASI_AIUPL 0x18 4380709Sjake#define ASI_AIUSL 0x19 4480709Sjake#define ASI_P 0x80 4580709Sjake#define ASI_S 0x81 4680709Sjake#define ASI_PNF 0x82 4780709Sjake#define ASI_SNF 0x83 4880709Sjake#define ASI_PL 0x88 49100180Stmm#define ASI_SL 0x89 5080709Sjake#define ASI_PNFL 0x8a 5180709Sjake#define ASI_SNFL 0x8b 5280709Sjake 5380709Sjake/* 54100180Stmm * UltraSPARC extensions. ASIs limited to a certain family are annotated. 5580709Sjake */ 5680709Sjake#define ASI_PHYS_USE_EC 0x14 5780709Sjake#define ASI_PHYS_BYPASS_EC_WITH_EBIT 0x15 5880709Sjake#define ASI_PHYS_USE_EC_L 0x1c 5980709Sjake#define ASI_PHYS_BYPASS_EC_WITH_EBIT_L 0x1d 6080709Sjake 6180709Sjake#define ASI_NUCLEUS_QUAD_LDD 0x24 6280709Sjake#define ASI_NUCLEUS_QUAD_LDD_L 0x2c 6380709Sjake 64100180Stmm#define ASI_PCACHE_STATUS_DATA 0x30 /* US-III Cu */ 65100180Stmm#define ASI_PCACHE_DATA 0x31 /* US-III Cu */ 66100180Stmm#define ASI_PCACHE_TAG 0x32 /* US-III Cu */ 67100180Stmm#define ASI_PCACHE_SNOOP_TAG 0x33 /* US-III Cu */ 68100180Stmm 69100180Stmm#define ASI_ATOMIC_QUAD_LDD_PHYS 0x34 /* US-III Cu */ 70100180Stmm 71100180Stmm#define ASI_WCACHE_VALID_BITS 0x38 /* US-III Cu */ 72100180Stmm#define ASI_WCACHE_DATA 0x39 /* US-III Cu */ 73100180Stmm#define ASI_WCACHE_TAG 0x3a /* US-III Cu */ 74100180Stmm#define ASI_WCACHE_SNOOP_TAG 0x3b /* US-III Cu */ 75100180Stmm 76100180Stmm#define ASI_ATOMIC_QUAD_LDD_PHYS_L 0x3c /* US-III Cu */ 77100180Stmm 78100180Stmm#define ASI_SRAM_FAST_INIT 0x40 /* US-III Cu */ 79100180Stmm 80100180Stmm#define ASI_DCACHE_INVALIDATE 0x42 /* US-III Cu */ 81100180Stmm#define ASI_DCACHE_UTAG 0x43 /* US-III Cu */ 82100180Stmm#define ASI_DCACHE_SNOOP_TAG 0x44 /* US-III Cu */ 83100180Stmm 84100180Stmm/* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */ 8582894Sjake#define ASI_LSU_CTL_REG 0x45 8682894Sjake 87100180Stmm#define ASI_DCACHE_DATA 0x46 88100180Stmm#define ASI_DCACHE_TAG 0x47 89100180Stmm 9082894Sjake#define ASI_INTR_DISPATCH_STATUS 0x48 9182894Sjake#define ASI_INTR_RECEIVE 0x49 92100180Stmm#define ASI_UPA_CONFIG_REG 0x4a /* US-I, II */ 9382894Sjake 94100180Stmm#define ASI_FIREPLANE_CONFIG_REG 0x4a /* US-III Cu */ 95100180Stmm#define AA_FIREPLANE_CONFIG 0x0 /* US-III Cu */ 96100180Stmm#define AA_FIREPLANE_ADDRESS 0x8 /* US-III Cu */ 97100180Stmm 98100180Stmm#define ASI_ESTATE_ERROR_EN_REG 0x4b 99100180Stmm#define ASI_AFSR 0x4c 100100180Stmm#define ASI_AFAR 0x4d 101100180Stmm 102100180Stmm#define ASI_ECACHE_TAG_DATA 0x4e 103100180Stmm 10482894Sjake#define ASI_IMMU_TAG_TARGET_REG 0x50 10580709Sjake#define ASI_IMMU 0x50 10680709Sjake#define AA_IMMU_TTR 0x0 10780709Sjake#define AA_IMMU_SFSR 0x18 10880709Sjake#define AA_IMMU_TSB 0x28 10980709Sjake#define AA_IMMU_TAR 0x30 110100180Stmm#define AA_IMMU_TSB_PEXT_REG 0x48 /* US-III family */ 111100180Stmm#define AA_IMMU_TSB_SEXT_REG 0x50 /* US-III family */ 112100180Stmm#define AA_IMMU_TSB_NEXT_REG 0x58 /* US-III family */ 11380709Sjake 11480709Sjake#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 11580709Sjake#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 116100180Stmm 117100180Stmm#define ASI_SERIAL_ID 0x53 /* US-III family */ 118100180Stmm 11980709Sjake#define ASI_ITLB_DATA_IN_REG 0x54 120100180Stmm/* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */ 12180709Sjake#define ASI_ITLB_DATA_ACCESS_REG 0x55 12280709Sjake#define ASI_ITLB_TAG_READ_REG 0x56 12380709Sjake#define ASI_IMMU_DEMAP 0x57 12480709Sjake 12580709Sjake#define ASI_DMMU_TAG_TARGET_REG 0x58 12680709Sjake#define ASI_DMMU 0x58 12780709Sjake#define AA_DMMU_TTR 0x0 12880709Sjake#define AA_DMMU_PCXR 0x8 12980709Sjake#define AA_DMMU_SCXR 0x10 13080709Sjake#define AA_DMMU_SFSR 0x18 13180709Sjake#define AA_DMMU_SFAR 0x20 13280709Sjake#define AA_DMMU_TSB 0x28 13380709Sjake#define AA_DMMU_TAR 0x30 13480709Sjake#define AA_DMMU_VWPR 0x38 13580709Sjake#define AA_DMMU_PWPR 0x40 136100180Stmm#define AA_DMMU_TSB_PEXT_REG 0x48 137100180Stmm#define AA_DMMU_TSB_SEXT_REG 0x50 138100180Stmm#define AA_DMMU_TSB_NEXT_REG 0x58 13980709Sjake 14080709Sjake#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 14180709Sjake#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a 14280709Sjake#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b 14380709Sjake#define ASI_DTLB_DATA_IN_REG 0x5c 144100180Stmm/* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */ 14580709Sjake#define ASI_DTLB_DATA_ACCESS_REG 0x5d 14680709Sjake#define ASI_DTLB_TAG_READ_REG 0x5e 14780709Sjake#define ASI_DMMU_DEMAP 0x5f 14880709Sjake 149100180Stmm#define ASI_IIU_INST_TRAP 0x60 /* US-III family */ 150100180Stmm 15186226Stmm#define ASI_ICACHE_INSTR 0x66 15286226Stmm#define ASI_ICACHE_TAG 0x67 153100180Stmm#define ASI_ICACHE_SNOOP_TAG 0x68 /* US-III family */ 154100180Stmm#define ASI_ICACHE_PRE_DECODE 0x6e /* US-I, II */ 155100180Stmm#define ASI_ICACHE_PRE_NEXT_FIELD 0x6f /* US-I, II */ 15686226Stmm 15781135Stmm#define ASI_BLK_AUIP 0x70 15881135Stmm#define ASI_BLK_AIUS 0x71 15981373Sjake 160100180Stmm#define ASI_MCU_CONFIG_REG 0x72 /* US-III Cu */ 161100180Stmm#define AA_MCU_TIMING1_REG 0x0 /* US-III Cu */ 162100180Stmm#define AA_MCU_TIMING2_REG 0x8 /* US-III Cu */ 163100180Stmm#define AA_MCU_TIMING3_REG 0x10 /* US-III Cu */ 164100180Stmm#define AA_MCU_TIMING4_REG 0x18 /* US-III Cu */ 165100180Stmm#define AA_MCU_DEC1_REG 0x20 /* US-III Cu */ 166100180Stmm#define AA_MCU_DEC2_REG 0x28 /* US-III Cu */ 167100180Stmm#define AA_MCU_DEC3_REG 0x30 /* US-III Cu */ 168100180Stmm#define AA_MCU_DEC4_REG 0x38 /* US-III Cu */ 169100180Stmm#define AA_MCU_ADDR_CNTL_REG 0x40 /* US-III Cu */ 170100180Stmm 171100180Stmm#define ASI_ECACHE_DATA 0x74 /* US-III Cu */ 172100180Stmm#define ASI_ECACHE_CONTROL 0x75 /* US-III Cu */ 17386226Stmm#define ASI_ECACHE_W 0x76 17486226Stmm 175100180Stmm/* 176100180Stmm * With the advent of the US-III, the numbering has changed, as additional 177100180Stmm * registers were inserted in between. We retain the original ordering for 178100180Stmm * now, and append an A to the inserted registers. 179100180Stmm * Exceptions are AA_SDB_INTR_D6 and AA_SDB_INTR_D7, which were appended 180100180Stmm * at the end. 181100180Stmm */ 18281373Sjake#define ASI_SDB_INTR_W 0x77 18381373Sjake#define AA_SDB_INTR_D0 0x40 184100180Stmm#define AA_SDB_INTR_D0A 0x48 /* US-III family */ 18581373Sjake#define AA_SDB_INTR_D1 0x50 186100180Stmm#define AA_SDB_INTR_D1A 0x5A /* US-III family */ 18781373Sjake#define AA_SDB_INTR_D2 0x60 188100180Stmm#define AA_SDB_INTR_D2A 0x68 /* US-III family */ 18989031Sjake#define AA_INTR_SEND 0x70 190100180Stmm#define AA_SDB_INTR_D6 0x80 /* US-III family */ 191100180Stmm#define AA_SDB_INTR_D7 0x88 /* US-III family */ 19281373Sjake 19381135Stmm#define ASI_BLK_AIUPL 0x78 19481135Stmm#define ASI_BLK_AIUSL 0x79 19581373Sjake 19686226Stmm#define ASI_ECACHE_R 0x7e 19786226Stmm 19881373Sjake#define ASI_SDB_INTR_R 0x7f 19981373Sjake 200100180Stmm#define ASI_PST8_P 0xc0 201100180Stmm#define ASI_PST8_S 0xc1 202100180Stmm#define ASI_PST16_P 0xc2 203100180Stmm#define ASI_PST16_S 0xc3 204100180Stmm#define ASI_PST32_P 0xc4 205100180Stmm#define ASI_PST32_S 0xc5 206100180Stmm 207100180Stmm#define ASI_PST8_PL 0xc8 208100180Stmm#define ASI_PST8_SL 0xc9 209100180Stmm#define ASI_PST16_PL 0xca 210100180Stmm#define ASI_PST16_SL 0xcb 211100180Stmm#define ASI_PST32_PL 0xcc 212100180Stmm#define ASI_PST32_SL 0xcd 213100180Stmm 214100180Stmm#define ASI_FL8_P 0xd0 215100180Stmm#define ASI_FL8_S 0xd1 216100180Stmm#define ASI_FL16_P 0xd2 217100180Stmm#define ASI_FL16_S 0xd3 218100180Stmm#define ASI_FL8_PL 0xd8 219100180Stmm#define ASI_FL8_SL 0xd9 220100180Stmm#define ASI_FL16_PL 0xda 221100180Stmm#define ASI_FL16_SL 0xdb 222100180Stmm 22386226Stmm#define ASI_BLK_COMMIT_P 0xe0 22486226Stmm#define ASI_BLK_COMMIT_S 0xe1 22581135Stmm#define ASI_BLK_P 0xf0 22681135Stmm#define ASI_BLK_S 0xf1 22781135Stmm#define ASI_BLK_PL 0xf8 22881135Stmm#define ASI_BLK_SL 0xf9 22981135Stmm 23080709Sjake#endif /* !_MACHINE_ASI_H_ */ 231