uninorthpci.c revision 208149 
1/*-
2 * Copyright (C) 2002 Benno Rice.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * $FreeBSD: head/sys/powerpc/powermac/uninorthpci.c 208149 2010-05-16 15:18:25Z nwhitehorn $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/module.h>
31#include <sys/bus.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34
35#include <dev/ofw/openfirm.h>
36#include <dev/ofw/ofw_pci.h>
37#include <dev/ofw/ofw_bus.h>
38#include <dev/ofw/ofw_bus_subr.h>
39
40#include <dev/pci/pcivar.h>
41#include <dev/pci/pcireg.h>
42
43#include <machine/bus.h>
44#include <machine/intr_machdep.h>
45#include <machine/md_var.h>
46#include <machine/pio.h>
47#include <machine/resource.h>
48
49#include <sys/rman.h>
50
51#include <powerpc/powermac/uninorthvar.h>
52
53#include <vm/vm.h>
54#include <vm/pmap.h>
55
56#include "pcib_if.h"
57
58#define	UNINORTH_DEBUG	0
59
60/*
61 * Device interface.
62 */
63static int		uninorth_probe(device_t);
64static int		uninorth_attach(device_t);
65
66/*
67 * Bus interface.
68 */
69static int		uninorth_read_ivar(device_t, device_t, int,
70			    uintptr_t *);
71static struct		resource * uninorth_alloc_resource(device_t bus,
72			    device_t child, int type, int *rid, u_long start,
73			    u_long end, u_long count, u_int flags);
74static int		uninorth_activate_resource(device_t bus, device_t child,
75			    int type, int rid, struct resource *res);
76
77/*
78 * pcib interface.
79 */
80static int		uninorth_maxslots(device_t);
81static u_int32_t	uninorth_read_config(device_t, u_int, u_int, u_int,
82			    u_int, int);
83static void		uninorth_write_config(device_t, u_int, u_int, u_int,
84			    u_int, u_int32_t, int);
85static int		uninorth_route_interrupt(device_t, device_t, int);
86
87/*
88 * OFW Bus interface
89 */
90
91static phandle_t	 uninorth_get_node(device_t bus, device_t dev);
92
93/*
94 * Local routines.
95 */
96static int		uninorth_enable_config(struct uninorth_softc *, u_int,
97			    u_int, u_int, u_int);
98
99/*
100 * Driver methods.
101 */
102static device_method_t	uninorth_methods[] = {
103	/* Device interface */
104	DEVMETHOD(device_probe,		uninorth_probe),
105	DEVMETHOD(device_attach,	uninorth_attach),
106
107	/* Bus interface */
108	DEVMETHOD(bus_print_child,	bus_generic_print_child),
109	DEVMETHOD(bus_read_ivar,	uninorth_read_ivar),
110	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
111	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
112	DEVMETHOD(bus_alloc_resource,	uninorth_alloc_resource),
113	DEVMETHOD(bus_activate_resource,	uninorth_activate_resource),
114
115	/* pcib interface */
116	DEVMETHOD(pcib_maxslots,	uninorth_maxslots),
117	DEVMETHOD(pcib_read_config,	uninorth_read_config),
118	DEVMETHOD(pcib_write_config,	uninorth_write_config),
119	DEVMETHOD(pcib_route_interrupt,	uninorth_route_interrupt),
120
121	/* ofw_bus interface */
122	DEVMETHOD(ofw_bus_get_node,     uninorth_get_node),
123
124	{ 0, 0 }
125};
126
127static driver_t	uninorth_driver = {
128	"pcib",
129	uninorth_methods,
130	sizeof(struct uninorth_softc)
131};
132
133static devclass_t	uninorth_devclass;
134
135DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
136
137static int
138uninorth_probe(device_t dev)
139{
140	const char	*type, *compatible;
141
142	type = ofw_bus_get_type(dev);
143	compatible = ofw_bus_get_compat(dev);
144
145	if (type == NULL || compatible == NULL)
146		return (ENXIO);
147
148	if (strcmp(type, "pci") != 0)
149		return (ENXIO);
150
151	if (strcmp(compatible, "uni-north") == 0) {
152		device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
153		return (0);
154	} else if (strcmp(compatible, "u3-agp") == 0) {
155		device_set_desc(dev, "Apple U3 Host-AGP bridge");
156		return (0);
157	} else if (strcmp(compatible, "u4-pcie") == 0) {
158		device_set_desc(dev, "IBM CPC945 PCI Express Root");
159		return (0);
160	}
161
162	return (ENXIO);
163}
164
165static int
166uninorth_attach(device_t dev)
167{
168	struct		uninorth_softc *sc;
169	const char	*compatible;
170	phandle_t	node;
171	u_int32_t	reg[3], busrange[2];
172	struct		uninorth_range *rp, *io, *mem[2];
173	int		nmem, i, error;
174
175	node = ofw_bus_get_node(dev);
176	sc = device_get_softc(dev);
177
178	if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
179		return (ENXIO);
180
181	if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
182		return (ENXIO);
183
184	sc->sc_ver = 0;
185	compatible = ofw_bus_get_compat(dev);
186	if (strcmp(compatible, "u3-agp") == 0)
187		sc->sc_ver = 3;
188	if (strcmp(compatible, "u4-pcie") == 0)
189		sc->sc_ver = 4;
190
191	sc->sc_dev = dev;
192	sc->sc_node = node;
193	if (sc->sc_ver >= 3) {
194	   sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
195	   sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
196	} else {
197	   sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
198	   sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
199	}
200	sc->sc_bus = busrange[0];
201
202	bzero(sc->sc_range, sizeof(sc->sc_range));
203	if (sc->sc_ver >= 3) {
204		/*
205		 * On Apple U3 systems, we have an otherwise standard
206		 * Uninorth controller driving AGP. The one difference
207		 * is that it uses a new PCI ranges format, so do the
208		 * translation.
209		 */
210
211		struct uninorth_range64 range64[6];
212		bzero(range64, sizeof(range64));
213
214		sc->sc_nrange = OF_getprop(node, "ranges", range64,
215		    sizeof(range64));
216		for (i = 0; range64[i].pci_hi != 0; i++) {
217			sc->sc_range[i].pci_hi = range64[i].pci_hi;
218			sc->sc_range[i].pci_mid = range64[i].pci_mid;
219			sc->sc_range[i].pci_lo = range64[i].pci_lo;
220			sc->sc_range[i].host = range64[i].host_lo;
221			sc->sc_range[i].size_hi = range64[i].size_hi;
222			sc->sc_range[i].size_lo = range64[i].size_lo;
223		}
224	} else {
225		sc->sc_nrange = OF_getprop(node, "ranges", sc->sc_range,
226		    sizeof(sc->sc_range));
227	}
228
229	if (sc->sc_nrange == -1) {
230		device_printf(dev, "could not get ranges\n");
231		return (ENXIO);
232	}
233
234	sc->sc_range[6].pci_hi = 0;
235	io = NULL;
236	nmem = 0;
237
238	for (rp = sc->sc_range; rp->pci_hi != 0; rp++) {
239		switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
240		case OFW_PCI_PHYS_HI_SPACE_CONFIG:
241			break;
242		case OFW_PCI_PHYS_HI_SPACE_IO:
243			io = rp;
244			break;
245		case OFW_PCI_PHYS_HI_SPACE_MEM32:
246			mem[nmem] = rp;
247			nmem++;
248			break;
249		case OFW_PCI_PHYS_HI_SPACE_MEM64:
250			break;
251		}
252	}
253
254	if (io == NULL) {
255		device_printf(dev, "can't find io range\n");
256		return (ENXIO);
257	}
258	sc->sc_io_rman.rm_type = RMAN_ARRAY;
259	sc->sc_io_rman.rm_descr = "UniNorth PCI I/O Ports";
260	sc->sc_iostart = io->host;
261	if (rman_init(&sc->sc_io_rman) != 0 ||
262	    rman_manage_region(&sc->sc_io_rman, io->pci_lo,
263	    io->pci_lo + io->size_lo - 1) != 0) {
264		panic("uninorth_attach: failed to set up I/O rman");
265	}
266
267	if (nmem == 0) {
268		device_printf(dev, "can't find mem ranges\n");
269		return (ENXIO);
270	}
271	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
272	sc->sc_mem_rman.rm_descr = "UniNorth PCI Memory";
273	error = rman_init(&sc->sc_mem_rman);
274	if (error) {
275		device_printf(dev, "rman_init() failed. error = %d\n", error);
276		return (error);
277	}
278	for (i = 0; i < nmem; i++) {
279		error = rman_manage_region(&sc->sc_mem_rman, mem[i]->pci_lo,
280		    mem[i]->pci_lo + mem[i]->size_lo - 1);
281		if (error) {
282			device_printf(dev,
283			    "rman_manage_region() failed. error = %d\n", error);
284			return (error);
285		}
286	}
287
288	ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(cell_t));
289
290	device_add_child(dev, "pci", device_get_unit(dev));
291	return (bus_generic_attach(dev));
292}
293
294static int
295uninorth_maxslots(device_t dev)
296{
297
298	return (PCI_SLOTMAX);
299}
300
301static u_int32_t
302uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
303    int width)
304{
305	struct		uninorth_softc *sc;
306	vm_offset_t	caoff;
307
308	sc = device_get_softc(dev);
309	caoff = sc->sc_data + (reg & 0x07);
310
311	if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
312		switch (width) {
313		case 1:
314			return (in8rb(caoff));
315			break;
316		case 2:
317			return (in16rb(caoff));
318			break;
319		case 4:
320			return (in32rb(caoff));
321			break;
322		}
323	}
324
325	return (0xffffffff);
326}
327
328static void
329uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
330    u_int reg, u_int32_t val, int width)
331{
332	struct		uninorth_softc *sc;
333	vm_offset_t	caoff;
334
335	sc = device_get_softc(dev);
336	caoff = sc->sc_data + (reg & 0x07);
337
338	if (uninorth_enable_config(sc, bus, slot, func, reg)) {
339		switch (width) {
340		case 1:
341			out8rb(caoff, val);
342			break;
343		case 2:
344			out16rb(caoff, val);
345			break;
346		case 4:
347			out32rb(caoff, val);
348			break;
349		}
350	}
351}
352
353static int
354uninorth_route_interrupt(device_t bus, device_t dev, int pin)
355{
356	struct uninorth_softc *sc;
357	struct ofw_pci_register reg;
358	uint32_t pintr, mintr;
359	uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
360
361	sc = device_get_softc(bus);
362	pintr = pin;
363	if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
364	    sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
365	    maskbuf))
366		return (mintr);
367
368	/* Maybe it's a real interrupt, not an intpin */
369	if (pin > 4)
370		return (pin);
371
372	device_printf(bus, "could not route pin %d for device %d.%d\n",
373	    pin, pci_get_slot(dev), pci_get_function(dev));
374	return (PCI_INVALID_IRQ);
375}
376
377static int
378uninorth_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
379{
380	struct	uninorth_softc *sc;
381
382	sc = device_get_softc(dev);
383
384	switch (which) {
385	case PCIB_IVAR_DOMAIN:
386		*result = device_get_unit(dev);
387		return (0);
388	case PCIB_IVAR_BUS:
389		*result = sc->sc_bus;
390		return (0);
391	}
392
393	return (ENOENT);
394}
395
396static struct resource *
397uninorth_alloc_resource(device_t bus, device_t child, int type, int *rid,
398    u_long start, u_long end, u_long count, u_int flags)
399{
400	struct			uninorth_softc *sc;
401	struct			resource *rv;
402	struct			rman *rm;
403	int			needactivate;
404
405	needactivate = flags & RF_ACTIVE;
406	flags &= ~RF_ACTIVE;
407
408	sc = device_get_softc(bus);
409
410	switch (type) {
411	case SYS_RES_MEMORY:
412		rm = &sc->sc_mem_rman;
413		break;
414
415	case SYS_RES_IOPORT:
416		rm = &sc->sc_io_rman;
417		break;
418
419	case SYS_RES_IRQ:
420		return (bus_alloc_resource(bus, type, rid, start, end, count,
421		    flags));
422
423	default:
424		device_printf(bus, "unknown resource request from %s\n",
425		    device_get_nameunit(child));
426		return (NULL);
427	}
428
429	rv = rman_reserve_resource(rm, start, end, count, flags, child);
430	if (rv == NULL) {
431		device_printf(bus, "failed to reserve resource for %s\n",
432		    device_get_nameunit(child));
433		return (NULL);
434	}
435
436	rman_set_rid(rv, *rid);
437
438	if (needactivate) {
439		if (bus_activate_resource(child, type, *rid, rv) != 0) {
440			device_printf(bus,
441			    "failed to activate resource for %s\n",
442			    device_get_nameunit(child));
443			rman_release_resource(rv);
444			return (NULL);
445		}
446	}
447
448	return (rv);
449}
450
451static int
452uninorth_activate_resource(device_t bus, device_t child, int type, int rid,
453    struct resource *res)
454{
455	void	*p;
456	struct	uninorth_softc *sc;
457
458	sc = device_get_softc(bus);
459
460	if (type == SYS_RES_IRQ)
461		return (bus_activate_resource(bus, type, rid, res));
462
463	if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
464		vm_offset_t start;
465
466		start = (vm_offset_t)rman_get_start(res);
467		/*
468		 * For i/o-ports, convert the start address to the
469		 * uninorth PCI i/o window
470		 */
471		if (type == SYS_RES_IOPORT)
472			start += sc->sc_iostart;
473
474		if (bootverbose)
475			printf("uninorth mapdev: start %zx, len %ld\n", start,
476			    rman_get_size(res));
477
478		p = pmap_mapdev(start, (vm_size_t)rman_get_size(res));
479		if (p == NULL)
480			return (ENOMEM);
481		rman_set_virtual(res, p);
482		rman_set_bustag(res, &bs_le_tag);
483		rman_set_bushandle(res, (u_long)p);
484	}
485
486	return (rman_activate_resource(res));
487}
488
489static int
490uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
491    u_int func, u_int reg)
492{
493	uint32_t	cfgval;
494	uint32_t	pass;
495
496	if (resource_int_value(device_get_name(sc->sc_dev),
497	        device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
498		if (pass == slot)
499			return (0);
500	}
501
502	/*
503	 * Issue type 0 configuration space accesses for the root bus.
504	 *
505	 * NOTE: On U4, issue only type 1 accesses. There is a secret
506	 * PCI Express <-> PCI Express bridge not present in the device tree,
507	 * and we need to route all of our configuration space through it.
508	 */
509	if (sc->sc_bus == bus && sc->sc_ver < 4) {
510		/*
511		 * No slots less than 11 on the primary bus on U3 and lower
512		 */
513		if (slot < 11)
514			return (0);
515
516		cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
517	} else {
518		cfgval = (bus << 16) | (slot << 11) | (func << 8) |
519		    (reg & 0xfc) | 1;
520	}
521
522	/* Set extended register bits on U4 */
523	if (sc->sc_ver == 4)
524		cfgval |= (reg >> 8) << 28;
525
526	do {
527		out32rb(sc->sc_addr, cfgval);
528	} while (in32rb(sc->sc_addr) != cfgval);
529
530	return (1);
531}
532
533static phandle_t
534uninorth_get_node(device_t bus, device_t dev)
535{
536	struct uninorth_softc *sc;
537
538	sc = device_get_softc(bus);
539	/* We only have one child, the PCI bus, which needs our own node. */
540
541	return sc->sc_node;
542}
543
544