ata_kauai.c revision 183409 
1/*-
2 * Copyright 2004 by Peter Grehan. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 *    derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/powerpc/powermac/ata_kauai.c 183409 2008-09-27 15:13:44Z nwhitehorn $");
30
31/*
32 * Mac 'Kauai' PCI ATA controller
33 */
34#include "opt_ata.h"
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/bus.h>
40#include <sys/malloc.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <sys/ata.h>
49#include <dev/ata/ata-all.h>
50#include <ata_if.h>
51
52#include <dev/ofw/openfirm.h>
53#include <powerpc/ofw/ofw_pci.h>
54#include <machine/intr_machdep.h>
55
56#include <dev/pci/pcivar.h>
57#include <dev/pci/pcireg.h>
58
59#include "ata_dbdma.h"
60
61#define  ATA_KAUAI_REGOFFSET	0x2000
62#define  ATA_KAUAI_DBDMAOFFSET	0x1000
63
64/*
65 * Offset to alt-control register from base
66 */
67#define  ATA_KAUAI_ALTOFFSET    (ATA_KAUAI_REGOFFSET + 0x160)
68
69/*
70 * Define the gap between registers
71 */
72#define ATA_KAUAI_REGGAP        16
73
74/*
75 * PIO and DMA access registers
76 */
77#define PIO_CONFIG_REG	(ATA_KAUAI_REGOFFSET + 0x200)
78#define UDMA_CONFIG_REG	(ATA_KAUAI_REGOFFSET + 0x210)
79#define DMA_IRQ_REG	(ATA_KAUAI_REGOFFSET + 0x300)
80
81#define USE_DBDMA_IRQ	0
82
83/*
84 * Define the kauai pci bus attachment.
85 */
86static  int  ata_kauai_probe(device_t dev);
87static  int  ata_kauai_attach(device_t dev);
88static  void ata_kauai_setmode(device_t parent, device_t dev);
89static  int  ata_kauai_begin_transaction(struct ata_request *request);
90
91static device_method_t ata_kauai_methods[] = {
92        /* Device interface */
93	DEVMETHOD(device_probe,		ata_kauai_probe),
94	DEVMETHOD(device_attach,	ata_kauai_attach),
95	DEVMETHOD(device_detach,	bus_generic_detach),
96	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
97	DEVMETHOD(device_suspend,	bus_generic_suspend),
98	DEVMETHOD(device_resume,	bus_generic_resume),
99
100	/* ATA interface */
101	DEVMETHOD(ata_setmode,		ata_kauai_setmode),
102	{ 0, 0 }
103};
104
105struct ata_kauai_softc {
106	struct ata_dbdma_channel sc_ch;
107
108	struct resource *sc_memr;
109
110	int shasta;
111
112	uint32_t udmaconf[2];
113	uint32_t wdmaconf[2];
114	uint32_t pioconf[2];
115};
116
117static driver_t ata_kauai_driver = {
118	"ata",
119	ata_kauai_methods,
120	sizeof(struct ata_kauai_softc),
121};
122
123DRIVER_MODULE(ata, pci, ata_kauai_driver, ata_devclass, 0, 0);
124MODULE_DEPEND(ata, ata, 1, 1, 1);
125
126/*
127 * PCI ID search table
128 */
129static struct kauai_pci_dev {
130        u_int32_t  kpd_devid;
131        char    *kpd_desc;
132} kauai_pci_devlist[] = {
133        { 0x0033106b, "Uninorth2 Kauai ATA Controller" },
134        { 0x003b106b, "Intrepid Kauai ATA Controller" },
135        { 0x0043106b, "K2 Kauai ATA Controller" },
136        { 0x0050106b, "Shasta Kauai ATA Controller" },
137        { 0x0069106b, "Intrepid-2 Kauai ATA Controller" },
138        { 0, NULL }
139};
140
141/*
142 * IDE transfer timings
143 */
144#define KAUAI_PIO_MASK	0xff000fff
145#define KAUAI_DMA_MASK	0x00fff000
146#define KAUAI_UDMA_MASK	0x0000ffff
147
148static const u_int pio_timing_kauai[] = {
149	0x08000a92,	/* PIO0 */
150	0x0800060f,	/* PIO1 */
151	0x0800038b,	/* PIO2 */
152	0x05000249,	/* PIO3 */
153	0x04000148	/* PIO4 */
154};
155static const u_int pio_timing_shasta[] = {
156	0x0a000c97,	/* PIO0 */
157	0x07000712,	/* PIO1 */
158	0x040003cd,	/* PIO2 */
159	0x0400028b,	/* PIO3 */
160	0x0400010a	/* PIO4 */
161};
162
163static const u_int dma_timing_kauai[] = {
164        0x00618000,	/* WDMA0 */
165        0x00209000,	/* WDMA1 */
166        0x00148000	/* WDMA2 */
167};
168static const u_int dma_timing_shasta[] = {
169        0x00820800,	/* WDMA0 */
170        0x0028b000,	/* WDMA1 */
171        0x001ca000	/* WDMA2 */
172};
173
174static const u_int udma_timing_kauai[] = {
175        0x000070c1,	/* UDMA0 */
176        0x00005d81,	/* UDMA1 */
177        0x00004a61,	/* UDMA2 */
178        0x00003a51,	/* UDMA3 */
179        0x00002a31,	/* UDMA4 */
180        0x00002921	/* UDMA5 */
181};
182static const u_int udma_timing_shasta[] = {
183        0x00035901,	/* UDMA0 */
184        0x000348b1,	/* UDMA1 */
185        0x00033881,	/* UDMA2 */
186        0x00033861,	/* UDMA3 */
187        0x00033841,	/* UDMA4 */
188        0x00033031,	/* UDMA5 */
189        0x00033021	/* UDMA6 */
190};
191
192static int
193ata_kauai_probe(device_t dev)
194{
195	struct ata_channel *ch;
196	struct ata_kauai_softc *sc;
197	u_long startp, countp;
198	u_int32_t devid;
199	phandle_t node;
200	char *compatstring = NULL;
201	int i, found, rid, status;
202
203	found = 0;
204	devid = pci_get_devid(dev);
205        for (i = 0; kauai_pci_devlist[i].kpd_desc != NULL; i++) {
206                if (devid == kauai_pci_devlist[i].kpd_devid) {
207			found = 1;
208                        device_set_desc(dev, kauai_pci_devlist[i].kpd_desc);
209		}
210	}
211
212	if (!found)
213		return (ENXIO);
214
215	node = ofw_pci_find_node(dev);
216	sc = device_get_softc(dev);
217	bzero(sc, sizeof(struct ata_kauai_softc));
218	ch = &sc->sc_ch.sc_ch;
219
220	OF_getprop_alloc(node, "compatible", 1, (void **)&compatstring);
221	if (strcmp(compatstring,"shasta-ata") == 0)
222		sc->shasta = 1;
223
224	free(compatstring, M_OFWPROP);
225
226
227	/*
228	 * This device seems to ignore writes to the interrupt
229	 * config register, resulting in interrupt resources
230	 * not being attached. If this is the case, use
231	 * Open Firmware to determine the irq, and then attach
232	 * the resource. This allows the ATA common code to
233	 * allocate the irq.
234	 */
235	status = bus_get_resource(dev, SYS_RES_IRQ, 0, &startp, &countp);
236	if (status == ENOENT) {
237		int *irq;
238		phandle_t iparent;
239		int icells, nintr, i;
240
241		/*
242		 * Horrible hack to handle Kauai devices that have their IRQs
243		 * set up in an utterly wrong way
244		 */
245		if (!sc->shasta)
246			bus_set_resource(dev, SYS_RES_IRQ, 0, 39, 1);
247
248		/*
249		 * For the rest of the interrupts, and the main Shasta
250		 * interrupt, get the IRQs from firmware.
251		 */
252		if (OF_getprop(node, "interrupt-parent", &iparent,
253		    sizeof(iparent)) == sizeof(iparent)) {
254			OF_getprop(iparent, "#interrupt-cells", &icells,
255			    sizeof(icells)) ;
256		}
257
258		nintr = OF_getprop_alloc(node, "interrupts", sizeof(*irq),
259		    (void **)&irq);
260
261		for (i = 0; i < nintr; i += icells)
262			bus_set_resource(dev, SYS_RES_IRQ,
263			    i/icells + !sc->shasta, irq[i], 1);
264
265		free(irq, M_OFWPROP);
266	}
267
268
269        rid = PCIR_BARS;
270	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
271	    RF_ACTIVE);
272        if (sc->sc_memr == NULL) {
273                device_printf(dev, "could not allocate memory\n");
274                return (ENXIO);
275        }
276
277	/*
278	 * Set up the resource vectors
279	 */
280        for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
281                ch->r_io[i].res = sc->sc_memr;
282                ch->r_io[i].offset = i*ATA_KAUAI_REGGAP + ATA_KAUAI_REGOFFSET;
283        }
284        ch->r_io[ATA_CONTROL].res = sc->sc_memr;
285        ch->r_io[ATA_CONTROL].offset = ATA_KAUAI_ALTOFFSET;
286	ata_default_registers(dev);
287
288        ch->unit = 0;
289        ch->flags |= ATA_USE_16BIT;
290	ata_generic_hw(dev);
291
292        return (ata_probe(dev));
293}
294
295#if USE_DBDMA_IRQ
296static int
297ata_kauai_dma_interrupt(struct ata_kauai_softc *sc)
298{
299	/* Clear the DMA interrupt bits */
300
301	bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000);
302
303	return ata_interrupt(sc);
304}
305#endif
306
307static int
308ata_kauai_attach(device_t dev)
309{
310	struct ata_kauai_softc *sc = device_get_softc(dev);
311#if USE_DBDMA_IRQ
312	int dbdma_irq_rid = 1;
313	struct resource *dbdma_irq;
314	void *cookie;
315#endif
316
317	pci_enable_busmaster(dev);
318
319	/* Init DMA engine */
320
321	sc->sc_ch.dbdma_rid = 1;
322	sc->sc_ch.dbdma_regs = sc->sc_memr;
323	sc->sc_ch.dbdma_offset = ATA_KAUAI_DBDMAOFFSET;
324
325	ata_dbdma_dmainit(dev);
326
327#if USE_DBDMA_IRQ
328	/* Bind to DBDMA interrupt as well */
329	if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
330	    &dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
331		bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
332		    (driver_intr_t *)ata_kauai_dma_interrupt, sc,&cookie);
333	}
334#endif
335
336	/* Set up initial mode */
337	if (sc->shasta)
338		sc->pioconf[0] = sc->pioconf[1] = pio_timing_shasta[4];
339	else
340		sc->pioconf[0] = sc->pioconf[1] = pio_timing_kauai[4];
341
342	sc->udmaconf[0] = sc->udmaconf[1] = 0;
343	sc->wdmaconf[0] = sc->wdmaconf[1] = 0;
344
345	bus_write_4(sc->sc_memr, PIO_CONFIG_REG, sc->pioconf[0]);
346
347	/* Magic FCR value from Apple */
348	bus_write_4(sc->sc_memr, 0, 0x00000007);
349
350	/* Set begin_transaction */
351	sc->sc_ch.sc_ch.hw.begin_transaction = ata_kauai_begin_transaction;
352
353	return ata_attach(dev);
354}
355
356static void
357ata_kauai_setmode(device_t parent, device_t dev)
358{
359	struct ata_device *atadev = device_get_softc(dev);
360	struct ata_kauai_softc *sc = device_get_softc(parent);
361	uint32_t mode;
362
363	mode = ata_limit_mode(dev,atadev->mode,
364	    (sc->shasta) ? ATA_UDMA6 : ATA_UDMA5);
365
366	if (ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
367		return;
368
369	atadev->mode = mode;
370
371	if (sc->shasta) {
372		switch (mode & ATA_DMA_MASK) {
373		    case ATA_UDMA0:
374			sc->udmaconf[atadev->unit]
375			    = udma_timing_shasta[mode & ATA_MODE_MASK];
376			break;
377		    case ATA_WDMA0:
378			sc->udmaconf[atadev->unit] = 0;
379			sc->wdmaconf[atadev->unit]
380			    = dma_timing_shasta[mode & ATA_MODE_MASK];
381			break;
382		    default:
383			sc->pioconf[atadev->unit]
384			    = pio_timing_shasta[(mode & ATA_MODE_MASK) -
385			    ATA_PIO0];
386			break;
387		}
388	} else {
389		switch (mode & ATA_DMA_MASK) {
390		    case ATA_UDMA0:
391			sc->udmaconf[atadev->unit]
392			    = udma_timing_kauai[mode & ATA_MODE_MASK];
393			break;
394		    case ATA_WDMA0:
395			sc->udmaconf[atadev->unit] = 0;
396			sc->wdmaconf[atadev->unit]
397			    = dma_timing_kauai[mode & ATA_MODE_MASK];
398			break;
399		    default:
400			sc->pioconf[atadev->unit]
401			    = pio_timing_kauai[(mode & ATA_MODE_MASK)
402			    - ATA_PIO0];
403			break;
404		}
405	}
406}
407
408static int
409ata_kauai_begin_transaction(struct ata_request *request)
410{
411	struct ata_device *atadev = device_get_softc(request->dev);
412	struct ata_kauai_softc *sc = device_get_softc(request->parent);
413
414	bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[atadev->unit]);
415	bus_write_4(sc->sc_memr, PIO_CONFIG_REG,
416	    sc->wdmaconf[atadev->unit] | sc->pioconf[atadev->unit]);
417
418	return ata_begin_transaction(request);
419}
420
421