1186227Sraj/*-
2186227Sraj * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3209908Sraj * Copyright 2006 by Juniper Networks.
4186227Sraj * All rights reserved.
5186227Sraj *
6186227Sraj * Redistribution and use in source and binary forms, with or without
7186227Sraj * modification, are permitted provided that the following conditions
8186227Sraj * are met:
9186227Sraj * 1. Redistributions of source code must retain the above copyright
10186227Sraj *    notice, this list of conditions and the following disclaimer.
11186227Sraj * 2. Redistributions in binary form must reproduce the above copyright
12186227Sraj *    notice, this list of conditions and the following disclaimer in the
13186227Sraj *    documentation and/or other materials provided with the distribution.
14186227Sraj *
15186227Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16186227Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17186227Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18186227Sraj * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19186227Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20186227Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21186227Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22186227Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23186227Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24186227Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25186227Sraj * SUCH DAMAGE.
26186227Sraj *
27186227Sraj * $FreeBSD$
28186227Sraj */
29186227Sraj
30186227Sraj#ifndef _MPC85XX_H_
31186227Sraj#define _MPC85XX_H_
32186227Sraj
33209908Sraj/*
34209908Sraj * Configuration control and status registers
35209908Sraj */
36209908Sraj#define	OCP85XX_CCSRBAR		(CCSRBAR_VA + 0x0)
37209908Sraj#define	OCP85XX_BPTR		(CCSRBAR_VA + 0x20)
38209908Sraj
39209908Sraj/*
40209908Sraj * E500 Coherency Module registers
41209908Sraj */
42209908Sraj#define	OCP85XX_EEBPCR		(CCSRBAR_VA + 0x1010)
43209908Sraj
44209908Sraj/*
45209908Sraj * Local access registers
46209908Sraj */
47209908Sraj#define	OCP85XX_LAWBAR(n)	(CCSRBAR_VA + 0xc08 + 0x20 * (n))
48209908Sraj#define	OCP85XX_LAWSR(n)	(CCSRBAR_VA + 0xc10 + 0x20 * (n))
49209908Sraj
50209908Sraj#define	OCP85XX_TGTIF_LBC	4
51209908Sraj#define	OCP85XX_TGTIF_RAM_INTL	11
52209908Sraj#define	OCP85XX_TGTIF_RIO	12
53209908Sraj#define	OCP85XX_TGTIF_RAM1	15
54209908Sraj#define	OCP85XX_TGTIF_RAM2	22
55209908Sraj
56209908Sraj/*
57209908Sraj * L2 cache registers
58209908Sraj */
59209908Sraj#define OCP85XX_L2CTL		(CCSRBAR_VA + 0x20000)
60209908Sraj
61209908Sraj/*
62209908Sraj * Power-On Reset configuration
63209908Sraj */
64209908Sraj#define	OCP85XX_PORDEVSR	(CCSRBAR_VA + 0xe000c)
65209908Sraj#define OCP85XX_PORDEVSR_IO_SEL	0x00780000
66209908Sraj#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
67209908Sraj
68209908Sraj#define	OCP85XX_PORDEVSR2	(CCSRBAR_VA + 0xe0014)
69209908Sraj
70209908Sraj/*
71209908Sraj * Status Registers.
72209908Sraj */
73209908Sraj#define	OCP85XX_RSTCR		(CCSRBAR_VA + 0xe00b0)
74209908Sraj
75209908Sraj/*
76209908Sraj * Prototypes.
77209908Sraj */
78186227Srajuint32_t ccsr_read4(uintptr_t addr);
79186227Srajvoid ccsr_write4(uintptr_t addr, uint32_t val);
80186288Srajint law_enable(int trgt, u_long addr, u_long size);
81186288Srajint law_disable(int trgt, u_long addr, u_long size);
82189757Srajint law_getmax(void);
83209908Srajint law_pci_target(struct resource *, int *, int *);
84186227Sraj
85186227Sraj#endif /* _MPC85XX_H_ */
86