1139825Simp/*- 286221Stmm * Copyright (c) 2009 Nathan Whitehorn 3181701Smarius * All rights reserved. 486221Stmm * 586221Stmm * Redistribution and use in source and binary forms, with or without 686221Stmm * modification, are permitted provided that the following conditions 786221Stmm * are met: 886221Stmm * 1. Redistributions of source code must retain the above copyright 986221Stmm * notice, this list of conditions and the following disclaimer. 1086221Stmm * 2. Redistributions in binary form must reproduce the above copyright 1186221Stmm * notice, this list of conditions and the following disclaimer in the 1286221Stmm * documentation and/or other materials provided with the distribution. 1386221Stmm * 1486221Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1586221Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1686221Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1786221Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1886221Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 1986221Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2086221Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2186221Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2286221Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2386221Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2486221Stmm * SUCH DAMAGE. 2586221Stmm */ 2686221Stmm 2786221Stmm#include <sys/cdefs.h> 2886221Stmm__FBSDID("$FreeBSD$"); 2986221Stmm 3086221Stmm#include <sys/param.h> 3186221Stmm#include <sys/systm.h> 3286221Stmm#include <sys/bus.h> 3386221Stmm#include <sys/cpu.h> 3486221Stmm#include <sys/kernel.h> 3586221Stmm#include <sys/module.h> 3686221Stmm 3786221Stmm#include "cpufreq_if.h" 3886221Stmm 3986221Stmmstruct dfs_softc { 4086221Stmm device_t dev; 4186221Stmm int dfs4; 4286221Stmm}; 4386221Stmm 4486221Stmmstatic void dfs_identify(driver_t *driver, device_t parent); 4586221Stmmstatic int dfs_probe(device_t dev); 46181701Smariusstatic int dfs_attach(device_t dev); 4786221Stmmstatic int dfs_settings(device_t dev, struct cf_setting *sets, int *count); 48112399Sjakestatic int dfs_set(device_t dev, const struct cf_setting *set); 49112399Sjakestatic int dfs_get(device_t dev, struct cf_setting *set); 50112399Sjakestatic int dfs_type(device_t dev, int *type); 51112399Sjake 52211049Smariusstatic device_method_t dfs_methods[] = { 53112399Sjake /* Device interface */ 5486221Stmm DEVMETHOD(device_identify, dfs_identify), 5597001Sjake DEVMETHOD(device_probe, dfs_probe), 5697001Sjake DEVMETHOD(device_attach, dfs_attach), 5797001Sjake 5897001Sjake /* cpufreq interface */ 5997001Sjake DEVMETHOD(cpufreq_drv_set, dfs_set), 6097001Sjake DEVMETHOD(cpufreq_drv_get, dfs_get), 6197001Sjake DEVMETHOD(cpufreq_drv_type, dfs_type), 6297001Sjake DEVMETHOD(cpufreq_drv_settings, dfs_settings), 6397001Sjake 6497001Sjake {0, 0} 6597001Sjake}; 6697001Sjake 6797001Sjakestatic driver_t dfs_driver = { 6897001Sjake "dfs", 6997001Sjake dfs_methods, 7097001Sjake sizeof(struct dfs_softc) 7197001Sjake}; 7297001Sjake 73166105Smariusstatic devclass_t dfs_devclass; 74166105SmariusDRIVER_MODULE(dfs, cpu, dfs_driver, dfs_devclass, 0, 0); 7586221Stmm 76181701Smarius/* 7786221Stmm * Bits of the HID1 register to enable DFS. See page 2-24 of "MPC7450 7886221Stmm * RISC Microprocessor Family Reference Manual", rev. 5. 79181701Smarius */ 80181701Smarius 81181701Smarius#define HID1_DFS2 (1UL << 22) 82181701Smarius#define HID1_DFS4 (1UL << 23) 83181701Smarius 84181701Smariusstatic void 8597001Sjakedfs_identify(driver_t *driver, device_t parent) 86181701Smarius{ 8797001Sjake uint16_t vers; 8886221Stmm vers = mfpvr() >> 16; 8986221Stmm 90117707Sjake /* Check for an MPC 7447A or 7448 CPU */ 91117707Sjake switch (vers) { 92211049Smarius case MPC7447A: 93211049Smarius case MPC7448: 94182689Smarius break; 95182689Smarius default: 96204152Smarius return; 97122464Sjake } 98113238Sjake 99113238Sjake /* Make sure we're not being doubly invoked. */ 100112399Sjake if (device_find_child(parent, "dfs", -1) != NULL) 101182689Smarius return; 102112399Sjake 103122464Sjake /* 104122464Sjake * We attach a child for every CPU since settings need to 105113238Sjake * be performed on every CPU in the SMP case. 106113238Sjake */ 107122464Sjake if (BUS_ADD_CHILD(parent, 10, "dfs", -1) == NULL) 108122464Sjake device_printf(parent, "add dfs child failed\n"); 109122464Sjake} 110113238Sjake 111113238Sjakestatic int 112112399Sjakedfs_probe(device_t dev) 113223719Smarius{ 114223719Smarius if (resource_disabled("dfs", 0)) 115223719Smarius return (ENXIO); 116223719Smarius 117223719Smarius device_set_desc(dev, "Dynamic Frequency Switching"); 118122464Sjake return (0); 119122464Sjake} 120112399Sjake 121112399Sjakestatic int 122112399Sjakedfs_attach(device_t dev) 123166105Smarius{ 124117707Sjake struct dfs_softc *sc; 125166105Smarius uint16_t vers; 126166105Smarius 127166105Smarius sc = device_get_softc(dev); 128 sc->dev = dev; 129 sc->dfs4 = 0; 130 vers = mfpvr() >> 16; 131 132 /* The 7448 supports divide-by-four as well */ 133 if (vers == MPC7448) 134 sc->dfs4 = 1; 135 136 cpufreq_register(dev); 137 return (0); 138} 139 140static int 141dfs_settings(device_t dev, struct cf_setting *sets, int *count) 142{ 143 struct dfs_softc *sc; 144 int states; 145 146 sc = device_get_softc(dev); 147 states = sc->dfs4 ? 3 : 2; 148 if (sets == NULL || count == NULL) 149 return (EINVAL); 150 if (*count < states) 151 return (E2BIG); 152 153 /* Return a list of valid settings for this driver. */ 154 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * states); 155 156 sets[0].freq = 10000; sets[0].dev = dev; 157 sets[1].freq = 5000; sets[1].dev = dev; 158 if (sc->dfs4) 159 sets[2].freq = 2500; sets[2].dev = dev; 160 *count = states; 161 162 return (0); 163} 164 165static int 166dfs_set(device_t dev, const struct cf_setting *set) 167{ 168 register_t hid1; 169 170 if (set == NULL) 171 return (EINVAL); 172 173 hid1 = mfspr(SPR_HID1); 174 hid1 &= ~(HID1_DFS2 | HID1_DFS4); 175 176 if (set->freq == 5000) 177 hid1 |= HID1_DFS2; 178 else if (set->freq == 2500) 179 hid1 |= HID1_DFS4; 180 181 /* 182 * Now set the HID1 register with new values. Calling sequence 183 * taken from page 2-26 of the MPC7450 family CPU manual. 184 */ 185 186 powerpc_sync(); 187 mtspr(SPR_HID1, hid1); 188 powerpc_sync(); isync(); 189 190 return (0); 191} 192 193static int 194dfs_get(device_t dev, struct cf_setting *set) 195{ 196 struct dfs_softc *sc; 197 register_t hid1; 198 199 if (set == NULL) 200 return (EINVAL); 201 sc = device_get_softc(dev); 202 203 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 204 205 hid1 = mfspr(SPR_HID1); 206 207 set->freq = 10000; 208 if (hid1 & HID1_DFS2) 209 set->freq = 5000; 210 else if (sc->dfs4 && (hid1 & HID1_DFS4)) 211 set->freq = 2500; 212 213 set->dev = dev; 214 215 return (0); 216} 217 218static int 219dfs_type(device_t dev, int *type) 220{ 221 222 if (type == NULL) 223 return (EINVAL); 224 225 *type = CPUFREQ_TYPE_RELATIVE; 226 return (0); 227} 228 229