pmap.c revision 254667
1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 254667 2013-08-22 18:12:24Z kib $"); 53 54#include <sys/param.h> 55#include <sys/malloc.h> 56#include <sys/ktr.h> 57#include <sys/proc.h> 58#include <sys/user.h> 59#include <sys/queue.h> 60#include <sys/systm.h> 61#include <sys/kernel.h> 62#include <sys/linker.h> 63#include <sys/msgbuf.h> 64#include <sys/lock.h> 65#include <sys/mutex.h> 66#include <sys/rwlock.h> 67#include <sys/sched.h> 68#include <sys/smp.h> 69#include <sys/vmmeter.h> 70 71#include <vm/vm.h> 72#include <vm/vm_page.h> 73#include <vm/vm_kern.h> 74#include <vm/vm_pageout.h> 75#include <vm/vm_extern.h> 76#include <vm/vm_object.h> 77#include <vm/vm_param.h> 78#include <vm/vm_map.h> 79#include <vm/vm_pager.h> 80#include <vm/uma.h> 81 82#include <machine/cpu.h> 83#include <machine/pcb.h> 84#include <machine/platform.h> 85 86#include <machine/tlb.h> 87#include <machine/spr.h> 88#include <machine/md_var.h> 89#include <machine/mmuvar.h> 90#include <machine/pmap.h> 91#include <machine/pte.h> 92 93#include "mmu_if.h" 94 95#ifdef DEBUG 96#define debugf(fmt, args...) printf(fmt, ##args) 97#else 98#define debugf(fmt, args...) 99#endif 100 101#define TODO panic("%s: not implemented", __func__); 102 103extern struct mtx sched_lock; 104 105extern int dumpsys_minidump; 106 107extern unsigned char _etext[]; 108extern unsigned char _end[]; 109 110extern uint32_t *bootinfo; 111 112#ifdef SMP 113extern uint32_t bp_ntlb1s; 114#endif 115 116vm_paddr_t ccsrbar_pa; 117vm_paddr_t kernload; 118vm_offset_t kernstart; 119vm_size_t kernsize; 120 121/* Message buffer and tables. */ 122static vm_offset_t data_start; 123static vm_size_t data_end; 124 125/* Phys/avail memory regions. */ 126static struct mem_region *availmem_regions; 127static int availmem_regions_sz; 128static struct mem_region *physmem_regions; 129static int physmem_regions_sz; 130 131/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 132static vm_offset_t zero_page_va; 133static struct mtx zero_page_mutex; 134 135static struct mtx tlbivax_mutex; 136 137/* 138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 139 * by idle thred only, no lock required. 140 */ 141static vm_offset_t zero_page_idle_va; 142 143/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 144static vm_offset_t copy_page_src_va; 145static vm_offset_t copy_page_dst_va; 146static struct mtx copy_page_mutex; 147 148/**************************************************************************/ 149/* PMAP */ 150/**************************************************************************/ 151 152static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 153 vm_prot_t, boolean_t); 154 155unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 156unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 157 158/* 159 * If user pmap is processed with mmu_booke_remove and the resident count 160 * drops to 0, there are no more pages to remove, so we need not continue. 161 */ 162#define PMAP_REMOVE_DONE(pmap) \ 163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 164 165extern void tid_flush(tlbtid_t); 166 167/**************************************************************************/ 168/* TLB and TID handling */ 169/**************************************************************************/ 170 171/* Translation ID busy table */ 172static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 173 174/* 175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 176 * core revisions and should be read from h/w registers during early config. 177 */ 178uint32_t tlb0_entries; 179uint32_t tlb0_ways; 180uint32_t tlb0_entries_per_way; 181 182#define TLB0_ENTRIES (tlb0_entries) 183#define TLB0_WAYS (tlb0_ways) 184#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186#define TLB1_ENTRIES 16 187 188/* In-ram copy of the TLB1 */ 189static tlb_entry_t tlb1[TLB1_ENTRIES]; 190 191/* Next free entry in the TLB1 */ 192static unsigned int tlb1_idx; 193 194static tlbtid_t tid_alloc(struct pmap *); 195 196static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 197 198static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 199static void tlb1_write_entry(unsigned int); 200static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 201static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 202 203static vm_size_t tsize2size(unsigned int); 204static unsigned int size2tsize(vm_size_t); 205static unsigned int ilog2(unsigned int); 206 207static void set_mas4_defaults(void); 208 209static inline void tlb0_flush_entry(vm_offset_t); 210static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 211 212/**************************************************************************/ 213/* Page table management */ 214/**************************************************************************/ 215 216static struct rwlock_padalign pvh_global_lock; 217 218/* Data for the pv entry allocation mechanism */ 219static uma_zone_t pvzone; 220static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 221 222#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 223 224#ifndef PMAP_SHPGPERPROC 225#define PMAP_SHPGPERPROC 200 226#endif 227 228static void ptbl_init(void); 229static struct ptbl_buf *ptbl_buf_alloc(void); 230static void ptbl_buf_free(struct ptbl_buf *); 231static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 232 233static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 234static void ptbl_free(mmu_t, pmap_t, unsigned int); 235static void ptbl_hold(mmu_t, pmap_t, unsigned int); 236static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 237 238static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 239static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 240static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 241static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 242 243static pv_entry_t pv_alloc(void); 244static void pv_free(pv_entry_t); 245static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 246static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 247 248/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 249#define PTBL_BUFS (128 * 16) 250 251struct ptbl_buf { 252 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 253 vm_offset_t kva; /* va of mapping */ 254}; 255 256/* ptbl free list and a lock used for access synchronization. */ 257static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 258static struct mtx ptbl_buf_freelist_lock; 259 260/* Base address of kva space allocated fot ptbl bufs. */ 261static vm_offset_t ptbl_buf_pool_vabase; 262 263/* Pointer to ptbl_buf structures. */ 264static struct ptbl_buf *ptbl_bufs; 265 266void pmap_bootstrap_ap(volatile uint32_t *); 267 268/* 269 * Kernel MMU interface 270 */ 271static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 272static void mmu_booke_clear_modify(mmu_t, vm_page_t); 273static void mmu_booke_clear_reference(mmu_t, vm_page_t); 274static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 275 vm_size_t, vm_offset_t); 276static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 277static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 278 vm_offset_t, vm_page_t *, vm_offset_t, int); 279static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 280 vm_prot_t, boolean_t); 281static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 282 vm_page_t, vm_prot_t); 283static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 284 vm_prot_t); 285static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 286static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 287 vm_prot_t); 288static void mmu_booke_init(mmu_t); 289static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 290static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 291static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 292static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 293static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 294 int); 295static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 296 vm_paddr_t *); 297static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 298 vm_object_t, vm_pindex_t, vm_size_t); 299static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 300static void mmu_booke_page_init(mmu_t, vm_page_t); 301static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 302static void mmu_booke_pinit(mmu_t, pmap_t); 303static void mmu_booke_pinit0(mmu_t, pmap_t); 304static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 305 vm_prot_t); 306static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 307static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 308static void mmu_booke_release(mmu_t, pmap_t); 309static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 310static void mmu_booke_remove_all(mmu_t, vm_page_t); 311static void mmu_booke_remove_write(mmu_t, vm_page_t); 312static void mmu_booke_zero_page(mmu_t, vm_page_t); 313static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 314static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 315static void mmu_booke_activate(mmu_t, struct thread *); 316static void mmu_booke_deactivate(mmu_t, struct thread *); 317static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 318static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 319static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 320static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 321static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 322static void mmu_booke_kremove(mmu_t, vm_offset_t); 323static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 324static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 325 vm_size_t); 326static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 327 vm_size_t, vm_size_t *); 328static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 329 vm_size_t, vm_offset_t); 330static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 331 332static mmu_method_t mmu_booke_methods[] = { 333 /* pmap dispatcher interface */ 334 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 335 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 336 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 337 MMUMETHOD(mmu_copy, mmu_booke_copy), 338 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 339 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 340 MMUMETHOD(mmu_enter, mmu_booke_enter), 341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 343 MMUMETHOD(mmu_extract, mmu_booke_extract), 344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 345 MMUMETHOD(mmu_init, mmu_booke_init), 346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 350 MMUMETHOD(mmu_map, mmu_booke_map), 351 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 354 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 356 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 358 MMUMETHOD(mmu_protect, mmu_booke_protect), 359 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 360 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 361 MMUMETHOD(mmu_release, mmu_booke_release), 362 MMUMETHOD(mmu_remove, mmu_booke_remove), 363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 369 MMUMETHOD(mmu_activate, mmu_booke_activate), 370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 377 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 378/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 380 381 /* dumpsys() support */ 382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 385 386 { 0, 0 } 387}; 388 389MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 390 391static inline void 392tlb_miss_lock(void) 393{ 394#ifdef SMP 395 struct pcpu *pc; 396 397 if (!smp_started) 398 return; 399 400 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 401 if (pc != pcpup) { 402 403 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 404 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 405 406 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 407 ("tlb_miss_lock: tried to lock self")); 408 409 tlb_lock(pc->pc_booke_tlb_lock); 410 411 CTR1(KTR_PMAP, "%s: locked", __func__); 412 } 413 } 414#endif 415} 416 417static inline void 418tlb_miss_unlock(void) 419{ 420#ifdef SMP 421 struct pcpu *pc; 422 423 if (!smp_started) 424 return; 425 426 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 427 if (pc != pcpup) { 428 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 429 __func__, pc->pc_cpuid); 430 431 tlb_unlock(pc->pc_booke_tlb_lock); 432 433 CTR1(KTR_PMAP, "%s: unlocked", __func__); 434 } 435 } 436#endif 437} 438 439/* Return number of entries in TLB0. */ 440static __inline void 441tlb0_get_tlbconf(void) 442{ 443 uint32_t tlb0_cfg; 444 445 tlb0_cfg = mfspr(SPR_TLB0CFG); 446 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 447 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 448 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 449} 450 451/* Initialize pool of kva ptbl buffers. */ 452static void 453ptbl_init(void) 454{ 455 int i; 456 457 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 458 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 459 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 460 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 461 462 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 463 TAILQ_INIT(&ptbl_buf_freelist); 464 465 for (i = 0; i < PTBL_BUFS; i++) { 466 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 467 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 468 } 469} 470 471/* Get a ptbl_buf from the freelist. */ 472static struct ptbl_buf * 473ptbl_buf_alloc(void) 474{ 475 struct ptbl_buf *buf; 476 477 mtx_lock(&ptbl_buf_freelist_lock); 478 buf = TAILQ_FIRST(&ptbl_buf_freelist); 479 if (buf != NULL) 480 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 481 mtx_unlock(&ptbl_buf_freelist_lock); 482 483 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 484 485 return (buf); 486} 487 488/* Return ptbl buff to free pool. */ 489static void 490ptbl_buf_free(struct ptbl_buf *buf) 491{ 492 493 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 494 495 mtx_lock(&ptbl_buf_freelist_lock); 496 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 497 mtx_unlock(&ptbl_buf_freelist_lock); 498} 499 500/* 501 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 502 */ 503static void 504ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 505{ 506 struct ptbl_buf *pbuf; 507 508 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 509 510 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 511 512 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 513 if (pbuf->kva == (vm_offset_t)ptbl) { 514 /* Remove from pmap ptbl buf list. */ 515 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 516 517 /* Free corresponding ptbl buf. */ 518 ptbl_buf_free(pbuf); 519 break; 520 } 521} 522 523/* Allocate page table. */ 524static pte_t * 525ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 526{ 527 vm_page_t mtbl[PTBL_PAGES]; 528 vm_page_t m; 529 struct ptbl_buf *pbuf; 530 unsigned int pidx; 531 pte_t *ptbl; 532 int i; 533 534 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 535 (pmap == kernel_pmap), pdir_idx); 536 537 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 538 ("ptbl_alloc: invalid pdir_idx")); 539 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 540 ("pte_alloc: valid ptbl entry exists!")); 541 542 pbuf = ptbl_buf_alloc(); 543 if (pbuf == NULL) 544 panic("pte_alloc: couldn't alloc kernel virtual memory"); 545 546 ptbl = (pte_t *)pbuf->kva; 547 548 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 549 550 /* Allocate ptbl pages, this will sleep! */ 551 for (i = 0; i < PTBL_PAGES; i++) { 552 pidx = (PTBL_PAGES * pdir_idx) + i; 553 while ((m = vm_page_alloc(NULL, pidx, 554 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 555 556 PMAP_UNLOCK(pmap); 557 rw_wunlock(&pvh_global_lock); 558 VM_WAIT; 559 rw_wlock(&pvh_global_lock); 560 PMAP_LOCK(pmap); 561 } 562 mtbl[i] = m; 563 } 564 565 /* Map allocated pages into kernel_pmap. */ 566 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 567 568 /* Zero whole ptbl. */ 569 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 570 571 /* Add pbuf to the pmap ptbl bufs list. */ 572 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 573 574 return (ptbl); 575} 576 577/* Free ptbl pages and invalidate pdir entry. */ 578static void 579ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 580{ 581 pte_t *ptbl; 582 vm_paddr_t pa; 583 vm_offset_t va; 584 vm_page_t m; 585 int i; 586 587 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 588 (pmap == kernel_pmap), pdir_idx); 589 590 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 591 ("ptbl_free: invalid pdir_idx")); 592 593 ptbl = pmap->pm_pdir[pdir_idx]; 594 595 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 596 597 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 598 599 /* 600 * Invalidate the pdir entry as soon as possible, so that other CPUs 601 * don't attempt to look up the page tables we are releasing. 602 */ 603 mtx_lock_spin(&tlbivax_mutex); 604 tlb_miss_lock(); 605 606 pmap->pm_pdir[pdir_idx] = NULL; 607 608 tlb_miss_unlock(); 609 mtx_unlock_spin(&tlbivax_mutex); 610 611 for (i = 0; i < PTBL_PAGES; i++) { 612 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 613 pa = pte_vatopa(mmu, kernel_pmap, va); 614 m = PHYS_TO_VM_PAGE(pa); 615 vm_page_free_zero(m); 616 atomic_subtract_int(&cnt.v_wire_count, 1); 617 mmu_booke_kremove(mmu, va); 618 } 619 620 ptbl_free_pmap_ptbl(pmap, ptbl); 621} 622 623/* 624 * Decrement ptbl pages hold count and attempt to free ptbl pages. 625 * Called when removing pte entry from ptbl. 626 * 627 * Return 1 if ptbl pages were freed. 628 */ 629static int 630ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 631{ 632 pte_t *ptbl; 633 vm_paddr_t pa; 634 vm_page_t m; 635 int i; 636 637 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 638 (pmap == kernel_pmap), pdir_idx); 639 640 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 641 ("ptbl_unhold: invalid pdir_idx")); 642 KASSERT((pmap != kernel_pmap), 643 ("ptbl_unhold: unholding kernel ptbl!")); 644 645 ptbl = pmap->pm_pdir[pdir_idx]; 646 647 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 648 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 649 ("ptbl_unhold: non kva ptbl")); 650 651 /* decrement hold count */ 652 for (i = 0; i < PTBL_PAGES; i++) { 653 pa = pte_vatopa(mmu, kernel_pmap, 654 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 655 m = PHYS_TO_VM_PAGE(pa); 656 m->wire_count--; 657 } 658 659 /* 660 * Free ptbl pages if there are no pte etries in this ptbl. 661 * wire_count has the same value for all ptbl pages, so check the last 662 * page. 663 */ 664 if (m->wire_count == 0) { 665 ptbl_free(mmu, pmap, pdir_idx); 666 667 //debugf("ptbl_unhold: e (freed ptbl)\n"); 668 return (1); 669 } 670 671 return (0); 672} 673 674/* 675 * Increment hold count for ptbl pages. This routine is used when a new pte 676 * entry is being inserted into the ptbl. 677 */ 678static void 679ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 680{ 681 vm_paddr_t pa; 682 pte_t *ptbl; 683 vm_page_t m; 684 int i; 685 686 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 687 pdir_idx); 688 689 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 690 ("ptbl_hold: invalid pdir_idx")); 691 KASSERT((pmap != kernel_pmap), 692 ("ptbl_hold: holding kernel ptbl!")); 693 694 ptbl = pmap->pm_pdir[pdir_idx]; 695 696 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 697 698 for (i = 0; i < PTBL_PAGES; i++) { 699 pa = pte_vatopa(mmu, kernel_pmap, 700 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 701 m = PHYS_TO_VM_PAGE(pa); 702 m->wire_count++; 703 } 704} 705 706/* Allocate pv_entry structure. */ 707pv_entry_t 708pv_alloc(void) 709{ 710 pv_entry_t pv; 711 712 pv_entry_count++; 713 if (pv_entry_count > pv_entry_high_water) 714 pagedaemon_wakeup(); 715 pv = uma_zalloc(pvzone, M_NOWAIT); 716 717 return (pv); 718} 719 720/* Free pv_entry structure. */ 721static __inline void 722pv_free(pv_entry_t pve) 723{ 724 725 pv_entry_count--; 726 uma_zfree(pvzone, pve); 727} 728 729 730/* Allocate and initialize pv_entry structure. */ 731static void 732pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 733{ 734 pv_entry_t pve; 735 736 //int su = (pmap == kernel_pmap); 737 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 738 // (u_int32_t)pmap, va, (u_int32_t)m); 739 740 pve = pv_alloc(); 741 if (pve == NULL) 742 panic("pv_insert: no pv entries!"); 743 744 pve->pv_pmap = pmap; 745 pve->pv_va = va; 746 747 /* add to pv_list */ 748 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 749 rw_assert(&pvh_global_lock, RA_WLOCKED); 750 751 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 752 753 //debugf("pv_insert: e\n"); 754} 755 756/* Destroy pv entry. */ 757static void 758pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 759{ 760 pv_entry_t pve; 761 762 //int su = (pmap == kernel_pmap); 763 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 764 765 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 766 rw_assert(&pvh_global_lock, RA_WLOCKED); 767 768 /* find pv entry */ 769 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 770 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 771 /* remove from pv_list */ 772 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 773 if (TAILQ_EMPTY(&m->md.pv_list)) 774 vm_page_aflag_clear(m, PGA_WRITEABLE); 775 776 /* free pv entry struct */ 777 pv_free(pve); 778 break; 779 } 780 } 781 782 //debugf("pv_remove: e\n"); 783} 784 785/* 786 * Clean pte entry, try to free page table page if requested. 787 * 788 * Return 1 if ptbl pages were freed, otherwise return 0. 789 */ 790static int 791pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 792{ 793 unsigned int pdir_idx = PDIR_IDX(va); 794 unsigned int ptbl_idx = PTBL_IDX(va); 795 vm_page_t m; 796 pte_t *ptbl; 797 pte_t *pte; 798 799 //int su = (pmap == kernel_pmap); 800 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 801 // su, (u_int32_t)pmap, va, flags); 802 803 ptbl = pmap->pm_pdir[pdir_idx]; 804 KASSERT(ptbl, ("pte_remove: null ptbl")); 805 806 pte = &ptbl[ptbl_idx]; 807 808 if (pte == NULL || !PTE_ISVALID(pte)) 809 return (0); 810 811 if (PTE_ISWIRED(pte)) 812 pmap->pm_stats.wired_count--; 813 814 /* Handle managed entry. */ 815 if (PTE_ISMANAGED(pte)) { 816 /* Get vm_page_t for mapped pte. */ 817 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 818 819 if (PTE_ISMODIFIED(pte)) 820 vm_page_dirty(m); 821 822 if (PTE_ISREFERENCED(pte)) 823 vm_page_aflag_set(m, PGA_REFERENCED); 824 825 pv_remove(pmap, va, m); 826 } 827 828 mtx_lock_spin(&tlbivax_mutex); 829 tlb_miss_lock(); 830 831 tlb0_flush_entry(va); 832 pte->flags = 0; 833 pte->rpn = 0; 834 835 tlb_miss_unlock(); 836 mtx_unlock_spin(&tlbivax_mutex); 837 838 pmap->pm_stats.resident_count--; 839 840 if (flags & PTBL_UNHOLD) { 841 //debugf("pte_remove: e (unhold)\n"); 842 return (ptbl_unhold(mmu, pmap, pdir_idx)); 843 } 844 845 //debugf("pte_remove: e\n"); 846 return (0); 847} 848 849/* 850 * Insert PTE for a given page and virtual address. 851 */ 852static void 853pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 854{ 855 unsigned int pdir_idx = PDIR_IDX(va); 856 unsigned int ptbl_idx = PTBL_IDX(va); 857 pte_t *ptbl, *pte; 858 859 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 860 pmap == kernel_pmap, pmap, va); 861 862 /* Get the page table pointer. */ 863 ptbl = pmap->pm_pdir[pdir_idx]; 864 865 if (ptbl == NULL) { 866 /* Allocate page table pages. */ 867 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 868 } else { 869 /* 870 * Check if there is valid mapping for requested 871 * va, if there is, remove it. 872 */ 873 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 874 if (PTE_ISVALID(pte)) { 875 pte_remove(mmu, pmap, va, PTBL_HOLD); 876 } else { 877 /* 878 * pte is not used, increment hold count 879 * for ptbl pages. 880 */ 881 if (pmap != kernel_pmap) 882 ptbl_hold(mmu, pmap, pdir_idx); 883 } 884 } 885 886 /* 887 * Insert pv_entry into pv_list for mapped page if part of managed 888 * memory. 889 */ 890 if ((m->oflags & VPO_UNMANAGED) == 0) { 891 flags |= PTE_MANAGED; 892 893 /* Create and insert pv entry. */ 894 pv_insert(pmap, va, m); 895 } 896 897 pmap->pm_stats.resident_count++; 898 899 mtx_lock_spin(&tlbivax_mutex); 900 tlb_miss_lock(); 901 902 tlb0_flush_entry(va); 903 if (pmap->pm_pdir[pdir_idx] == NULL) { 904 /* 905 * If we just allocated a new page table, hook it in 906 * the pdir. 907 */ 908 pmap->pm_pdir[pdir_idx] = ptbl; 909 } 910 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 911 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 912 pte->flags |= (PTE_VALID | flags); 913 914 tlb_miss_unlock(); 915 mtx_unlock_spin(&tlbivax_mutex); 916} 917 918/* Return the pa for the given pmap/va. */ 919static vm_paddr_t 920pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 921{ 922 vm_paddr_t pa = 0; 923 pte_t *pte; 924 925 pte = pte_find(mmu, pmap, va); 926 if ((pte != NULL) && PTE_ISVALID(pte)) 927 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 928 return (pa); 929} 930 931/* Get a pointer to a PTE in a page table. */ 932static pte_t * 933pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 934{ 935 unsigned int pdir_idx = PDIR_IDX(va); 936 unsigned int ptbl_idx = PTBL_IDX(va); 937 938 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 939 940 if (pmap->pm_pdir[pdir_idx]) 941 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 942 943 return (NULL); 944} 945 946/**************************************************************************/ 947/* PMAP related */ 948/**************************************************************************/ 949 950/* 951 * This is called during booke_init, before the system is really initialized. 952 */ 953static void 954mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 955{ 956 vm_offset_t phys_kernelend; 957 struct mem_region *mp, *mp1; 958 int cnt, i, j; 959 u_int s, e, sz; 960 u_int phys_avail_count; 961 vm_size_t physsz, hwphyssz, kstack0_sz; 962 vm_offset_t kernel_pdir, kstack0, va; 963 vm_paddr_t kstack0_phys; 964 void *dpcpu; 965 pte_t *pte; 966 967 debugf("mmu_booke_bootstrap: entered\n"); 968 969 /* Initialize invalidation mutex */ 970 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 971 972 /* Read TLB0 size and associativity. */ 973 tlb0_get_tlbconf(); 974 975 /* 976 * Align kernel start and end address (kernel image). 977 * Note that kernel end does not necessarily relate to kernsize. 978 * kernsize is the size of the kernel that is actually mapped. 979 * Also note that "start - 1" is deliberate. With SMP, the 980 * entry point is exactly a page from the actual load address. 981 * As such, trunc_page() has no effect and we're off by a page. 982 * Since we always have the ELF header between the load address 983 * and the entry point, we can safely subtract 1 to compensate. 984 */ 985 kernstart = trunc_page(start - 1); 986 data_start = round_page(kernelend); 987 data_end = data_start; 988 989 /* 990 * Addresses of preloaded modules (like file systems) use 991 * physical addresses. Make sure we relocate those into 992 * virtual addresses. 993 */ 994 preload_addr_relocate = kernstart - kernload; 995 996 /* Allocate the dynamic per-cpu area. */ 997 dpcpu = (void *)data_end; 998 data_end += DPCPU_SIZE; 999 1000 /* Allocate space for the message buffer. */ 1001 msgbufp = (struct msgbuf *)data_end; 1002 data_end += msgbufsize; 1003 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1004 data_end); 1005 1006 data_end = round_page(data_end); 1007 1008 /* Allocate space for ptbl_bufs. */ 1009 ptbl_bufs = (struct ptbl_buf *)data_end; 1010 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1011 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1012 data_end); 1013 1014 data_end = round_page(data_end); 1015 1016 /* Allocate PTE tables for kernel KVA. */ 1017 kernel_pdir = data_end; 1018 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1019 PDIR_SIZE - 1) / PDIR_SIZE; 1020 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1021 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1022 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1023 1024 debugf(" data_end: 0x%08x\n", data_end); 1025 if (data_end - kernstart > kernsize) { 1026 kernsize += tlb1_mapin_region(kernstart + kernsize, 1027 kernload + kernsize, (data_end - kernstart) - kernsize); 1028 } 1029 data_end = kernstart + kernsize; 1030 debugf(" updated data_end: 0x%08x\n", data_end); 1031 1032 /* 1033 * Clear the structures - note we can only do it safely after the 1034 * possible additional TLB1 translations are in place (above) so that 1035 * all range up to the currently calculated 'data_end' is covered. 1036 */ 1037 dpcpu_init(dpcpu, 0); 1038 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1039 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1040 1041 /*******************************************************/ 1042 /* Set the start and end of kva. */ 1043 /*******************************************************/ 1044 virtual_avail = round_page(data_end); 1045 virtual_end = VM_MAX_KERNEL_ADDRESS; 1046 1047 /* Allocate KVA space for page zero/copy operations. */ 1048 zero_page_va = virtual_avail; 1049 virtual_avail += PAGE_SIZE; 1050 zero_page_idle_va = virtual_avail; 1051 virtual_avail += PAGE_SIZE; 1052 copy_page_src_va = virtual_avail; 1053 virtual_avail += PAGE_SIZE; 1054 copy_page_dst_va = virtual_avail; 1055 virtual_avail += PAGE_SIZE; 1056 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1057 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1058 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1059 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1060 1061 /* Initialize page zero/copy mutexes. */ 1062 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1063 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1064 1065 /* Allocate KVA space for ptbl bufs. */ 1066 ptbl_buf_pool_vabase = virtual_avail; 1067 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1068 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1069 ptbl_buf_pool_vabase, virtual_avail); 1070 1071 /* Calculate corresponding physical addresses for the kernel region. */ 1072 phys_kernelend = kernload + kernsize; 1073 debugf("kernel image and allocated data:\n"); 1074 debugf(" kernload = 0x%08x\n", kernload); 1075 debugf(" kernstart = 0x%08x\n", kernstart); 1076 debugf(" kernsize = 0x%08x\n", kernsize); 1077 1078 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1079 panic("mmu_booke_bootstrap: phys_avail too small"); 1080 1081 /* 1082 * Remove kernel physical address range from avail regions list. Page 1083 * align all regions. Non-page aligned memory isn't very interesting 1084 * to us. Also, sort the entries for ascending addresses. 1085 */ 1086 1087 /* Retrieve phys/avail mem regions */ 1088 mem_regions(&physmem_regions, &physmem_regions_sz, 1089 &availmem_regions, &availmem_regions_sz); 1090 sz = 0; 1091 cnt = availmem_regions_sz; 1092 debugf("processing avail regions:\n"); 1093 for (mp = availmem_regions; mp->mr_size; mp++) { 1094 s = mp->mr_start; 1095 e = mp->mr_start + mp->mr_size; 1096 debugf(" %08x-%08x -> ", s, e); 1097 /* Check whether this region holds all of the kernel. */ 1098 if (s < kernload && e > phys_kernelend) { 1099 availmem_regions[cnt].mr_start = phys_kernelend; 1100 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1101 e = kernload; 1102 } 1103 /* Look whether this regions starts within the kernel. */ 1104 if (s >= kernload && s < phys_kernelend) { 1105 if (e <= phys_kernelend) 1106 goto empty; 1107 s = phys_kernelend; 1108 } 1109 /* Now look whether this region ends within the kernel. */ 1110 if (e > kernload && e <= phys_kernelend) { 1111 if (s >= kernload) 1112 goto empty; 1113 e = kernload; 1114 } 1115 /* Now page align the start and size of the region. */ 1116 s = round_page(s); 1117 e = trunc_page(e); 1118 if (e < s) 1119 e = s; 1120 sz = e - s; 1121 debugf("%08x-%08x = %x\n", s, e, sz); 1122 1123 /* Check whether some memory is left here. */ 1124 if (sz == 0) { 1125 empty: 1126 memmove(mp, mp + 1, 1127 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1128 cnt--; 1129 mp--; 1130 continue; 1131 } 1132 1133 /* Do an insertion sort. */ 1134 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1135 if (s < mp1->mr_start) 1136 break; 1137 if (mp1 < mp) { 1138 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1139 mp1->mr_start = s; 1140 mp1->mr_size = sz; 1141 } else { 1142 mp->mr_start = s; 1143 mp->mr_size = sz; 1144 } 1145 } 1146 availmem_regions_sz = cnt; 1147 1148 /*******************************************************/ 1149 /* Steal physical memory for kernel stack from the end */ 1150 /* of the first avail region */ 1151 /*******************************************************/ 1152 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1153 kstack0_phys = availmem_regions[0].mr_start + 1154 availmem_regions[0].mr_size; 1155 kstack0_phys -= kstack0_sz; 1156 availmem_regions[0].mr_size -= kstack0_sz; 1157 1158 /*******************************************************/ 1159 /* Fill in phys_avail table, based on availmem_regions */ 1160 /*******************************************************/ 1161 phys_avail_count = 0; 1162 physsz = 0; 1163 hwphyssz = 0; 1164 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1165 1166 debugf("fill in phys_avail:\n"); 1167 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1168 1169 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1170 availmem_regions[i].mr_start, 1171 availmem_regions[i].mr_start + 1172 availmem_regions[i].mr_size, 1173 availmem_regions[i].mr_size); 1174 1175 if (hwphyssz != 0 && 1176 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1177 debugf(" hw.physmem adjust\n"); 1178 if (physsz < hwphyssz) { 1179 phys_avail[j] = availmem_regions[i].mr_start; 1180 phys_avail[j + 1] = 1181 availmem_regions[i].mr_start + 1182 hwphyssz - physsz; 1183 physsz = hwphyssz; 1184 phys_avail_count++; 1185 } 1186 break; 1187 } 1188 1189 phys_avail[j] = availmem_regions[i].mr_start; 1190 phys_avail[j + 1] = availmem_regions[i].mr_start + 1191 availmem_regions[i].mr_size; 1192 phys_avail_count++; 1193 physsz += availmem_regions[i].mr_size; 1194 } 1195 physmem = btoc(physsz); 1196 1197 /* Calculate the last available physical address. */ 1198 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1199 ; 1200 Maxmem = powerpc_btop(phys_avail[i + 1]); 1201 1202 debugf("Maxmem = 0x%08lx\n", Maxmem); 1203 debugf("phys_avail_count = %d\n", phys_avail_count); 1204 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1205 physmem); 1206 1207 /*******************************************************/ 1208 /* Initialize (statically allocated) kernel pmap. */ 1209 /*******************************************************/ 1210 PMAP_LOCK_INIT(kernel_pmap); 1211 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1212 1213 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1214 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1215 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1216 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1217 1218 /* Initialize kernel pdir */ 1219 for (i = 0; i < kernel_ptbls; i++) 1220 kernel_pmap->pm_pdir[kptbl_min + i] = 1221 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1222 1223 for (i = 0; i < MAXCPU; i++) { 1224 kernel_pmap->pm_tid[i] = TID_KERNEL; 1225 1226 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1227 tidbusy[i][0] = kernel_pmap; 1228 } 1229 1230 /* 1231 * Fill in PTEs covering kernel code and data. They are not required 1232 * for address translation, as this area is covered by static TLB1 1233 * entries, but for pte_vatopa() to work correctly with kernel area 1234 * addresses. 1235 */ 1236 for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1237 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1238 pte->rpn = kernload + (va - kernstart); 1239 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1240 PTE_VALID; 1241 } 1242 /* Mark kernel_pmap active on all CPUs */ 1243 CPU_FILL(&kernel_pmap->pm_active); 1244 1245 /* 1246 * Initialize the global pv list lock. 1247 */ 1248 rw_init(&pvh_global_lock, "pmap pv global"); 1249 1250 /*******************************************************/ 1251 /* Final setup */ 1252 /*******************************************************/ 1253 1254 /* Enter kstack0 into kernel map, provide guard page */ 1255 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1256 thread0.td_kstack = kstack0; 1257 thread0.td_kstack_pages = KSTACK_PAGES; 1258 1259 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1260 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1261 kstack0_phys, kstack0_phys + kstack0_sz); 1262 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1263 1264 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1265 for (i = 0; i < KSTACK_PAGES; i++) { 1266 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1267 kstack0 += PAGE_SIZE; 1268 kstack0_phys += PAGE_SIZE; 1269 } 1270 1271 debugf("virtual_avail = %08x\n", virtual_avail); 1272 debugf("virtual_end = %08x\n", virtual_end); 1273 1274 debugf("mmu_booke_bootstrap: exit\n"); 1275} 1276 1277void 1278pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1279{ 1280 int i; 1281 1282 /* 1283 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1284 * have the snapshot of its contents in the s/w tlb1[] table, so use 1285 * these values directly to (re)program AP's TLB1 hardware. 1286 */ 1287 for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1288 /* Skip invalid entries */ 1289 if (!(tlb1[i].mas1 & MAS1_VALID)) 1290 continue; 1291 1292 tlb1_write_entry(i); 1293 } 1294 1295 set_mas4_defaults(); 1296} 1297 1298/* 1299 * Get the physical page address for the given pmap/virtual address. 1300 */ 1301static vm_paddr_t 1302mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1303{ 1304 vm_paddr_t pa; 1305 1306 PMAP_LOCK(pmap); 1307 pa = pte_vatopa(mmu, pmap, va); 1308 PMAP_UNLOCK(pmap); 1309 1310 return (pa); 1311} 1312 1313/* 1314 * Extract the physical page address associated with the given 1315 * kernel virtual address. 1316 */ 1317static vm_paddr_t 1318mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1319{ 1320 1321 return (pte_vatopa(mmu, kernel_pmap, va)); 1322} 1323 1324/* 1325 * Initialize the pmap module. 1326 * Called by vm_init, to initialize any structures that the pmap 1327 * system needs to map virtual memory. 1328 */ 1329static void 1330mmu_booke_init(mmu_t mmu) 1331{ 1332 int shpgperproc = PMAP_SHPGPERPROC; 1333 1334 /* 1335 * Initialize the address space (zone) for the pv entries. Set a 1336 * high water mark so that the system can recover from excessive 1337 * numbers of pv entries. 1338 */ 1339 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1340 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1341 1342 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1343 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1344 1345 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1346 pv_entry_high_water = 9 * (pv_entry_max / 10); 1347 1348 uma_zone_reserve_kva(pvzone, pv_entry_max); 1349 1350 /* Pre-fill pvzone with initial number of pv entries. */ 1351 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1352 1353 /* Initialize ptbl allocation. */ 1354 ptbl_init(); 1355} 1356 1357/* 1358 * Map a list of wired pages into kernel virtual address space. This is 1359 * intended for temporary mappings which do not need page modification or 1360 * references recorded. Existing mappings in the region are overwritten. 1361 */ 1362static void 1363mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1364{ 1365 vm_offset_t va; 1366 1367 va = sva; 1368 while (count-- > 0) { 1369 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1370 va += PAGE_SIZE; 1371 m++; 1372 } 1373} 1374 1375/* 1376 * Remove page mappings from kernel virtual address space. Intended for 1377 * temporary mappings entered by mmu_booke_qenter. 1378 */ 1379static void 1380mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1381{ 1382 vm_offset_t va; 1383 1384 va = sva; 1385 while (count-- > 0) { 1386 mmu_booke_kremove(mmu, va); 1387 va += PAGE_SIZE; 1388 } 1389} 1390 1391/* 1392 * Map a wired page into kernel virtual address space. 1393 */ 1394static void 1395mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1396{ 1397 unsigned int pdir_idx = PDIR_IDX(va); 1398 unsigned int ptbl_idx = PTBL_IDX(va); 1399 uint32_t flags; 1400 pte_t *pte; 1401 1402 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1403 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1404 1405 flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1406 1407 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1408 1409 mtx_lock_spin(&tlbivax_mutex); 1410 tlb_miss_lock(); 1411 1412 if (PTE_ISVALID(pte)) { 1413 1414 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1415 1416 /* Flush entry from TLB0 */ 1417 tlb0_flush_entry(va); 1418 } 1419 1420 pte->rpn = pa & ~PTE_PA_MASK; 1421 pte->flags = flags; 1422 1423 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1424 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1425 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1426 1427 /* Flush the real memory from the instruction cache. */ 1428 if ((flags & (PTE_I | PTE_G)) == 0) { 1429 __syncicache((void *)va, PAGE_SIZE); 1430 } 1431 1432 tlb_miss_unlock(); 1433 mtx_unlock_spin(&tlbivax_mutex); 1434} 1435 1436/* 1437 * Remove a page from kernel page table. 1438 */ 1439static void 1440mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1441{ 1442 unsigned int pdir_idx = PDIR_IDX(va); 1443 unsigned int ptbl_idx = PTBL_IDX(va); 1444 pte_t *pte; 1445 1446// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1447 1448 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1449 (va <= VM_MAX_KERNEL_ADDRESS)), 1450 ("mmu_booke_kremove: invalid va")); 1451 1452 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1453 1454 if (!PTE_ISVALID(pte)) { 1455 1456 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1457 1458 return; 1459 } 1460 1461 mtx_lock_spin(&tlbivax_mutex); 1462 tlb_miss_lock(); 1463 1464 /* Invalidate entry in TLB0, update PTE. */ 1465 tlb0_flush_entry(va); 1466 pte->flags = 0; 1467 pte->rpn = 0; 1468 1469 tlb_miss_unlock(); 1470 mtx_unlock_spin(&tlbivax_mutex); 1471} 1472 1473/* 1474 * Initialize pmap associated with process 0. 1475 */ 1476static void 1477mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1478{ 1479 1480 PMAP_LOCK_INIT(pmap); 1481 mmu_booke_pinit(mmu, pmap); 1482 PCPU_SET(curpmap, pmap); 1483} 1484 1485/* 1486 * Initialize a preallocated and zeroed pmap structure, 1487 * such as one in a vmspace structure. 1488 */ 1489static void 1490mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1491{ 1492 int i; 1493 1494 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1495 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1496 1497 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1498 1499 for (i = 0; i < MAXCPU; i++) 1500 pmap->pm_tid[i] = TID_NONE; 1501 CPU_ZERO(&kernel_pmap->pm_active); 1502 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1503 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1504 TAILQ_INIT(&pmap->pm_ptbl_list); 1505} 1506 1507/* 1508 * Release any resources held by the given physical map. 1509 * Called when a pmap initialized by mmu_booke_pinit is being released. 1510 * Should only be called if the map contains no valid mappings. 1511 */ 1512static void 1513mmu_booke_release(mmu_t mmu, pmap_t pmap) 1514{ 1515 1516 KASSERT(pmap->pm_stats.resident_count == 0, 1517 ("pmap_release: pmap resident count %ld != 0", 1518 pmap->pm_stats.resident_count)); 1519} 1520 1521/* 1522 * Insert the given physical page at the specified virtual address in the 1523 * target physical map with the protection requested. If specified the page 1524 * will be wired down. 1525 */ 1526static void 1527mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1528 vm_prot_t prot, boolean_t wired) 1529{ 1530 1531 rw_wlock(&pvh_global_lock); 1532 PMAP_LOCK(pmap); 1533 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1534 rw_wunlock(&pvh_global_lock); 1535 PMAP_UNLOCK(pmap); 1536} 1537 1538static void 1539mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1540 vm_prot_t prot, boolean_t wired) 1541{ 1542 pte_t *pte; 1543 vm_paddr_t pa; 1544 uint32_t flags; 1545 int su, sync; 1546 1547 pa = VM_PAGE_TO_PHYS(m); 1548 su = (pmap == kernel_pmap); 1549 sync = 0; 1550 1551 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1552 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1553 // (u_int32_t)pmap, su, pmap->pm_tid, 1554 // (u_int32_t)m, va, pa, prot, wired); 1555 1556 if (su) { 1557 KASSERT(((va >= virtual_avail) && 1558 (va <= VM_MAX_KERNEL_ADDRESS)), 1559 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1560 } else { 1561 KASSERT((va <= VM_MAXUSER_ADDRESS), 1562 ("mmu_booke_enter_locked: user pmap, non user va")); 1563 } 1564 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1565 VM_OBJECT_ASSERT_LOCKED(m->object); 1566 1567 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1568 1569 /* 1570 * If there is an existing mapping, and the physical address has not 1571 * changed, must be protection or wiring change. 1572 */ 1573 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1574 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1575 1576 /* 1577 * Before actually updating pte->flags we calculate and 1578 * prepare its new value in a helper var. 1579 */ 1580 flags = pte->flags; 1581 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1582 1583 /* Wiring change, just update stats. */ 1584 if (wired) { 1585 if (!PTE_ISWIRED(pte)) { 1586 flags |= PTE_WIRED; 1587 pmap->pm_stats.wired_count++; 1588 } 1589 } else { 1590 if (PTE_ISWIRED(pte)) { 1591 flags &= ~PTE_WIRED; 1592 pmap->pm_stats.wired_count--; 1593 } 1594 } 1595 1596 if (prot & VM_PROT_WRITE) { 1597 /* Add write permissions. */ 1598 flags |= PTE_SW; 1599 if (!su) 1600 flags |= PTE_UW; 1601 1602 if ((flags & PTE_MANAGED) != 0) 1603 vm_page_aflag_set(m, PGA_WRITEABLE); 1604 } else { 1605 /* Handle modified pages, sense modify status. */ 1606 1607 /* 1608 * The PTE_MODIFIED flag could be set by underlying 1609 * TLB misses since we last read it (above), possibly 1610 * other CPUs could update it so we check in the PTE 1611 * directly rather than rely on that saved local flags 1612 * copy. 1613 */ 1614 if (PTE_ISMODIFIED(pte)) 1615 vm_page_dirty(m); 1616 } 1617 1618 if (prot & VM_PROT_EXECUTE) { 1619 flags |= PTE_SX; 1620 if (!su) 1621 flags |= PTE_UX; 1622 1623 /* 1624 * Check existing flags for execute permissions: if we 1625 * are turning execute permissions on, icache should 1626 * be flushed. 1627 */ 1628 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1629 sync++; 1630 } 1631 1632 flags &= ~PTE_REFERENCED; 1633 1634 /* 1635 * The new flags value is all calculated -- only now actually 1636 * update the PTE. 1637 */ 1638 mtx_lock_spin(&tlbivax_mutex); 1639 tlb_miss_lock(); 1640 1641 tlb0_flush_entry(va); 1642 pte->flags = flags; 1643 1644 tlb_miss_unlock(); 1645 mtx_unlock_spin(&tlbivax_mutex); 1646 1647 } else { 1648 /* 1649 * If there is an existing mapping, but it's for a different 1650 * physical address, pte_enter() will delete the old mapping. 1651 */ 1652 //if ((pte != NULL) && PTE_ISVALID(pte)) 1653 // debugf("mmu_booke_enter_locked: replace\n"); 1654 //else 1655 // debugf("mmu_booke_enter_locked: new\n"); 1656 1657 /* Now set up the flags and install the new mapping. */ 1658 flags = (PTE_SR | PTE_VALID); 1659 flags |= PTE_M; 1660 1661 if (!su) 1662 flags |= PTE_UR; 1663 1664 if (prot & VM_PROT_WRITE) { 1665 flags |= PTE_SW; 1666 if (!su) 1667 flags |= PTE_UW; 1668 1669 if ((m->oflags & VPO_UNMANAGED) == 0) 1670 vm_page_aflag_set(m, PGA_WRITEABLE); 1671 } 1672 1673 if (prot & VM_PROT_EXECUTE) { 1674 flags |= PTE_SX; 1675 if (!su) 1676 flags |= PTE_UX; 1677 } 1678 1679 /* If its wired update stats. */ 1680 if (wired) { 1681 pmap->pm_stats.wired_count++; 1682 flags |= PTE_WIRED; 1683 } 1684 1685 pte_enter(mmu, pmap, m, va, flags); 1686 1687 /* Flush the real memory from the instruction cache. */ 1688 if (prot & VM_PROT_EXECUTE) 1689 sync++; 1690 } 1691 1692 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1693 __syncicache((void *)va, PAGE_SIZE); 1694 sync = 0; 1695 } 1696} 1697 1698/* 1699 * Maps a sequence of resident pages belonging to the same object. 1700 * The sequence begins with the given page m_start. This page is 1701 * mapped at the given virtual address start. Each subsequent page is 1702 * mapped at a virtual address that is offset from start by the same 1703 * amount as the page is offset from m_start within the object. The 1704 * last page in the sequence is the page with the largest offset from 1705 * m_start that can be mapped at a virtual address less than the given 1706 * virtual address end. Not every virtual page between start and end 1707 * is mapped; only those for which a resident page exists with the 1708 * corresponding offset from m_start are mapped. 1709 */ 1710static void 1711mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1712 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1713{ 1714 vm_page_t m; 1715 vm_pindex_t diff, psize; 1716 1717 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1718 1719 psize = atop(end - start); 1720 m = m_start; 1721 rw_wlock(&pvh_global_lock); 1722 PMAP_LOCK(pmap); 1723 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1724 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1725 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1726 m = TAILQ_NEXT(m, listq); 1727 } 1728 rw_wunlock(&pvh_global_lock); 1729 PMAP_UNLOCK(pmap); 1730} 1731 1732static void 1733mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1734 vm_prot_t prot) 1735{ 1736 1737 rw_wlock(&pvh_global_lock); 1738 PMAP_LOCK(pmap); 1739 mmu_booke_enter_locked(mmu, pmap, va, m, 1740 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1741 rw_wunlock(&pvh_global_lock); 1742 PMAP_UNLOCK(pmap); 1743} 1744 1745/* 1746 * Remove the given range of addresses from the specified map. 1747 * 1748 * It is assumed that the start and end are properly rounded to the page size. 1749 */ 1750static void 1751mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1752{ 1753 pte_t *pte; 1754 uint8_t hold_flag; 1755 1756 int su = (pmap == kernel_pmap); 1757 1758 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1759 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1760 1761 if (su) { 1762 KASSERT(((va >= virtual_avail) && 1763 (va <= VM_MAX_KERNEL_ADDRESS)), 1764 ("mmu_booke_remove: kernel pmap, non kernel va")); 1765 } else { 1766 KASSERT((va <= VM_MAXUSER_ADDRESS), 1767 ("mmu_booke_remove: user pmap, non user va")); 1768 } 1769 1770 if (PMAP_REMOVE_DONE(pmap)) { 1771 //debugf("mmu_booke_remove: e (empty)\n"); 1772 return; 1773 } 1774 1775 hold_flag = PTBL_HOLD_FLAG(pmap); 1776 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1777 1778 rw_wlock(&pvh_global_lock); 1779 PMAP_LOCK(pmap); 1780 for (; va < endva; va += PAGE_SIZE) { 1781 pte = pte_find(mmu, pmap, va); 1782 if ((pte != NULL) && PTE_ISVALID(pte)) 1783 pte_remove(mmu, pmap, va, hold_flag); 1784 } 1785 PMAP_UNLOCK(pmap); 1786 rw_wunlock(&pvh_global_lock); 1787 1788 //debugf("mmu_booke_remove: e\n"); 1789} 1790 1791/* 1792 * Remove physical page from all pmaps in which it resides. 1793 */ 1794static void 1795mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1796{ 1797 pv_entry_t pv, pvn; 1798 uint8_t hold_flag; 1799 1800 rw_wlock(&pvh_global_lock); 1801 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1802 pvn = TAILQ_NEXT(pv, pv_link); 1803 1804 PMAP_LOCK(pv->pv_pmap); 1805 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1806 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1807 PMAP_UNLOCK(pv->pv_pmap); 1808 } 1809 vm_page_aflag_clear(m, PGA_WRITEABLE); 1810 rw_wunlock(&pvh_global_lock); 1811} 1812 1813/* 1814 * Map a range of physical addresses into kernel virtual address space. 1815 */ 1816static vm_offset_t 1817mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1818 vm_paddr_t pa_end, int prot) 1819{ 1820 vm_offset_t sva = *virt; 1821 vm_offset_t va = sva; 1822 1823 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1824 // sva, pa_start, pa_end); 1825 1826 while (pa_start < pa_end) { 1827 mmu_booke_kenter(mmu, va, pa_start); 1828 va += PAGE_SIZE; 1829 pa_start += PAGE_SIZE; 1830 } 1831 *virt = va; 1832 1833 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1834 return (sva); 1835} 1836 1837/* 1838 * The pmap must be activated before it's address space can be accessed in any 1839 * way. 1840 */ 1841static void 1842mmu_booke_activate(mmu_t mmu, struct thread *td) 1843{ 1844 pmap_t pmap; 1845 u_int cpuid; 1846 1847 pmap = &td->td_proc->p_vmspace->vm_pmap; 1848 1849 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1850 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1851 1852 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1853 1854 mtx_lock_spin(&sched_lock); 1855 1856 cpuid = PCPU_GET(cpuid); 1857 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1858 PCPU_SET(curpmap, pmap); 1859 1860 if (pmap->pm_tid[cpuid] == TID_NONE) 1861 tid_alloc(pmap); 1862 1863 /* Load PID0 register with pmap tid value. */ 1864 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1865 __asm __volatile("isync"); 1866 1867 mtx_unlock_spin(&sched_lock); 1868 1869 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1870 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1871} 1872 1873/* 1874 * Deactivate the specified process's address space. 1875 */ 1876static void 1877mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1878{ 1879 pmap_t pmap; 1880 1881 pmap = &td->td_proc->p_vmspace->vm_pmap; 1882 1883 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1884 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1885 1886 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1887 PCPU_SET(curpmap, NULL); 1888} 1889 1890/* 1891 * Copy the range specified by src_addr/len 1892 * from the source map to the range dst_addr/len 1893 * in the destination map. 1894 * 1895 * This routine is only advisory and need not do anything. 1896 */ 1897static void 1898mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1899 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1900{ 1901 1902} 1903 1904/* 1905 * Set the physical protection on the specified range of this map as requested. 1906 */ 1907static void 1908mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1909 vm_prot_t prot) 1910{ 1911 vm_offset_t va; 1912 vm_page_t m; 1913 pte_t *pte; 1914 1915 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1916 mmu_booke_remove(mmu, pmap, sva, eva); 1917 return; 1918 } 1919 1920 if (prot & VM_PROT_WRITE) 1921 return; 1922 1923 PMAP_LOCK(pmap); 1924 for (va = sva; va < eva; va += PAGE_SIZE) { 1925 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1926 if (PTE_ISVALID(pte)) { 1927 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1928 1929 mtx_lock_spin(&tlbivax_mutex); 1930 tlb_miss_lock(); 1931 1932 /* Handle modified pages. */ 1933 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1934 vm_page_dirty(m); 1935 1936 tlb0_flush_entry(va); 1937 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1938 1939 tlb_miss_unlock(); 1940 mtx_unlock_spin(&tlbivax_mutex); 1941 } 1942 } 1943 } 1944 PMAP_UNLOCK(pmap); 1945} 1946 1947/* 1948 * Clear the write and modified bits in each of the given page's mappings. 1949 */ 1950static void 1951mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1952{ 1953 pv_entry_t pv; 1954 pte_t *pte; 1955 1956 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1957 ("mmu_booke_remove_write: page %p is not managed", m)); 1958 1959 /* 1960 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1961 * set by another thread while the object is locked. Thus, 1962 * if PGA_WRITEABLE is clear, no page table entries need updating. 1963 */ 1964 VM_OBJECT_ASSERT_WLOCKED(m->object); 1965 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1966 return; 1967 rw_wlock(&pvh_global_lock); 1968 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1969 PMAP_LOCK(pv->pv_pmap); 1970 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1971 if (PTE_ISVALID(pte)) { 1972 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1973 1974 mtx_lock_spin(&tlbivax_mutex); 1975 tlb_miss_lock(); 1976 1977 /* Handle modified pages. */ 1978 if (PTE_ISMODIFIED(pte)) 1979 vm_page_dirty(m); 1980 1981 /* Flush mapping from TLB0. */ 1982 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1983 1984 tlb_miss_unlock(); 1985 mtx_unlock_spin(&tlbivax_mutex); 1986 } 1987 } 1988 PMAP_UNLOCK(pv->pv_pmap); 1989 } 1990 vm_page_aflag_clear(m, PGA_WRITEABLE); 1991 rw_wunlock(&pvh_global_lock); 1992} 1993 1994static void 1995mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1996{ 1997 pte_t *pte; 1998 pmap_t pmap; 1999 vm_page_t m; 2000 vm_offset_t addr; 2001 vm_paddr_t pa; 2002 int active, valid; 2003 2004 va = trunc_page(va); 2005 sz = round_page(sz); 2006 2007 rw_wlock(&pvh_global_lock); 2008 pmap = PCPU_GET(curpmap); 2009 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2010 while (sz > 0) { 2011 PMAP_LOCK(pm); 2012 pte = pte_find(mmu, pm, va); 2013 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2014 if (valid) 2015 pa = PTE_PA(pte); 2016 PMAP_UNLOCK(pm); 2017 if (valid) { 2018 if (!active) { 2019 /* Create a mapping in the active pmap. */ 2020 addr = 0; 2021 m = PHYS_TO_VM_PAGE(pa); 2022 PMAP_LOCK(pmap); 2023 pte_enter(mmu, pmap, m, addr, 2024 PTE_SR | PTE_VALID | PTE_UR); 2025 __syncicache((void *)addr, PAGE_SIZE); 2026 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2027 PMAP_UNLOCK(pmap); 2028 } else 2029 __syncicache((void *)va, PAGE_SIZE); 2030 } 2031 va += PAGE_SIZE; 2032 sz -= PAGE_SIZE; 2033 } 2034 rw_wunlock(&pvh_global_lock); 2035} 2036 2037/* 2038 * Atomically extract and hold the physical page with the given 2039 * pmap and virtual address pair if that mapping permits the given 2040 * protection. 2041 */ 2042static vm_page_t 2043mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2044 vm_prot_t prot) 2045{ 2046 pte_t *pte; 2047 vm_page_t m; 2048 uint32_t pte_wbit; 2049 vm_paddr_t pa; 2050 2051 m = NULL; 2052 pa = 0; 2053 PMAP_LOCK(pmap); 2054retry: 2055 pte = pte_find(mmu, pmap, va); 2056 if ((pte != NULL) && PTE_ISVALID(pte)) { 2057 if (pmap == kernel_pmap) 2058 pte_wbit = PTE_SW; 2059 else 2060 pte_wbit = PTE_UW; 2061 2062 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2063 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2064 goto retry; 2065 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2066 vm_page_hold(m); 2067 } 2068 } 2069 2070 PA_UNLOCK_COND(pa); 2071 PMAP_UNLOCK(pmap); 2072 return (m); 2073} 2074 2075/* 2076 * Initialize a vm_page's machine-dependent fields. 2077 */ 2078static void 2079mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2080{ 2081 2082 TAILQ_INIT(&m->md.pv_list); 2083} 2084 2085/* 2086 * mmu_booke_zero_page_area zeros the specified hardware page by 2087 * mapping it into virtual memory and using bzero to clear 2088 * its contents. 2089 * 2090 * off and size must reside within a single page. 2091 */ 2092static void 2093mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2094{ 2095 vm_offset_t va; 2096 2097 /* XXX KASSERT off and size are within a single page? */ 2098 2099 mtx_lock(&zero_page_mutex); 2100 va = zero_page_va; 2101 2102 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2103 bzero((caddr_t)va + off, size); 2104 mmu_booke_kremove(mmu, va); 2105 2106 mtx_unlock(&zero_page_mutex); 2107} 2108 2109/* 2110 * mmu_booke_zero_page zeros the specified hardware page. 2111 */ 2112static void 2113mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2114{ 2115 2116 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2117} 2118 2119/* 2120 * mmu_booke_copy_page copies the specified (machine independent) page by 2121 * mapping the page into virtual memory and using memcopy to copy the page, 2122 * one machine dependent page at a time. 2123 */ 2124static void 2125mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2126{ 2127 vm_offset_t sva, dva; 2128 2129 sva = copy_page_src_va; 2130 dva = copy_page_dst_va; 2131 2132 mtx_lock(©_page_mutex); 2133 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2134 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2135 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2136 mmu_booke_kremove(mmu, dva); 2137 mmu_booke_kremove(mmu, sva); 2138 mtx_unlock(©_page_mutex); 2139} 2140 2141static inline void 2142mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2143 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2144{ 2145 void *a_cp, *b_cp; 2146 vm_offset_t a_pg_offset, b_pg_offset; 2147 int cnt; 2148 2149 mtx_lock(©_page_mutex); 2150 while (xfersize > 0) { 2151 a_pg_offset = a_offset & PAGE_MASK; 2152 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2153 mmu_booke_kenter(mmu, copy_page_src_va, 2154 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2155 a_cp = (char *)copy_page_src_va + a_pg_offset; 2156 b_pg_offset = b_offset & PAGE_MASK; 2157 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2158 mmu_booke_kenter(mmu, copy_page_dst_va, 2159 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2160 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2161 bcopy(a_cp, b_cp, cnt); 2162 mmu_booke_kremove(mmu, copy_page_dst_va); 2163 mmu_booke_kremove(mmu, copy_page_src_va); 2164 a_offset += cnt; 2165 b_offset += cnt; 2166 xfersize -= cnt; 2167 } 2168 mtx_unlock(©_page_mutex); 2169} 2170 2171/* 2172 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2173 * into virtual memory and using bzero to clear its contents. This is intended 2174 * to be called from the vm_pagezero process only and outside of Giant. No 2175 * lock is required. 2176 */ 2177static void 2178mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2179{ 2180 vm_offset_t va; 2181 2182 va = zero_page_idle_va; 2183 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2184 bzero((caddr_t)va, PAGE_SIZE); 2185 mmu_booke_kremove(mmu, va); 2186} 2187 2188/* 2189 * Return whether or not the specified physical page was modified 2190 * in any of physical maps. 2191 */ 2192static boolean_t 2193mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2194{ 2195 pte_t *pte; 2196 pv_entry_t pv; 2197 boolean_t rv; 2198 2199 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2200 ("mmu_booke_is_modified: page %p is not managed", m)); 2201 rv = FALSE; 2202 2203 /* 2204 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2205 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2206 * is clear, no PTEs can be modified. 2207 */ 2208 VM_OBJECT_ASSERT_WLOCKED(m->object); 2209 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2210 return (rv); 2211 rw_wlock(&pvh_global_lock); 2212 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2213 PMAP_LOCK(pv->pv_pmap); 2214 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2215 PTE_ISVALID(pte)) { 2216 if (PTE_ISMODIFIED(pte)) 2217 rv = TRUE; 2218 } 2219 PMAP_UNLOCK(pv->pv_pmap); 2220 if (rv) 2221 break; 2222 } 2223 rw_wunlock(&pvh_global_lock); 2224 return (rv); 2225} 2226 2227/* 2228 * Return whether or not the specified virtual address is eligible 2229 * for prefault. 2230 */ 2231static boolean_t 2232mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2233{ 2234 2235 return (FALSE); 2236} 2237 2238/* 2239 * Return whether or not the specified physical page was referenced 2240 * in any physical maps. 2241 */ 2242static boolean_t 2243mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2244{ 2245 pte_t *pte; 2246 pv_entry_t pv; 2247 boolean_t rv; 2248 2249 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2250 ("mmu_booke_is_referenced: page %p is not managed", m)); 2251 rv = FALSE; 2252 rw_wlock(&pvh_global_lock); 2253 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2254 PMAP_LOCK(pv->pv_pmap); 2255 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2256 PTE_ISVALID(pte)) { 2257 if (PTE_ISREFERENCED(pte)) 2258 rv = TRUE; 2259 } 2260 PMAP_UNLOCK(pv->pv_pmap); 2261 if (rv) 2262 break; 2263 } 2264 rw_wunlock(&pvh_global_lock); 2265 return (rv); 2266} 2267 2268/* 2269 * Clear the modify bits on the specified physical page. 2270 */ 2271static void 2272mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2273{ 2274 pte_t *pte; 2275 pv_entry_t pv; 2276 2277 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2278 ("mmu_booke_clear_modify: page %p is not managed", m)); 2279 VM_OBJECT_ASSERT_WLOCKED(m->object); 2280 KASSERT(!vm_page_xbusied(m), 2281 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2282 2283 /* 2284 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2285 * If the object containing the page is locked and the page is not 2286 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2287 */ 2288 if ((m->aflags & PGA_WRITEABLE) == 0) 2289 return; 2290 rw_wlock(&pvh_global_lock); 2291 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2292 PMAP_LOCK(pv->pv_pmap); 2293 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2294 PTE_ISVALID(pte)) { 2295 mtx_lock_spin(&tlbivax_mutex); 2296 tlb_miss_lock(); 2297 2298 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2299 tlb0_flush_entry(pv->pv_va); 2300 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2301 PTE_REFERENCED); 2302 } 2303 2304 tlb_miss_unlock(); 2305 mtx_unlock_spin(&tlbivax_mutex); 2306 } 2307 PMAP_UNLOCK(pv->pv_pmap); 2308 } 2309 rw_wunlock(&pvh_global_lock); 2310} 2311 2312/* 2313 * Return a count of reference bits for a page, clearing those bits. 2314 * It is not necessary for every reference bit to be cleared, but it 2315 * is necessary that 0 only be returned when there are truly no 2316 * reference bits set. 2317 * 2318 * XXX: The exact number of bits to check and clear is a matter that 2319 * should be tested and standardized at some point in the future for 2320 * optimal aging of shared pages. 2321 */ 2322static int 2323mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2324{ 2325 pte_t *pte; 2326 pv_entry_t pv; 2327 int count; 2328 2329 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2330 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2331 count = 0; 2332 rw_wlock(&pvh_global_lock); 2333 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2334 PMAP_LOCK(pv->pv_pmap); 2335 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2336 PTE_ISVALID(pte)) { 2337 if (PTE_ISREFERENCED(pte)) { 2338 mtx_lock_spin(&tlbivax_mutex); 2339 tlb_miss_lock(); 2340 2341 tlb0_flush_entry(pv->pv_va); 2342 pte->flags &= ~PTE_REFERENCED; 2343 2344 tlb_miss_unlock(); 2345 mtx_unlock_spin(&tlbivax_mutex); 2346 2347 if (++count > 4) { 2348 PMAP_UNLOCK(pv->pv_pmap); 2349 break; 2350 } 2351 } 2352 } 2353 PMAP_UNLOCK(pv->pv_pmap); 2354 } 2355 rw_wunlock(&pvh_global_lock); 2356 return (count); 2357} 2358 2359/* 2360 * Clear the reference bit on the specified physical page. 2361 */ 2362static void 2363mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2364{ 2365 pte_t *pte; 2366 pv_entry_t pv; 2367 2368 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2369 ("mmu_booke_clear_reference: page %p is not managed", m)); 2370 rw_wlock(&pvh_global_lock); 2371 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2372 PMAP_LOCK(pv->pv_pmap); 2373 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2374 PTE_ISVALID(pte)) { 2375 if (PTE_ISREFERENCED(pte)) { 2376 mtx_lock_spin(&tlbivax_mutex); 2377 tlb_miss_lock(); 2378 2379 tlb0_flush_entry(pv->pv_va); 2380 pte->flags &= ~PTE_REFERENCED; 2381 2382 tlb_miss_unlock(); 2383 mtx_unlock_spin(&tlbivax_mutex); 2384 } 2385 } 2386 PMAP_UNLOCK(pv->pv_pmap); 2387 } 2388 rw_wunlock(&pvh_global_lock); 2389} 2390 2391/* 2392 * Change wiring attribute for a map/virtual-address pair. 2393 */ 2394static void 2395mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2396{ 2397 pte_t *pte; 2398 2399 PMAP_LOCK(pmap); 2400 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2401 if (wired) { 2402 if (!PTE_ISWIRED(pte)) { 2403 pte->flags |= PTE_WIRED; 2404 pmap->pm_stats.wired_count++; 2405 } 2406 } else { 2407 if (PTE_ISWIRED(pte)) { 2408 pte->flags &= ~PTE_WIRED; 2409 pmap->pm_stats.wired_count--; 2410 } 2411 } 2412 } 2413 PMAP_UNLOCK(pmap); 2414} 2415 2416/* 2417 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2418 * page. This count may be changed upwards or downwards in the future; it is 2419 * only necessary that true be returned for a small subset of pmaps for proper 2420 * page aging. 2421 */ 2422static boolean_t 2423mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2424{ 2425 pv_entry_t pv; 2426 int loops; 2427 boolean_t rv; 2428 2429 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2430 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2431 loops = 0; 2432 rv = FALSE; 2433 rw_wlock(&pvh_global_lock); 2434 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2435 if (pv->pv_pmap == pmap) { 2436 rv = TRUE; 2437 break; 2438 } 2439 if (++loops >= 16) 2440 break; 2441 } 2442 rw_wunlock(&pvh_global_lock); 2443 return (rv); 2444} 2445 2446/* 2447 * Return the number of managed mappings to the given physical page that are 2448 * wired. 2449 */ 2450static int 2451mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2452{ 2453 pv_entry_t pv; 2454 pte_t *pte; 2455 int count = 0; 2456 2457 if ((m->oflags & VPO_UNMANAGED) != 0) 2458 return (count); 2459 rw_wlock(&pvh_global_lock); 2460 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2461 PMAP_LOCK(pv->pv_pmap); 2462 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2463 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2464 count++; 2465 PMAP_UNLOCK(pv->pv_pmap); 2466 } 2467 rw_wunlock(&pvh_global_lock); 2468 return (count); 2469} 2470 2471static int 2472mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2473{ 2474 int i; 2475 vm_offset_t va; 2476 2477 /* 2478 * This currently does not work for entries that 2479 * overlap TLB1 entries. 2480 */ 2481 for (i = 0; i < tlb1_idx; i ++) { 2482 if (tlb1_iomapped(i, pa, size, &va) == 0) 2483 return (0); 2484 } 2485 2486 return (EFAULT); 2487} 2488 2489vm_offset_t 2490mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2491 vm_size_t *sz) 2492{ 2493 vm_paddr_t pa, ppa; 2494 vm_offset_t va; 2495 vm_size_t gran; 2496 2497 /* Raw physical memory dumps don't have a virtual address. */ 2498 if (md->md_vaddr == ~0UL) { 2499 /* We always map a 256MB page at 256M. */ 2500 gran = 256 * 1024 * 1024; 2501 pa = md->md_paddr + ofs; 2502 ppa = pa & ~(gran - 1); 2503 ofs = pa - ppa; 2504 va = gran; 2505 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2506 if (*sz > (gran - ofs)) 2507 *sz = gran - ofs; 2508 return (va + ofs); 2509 } 2510 2511 /* Minidumps are based on virtual memory addresses. */ 2512 va = md->md_vaddr + ofs; 2513 if (va >= kernstart + kernsize) { 2514 gran = PAGE_SIZE - (va & PAGE_MASK); 2515 if (*sz > gran) 2516 *sz = gran; 2517 } 2518 return (va); 2519} 2520 2521void 2522mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2523 vm_offset_t va) 2524{ 2525 2526 /* Raw physical memory dumps don't have a virtual address. */ 2527 if (md->md_vaddr == ~0UL) { 2528 tlb1_idx--; 2529 tlb1[tlb1_idx].mas1 = 0; 2530 tlb1[tlb1_idx].mas2 = 0; 2531 tlb1[tlb1_idx].mas3 = 0; 2532 tlb1_write_entry(tlb1_idx); 2533 return; 2534 } 2535 2536 /* Minidumps are based on virtual memory addresses. */ 2537 /* Nothing to do... */ 2538} 2539 2540struct pmap_md * 2541mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2542{ 2543 static struct pmap_md md; 2544 pte_t *pte; 2545 vm_offset_t va; 2546 2547 if (dumpsys_minidump) { 2548 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2549 if (prev == NULL) { 2550 /* 1st: kernel .data and .bss. */ 2551 md.md_index = 1; 2552 md.md_vaddr = trunc_page((uintptr_t)_etext); 2553 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2554 return (&md); 2555 } 2556 switch (prev->md_index) { 2557 case 1: 2558 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2559 md.md_index = 2; 2560 md.md_vaddr = data_start; 2561 md.md_size = data_end - data_start; 2562 break; 2563 case 2: 2564 /* 3rd: kernel VM. */ 2565 va = prev->md_vaddr + prev->md_size; 2566 /* Find start of next chunk (from va). */ 2567 while (va < virtual_end) { 2568 /* Don't dump the buffer cache. */ 2569 if (va >= kmi.buffer_sva && 2570 va < kmi.buffer_eva) { 2571 va = kmi.buffer_eva; 2572 continue; 2573 } 2574 pte = pte_find(mmu, kernel_pmap, va); 2575 if (pte != NULL && PTE_ISVALID(pte)) 2576 break; 2577 va += PAGE_SIZE; 2578 } 2579 if (va < virtual_end) { 2580 md.md_vaddr = va; 2581 va += PAGE_SIZE; 2582 /* Find last page in chunk. */ 2583 while (va < virtual_end) { 2584 /* Don't run into the buffer cache. */ 2585 if (va == kmi.buffer_sva) 2586 break; 2587 pte = pte_find(mmu, kernel_pmap, va); 2588 if (pte == NULL || !PTE_ISVALID(pte)) 2589 break; 2590 va += PAGE_SIZE; 2591 } 2592 md.md_size = va - md.md_vaddr; 2593 break; 2594 } 2595 md.md_index = 3; 2596 /* FALLTHROUGH */ 2597 default: 2598 return (NULL); 2599 } 2600 } else { /* minidumps */ 2601 mem_regions(&physmem_regions, &physmem_regions_sz, 2602 &availmem_regions, &availmem_regions_sz); 2603 2604 if (prev == NULL) { 2605 /* first physical chunk. */ 2606 md.md_paddr = physmem_regions[0].mr_start; 2607 md.md_size = physmem_regions[0].mr_size; 2608 md.md_vaddr = ~0UL; 2609 md.md_index = 1; 2610 } else if (md.md_index < physmem_regions_sz) { 2611 md.md_paddr = physmem_regions[md.md_index].mr_start; 2612 md.md_size = physmem_regions[md.md_index].mr_size; 2613 md.md_vaddr = ~0UL; 2614 md.md_index++; 2615 } else { 2616 /* There's no next physical chunk. */ 2617 return (NULL); 2618 } 2619 } 2620 2621 return (&md); 2622} 2623 2624/* 2625 * Map a set of physical memory pages into the kernel virtual address space. 2626 * Return a pointer to where it is mapped. This routine is intended to be used 2627 * for mapping device memory, NOT real memory. 2628 */ 2629static void * 2630mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2631{ 2632 void *res; 2633 uintptr_t va; 2634 vm_size_t sz; 2635 2636 /* 2637 * CCSR is premapped. Note that (pa + size - 1) is there to make sure 2638 * we don't wrap around. Devices on the local bus typically extend all 2639 * the way up to and including 0xffffffff. In that case (pa + size) 2640 * would be 0. This creates a false positive (i.e. we think it's 2641 * within the CCSR) and not create a mapping. 2642 */ 2643 if (pa >= ccsrbar_pa && (pa + size - 1) < (ccsrbar_pa + CCSRBAR_SIZE)) { 2644 va = CCSRBAR_VA + (pa - ccsrbar_pa); 2645 return ((void *)va); 2646 } 2647 2648 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2649 res = (void *)va; 2650 2651 do { 2652 sz = 1 << (ilog2(size) & ~1); 2653 if (bootverbose) 2654 printf("Wiring VA=%x to PA=%x (size=%x), " 2655 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2656 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2657 size -= sz; 2658 pa += sz; 2659 va += sz; 2660 } while (size > 0); 2661 2662 return (res); 2663} 2664 2665/* 2666 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2667 */ 2668static void 2669mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2670{ 2671 vm_offset_t base, offset; 2672 2673 /* 2674 * Unmap only if this is inside kernel virtual space. 2675 */ 2676 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2677 base = trunc_page(va); 2678 offset = va & PAGE_MASK; 2679 size = roundup(offset + size, PAGE_SIZE); 2680 kva_free(base, size); 2681 } 2682} 2683 2684/* 2685 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2686 * specified pmap. This eliminates the blast of soft faults on process startup 2687 * and immediately after an mmap. 2688 */ 2689static void 2690mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2691 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2692{ 2693 2694 VM_OBJECT_ASSERT_WLOCKED(object); 2695 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2696 ("mmu_booke_object_init_pt: non-device object")); 2697} 2698 2699/* 2700 * Perform the pmap work for mincore. 2701 */ 2702static int 2703mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2704 vm_paddr_t *locked_pa) 2705{ 2706 2707 TODO; 2708 return (0); 2709} 2710 2711/**************************************************************************/ 2712/* TID handling */ 2713/**************************************************************************/ 2714 2715/* 2716 * Allocate a TID. If necessary, steal one from someone else. 2717 * The new TID is flushed from the TLB before returning. 2718 */ 2719static tlbtid_t 2720tid_alloc(pmap_t pmap) 2721{ 2722 tlbtid_t tid; 2723 int thiscpu; 2724 2725 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2726 2727 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2728 2729 thiscpu = PCPU_GET(cpuid); 2730 2731 tid = PCPU_GET(tid_next); 2732 if (tid > TID_MAX) 2733 tid = TID_MIN; 2734 PCPU_SET(tid_next, tid + 1); 2735 2736 /* If we are stealing TID then clear the relevant pmap's field */ 2737 if (tidbusy[thiscpu][tid] != NULL) { 2738 2739 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2740 2741 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2742 2743 /* Flush all entries from TLB0 matching this TID. */ 2744 tid_flush(tid); 2745 } 2746 2747 tidbusy[thiscpu][tid] = pmap; 2748 pmap->pm_tid[thiscpu] = tid; 2749 __asm __volatile("msync; isync"); 2750 2751 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2752 PCPU_GET(tid_next)); 2753 2754 return (tid); 2755} 2756 2757/**************************************************************************/ 2758/* TLB0 handling */ 2759/**************************************************************************/ 2760 2761static void 2762tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2763 uint32_t mas7) 2764{ 2765 int as; 2766 char desc[3]; 2767 tlbtid_t tid; 2768 vm_size_t size; 2769 unsigned int tsize; 2770 2771 desc[2] = '\0'; 2772 if (mas1 & MAS1_VALID) 2773 desc[0] = 'V'; 2774 else 2775 desc[0] = ' '; 2776 2777 if (mas1 & MAS1_IPROT) 2778 desc[1] = 'P'; 2779 else 2780 desc[1] = ' '; 2781 2782 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2783 tid = MAS1_GETTID(mas1); 2784 2785 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2786 size = 0; 2787 if (tsize) 2788 size = tsize2size(tsize); 2789 2790 debugf("%3d: (%s) [AS=%d] " 2791 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2792 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2793 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2794} 2795 2796/* Convert TLB0 va and way number to tlb0[] table index. */ 2797static inline unsigned int 2798tlb0_tableidx(vm_offset_t va, unsigned int way) 2799{ 2800 unsigned int idx; 2801 2802 idx = (way * TLB0_ENTRIES_PER_WAY); 2803 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2804 return (idx); 2805} 2806 2807/* 2808 * Invalidate TLB0 entry. 2809 */ 2810static inline void 2811tlb0_flush_entry(vm_offset_t va) 2812{ 2813 2814 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2815 2816 mtx_assert(&tlbivax_mutex, MA_OWNED); 2817 2818 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2819 __asm __volatile("isync; msync"); 2820 __asm __volatile("tlbsync; msync"); 2821 2822 CTR1(KTR_PMAP, "%s: e", __func__); 2823} 2824 2825/* Print out contents of the MAS registers for each TLB0 entry */ 2826void 2827tlb0_print_tlbentries(void) 2828{ 2829 uint32_t mas0, mas1, mas2, mas3, mas7; 2830 int entryidx, way, idx; 2831 2832 debugf("TLB0 entries:\n"); 2833 for (way = 0; way < TLB0_WAYS; way ++) 2834 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2835 2836 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2837 mtspr(SPR_MAS0, mas0); 2838 __asm __volatile("isync"); 2839 2840 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2841 mtspr(SPR_MAS2, mas2); 2842 2843 __asm __volatile("isync; tlbre"); 2844 2845 mas1 = mfspr(SPR_MAS1); 2846 mas2 = mfspr(SPR_MAS2); 2847 mas3 = mfspr(SPR_MAS3); 2848 mas7 = mfspr(SPR_MAS7); 2849 2850 idx = tlb0_tableidx(mas2, way); 2851 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2852 } 2853} 2854 2855/**************************************************************************/ 2856/* TLB1 handling */ 2857/**************************************************************************/ 2858 2859/* 2860 * TLB1 mapping notes: 2861 * 2862 * TLB1[0] CCSRBAR 2863 * TLB1[1] Kernel text and data. 2864 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2865 * windows, other devices mappings. 2866 */ 2867 2868/* 2869 * Write given entry to TLB1 hardware. 2870 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2871 */ 2872static void 2873tlb1_write_entry(unsigned int idx) 2874{ 2875 uint32_t mas0, mas7; 2876 2877 //debugf("tlb1_write_entry: s\n"); 2878 2879 /* Clear high order RPN bits */ 2880 mas7 = 0; 2881 2882 /* Select entry */ 2883 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2884 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2885 2886 mtspr(SPR_MAS0, mas0); 2887 __asm __volatile("isync"); 2888 mtspr(SPR_MAS1, tlb1[idx].mas1); 2889 __asm __volatile("isync"); 2890 mtspr(SPR_MAS2, tlb1[idx].mas2); 2891 __asm __volatile("isync"); 2892 mtspr(SPR_MAS3, tlb1[idx].mas3); 2893 __asm __volatile("isync"); 2894 mtspr(SPR_MAS7, mas7); 2895 __asm __volatile("isync; tlbwe; isync; msync"); 2896 2897 //debugf("tlb1_write_entry: e\n"); 2898} 2899 2900/* 2901 * Return the largest uint value log such that 2^log <= num. 2902 */ 2903static unsigned int 2904ilog2(unsigned int num) 2905{ 2906 int lz; 2907 2908 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2909 return (31 - lz); 2910} 2911 2912/* 2913 * Convert TLB TSIZE value to mapped region size. 2914 */ 2915static vm_size_t 2916tsize2size(unsigned int tsize) 2917{ 2918 2919 /* 2920 * size = 4^tsize KB 2921 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2922 */ 2923 2924 return ((1 << (2 * tsize)) * 1024); 2925} 2926 2927/* 2928 * Convert region size (must be power of 4) to TLB TSIZE value. 2929 */ 2930static unsigned int 2931size2tsize(vm_size_t size) 2932{ 2933 2934 return (ilog2(size) / 2 - 5); 2935} 2936 2937/* 2938 * Register permanent kernel mapping in TLB1. 2939 * 2940 * Entries are created starting from index 0 (current free entry is 2941 * kept in tlb1_idx) and are not supposed to be invalidated. 2942 */ 2943static int 2944tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2945 uint32_t flags) 2946{ 2947 uint32_t ts, tid; 2948 int tsize; 2949 2950 if (tlb1_idx >= TLB1_ENTRIES) { 2951 printf("tlb1_set_entry: TLB1 full!\n"); 2952 return (-1); 2953 } 2954 2955 /* Convert size to TSIZE */ 2956 tsize = size2tsize(size); 2957 2958 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2959 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2960 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2961 2962 /* XXX LOCK tlb1[] */ 2963 2964 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2965 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2966 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2967 2968 /* Set supervisor RWX permission bits */ 2969 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2970 2971 tlb1_write_entry(tlb1_idx++); 2972 2973 /* XXX UNLOCK tlb1[] */ 2974 2975 /* 2976 * XXX in general TLB1 updates should be propagated between CPUs, 2977 * since current design assumes to have the same TLB1 set-up on all 2978 * cores. 2979 */ 2980 return (0); 2981} 2982 2983/* 2984 * Map in contiguous RAM region into the TLB1 using maximum of 2985 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2986 * 2987 * If necessary round up last entry size and return total size 2988 * used by all allocated entries. 2989 */ 2990vm_size_t 2991tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 2992{ 2993 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 2994 vm_size_t mapped, pgsz, base, mask; 2995 int idx, nents; 2996 2997 /* Round up to the next 1M */ 2998 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 2999 3000 mapped = 0; 3001 idx = 0; 3002 base = va; 3003 pgsz = 64*1024*1024; 3004 while (mapped < size) { 3005 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3006 while (pgsz > (size - mapped)) 3007 pgsz >>= 2; 3008 pgs[idx++] = pgsz; 3009 mapped += pgsz; 3010 } 3011 3012 /* We under-map. Correct for this. */ 3013 if (mapped < size) { 3014 while (pgs[idx - 1] == pgsz) { 3015 idx--; 3016 mapped -= pgsz; 3017 } 3018 /* XXX We may increase beyond out starting point. */ 3019 pgsz <<= 2; 3020 pgs[idx++] = pgsz; 3021 mapped += pgsz; 3022 } 3023 } 3024 3025 nents = idx; 3026 mask = pgs[0] - 1; 3027 /* Align address to the boundary */ 3028 if (va & mask) { 3029 va = (va + mask) & ~mask; 3030 pa = (pa + mask) & ~mask; 3031 } 3032 3033 for (idx = 0; idx < nents; idx++) { 3034 pgsz = pgs[idx]; 3035 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3036 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3037 pa += pgsz; 3038 va += pgsz; 3039 } 3040 3041 mapped = (va - base); 3042 debugf("mapped size 0x%08x (wasted space 0x%08x)\n", 3043 mapped, mapped - size); 3044 return (mapped); 3045} 3046 3047/* 3048 * TLB1 initialization routine, to be called after the very first 3049 * assembler level setup done in locore.S. 3050 */ 3051void 3052tlb1_init(vm_offset_t ccsrbar) 3053{ 3054 uint32_t mas0, mas1, mas3; 3055 uint32_t tsz; 3056 u_int i; 3057 3058 ccsrbar_pa = ccsrbar; 3059 3060 if (bootinfo != NULL && bootinfo[0] != 1) { 3061 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3062 } else 3063 tlb1_idx = 1; 3064 3065 /* The first entry/entries are used to map the kernel. */ 3066 for (i = 0; i < tlb1_idx; i++) { 3067 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3068 mtspr(SPR_MAS0, mas0); 3069 __asm __volatile("isync; tlbre"); 3070 3071 mas1 = mfspr(SPR_MAS1); 3072 if ((mas1 & MAS1_VALID) == 0) 3073 continue; 3074 3075 mas3 = mfspr(SPR_MAS3); 3076 3077 tlb1[i].mas1 = mas1; 3078 tlb1[i].mas2 = mfspr(SPR_MAS2); 3079 tlb1[i].mas3 = mas3; 3080 3081 if (i == 0) 3082 kernload = mas3 & MAS3_RPN; 3083 3084 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3085 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3086 } 3087 3088 /* Map in CCSRBAR. */ 3089 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3090 3091#ifdef SMP 3092 bp_ntlb1s = tlb1_idx; 3093#endif 3094 3095 /* Purge the remaining entries */ 3096 for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3097 tlb1_write_entry(i); 3098 3099 /* Setup TLB miss defaults */ 3100 set_mas4_defaults(); 3101} 3102 3103/* 3104 * Setup MAS4 defaults. 3105 * These values are loaded to MAS0-2 on a TLB miss. 3106 */ 3107static void 3108set_mas4_defaults(void) 3109{ 3110 uint32_t mas4; 3111 3112 /* Defaults: TLB0, PID0, TSIZED=4K */ 3113 mas4 = MAS4_TLBSELD0; 3114 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3115#ifdef SMP 3116 mas4 |= MAS4_MD; 3117#endif 3118 mtspr(SPR_MAS4, mas4); 3119 __asm __volatile("isync"); 3120} 3121 3122/* 3123 * Print out contents of the MAS registers for each TLB1 entry 3124 */ 3125void 3126tlb1_print_tlbentries(void) 3127{ 3128 uint32_t mas0, mas1, mas2, mas3, mas7; 3129 int i; 3130 3131 debugf("TLB1 entries:\n"); 3132 for (i = 0; i < TLB1_ENTRIES; i++) { 3133 3134 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3135 mtspr(SPR_MAS0, mas0); 3136 3137 __asm __volatile("isync; tlbre"); 3138 3139 mas1 = mfspr(SPR_MAS1); 3140 mas2 = mfspr(SPR_MAS2); 3141 mas3 = mfspr(SPR_MAS3); 3142 mas7 = mfspr(SPR_MAS7); 3143 3144 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3145 } 3146} 3147 3148/* 3149 * Print out contents of the in-ram tlb1 table. 3150 */ 3151void 3152tlb1_print_entries(void) 3153{ 3154 int i; 3155 3156 debugf("tlb1[] table entries:\n"); 3157 for (i = 0; i < TLB1_ENTRIES; i++) 3158 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3159} 3160 3161/* 3162 * Return 0 if the physical IO range is encompassed by one of the 3163 * the TLB1 entries, otherwise return related error code. 3164 */ 3165static int 3166tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3167{ 3168 uint32_t prot; 3169 vm_paddr_t pa_start; 3170 vm_paddr_t pa_end; 3171 unsigned int entry_tsize; 3172 vm_size_t entry_size; 3173 3174 *va = (vm_offset_t)NULL; 3175 3176 /* Skip invalid entries */ 3177 if (!(tlb1[i].mas1 & MAS1_VALID)) 3178 return (EINVAL); 3179 3180 /* 3181 * The entry must be cache-inhibited, guarded, and r/w 3182 * so it can function as an i/o page 3183 */ 3184 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3185 if (prot != (MAS2_I | MAS2_G)) 3186 return (EPERM); 3187 3188 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3189 if (prot != (MAS3_SR | MAS3_SW)) 3190 return (EPERM); 3191 3192 /* The address should be within the entry range. */ 3193 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3194 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3195 3196 entry_size = tsize2size(entry_tsize); 3197 pa_start = tlb1[i].mas3 & MAS3_RPN; 3198 pa_end = pa_start + entry_size - 1; 3199 3200 if ((pa < pa_start) || ((pa + size) > pa_end)) 3201 return (ERANGE); 3202 3203 /* Return virtual address of this mapping. */ 3204 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3205 return (0); 3206} 3207