platform_bare.c revision 224611
1/*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 224611 2011-08-02 15:35:43Z marcel $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> 37 38#include <machine/bus.h> 39#include <machine/cpu.h> 40#include <machine/hid.h> 41#include <machine/platform.h> 42#include <machine/platformvar.h> 43#include <machine/smp.h> 44#include <machine/spr.h> 45#include <machine/vmparam.h> 46 47#include <dev/fdt/fdt_common.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50#include <dev/ofw/openfirm.h> 51 52#include <powerpc/mpc85xx/mpc85xx.h> 53 54#include "platform_if.h" 55 56#ifdef SMP 57extern void *ap_pcpu; 58extern uint8_t __boot_page[]; /* Boot page body */ 59extern uint32_t kernload_ap; /* Kernel physical load address */ 60#endif 61 62extern uint32_t *bootinfo; 63 64static int cpu, maxcpu; 65 66static int bare_probe(platform_t); 67static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 68 struct mem_region **avail, int *availsz); 69static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 70static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 71static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 72static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 73static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 74 75static void e500_reset(platform_t); 76 77static platform_method_t bare_methods[] = { 78 PLATFORMMETHOD(platform_probe, bare_probe), 79 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 80 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 81 82 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 83 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 84 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 85 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 86 87 PLATFORMMETHOD(platform_reset, e500_reset), 88 89 { 0, 0 } 90}; 91 92static platform_def_t bare_platform = { 93 "bare metal", 94 bare_methods, 95 0 96}; 97 98PLATFORM_DEF(bare_platform); 99 100static int 101bare_probe(platform_t plat) 102{ 103 uint32_t ver, sr; 104 int i, law_max, tgt; 105 106 ver = SVR_VER(mfspr(SPR_SVR)); 107 switch (ver & ~0x0008) { /* Mask Security Enabled bit */ 108 case SVR_P4080: 109 maxcpu = 8; 110 break; 111 case SVR_P4040: 112 maxcpu = 4; 113 break; 114 case SVR_MPC8572: 115 case SVR_P1020: 116 case SVR_P2020: 117 maxcpu = 2; 118 break; 119 default: 120 maxcpu = 1; 121 break; 122 } 123 124 /* 125 * Clear local access windows. Skip DRAM entries, so we don't shoot 126 * ourselves in the foot. 127 */ 128 law_max = law_getmax(); 129 for (i = 0; i < law_max; i++) { 130 sr = ccsr_read4(OCP85XX_LAWSR(i)); 131 if ((sr & 0x80000000) == 0) 132 continue; 133 tgt = (sr & 0x01f00000) >> 20; 134 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 135 tgt == OCP85XX_TGTIF_RAM_INTL) 136 continue; 137 138 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 139 } 140 141 return (BUS_PROBE_GENERIC); 142} 143 144#define MEM_REGIONS 8 145static struct mem_region avail_regions[MEM_REGIONS]; 146 147void 148bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 149 struct mem_region **avail, int *availsz) 150{ 151 uint32_t memsize; 152 int i, rv; 153 154 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 155 156 if (rv != 0) 157 return; 158 159 for (i = 0; i < *availsz; i++) { 160 if (avail_regions[i].mr_start < 1048576) { 161 avail_regions[i].mr_size = 162 avail_regions[i].mr_size - 163 (1048576 - avail_regions[i].mr_start); 164 avail_regions[i].mr_start = 1048576; 165 } 166 } 167 *avail = avail_regions; 168 169 /* On the bare metal platform phys == avail memory */ 170 *physsz = *availsz; 171 *phys = *avail; 172} 173 174static u_long 175bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 176{ 177 u_long ticks; 178 phandle_t cpus, child; 179 pcell_t freq; 180 181 if (bootinfo != NULL) 182 if (bootinfo[0] == 1) { 183 /* Backward compatibility. See 8-STABLE. */ 184 ticks = bootinfo[3] >> 3; 185 } else { 186 /* Compatbility with Juniper's loader. */ 187 ticks = bootinfo[5] >> 3; 188 } else 189 ticks = 0; 190 191 if ((cpus = OF_finddevice("/cpus")) == 0) 192 goto out; 193 194 if ((child = OF_child(cpus)) == 0) 195 goto out; 196 197 freq = 0; 198 if (OF_getprop(child, "bus-frequency", (void *)&freq, 199 sizeof(freq)) <= 0) 200 goto out; 201 202 /* 203 * Time Base and Decrementer are updated every 8 CCB bus clocks. 204 * HID0[SEL_TBCLK] = 0 205 */ 206 if (freq != 0) 207 ticks = freq / 8; 208 209out: 210 if (ticks <= 0) 211 panic("Unable to determine timebase frequency!"); 212 213 return (ticks); 214} 215 216static int 217bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 218{ 219 220 cpu = 0; 221 cpuref->cr_cpuid = cpu; 222 cpuref->cr_hwref = cpuref->cr_cpuid; 223 if (bootverbose) 224 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 225 cpu++; 226 227 return (0); 228} 229 230static int 231bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 232{ 233 234 if (cpu >= maxcpu) 235 return (ENOENT); 236 237 cpuref->cr_cpuid = cpu++; 238 cpuref->cr_hwref = cpuref->cr_cpuid; 239 if (bootverbose) 240 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 241 242 return (0); 243} 244 245static int 246bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 247{ 248 249 cpuref->cr_cpuid = mfspr(SPR_PIR); 250 cpuref->cr_hwref = cpuref->cr_cpuid; 251 252 return (0); 253} 254 255static int 256bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 257{ 258#ifdef SMP 259 uint32_t bptr, eebpcr; 260 int timeout; 261 262 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 263 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) { 264 printf("%s: CPU=%d already out of hold-off state!\n", 265 __func__, pc->pc_cpuid); 266 return (ENXIO); 267 } 268 269 ap_pcpu = pc; 270 __asm __volatile("msync; isync"); 271 272 /* 273 * Set BPTR to the physical address of the boot page 274 */ 275 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload_ap; 276 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 277 278 /* 279 * Release AP from hold-off state 280 */ 281 eebpcr |= (1 << (pc->pc_cpuid + 24)); 282 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 283 __asm __volatile("isync; msync"); 284 285 timeout = 500; 286 while (!pc->pc_awake && timeout--) 287 DELAY(1000); /* wait 1ms */ 288 289 return ((pc->pc_awake) ? 0 : EBUSY); 290#else 291 /* No SMP support */ 292 return (ENXIO); 293#endif 294} 295 296static void 297e500_reset(platform_t plat) 298{ 299 300 /* 301 * Try the dedicated reset register first. 302 * If the SoC doesn't have one, we'll fall 303 * back to using the debug control register. 304 */ 305 ccsr_write4(OCP85XX_RSTCR, 2); 306 307 /* Clear DBCR0, disables debug interrupts and events. */ 308 mtspr(SPR_DBCR0, 0); 309 __asm __volatile("isync"); 310 311 /* Enable Debug Interrupts in MSR. */ 312 mtmsr(mfmsr() | PSL_DE); 313 314 /* Enable debug interrupts and issue reset. */ 315 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 316 317 printf("Reset failed...\n"); 318 while (1); 319} 320 321