platform_bare.c revision 222392
1/*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 222392 2011-05-27 23:18:41Z marcel $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> 37 38#include <machine/bus.h> 39#include <machine/cpu.h> 40#include <machine/hid.h> 41#include <machine/platform.h> 42#include <machine/platformvar.h> 43#include <machine/smp.h> 44#include <machine/spr.h> 45#include <machine/vmparam.h> 46 47#include <dev/fdt/fdt_common.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50#include <dev/ofw/openfirm.h> 51 52#include <powerpc/mpc85xx/mpc85xx.h> 53 54#include "platform_if.h" 55 56#ifdef SMP 57extern void *ap_pcpu; 58extern uint8_t __boot_page[]; /* Boot page body */ 59extern uint32_t kernload; /* Kernel physical load address */ 60#endif 61 62extern uint32_t *bootinfo; 63 64static int cpu, maxcpu; 65 66static int bare_probe(platform_t); 67static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 68 struct mem_region **avail, int *availsz); 69static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 70static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 71static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 72static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 73static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 74 75static void e500_reset(platform_t); 76 77static platform_method_t bare_methods[] = { 78 PLATFORMMETHOD(platform_probe, bare_probe), 79 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 80 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 81 82 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 83 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 84 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 85 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 86 87 PLATFORMMETHOD(platform_reset, e500_reset), 88 89 { 0, 0 } 90}; 91 92static platform_def_t bare_platform = { 93 "bare metal", 94 bare_methods, 95 0 96}; 97 98PLATFORM_DEF(bare_platform); 99 100static int 101bare_probe(platform_t plat) 102{ 103 uint32_t ver, sr; 104 int i, law_max, tgt; 105 106 ver = SVR_VER(mfspr(SPR_SVR)); 107 108 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 || 109 ver == SVR_P1020E || ver == SVR_P1020 || 110 ver == SVR_P2020E || ver == SVR_P2020) 111 maxcpu = 2; 112 else 113 maxcpu = 1; 114 115 /* 116 * Clear local access windows. Skip DRAM entries, so we don't shoot 117 * ourselves in the foot. 118 */ 119 law_max = law_getmax(); 120 for (i = 0; i < law_max; i++) { 121 sr = ccsr_read4(OCP85XX_LAWSR(i)); 122 if ((sr & 0x80000000) == 0) 123 continue; 124 tgt = (sr & 0x01f00000) >> 20; 125 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 126 tgt == OCP85XX_TGTIF_RAM_INTL) 127 continue; 128 129 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 130 } 131 132 return (BUS_PROBE_GENERIC); 133} 134 135#define MEM_REGIONS 8 136static struct mem_region avail_regions[MEM_REGIONS]; 137 138void 139bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 140 struct mem_region **avail, int *availsz) 141{ 142 uint32_t memsize; 143 int i, rv; 144 145 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 146 147 if (rv != 0) 148 return; 149 150 for (i = 0; i < *availsz; i++) { 151 if (avail_regions[i].mr_start < 1048576) { 152 avail_regions[i].mr_size = 153 avail_regions[i].mr_size - 154 (1048576 - avail_regions[i].mr_start); 155 avail_regions[i].mr_start = 1048576; 156 } 157 } 158 *avail = avail_regions; 159 160 /* On the bare metal platform phys == avail memory */ 161 *physsz = *availsz; 162 *phys = *avail; 163} 164 165static u_long 166bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 167{ 168 u_long ticks; 169 phandle_t cpus, child; 170 pcell_t freq; 171 172 if (bootinfo != NULL) { 173 /* Backward compatibility. See 8-STABLE. */ 174 ticks = bootinfo[3] >> 3; 175 } else 176 ticks = 0; 177 178 if ((cpus = OF_finddevice("/cpus")) == 0) 179 goto out; 180 181 if ((child = OF_child(cpus)) == 0) 182 goto out; 183 184 freq = 0; 185 if (OF_getprop(child, "bus-frequency", (void *)&freq, 186 sizeof(freq)) <= 0) 187 goto out; 188 189 /* 190 * Time Base and Decrementer are updated every 8 CCB bus clocks. 191 * HID0[SEL_TBCLK] = 0 192 */ 193 if (freq != 0) 194 ticks = freq / 8; 195 196out: 197 if (ticks <= 0) 198 panic("Unable to determine timebase frequency!"); 199 200 return (ticks); 201} 202 203static int 204bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 205{ 206 207 cpu = 0; 208 cpuref->cr_cpuid = cpu; 209 cpuref->cr_hwref = cpuref->cr_cpuid; 210 if (bootverbose) 211 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 212 cpu++; 213 214 return (0); 215} 216 217static int 218bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 219{ 220 221 if (cpu >= maxcpu) 222 return (ENOENT); 223 224 cpuref->cr_cpuid = cpu++; 225 cpuref->cr_hwref = cpuref->cr_cpuid; 226 if (bootverbose) 227 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 228 229 return (0); 230} 231 232static int 233bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 234{ 235 236 cpuref->cr_cpuid = mfspr(SPR_PIR); 237 cpuref->cr_hwref = cpuref->cr_cpuid; 238 239 return (0); 240} 241 242static int 243bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 244{ 245#ifdef SMP 246 uint32_t bptr, eebpcr; 247 int timeout; 248 249 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 250 if ((eebpcr & (pc->pc_cpumask << 24)) != 0) { 251 printf("%s: CPU=%d already out of hold-off state!\n", 252 __func__, pc->pc_cpuid); 253 return (ENXIO); 254 } 255 256 ap_pcpu = pc; 257 __asm __volatile("msync; isync"); 258 259 /* 260 * Set BPTR to the physical address of the boot page 261 */ 262 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 263 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 264 265 /* 266 * Release AP from hold-off state 267 */ 268 eebpcr |= (pc->pc_cpumask << 24); 269 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 270 __asm __volatile("isync; msync"); 271 272 timeout = 500; 273 while (!pc->pc_awake && timeout--) 274 DELAY(1000); /* wait 1ms */ 275 276 return ((pc->pc_awake) ? 0 : EBUSY); 277#else 278 /* No SMP support */ 279 return (ENXIO); 280#endif 281} 282 283static void 284e500_reset(platform_t plat) 285{ 286 287 /* 288 * Try the dedicated reset register first. 289 * If the SoC doesn't have one, we'll fall 290 * back to using the debug control register. 291 */ 292 ccsr_write4(OCP85XX_RSTCR, 2); 293 294 /* Clear DBCR0, disables debug interrupts and events. */ 295 mtspr(SPR_DBCR0, 0); 296 __asm __volatile("isync"); 297 298 /* Enable Debug Interrupts in MSR. */ 299 mtmsr(mfmsr() | PSL_DE); 300 301 /* Enable debug interrupts and issue reset. */ 302 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 303 304 printf("Reset failed...\n"); 305 while (1); 306} 307 308