mmu_oea.c revision 238159
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 238159 2012-07-06 02:18:49Z alc $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/queue.h> 122#include <sys/cpuset.h> 123#include <sys/ktr.h> 124#include <sys/lock.h> 125#include <sys/msgbuf.h> 126#include <sys/mutex.h> 127#include <sys/proc.h> 128#include <sys/rwlock.h> 129#include <sys/sched.h> 130#include <sys/sysctl.h> 131#include <sys/systm.h> 132#include <sys/vmmeter.h> 133 134#include <dev/ofw/openfirm.h> 135 136#include <vm/vm.h> 137#include <vm/vm_param.h> 138#include <vm/vm_kern.h> 139#include <vm/vm_page.h> 140#include <vm/vm_map.h> 141#include <vm/vm_object.h> 142#include <vm/vm_extern.h> 143#include <vm/vm_pageout.h> 144#include <vm/vm_pager.h> 145#include <vm/uma.h> 146 147#include <machine/cpu.h> 148#include <machine/platform.h> 149#include <machine/bat.h> 150#include <machine/frame.h> 151#include <machine/md_var.h> 152#include <machine/psl.h> 153#include <machine/pte.h> 154#include <machine/smp.h> 155#include <machine/sr.h> 156#include <machine/mmuvar.h> 157#include <machine/trap_aim.h> 158 159#include "mmu_if.h" 160 161#define MOEA_DEBUG 162 163#define TODO panic("%s: not implemented", __func__); 164 165#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 166#define VSID_TO_SR(vsid) ((vsid) & 0xf) 167#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 168 169struct ofw_map { 170 vm_offset_t om_va; 171 vm_size_t om_len; 172 vm_offset_t om_pa; 173 u_int om_mode; 174}; 175 176/* 177 * Map of physical memory regions. 178 */ 179static struct mem_region *regions; 180static struct mem_region *pregions; 181static u_int phys_avail_count; 182static int regions_sz, pregions_sz; 183static struct ofw_map *translations; 184 185/* 186 * Lock for the pteg and pvo tables. 187 */ 188struct mtx moea_table_mutex; 189struct mtx moea_vsid_mutex; 190 191/* tlbie instruction synchronization */ 192static struct mtx tlbie_mtx; 193 194/* 195 * PTEG data. 196 */ 197static struct pteg *moea_pteg_table; 198u_int moea_pteg_count; 199u_int moea_pteg_mask; 200 201/* 202 * PVO data. 203 */ 204struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 205struct pvo_head moea_pvo_kunmanaged = 206 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 207 208/* 209 * Isolate the global pv list lock from data and other locks to prevent false 210 * sharing within the cache. 211 */ 212static struct { 213 struct rwlock lock; 214 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)]; 215} pvh_global __aligned(CACHE_LINE_SIZE); 216 217#define pvh_global_lock pvh_global.lock 218 219uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 220uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 221 222#define BPVO_POOL_SIZE 32768 223static struct pvo_entry *moea_bpvo_pool; 224static int moea_bpvo_pool_index = 0; 225 226#define VSID_NBPW (sizeof(u_int32_t) * 8) 227static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 228 229static boolean_t moea_initialized = FALSE; 230 231/* 232 * Statistics. 233 */ 234u_int moea_pte_valid = 0; 235u_int moea_pte_overflow = 0; 236u_int moea_pte_replacements = 0; 237u_int moea_pvo_entries = 0; 238u_int moea_pvo_enter_calls = 0; 239u_int moea_pvo_remove_calls = 0; 240u_int moea_pte_spills = 0; 241SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 242 0, ""); 243SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 244 &moea_pte_overflow, 0, ""); 245SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 246 &moea_pte_replacements, 0, ""); 247SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 248 0, ""); 249SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 250 &moea_pvo_enter_calls, 0, ""); 251SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 252 &moea_pvo_remove_calls, 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 254 &moea_pte_spills, 0, ""); 255 256/* 257 * Allocate physical memory for use in moea_bootstrap. 258 */ 259static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 260 261/* 262 * PTE calls. 263 */ 264static int moea_pte_insert(u_int, struct pte *); 265 266/* 267 * PVO calls. 268 */ 269static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 270 vm_offset_t, vm_offset_t, u_int, int); 271static void moea_pvo_remove(struct pvo_entry *, int); 272static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 273static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 274 275/* 276 * Utility routines. 277 */ 278static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 279 vm_prot_t, boolean_t); 280static void moea_syncicache(vm_offset_t, vm_size_t); 281static boolean_t moea_query_bit(vm_page_t, int); 282static u_int moea_clear_bit(vm_page_t, int); 283static void moea_kremove(mmu_t, vm_offset_t); 284int moea_pte_spill(vm_offset_t); 285 286/* 287 * Kernel MMU interface 288 */ 289void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 290void moea_clear_modify(mmu_t, vm_page_t); 291void moea_clear_reference(mmu_t, vm_page_t); 292void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 293void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 294void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 295 vm_prot_t); 296void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 297vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 298vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 299void moea_init(mmu_t); 300boolean_t moea_is_modified(mmu_t, vm_page_t); 301boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 302boolean_t moea_is_referenced(mmu_t, vm_page_t); 303boolean_t moea_ts_referenced(mmu_t, vm_page_t); 304vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 305boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 306int moea_page_wired_mappings(mmu_t, vm_page_t); 307void moea_pinit(mmu_t, pmap_t); 308void moea_pinit0(mmu_t, pmap_t); 309void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 310void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 311void moea_qremove(mmu_t, vm_offset_t, int); 312void moea_release(mmu_t, pmap_t); 313void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 314void moea_remove_all(mmu_t, vm_page_t); 315void moea_remove_write(mmu_t, vm_page_t); 316void moea_zero_page(mmu_t, vm_page_t); 317void moea_zero_page_area(mmu_t, vm_page_t, int, int); 318void moea_zero_page_idle(mmu_t, vm_page_t); 319void moea_activate(mmu_t, struct thread *); 320void moea_deactivate(mmu_t, struct thread *); 321void moea_cpu_bootstrap(mmu_t, int); 322void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 323void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 324void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 325void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 326vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 327void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 328void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 329void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 330boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 331static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 332 333static mmu_method_t moea_methods[] = { 334 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 335 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 336 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 337 MMUMETHOD(mmu_copy_page, moea_copy_page), 338 MMUMETHOD(mmu_enter, moea_enter), 339 MMUMETHOD(mmu_enter_object, moea_enter_object), 340 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 341 MMUMETHOD(mmu_extract, moea_extract), 342 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 343 MMUMETHOD(mmu_init, moea_init), 344 MMUMETHOD(mmu_is_modified, moea_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 348 MMUMETHOD(mmu_map, moea_map), 349 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 350 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 351 MMUMETHOD(mmu_pinit, moea_pinit), 352 MMUMETHOD(mmu_pinit0, moea_pinit0), 353 MMUMETHOD(mmu_protect, moea_protect), 354 MMUMETHOD(mmu_qenter, moea_qenter), 355 MMUMETHOD(mmu_qremove, moea_qremove), 356 MMUMETHOD(mmu_release, moea_release), 357 MMUMETHOD(mmu_remove, moea_remove), 358 MMUMETHOD(mmu_remove_all, moea_remove_all), 359 MMUMETHOD(mmu_remove_write, moea_remove_write), 360 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 361 MMUMETHOD(mmu_zero_page, moea_zero_page), 362 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 363 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 364 MMUMETHOD(mmu_activate, moea_activate), 365 MMUMETHOD(mmu_deactivate, moea_deactivate), 366 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 370 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 371 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 372 MMUMETHOD(mmu_mapdev, moea_mapdev), 373 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 374 MMUMETHOD(mmu_kextract, moea_kextract), 375 MMUMETHOD(mmu_kenter, moea_kenter), 376 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378 379 { 0, 0 } 380}; 381 382MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 383 384static __inline uint32_t 385moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 386{ 387 uint32_t pte_lo; 388 int i; 389 390 if (ma != VM_MEMATTR_DEFAULT) { 391 switch (ma) { 392 case VM_MEMATTR_UNCACHEABLE: 393 return (PTE_I | PTE_G); 394 case VM_MEMATTR_WRITE_COMBINING: 395 case VM_MEMATTR_WRITE_BACK: 396 case VM_MEMATTR_PREFETCHABLE: 397 return (PTE_I); 398 case VM_MEMATTR_WRITE_THROUGH: 399 return (PTE_W | PTE_M); 400 } 401 } 402 403 /* 404 * Assume the page is cache inhibited and access is guarded unless 405 * it's in our available memory array. 406 */ 407 pte_lo = PTE_I | PTE_G; 408 for (i = 0; i < pregions_sz; i++) { 409 if ((pa >= pregions[i].mr_start) && 410 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 411 pte_lo = PTE_M; 412 break; 413 } 414 } 415 416 return pte_lo; 417} 418 419static void 420tlbie(vm_offset_t va) 421{ 422 423 mtx_lock_spin(&tlbie_mtx); 424 __asm __volatile("ptesync"); 425 __asm __volatile("tlbie %0" :: "r"(va)); 426 __asm __volatile("eieio; tlbsync; ptesync"); 427 mtx_unlock_spin(&tlbie_mtx); 428} 429 430static void 431tlbia(void) 432{ 433 vm_offset_t va; 434 435 for (va = 0; va < 0x00040000; va += 0x00001000) { 436 __asm __volatile("tlbie %0" :: "r"(va)); 437 powerpc_sync(); 438 } 439 __asm __volatile("tlbsync"); 440 powerpc_sync(); 441} 442 443static __inline int 444va_to_sr(u_int *sr, vm_offset_t va) 445{ 446 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 447} 448 449static __inline u_int 450va_to_pteg(u_int sr, vm_offset_t addr) 451{ 452 u_int hash; 453 454 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 455 ADDR_PIDX_SHFT); 456 return (hash & moea_pteg_mask); 457} 458 459static __inline struct pvo_head * 460vm_page_to_pvoh(vm_page_t m) 461{ 462 463 return (&m->md.mdpg_pvoh); 464} 465 466static __inline void 467moea_attr_clear(vm_page_t m, int ptebit) 468{ 469 470 rw_assert(&pvh_global_lock, RA_WLOCKED); 471 m->md.mdpg_attrs &= ~ptebit; 472} 473 474static __inline int 475moea_attr_fetch(vm_page_t m) 476{ 477 478 return (m->md.mdpg_attrs); 479} 480 481static __inline void 482moea_attr_save(vm_page_t m, int ptebit) 483{ 484 485 rw_assert(&pvh_global_lock, RA_WLOCKED); 486 m->md.mdpg_attrs |= ptebit; 487} 488 489static __inline int 490moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 491{ 492 if (pt->pte_hi == pvo_pt->pte_hi) 493 return (1); 494 495 return (0); 496} 497 498static __inline int 499moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 500{ 501 return (pt->pte_hi & ~PTE_VALID) == 502 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 503 ((va >> ADDR_API_SHFT) & PTE_API) | which); 504} 505 506static __inline void 507moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 508{ 509 510 mtx_assert(&moea_table_mutex, MA_OWNED); 511 512 /* 513 * Construct a PTE. Default to IMB initially. Valid bit only gets 514 * set when the real pte is set in memory. 515 * 516 * Note: Don't set the valid bit for correct operation of tlb update. 517 */ 518 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 519 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 520 pt->pte_lo = pte_lo; 521} 522 523static __inline void 524moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 525{ 526 527 mtx_assert(&moea_table_mutex, MA_OWNED); 528 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 529} 530 531static __inline void 532moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 533{ 534 535 mtx_assert(&moea_table_mutex, MA_OWNED); 536 537 /* 538 * As shown in Section 7.6.3.2.3 539 */ 540 pt->pte_lo &= ~ptebit; 541 tlbie(va); 542} 543 544static __inline void 545moea_pte_set(struct pte *pt, struct pte *pvo_pt) 546{ 547 548 mtx_assert(&moea_table_mutex, MA_OWNED); 549 pvo_pt->pte_hi |= PTE_VALID; 550 551 /* 552 * Update the PTE as defined in section 7.6.3.1. 553 * Note that the REF/CHG bits are from pvo_pt and thus should havce 554 * been saved so this routine can restore them (if desired). 555 */ 556 pt->pte_lo = pvo_pt->pte_lo; 557 powerpc_sync(); 558 pt->pte_hi = pvo_pt->pte_hi; 559 powerpc_sync(); 560 moea_pte_valid++; 561} 562 563static __inline void 564moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 565{ 566 567 mtx_assert(&moea_table_mutex, MA_OWNED); 568 pvo_pt->pte_hi &= ~PTE_VALID; 569 570 /* 571 * Force the reg & chg bits back into the PTEs. 572 */ 573 powerpc_sync(); 574 575 /* 576 * Invalidate the pte. 577 */ 578 pt->pte_hi &= ~PTE_VALID; 579 580 tlbie(va); 581 582 /* 583 * Save the reg & chg bits. 584 */ 585 moea_pte_synch(pt, pvo_pt); 586 moea_pte_valid--; 587} 588 589static __inline void 590moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 591{ 592 593 /* 594 * Invalidate the PTE 595 */ 596 moea_pte_unset(pt, pvo_pt, va); 597 moea_pte_set(pt, pvo_pt); 598} 599 600/* 601 * Quick sort callout for comparing memory regions. 602 */ 603static int om_cmp(const void *a, const void *b); 604 605static int 606om_cmp(const void *a, const void *b) 607{ 608 const struct ofw_map *mapa; 609 const struct ofw_map *mapb; 610 611 mapa = a; 612 mapb = b; 613 if (mapa->om_pa < mapb->om_pa) 614 return (-1); 615 else if (mapa->om_pa > mapb->om_pa) 616 return (1); 617 else 618 return (0); 619} 620 621void 622moea_cpu_bootstrap(mmu_t mmup, int ap) 623{ 624 u_int sdr; 625 int i; 626 627 if (ap) { 628 powerpc_sync(); 629 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 630 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 631 isync(); 632 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 633 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 634 isync(); 635 } 636 637 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 638 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 639 isync(); 640 641 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 642 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 643 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 644 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 645 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 646 isync(); 647 648 for (i = 0; i < 16; i++) 649 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 650 powerpc_sync(); 651 652 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 653 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 654 isync(); 655 656 tlbia(); 657} 658 659void 660moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 661{ 662 ihandle_t mmui; 663 phandle_t chosen, mmu; 664 int sz; 665 int i, j; 666 vm_size_t size, physsz, hwphyssz; 667 vm_offset_t pa, va, off; 668 void *dpcpu; 669 register_t msr; 670 671 /* 672 * Set up BAT0 to map the lowest 256 MB area 673 */ 674 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 675 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 676 677 /* 678 * Map PCI memory space. 679 */ 680 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 681 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 682 683 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 684 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 685 686 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 687 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 688 689 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 690 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 691 692 /* 693 * Map obio devices. 694 */ 695 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 696 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 697 698 /* 699 * Use an IBAT and a DBAT to map the bottom segment of memory 700 * where we are. Turn off instruction relocation temporarily 701 * to prevent faults while reprogramming the IBAT. 702 */ 703 msr = mfmsr(); 704 mtmsr(msr & ~PSL_IR); 705 __asm (".balign 32; \n" 706 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 707 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 708 :: "r"(battable[0].batu), "r"(battable[0].batl)); 709 mtmsr(msr); 710 711 /* map pci space */ 712 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 713 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 714 isync(); 715 716 /* set global direct map flag */ 717 hw_direct_map = 1; 718 719 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 720 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 721 722 for (i = 0; i < pregions_sz; i++) { 723 vm_offset_t pa; 724 vm_offset_t end; 725 726 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 727 pregions[i].mr_start, 728 pregions[i].mr_start + pregions[i].mr_size, 729 pregions[i].mr_size); 730 /* 731 * Install entries into the BAT table to allow all 732 * of physmem to be convered by on-demand BAT entries. 733 * The loop will sometimes set the same battable element 734 * twice, but that's fine since they won't be used for 735 * a while yet. 736 */ 737 pa = pregions[i].mr_start & 0xf0000000; 738 end = pregions[i].mr_start + pregions[i].mr_size; 739 do { 740 u_int n = pa >> ADDR_SR_SHFT; 741 742 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 743 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 744 pa += SEGMENT_LENGTH; 745 } while (pa < end); 746 } 747 748 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 749 panic("moea_bootstrap: phys_avail too small"); 750 751 phys_avail_count = 0; 752 physsz = 0; 753 hwphyssz = 0; 754 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 755 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 756 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 757 regions[i].mr_start + regions[i].mr_size, 758 regions[i].mr_size); 759 if (hwphyssz != 0 && 760 (physsz + regions[i].mr_size) >= hwphyssz) { 761 if (physsz < hwphyssz) { 762 phys_avail[j] = regions[i].mr_start; 763 phys_avail[j + 1] = regions[i].mr_start + 764 hwphyssz - physsz; 765 physsz = hwphyssz; 766 phys_avail_count++; 767 } 768 break; 769 } 770 phys_avail[j] = regions[i].mr_start; 771 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 772 phys_avail_count++; 773 physsz += regions[i].mr_size; 774 } 775 776 /* Check for overlap with the kernel and exception vectors */ 777 for (j = 0; j < 2*phys_avail_count; j+=2) { 778 if (phys_avail[j] < EXC_LAST) 779 phys_avail[j] += EXC_LAST; 780 781 if (kernelstart >= phys_avail[j] && 782 kernelstart < phys_avail[j+1]) { 783 if (kernelend < phys_avail[j+1]) { 784 phys_avail[2*phys_avail_count] = 785 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 786 phys_avail[2*phys_avail_count + 1] = 787 phys_avail[j+1]; 788 phys_avail_count++; 789 } 790 791 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 792 } 793 794 if (kernelend >= phys_avail[j] && 795 kernelend < phys_avail[j+1]) { 796 if (kernelstart > phys_avail[j]) { 797 phys_avail[2*phys_avail_count] = phys_avail[j]; 798 phys_avail[2*phys_avail_count + 1] = 799 kernelstart & ~PAGE_MASK; 800 phys_avail_count++; 801 } 802 803 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 804 } 805 } 806 807 physmem = btoc(physsz); 808 809 /* 810 * Allocate PTEG table. 811 */ 812#ifdef PTEGCOUNT 813 moea_pteg_count = PTEGCOUNT; 814#else 815 moea_pteg_count = 0x1000; 816 817 while (moea_pteg_count < physmem) 818 moea_pteg_count <<= 1; 819 820 moea_pteg_count >>= 1; 821#endif /* PTEGCOUNT */ 822 823 size = moea_pteg_count * sizeof(struct pteg); 824 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 825 size); 826 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 827 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 828 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 829 moea_pteg_mask = moea_pteg_count - 1; 830 831 /* 832 * Allocate pv/overflow lists. 833 */ 834 size = sizeof(struct pvo_head) * moea_pteg_count; 835 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 836 PAGE_SIZE); 837 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 838 for (i = 0; i < moea_pteg_count; i++) 839 LIST_INIT(&moea_pvo_table[i]); 840 841 /* 842 * Initialize the lock that synchronizes access to the pteg and pvo 843 * tables. 844 */ 845 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 846 MTX_RECURSE); 847 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 848 849 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 850 851 /* 852 * Initialise the unmanaged pvo pool. 853 */ 854 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 855 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 856 moea_bpvo_pool_index = 0; 857 858 /* 859 * Make sure kernel vsid is allocated as well as VSID 0. 860 */ 861 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 862 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 863 moea_vsid_bitmap[0] |= 1; 864 865 /* 866 * Initialize the kernel pmap (which is statically allocated). 867 */ 868 PMAP_LOCK_INIT(kernel_pmap); 869 for (i = 0; i < 16; i++) 870 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 871 CPU_FILL(&kernel_pmap->pm_active); 872 RB_INIT(&kernel_pmap->pmap_pvo); 873 874 /* 875 * Initialize the global pv list lock. 876 */ 877 rw_init(&pvh_global_lock, "pmap pv global"); 878 879 /* 880 * Set up the Open Firmware mappings 881 */ 882 chosen = OF_finddevice("/chosen"); 883 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 884 (mmu = OF_instance_to_package(mmui)) != -1 && 885 (sz = OF_getproplen(mmu, "translations")) != -1) { 886 translations = NULL; 887 for (i = 0; phys_avail[i] != 0; i += 2) { 888 if (phys_avail[i + 1] >= sz) { 889 translations = (struct ofw_map *)phys_avail[i]; 890 break; 891 } 892 } 893 if (translations == NULL) 894 panic("moea_bootstrap: no space to copy translations"); 895 bzero(translations, sz); 896 if (OF_getprop(mmu, "translations", translations, sz) == -1) 897 panic("moea_bootstrap: can't get ofw translations"); 898 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 899 sz /= sizeof(*translations); 900 qsort(translations, sz, sizeof (*translations), om_cmp); 901 for (i = 0; i < sz; i++) { 902 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 903 translations[i].om_pa, translations[i].om_va, 904 translations[i].om_len); 905 906 /* 907 * If the mapping is 1:1, let the RAM and device 908 * on-demand BAT tables take care of the translation. 909 */ 910 if (translations[i].om_va == translations[i].om_pa) 911 continue; 912 913 /* Enter the pages */ 914 for (off = 0; off < translations[i].om_len; 915 off += PAGE_SIZE) 916 moea_kenter(mmup, translations[i].om_va + off, 917 translations[i].om_pa + off); 918 } 919 } 920 921 /* 922 * Calculate the last available physical address. 923 */ 924 for (i = 0; phys_avail[i + 2] != 0; i += 2) 925 ; 926 Maxmem = powerpc_btop(phys_avail[i + 1]); 927 928 moea_cpu_bootstrap(mmup,0); 929 930 pmap_bootstrapped++; 931 932 /* 933 * Set the start and end of kva. 934 */ 935 virtual_avail = VM_MIN_KERNEL_ADDRESS; 936 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 937 938 /* 939 * Allocate a kernel stack with a guard page for thread0 and map it 940 * into the kernel page map. 941 */ 942 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 943 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 944 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 945 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 946 thread0.td_kstack = va; 947 thread0.td_kstack_pages = KSTACK_PAGES; 948 for (i = 0; i < KSTACK_PAGES; i++) { 949 moea_kenter(mmup, va, pa); 950 pa += PAGE_SIZE; 951 va += PAGE_SIZE; 952 } 953 954 /* 955 * Allocate virtual address space for the message buffer. 956 */ 957 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 958 msgbufp = (struct msgbuf *)virtual_avail; 959 va = virtual_avail; 960 virtual_avail += round_page(msgbufsize); 961 while (va < virtual_avail) { 962 moea_kenter(mmup, va, pa); 963 pa += PAGE_SIZE; 964 va += PAGE_SIZE; 965 } 966 967 /* 968 * Allocate virtual address space for the dynamic percpu area. 969 */ 970 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 971 dpcpu = (void *)virtual_avail; 972 va = virtual_avail; 973 virtual_avail += DPCPU_SIZE; 974 while (va < virtual_avail) { 975 moea_kenter(mmup, va, pa); 976 pa += PAGE_SIZE; 977 va += PAGE_SIZE; 978 } 979 dpcpu_init(dpcpu, 0); 980} 981 982/* 983 * Activate a user pmap. The pmap must be activated before it's address 984 * space can be accessed in any way. 985 */ 986void 987moea_activate(mmu_t mmu, struct thread *td) 988{ 989 pmap_t pm, pmr; 990 991 /* 992 * Load all the data we need up front to encourage the compiler to 993 * not issue any loads while we have interrupts disabled below. 994 */ 995 pm = &td->td_proc->p_vmspace->vm_pmap; 996 pmr = pm->pmap_phys; 997 998 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 999 PCPU_SET(curpmap, pmr); 1000} 1001 1002void 1003moea_deactivate(mmu_t mmu, struct thread *td) 1004{ 1005 pmap_t pm; 1006 1007 pm = &td->td_proc->p_vmspace->vm_pmap; 1008 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1009 PCPU_SET(curpmap, NULL); 1010} 1011 1012void 1013moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1014{ 1015 struct pvo_entry *pvo; 1016 1017 PMAP_LOCK(pm); 1018 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1019 1020 if (pvo != NULL) { 1021 if (wired) { 1022 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1023 pm->pm_stats.wired_count++; 1024 pvo->pvo_vaddr |= PVO_WIRED; 1025 } else { 1026 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1027 pm->pm_stats.wired_count--; 1028 pvo->pvo_vaddr &= ~PVO_WIRED; 1029 } 1030 } 1031 PMAP_UNLOCK(pm); 1032} 1033 1034void 1035moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1036{ 1037 vm_offset_t dst; 1038 vm_offset_t src; 1039 1040 dst = VM_PAGE_TO_PHYS(mdst); 1041 src = VM_PAGE_TO_PHYS(msrc); 1042 1043 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1044} 1045 1046/* 1047 * Zero a page of physical memory by temporarily mapping it into the tlb. 1048 */ 1049void 1050moea_zero_page(mmu_t mmu, vm_page_t m) 1051{ 1052 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1053 void *va = (void *)pa; 1054 1055 bzero(va, PAGE_SIZE); 1056} 1057 1058void 1059moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1060{ 1061 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1062 void *va = (void *)(pa + off); 1063 1064 bzero(va, size); 1065} 1066 1067void 1068moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1069{ 1070 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1071 void *va = (void *)pa; 1072 1073 bzero(va, PAGE_SIZE); 1074} 1075 1076/* 1077 * Map the given physical page at the specified virtual address in the 1078 * target pmap with the protection requested. If specified the page 1079 * will be wired down. 1080 */ 1081void 1082moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1083 boolean_t wired) 1084{ 1085 1086 rw_wlock(&pvh_global_lock); 1087 PMAP_LOCK(pmap); 1088 moea_enter_locked(pmap, va, m, prot, wired); 1089 rw_wunlock(&pvh_global_lock); 1090 PMAP_UNLOCK(pmap); 1091} 1092 1093/* 1094 * Map the given physical page at the specified virtual address in the 1095 * target pmap with the protection requested. If specified the page 1096 * will be wired down. 1097 * 1098 * The page queues and pmap must be locked. 1099 */ 1100static void 1101moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1102 boolean_t wired) 1103{ 1104 struct pvo_head *pvo_head; 1105 uma_zone_t zone; 1106 vm_page_t pg; 1107 u_int pte_lo, pvo_flags; 1108 int error; 1109 1110 if (!moea_initialized) { 1111 pvo_head = &moea_pvo_kunmanaged; 1112 zone = moea_upvo_zone; 1113 pvo_flags = 0; 1114 pg = NULL; 1115 } else { 1116 pvo_head = vm_page_to_pvoh(m); 1117 pg = m; 1118 zone = moea_mpvo_zone; 1119 pvo_flags = PVO_MANAGED; 1120 } 1121 if (pmap_bootstrapped) 1122 rw_assert(&pvh_global_lock, RA_WLOCKED); 1123 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1124 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 1125 VM_OBJECT_LOCKED(m->object), 1126 ("moea_enter_locked: page %p is not busy", m)); 1127 1128 /* XXX change the pvo head for fake pages */ 1129 if ((m->oflags & VPO_UNMANAGED) != 0) { 1130 pvo_flags &= ~PVO_MANAGED; 1131 pvo_head = &moea_pvo_kunmanaged; 1132 zone = moea_upvo_zone; 1133 } 1134 1135 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1136 1137 if (prot & VM_PROT_WRITE) { 1138 pte_lo |= PTE_BW; 1139 if (pmap_bootstrapped && 1140 (m->oflags & VPO_UNMANAGED) == 0) 1141 vm_page_aflag_set(m, PGA_WRITEABLE); 1142 } else 1143 pte_lo |= PTE_BR; 1144 1145 if (prot & VM_PROT_EXECUTE) 1146 pvo_flags |= PVO_EXECUTABLE; 1147 1148 if (wired) 1149 pvo_flags |= PVO_WIRED; 1150 1151 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1152 pte_lo, pvo_flags); 1153 1154 /* 1155 * Flush the real page from the instruction cache. This has be done 1156 * for all user mappings to prevent information leakage via the 1157 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1158 * mapping for a page. 1159 */ 1160 if (pmap != kernel_pmap && error == ENOENT && 1161 (pte_lo & (PTE_I | PTE_G)) == 0) 1162 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1163} 1164 1165/* 1166 * Maps a sequence of resident pages belonging to the same object. 1167 * The sequence begins with the given page m_start. This page is 1168 * mapped at the given virtual address start. Each subsequent page is 1169 * mapped at a virtual address that is offset from start by the same 1170 * amount as the page is offset from m_start within the object. The 1171 * last page in the sequence is the page with the largest offset from 1172 * m_start that can be mapped at a virtual address less than the given 1173 * virtual address end. Not every virtual page between start and end 1174 * is mapped; only those for which a resident page exists with the 1175 * corresponding offset from m_start are mapped. 1176 */ 1177void 1178moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1179 vm_page_t m_start, vm_prot_t prot) 1180{ 1181 vm_page_t m; 1182 vm_pindex_t diff, psize; 1183 1184 psize = atop(end - start); 1185 m = m_start; 1186 rw_wlock(&pvh_global_lock); 1187 PMAP_LOCK(pm); 1188 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1189 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1190 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1191 m = TAILQ_NEXT(m, listq); 1192 } 1193 rw_wunlock(&pvh_global_lock); 1194 PMAP_UNLOCK(pm); 1195} 1196 1197void 1198moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1199 vm_prot_t prot) 1200{ 1201 1202 rw_wlock(&pvh_global_lock); 1203 PMAP_LOCK(pm); 1204 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1205 FALSE); 1206 rw_wunlock(&pvh_global_lock); 1207 PMAP_UNLOCK(pm); 1208} 1209 1210vm_paddr_t 1211moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1212{ 1213 struct pvo_entry *pvo; 1214 vm_paddr_t pa; 1215 1216 PMAP_LOCK(pm); 1217 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1218 if (pvo == NULL) 1219 pa = 0; 1220 else 1221 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1222 PMAP_UNLOCK(pm); 1223 return (pa); 1224} 1225 1226/* 1227 * Atomically extract and hold the physical page with the given 1228 * pmap and virtual address pair if that mapping permits the given 1229 * protection. 1230 */ 1231vm_page_t 1232moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1233{ 1234 struct pvo_entry *pvo; 1235 vm_page_t m; 1236 vm_paddr_t pa; 1237 1238 m = NULL; 1239 pa = 0; 1240 PMAP_LOCK(pmap); 1241retry: 1242 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1243 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1244 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1245 (prot & VM_PROT_WRITE) == 0)) { 1246 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1247 goto retry; 1248 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1249 vm_page_hold(m); 1250 } 1251 PA_UNLOCK_COND(pa); 1252 PMAP_UNLOCK(pmap); 1253 return (m); 1254} 1255 1256void 1257moea_init(mmu_t mmu) 1258{ 1259 1260 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1261 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1262 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1263 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1264 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1265 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1266 moea_initialized = TRUE; 1267} 1268 1269boolean_t 1270moea_is_referenced(mmu_t mmu, vm_page_t m) 1271{ 1272 1273 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1274 ("moea_is_referenced: page %p is not managed", m)); 1275 return (moea_query_bit(m, PTE_REF)); 1276} 1277 1278boolean_t 1279moea_is_modified(mmu_t mmu, vm_page_t m) 1280{ 1281 1282 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1283 ("moea_is_modified: page %p is not managed", m)); 1284 1285 /* 1286 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 1287 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1288 * is clear, no PTEs can have PTE_CHG set. 1289 */ 1290 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1291 if ((m->oflags & VPO_BUSY) == 0 && 1292 (m->aflags & PGA_WRITEABLE) == 0) 1293 return (FALSE); 1294 return (moea_query_bit(m, PTE_CHG)); 1295} 1296 1297boolean_t 1298moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1299{ 1300 struct pvo_entry *pvo; 1301 boolean_t rv; 1302 1303 PMAP_LOCK(pmap); 1304 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1305 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1306 PMAP_UNLOCK(pmap); 1307 return (rv); 1308} 1309 1310void 1311moea_clear_reference(mmu_t mmu, vm_page_t m) 1312{ 1313 1314 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1315 ("moea_clear_reference: page %p is not managed", m)); 1316 moea_clear_bit(m, PTE_REF); 1317} 1318 1319void 1320moea_clear_modify(mmu_t mmu, vm_page_t m) 1321{ 1322 1323 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1324 ("moea_clear_modify: page %p is not managed", m)); 1325 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1326 KASSERT((m->oflags & VPO_BUSY) == 0, 1327 ("moea_clear_modify: page %p is busy", m)); 1328 1329 /* 1330 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1331 * set. If the object containing the page is locked and the page is 1332 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 1333 */ 1334 if ((m->aflags & PGA_WRITEABLE) == 0) 1335 return; 1336 moea_clear_bit(m, PTE_CHG); 1337} 1338 1339/* 1340 * Clear the write and modified bits in each of the given page's mappings. 1341 */ 1342void 1343moea_remove_write(mmu_t mmu, vm_page_t m) 1344{ 1345 struct pvo_entry *pvo; 1346 struct pte *pt; 1347 pmap_t pmap; 1348 u_int lo; 1349 1350 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1351 ("moea_remove_write: page %p is not managed", m)); 1352 1353 /* 1354 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 1355 * another thread while the object is locked. Thus, if PGA_WRITEABLE 1356 * is clear, no page table entries need updating. 1357 */ 1358 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1359 if ((m->oflags & VPO_BUSY) == 0 && 1360 (m->aflags & PGA_WRITEABLE) == 0) 1361 return; 1362 rw_wlock(&pvh_global_lock); 1363 lo = moea_attr_fetch(m); 1364 powerpc_sync(); 1365 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1366 pmap = pvo->pvo_pmap; 1367 PMAP_LOCK(pmap); 1368 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1369 pt = moea_pvo_to_pte(pvo, -1); 1370 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1371 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1372 if (pt != NULL) { 1373 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1374 lo |= pvo->pvo_pte.pte.pte_lo; 1375 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1376 moea_pte_change(pt, &pvo->pvo_pte.pte, 1377 pvo->pvo_vaddr); 1378 mtx_unlock(&moea_table_mutex); 1379 } 1380 } 1381 PMAP_UNLOCK(pmap); 1382 } 1383 if ((lo & PTE_CHG) != 0) { 1384 moea_attr_clear(m, PTE_CHG); 1385 vm_page_dirty(m); 1386 } 1387 vm_page_aflag_clear(m, PGA_WRITEABLE); 1388 rw_wunlock(&pvh_global_lock); 1389} 1390 1391/* 1392 * moea_ts_referenced: 1393 * 1394 * Return a count of reference bits for a page, clearing those bits. 1395 * It is not necessary for every reference bit to be cleared, but it 1396 * is necessary that 0 only be returned when there are truly no 1397 * reference bits set. 1398 * 1399 * XXX: The exact number of bits to check and clear is a matter that 1400 * should be tested and standardized at some point in the future for 1401 * optimal aging of shared pages. 1402 */ 1403boolean_t 1404moea_ts_referenced(mmu_t mmu, vm_page_t m) 1405{ 1406 1407 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1408 ("moea_ts_referenced: page %p is not managed", m)); 1409 return (moea_clear_bit(m, PTE_REF)); 1410} 1411 1412/* 1413 * Modify the WIMG settings of all mappings for a page. 1414 */ 1415void 1416moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1417{ 1418 struct pvo_entry *pvo; 1419 struct pvo_head *pvo_head; 1420 struct pte *pt; 1421 pmap_t pmap; 1422 u_int lo; 1423 1424 if ((m->oflags & VPO_UNMANAGED) != 0) { 1425 m->md.mdpg_cache_attrs = ma; 1426 return; 1427 } 1428 1429 rw_wlock(&pvh_global_lock); 1430 pvo_head = vm_page_to_pvoh(m); 1431 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1432 1433 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1434 pmap = pvo->pvo_pmap; 1435 PMAP_LOCK(pmap); 1436 pt = moea_pvo_to_pte(pvo, -1); 1437 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1438 pvo->pvo_pte.pte.pte_lo |= lo; 1439 if (pt != NULL) { 1440 moea_pte_change(pt, &pvo->pvo_pte.pte, 1441 pvo->pvo_vaddr); 1442 if (pvo->pvo_pmap == kernel_pmap) 1443 isync(); 1444 } 1445 mtx_unlock(&moea_table_mutex); 1446 PMAP_UNLOCK(pmap); 1447 } 1448 m->md.mdpg_cache_attrs = ma; 1449 rw_wunlock(&pvh_global_lock); 1450} 1451 1452/* 1453 * Map a wired page into kernel virtual address space. 1454 */ 1455void 1456moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1457{ 1458 1459 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1460} 1461 1462void 1463moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1464{ 1465 u_int pte_lo; 1466 int error; 1467 1468#if 0 1469 if (va < VM_MIN_KERNEL_ADDRESS) 1470 panic("moea_kenter: attempt to enter non-kernel address %#x", 1471 va); 1472#endif 1473 1474 pte_lo = moea_calc_wimg(pa, ma); 1475 1476 PMAP_LOCK(kernel_pmap); 1477 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1478 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1479 1480 if (error != 0 && error != ENOENT) 1481 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1482 pa, error); 1483 1484 PMAP_UNLOCK(kernel_pmap); 1485} 1486 1487/* 1488 * Extract the physical page address associated with the given kernel virtual 1489 * address. 1490 */ 1491vm_paddr_t 1492moea_kextract(mmu_t mmu, vm_offset_t va) 1493{ 1494 struct pvo_entry *pvo; 1495 vm_paddr_t pa; 1496 1497 /* 1498 * Allow direct mappings on 32-bit OEA 1499 */ 1500 if (va < VM_MIN_KERNEL_ADDRESS) { 1501 return (va); 1502 } 1503 1504 PMAP_LOCK(kernel_pmap); 1505 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1506 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1507 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1508 PMAP_UNLOCK(kernel_pmap); 1509 return (pa); 1510} 1511 1512/* 1513 * Remove a wired page from kernel virtual address space. 1514 */ 1515void 1516moea_kremove(mmu_t mmu, vm_offset_t va) 1517{ 1518 1519 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1520} 1521 1522/* 1523 * Map a range of physical addresses into kernel virtual address space. 1524 * 1525 * The value passed in *virt is a suggested virtual address for the mapping. 1526 * Architectures which can support a direct-mapped physical to virtual region 1527 * can return the appropriate address within that region, leaving '*virt' 1528 * unchanged. We cannot and therefore do not; *virt is updated with the 1529 * first usable address after the mapped region. 1530 */ 1531vm_offset_t 1532moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1533 vm_paddr_t pa_end, int prot) 1534{ 1535 vm_offset_t sva, va; 1536 1537 sva = *virt; 1538 va = sva; 1539 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1540 moea_kenter(mmu, va, pa_start); 1541 *virt = va; 1542 return (sva); 1543} 1544 1545/* 1546 * Returns true if the pmap's pv is one of the first 1547 * 16 pvs linked to from this page. This count may 1548 * be changed upwards or downwards in the future; it 1549 * is only necessary that true be returned for a small 1550 * subset of pmaps for proper page aging. 1551 */ 1552boolean_t 1553moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1554{ 1555 int loops; 1556 struct pvo_entry *pvo; 1557 boolean_t rv; 1558 1559 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1560 ("moea_page_exists_quick: page %p is not managed", m)); 1561 loops = 0; 1562 rv = FALSE; 1563 rw_wlock(&pvh_global_lock); 1564 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1565 if (pvo->pvo_pmap == pmap) { 1566 rv = TRUE; 1567 break; 1568 } 1569 if (++loops >= 16) 1570 break; 1571 } 1572 rw_wunlock(&pvh_global_lock); 1573 return (rv); 1574} 1575 1576/* 1577 * Return the number of managed mappings to the given physical page 1578 * that are wired. 1579 */ 1580int 1581moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1582{ 1583 struct pvo_entry *pvo; 1584 int count; 1585 1586 count = 0; 1587 if ((m->oflags & VPO_UNMANAGED) != 0) 1588 return (count); 1589 rw_wlock(&pvh_global_lock); 1590 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1591 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1592 count++; 1593 rw_wunlock(&pvh_global_lock); 1594 return (count); 1595} 1596 1597static u_int moea_vsidcontext; 1598 1599void 1600moea_pinit(mmu_t mmu, pmap_t pmap) 1601{ 1602 int i, mask; 1603 u_int entropy; 1604 1605 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1606 PMAP_LOCK_INIT(pmap); 1607 RB_INIT(&pmap->pmap_pvo); 1608 1609 entropy = 0; 1610 __asm __volatile("mftb %0" : "=r"(entropy)); 1611 1612 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1613 == NULL) { 1614 pmap->pmap_phys = pmap; 1615 } 1616 1617 1618 mtx_lock(&moea_vsid_mutex); 1619 /* 1620 * Allocate some segment registers for this pmap. 1621 */ 1622 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1623 u_int hash, n; 1624 1625 /* 1626 * Create a new value by mutiplying by a prime and adding in 1627 * entropy from the timebase register. This is to make the 1628 * VSID more random so that the PT hash function collides 1629 * less often. (Note that the prime casues gcc to do shifts 1630 * instead of a multiply.) 1631 */ 1632 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1633 hash = moea_vsidcontext & (NPMAPS - 1); 1634 if (hash == 0) /* 0 is special, avoid it */ 1635 continue; 1636 n = hash >> 5; 1637 mask = 1 << (hash & (VSID_NBPW - 1)); 1638 hash = (moea_vsidcontext & 0xfffff); 1639 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1640 /* anything free in this bucket? */ 1641 if (moea_vsid_bitmap[n] == 0xffffffff) { 1642 entropy = (moea_vsidcontext >> 20); 1643 continue; 1644 } 1645 i = ffs(~moea_vsid_bitmap[n]) - 1; 1646 mask = 1 << i; 1647 hash &= 0xfffff & ~(VSID_NBPW - 1); 1648 hash |= i; 1649 } 1650 KASSERT(!(moea_vsid_bitmap[n] & mask), 1651 ("Allocating in-use VSID group %#x\n", hash)); 1652 moea_vsid_bitmap[n] |= mask; 1653 for (i = 0; i < 16; i++) 1654 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1655 mtx_unlock(&moea_vsid_mutex); 1656 return; 1657 } 1658 1659 mtx_unlock(&moea_vsid_mutex); 1660 panic("moea_pinit: out of segments"); 1661} 1662 1663/* 1664 * Initialize the pmap associated with process 0. 1665 */ 1666void 1667moea_pinit0(mmu_t mmu, pmap_t pm) 1668{ 1669 1670 moea_pinit(mmu, pm); 1671 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1672} 1673 1674/* 1675 * Set the physical protection on the specified range of this map as requested. 1676 */ 1677void 1678moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1679 vm_prot_t prot) 1680{ 1681 struct pvo_entry *pvo, *tpvo, key; 1682 struct pte *pt; 1683 1684 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1685 ("moea_protect: non current pmap")); 1686 1687 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1688 moea_remove(mmu, pm, sva, eva); 1689 return; 1690 } 1691 1692 rw_wlock(&pvh_global_lock); 1693 PMAP_LOCK(pm); 1694 key.pvo_vaddr = sva; 1695 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1696 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1697 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1698 if ((prot & VM_PROT_EXECUTE) == 0) 1699 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1700 1701 /* 1702 * Grab the PTE pointer before we diddle with the cached PTE 1703 * copy. 1704 */ 1705 pt = moea_pvo_to_pte(pvo, -1); 1706 /* 1707 * Change the protection of the page. 1708 */ 1709 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1710 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1711 1712 /* 1713 * If the PVO is in the page table, update that pte as well. 1714 */ 1715 if (pt != NULL) { 1716 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1717 mtx_unlock(&moea_table_mutex); 1718 } 1719 } 1720 rw_wunlock(&pvh_global_lock); 1721 PMAP_UNLOCK(pm); 1722} 1723 1724/* 1725 * Map a list of wired pages into kernel virtual address space. This is 1726 * intended for temporary mappings which do not need page modification or 1727 * references recorded. Existing mappings in the region are overwritten. 1728 */ 1729void 1730moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1731{ 1732 vm_offset_t va; 1733 1734 va = sva; 1735 while (count-- > 0) { 1736 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1737 va += PAGE_SIZE; 1738 m++; 1739 } 1740} 1741 1742/* 1743 * Remove page mappings from kernel virtual address space. Intended for 1744 * temporary mappings entered by moea_qenter. 1745 */ 1746void 1747moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1748{ 1749 vm_offset_t va; 1750 1751 va = sva; 1752 while (count-- > 0) { 1753 moea_kremove(mmu, va); 1754 va += PAGE_SIZE; 1755 } 1756} 1757 1758void 1759moea_release(mmu_t mmu, pmap_t pmap) 1760{ 1761 int idx, mask; 1762 1763 /* 1764 * Free segment register's VSID 1765 */ 1766 if (pmap->pm_sr[0] == 0) 1767 panic("moea_release"); 1768 1769 mtx_lock(&moea_vsid_mutex); 1770 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1771 mask = 1 << (idx % VSID_NBPW); 1772 idx /= VSID_NBPW; 1773 moea_vsid_bitmap[idx] &= ~mask; 1774 mtx_unlock(&moea_vsid_mutex); 1775 PMAP_LOCK_DESTROY(pmap); 1776} 1777 1778/* 1779 * Remove the given range of addresses from the specified map. 1780 */ 1781void 1782moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1783{ 1784 struct pvo_entry *pvo, *tpvo, key; 1785 1786 rw_wlock(&pvh_global_lock); 1787 PMAP_LOCK(pm); 1788 key.pvo_vaddr = sva; 1789 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1790 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1791 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1792 moea_pvo_remove(pvo, -1); 1793 } 1794 PMAP_UNLOCK(pm); 1795 rw_wunlock(&pvh_global_lock); 1796} 1797 1798/* 1799 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1800 * will reflect changes in pte's back to the vm_page. 1801 */ 1802void 1803moea_remove_all(mmu_t mmu, vm_page_t m) 1804{ 1805 struct pvo_head *pvo_head; 1806 struct pvo_entry *pvo, *next_pvo; 1807 pmap_t pmap; 1808 1809 rw_wlock(&pvh_global_lock); 1810 pvo_head = vm_page_to_pvoh(m); 1811 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1812 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1813 1814 pmap = pvo->pvo_pmap; 1815 PMAP_LOCK(pmap); 1816 moea_pvo_remove(pvo, -1); 1817 PMAP_UNLOCK(pmap); 1818 } 1819 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) { 1820 moea_attr_clear(m, PTE_CHG); 1821 vm_page_dirty(m); 1822 } 1823 vm_page_aflag_clear(m, PGA_WRITEABLE); 1824 rw_wunlock(&pvh_global_lock); 1825} 1826 1827/* 1828 * Allocate a physical page of memory directly from the phys_avail map. 1829 * Can only be called from moea_bootstrap before avail start and end are 1830 * calculated. 1831 */ 1832static vm_offset_t 1833moea_bootstrap_alloc(vm_size_t size, u_int align) 1834{ 1835 vm_offset_t s, e; 1836 int i, j; 1837 1838 size = round_page(size); 1839 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1840 if (align != 0) 1841 s = (phys_avail[i] + align - 1) & ~(align - 1); 1842 else 1843 s = phys_avail[i]; 1844 e = s + size; 1845 1846 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1847 continue; 1848 1849 if (s == phys_avail[i]) { 1850 phys_avail[i] += size; 1851 } else if (e == phys_avail[i + 1]) { 1852 phys_avail[i + 1] -= size; 1853 } else { 1854 for (j = phys_avail_count * 2; j > i; j -= 2) { 1855 phys_avail[j] = phys_avail[j - 2]; 1856 phys_avail[j + 1] = phys_avail[j - 1]; 1857 } 1858 1859 phys_avail[i + 3] = phys_avail[i + 1]; 1860 phys_avail[i + 1] = s; 1861 phys_avail[i + 2] = e; 1862 phys_avail_count++; 1863 } 1864 1865 return (s); 1866 } 1867 panic("moea_bootstrap_alloc: could not allocate memory"); 1868} 1869 1870static void 1871moea_syncicache(vm_offset_t pa, vm_size_t len) 1872{ 1873 __syncicache((void *)pa, len); 1874} 1875 1876static int 1877moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1878 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1879{ 1880 struct pvo_entry *pvo; 1881 u_int sr; 1882 int first; 1883 u_int ptegidx; 1884 int i; 1885 int bootstrap; 1886 1887 moea_pvo_enter_calls++; 1888 first = 0; 1889 bootstrap = 0; 1890 1891 /* 1892 * Compute the PTE Group index. 1893 */ 1894 va &= ~ADDR_POFF; 1895 sr = va_to_sr(pm->pm_sr, va); 1896 ptegidx = va_to_pteg(sr, va); 1897 1898 /* 1899 * Remove any existing mapping for this page. Reuse the pvo entry if 1900 * there is a mapping. 1901 */ 1902 mtx_lock(&moea_table_mutex); 1903 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1904 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1905 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1906 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1907 (pte_lo & PTE_PP)) { 1908 mtx_unlock(&moea_table_mutex); 1909 return (0); 1910 } 1911 moea_pvo_remove(pvo, -1); 1912 break; 1913 } 1914 } 1915 1916 /* 1917 * If we aren't overwriting a mapping, try to allocate. 1918 */ 1919 if (moea_initialized) { 1920 pvo = uma_zalloc(zone, M_NOWAIT); 1921 } else { 1922 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1923 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1924 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1925 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1926 } 1927 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1928 moea_bpvo_pool_index++; 1929 bootstrap = 1; 1930 } 1931 1932 if (pvo == NULL) { 1933 mtx_unlock(&moea_table_mutex); 1934 return (ENOMEM); 1935 } 1936 1937 moea_pvo_entries++; 1938 pvo->pvo_vaddr = va; 1939 pvo->pvo_pmap = pm; 1940 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1941 pvo->pvo_vaddr &= ~ADDR_POFF; 1942 if (flags & VM_PROT_EXECUTE) 1943 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1944 if (flags & PVO_WIRED) 1945 pvo->pvo_vaddr |= PVO_WIRED; 1946 if (pvo_head != &moea_pvo_kunmanaged) 1947 pvo->pvo_vaddr |= PVO_MANAGED; 1948 if (bootstrap) 1949 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1950 1951 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1952 1953 /* 1954 * Add to pmap list 1955 */ 1956 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1957 1958 /* 1959 * Remember if the list was empty and therefore will be the first 1960 * item. 1961 */ 1962 if (LIST_FIRST(pvo_head) == NULL) 1963 first = 1; 1964 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1965 1966 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1967 pm->pm_stats.wired_count++; 1968 pm->pm_stats.resident_count++; 1969 1970 /* 1971 * We hope this succeeds but it isn't required. 1972 */ 1973 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1974 if (i >= 0) { 1975 PVO_PTEGIDX_SET(pvo, i); 1976 } else { 1977 panic("moea_pvo_enter: overflow"); 1978 moea_pte_overflow++; 1979 } 1980 mtx_unlock(&moea_table_mutex); 1981 1982 return (first ? ENOENT : 0); 1983} 1984 1985static void 1986moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1987{ 1988 struct pte *pt; 1989 1990 /* 1991 * If there is an active pte entry, we need to deactivate it (and 1992 * save the ref & cfg bits). 1993 */ 1994 pt = moea_pvo_to_pte(pvo, pteidx); 1995 if (pt != NULL) { 1996 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1997 mtx_unlock(&moea_table_mutex); 1998 PVO_PTEGIDX_CLR(pvo); 1999 } else { 2000 moea_pte_overflow--; 2001 } 2002 2003 /* 2004 * Update our statistics. 2005 */ 2006 pvo->pvo_pmap->pm_stats.resident_count--; 2007 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2008 pvo->pvo_pmap->pm_stats.wired_count--; 2009 2010 /* 2011 * Save the REF/CHG bits into their cache if the page is managed. 2012 */ 2013 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2014 struct vm_page *pg; 2015 2016 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2017 if (pg != NULL) { 2018 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2019 (PTE_REF | PTE_CHG)); 2020 } 2021 } 2022 2023 /* 2024 * Remove this PVO from the PV and pmap lists. 2025 */ 2026 LIST_REMOVE(pvo, pvo_vlink); 2027 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2028 2029 /* 2030 * Remove this from the overflow list and return it to the pool 2031 * if we aren't going to reuse it. 2032 */ 2033 LIST_REMOVE(pvo, pvo_olink); 2034 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2035 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2036 moea_upvo_zone, pvo); 2037 moea_pvo_entries--; 2038 moea_pvo_remove_calls++; 2039} 2040 2041static __inline int 2042moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2043{ 2044 int pteidx; 2045 2046 /* 2047 * We can find the actual pte entry without searching by grabbing 2048 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2049 * noticing the HID bit. 2050 */ 2051 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2052 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2053 pteidx ^= moea_pteg_mask * 8; 2054 2055 return (pteidx); 2056} 2057 2058static struct pvo_entry * 2059moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2060{ 2061 struct pvo_entry *pvo; 2062 int ptegidx; 2063 u_int sr; 2064 2065 va &= ~ADDR_POFF; 2066 sr = va_to_sr(pm->pm_sr, va); 2067 ptegidx = va_to_pteg(sr, va); 2068 2069 mtx_lock(&moea_table_mutex); 2070 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2071 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2072 if (pteidx_p) 2073 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2074 break; 2075 } 2076 } 2077 mtx_unlock(&moea_table_mutex); 2078 2079 return (pvo); 2080} 2081 2082static struct pte * 2083moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2084{ 2085 struct pte *pt; 2086 2087 /* 2088 * If we haven't been supplied the ptegidx, calculate it. 2089 */ 2090 if (pteidx == -1) { 2091 int ptegidx; 2092 u_int sr; 2093 2094 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2095 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2096 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2097 } 2098 2099 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2100 mtx_lock(&moea_table_mutex); 2101 2102 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2103 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2104 "valid pte index", pvo); 2105 } 2106 2107 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2108 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2109 "pvo but no valid pte", pvo); 2110 } 2111 2112 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2113 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2114 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2115 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2116 } 2117 2118 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2119 != 0) { 2120 panic("moea_pvo_to_pte: pvo %p pte does not match " 2121 "pte %p in moea_pteg_table", pvo, pt); 2122 } 2123 2124 mtx_assert(&moea_table_mutex, MA_OWNED); 2125 return (pt); 2126 } 2127 2128 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2129 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2130 "moea_pteg_table but valid in pvo", pvo, pt); 2131 } 2132 2133 mtx_unlock(&moea_table_mutex); 2134 return (NULL); 2135} 2136 2137/* 2138 * XXX: THIS STUFF SHOULD BE IN pte.c? 2139 */ 2140int 2141moea_pte_spill(vm_offset_t addr) 2142{ 2143 struct pvo_entry *source_pvo, *victim_pvo; 2144 struct pvo_entry *pvo; 2145 int ptegidx, i, j; 2146 u_int sr; 2147 struct pteg *pteg; 2148 struct pte *pt; 2149 2150 moea_pte_spills++; 2151 2152 sr = mfsrin(addr); 2153 ptegidx = va_to_pteg(sr, addr); 2154 2155 /* 2156 * Have to substitute some entry. Use the primary hash for this. 2157 * Use low bits of timebase as random generator. 2158 */ 2159 pteg = &moea_pteg_table[ptegidx]; 2160 mtx_lock(&moea_table_mutex); 2161 __asm __volatile("mftb %0" : "=r"(i)); 2162 i &= 7; 2163 pt = &pteg->pt[i]; 2164 2165 source_pvo = NULL; 2166 victim_pvo = NULL; 2167 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2168 /* 2169 * We need to find a pvo entry for this address. 2170 */ 2171 if (source_pvo == NULL && 2172 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2173 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2174 /* 2175 * Now found an entry to be spilled into the pteg. 2176 * The PTE is now valid, so we know it's active. 2177 */ 2178 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2179 2180 if (j >= 0) { 2181 PVO_PTEGIDX_SET(pvo, j); 2182 moea_pte_overflow--; 2183 mtx_unlock(&moea_table_mutex); 2184 return (1); 2185 } 2186 2187 source_pvo = pvo; 2188 2189 if (victim_pvo != NULL) 2190 break; 2191 } 2192 2193 /* 2194 * We also need the pvo entry of the victim we are replacing 2195 * so save the R & C bits of the PTE. 2196 */ 2197 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2198 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2199 victim_pvo = pvo; 2200 if (source_pvo != NULL) 2201 break; 2202 } 2203 } 2204 2205 if (source_pvo == NULL) { 2206 mtx_unlock(&moea_table_mutex); 2207 return (0); 2208 } 2209 2210 if (victim_pvo == NULL) { 2211 if ((pt->pte_hi & PTE_HID) == 0) 2212 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2213 "entry", pt); 2214 2215 /* 2216 * If this is a secondary PTE, we need to search it's primary 2217 * pvo bucket for the matching PVO. 2218 */ 2219 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2220 pvo_olink) { 2221 /* 2222 * We also need the pvo entry of the victim we are 2223 * replacing so save the R & C bits of the PTE. 2224 */ 2225 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2226 victim_pvo = pvo; 2227 break; 2228 } 2229 } 2230 2231 if (victim_pvo == NULL) 2232 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2233 "entry", pt); 2234 } 2235 2236 /* 2237 * We are invalidating the TLB entry for the EA we are replacing even 2238 * though it's valid. If we don't, we lose any ref/chg bit changes 2239 * contained in the TLB entry. 2240 */ 2241 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2242 2243 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2244 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2245 2246 PVO_PTEGIDX_CLR(victim_pvo); 2247 PVO_PTEGIDX_SET(source_pvo, i); 2248 moea_pte_replacements++; 2249 2250 mtx_unlock(&moea_table_mutex); 2251 return (1); 2252} 2253 2254static int 2255moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2256{ 2257 struct pte *pt; 2258 int i; 2259 2260 mtx_assert(&moea_table_mutex, MA_OWNED); 2261 2262 /* 2263 * First try primary hash. 2264 */ 2265 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2266 if ((pt->pte_hi & PTE_VALID) == 0) { 2267 pvo_pt->pte_hi &= ~PTE_HID; 2268 moea_pte_set(pt, pvo_pt); 2269 return (i); 2270 } 2271 } 2272 2273 /* 2274 * Now try secondary hash. 2275 */ 2276 ptegidx ^= moea_pteg_mask; 2277 2278 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2279 if ((pt->pte_hi & PTE_VALID) == 0) { 2280 pvo_pt->pte_hi |= PTE_HID; 2281 moea_pte_set(pt, pvo_pt); 2282 return (i); 2283 } 2284 } 2285 2286 panic("moea_pte_insert: overflow"); 2287 return (-1); 2288} 2289 2290static boolean_t 2291moea_query_bit(vm_page_t m, int ptebit) 2292{ 2293 struct pvo_entry *pvo; 2294 struct pte *pt; 2295 2296 if (moea_attr_fetch(m) & ptebit) 2297 return (TRUE); 2298 2299 rw_wlock(&pvh_global_lock); 2300 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2301 2302 /* 2303 * See if we saved the bit off. If so, cache it and return 2304 * success. 2305 */ 2306 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2307 moea_attr_save(m, ptebit); 2308 rw_wunlock(&pvh_global_lock); 2309 return (TRUE); 2310 } 2311 } 2312 2313 /* 2314 * No luck, now go through the hard part of looking at the PTEs 2315 * themselves. Sync so that any pending REF/CHG bits are flushed to 2316 * the PTEs. 2317 */ 2318 powerpc_sync(); 2319 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2320 2321 /* 2322 * See if this pvo has a valid PTE. if so, fetch the 2323 * REF/CHG bits from the valid PTE. If the appropriate 2324 * ptebit is set, cache it and return success. 2325 */ 2326 pt = moea_pvo_to_pte(pvo, -1); 2327 if (pt != NULL) { 2328 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2329 mtx_unlock(&moea_table_mutex); 2330 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2331 moea_attr_save(m, ptebit); 2332 rw_wunlock(&pvh_global_lock); 2333 return (TRUE); 2334 } 2335 } 2336 } 2337 2338 rw_wunlock(&pvh_global_lock); 2339 return (FALSE); 2340} 2341 2342static u_int 2343moea_clear_bit(vm_page_t m, int ptebit) 2344{ 2345 u_int count; 2346 struct pvo_entry *pvo; 2347 struct pte *pt; 2348 2349 rw_wlock(&pvh_global_lock); 2350 2351 /* 2352 * Clear the cached value. 2353 */ 2354 moea_attr_clear(m, ptebit); 2355 2356 /* 2357 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2358 * we can reset the right ones). note that since the pvo entries and 2359 * list heads are accessed via BAT0 and are never placed in the page 2360 * table, we don't have to worry about further accesses setting the 2361 * REF/CHG bits. 2362 */ 2363 powerpc_sync(); 2364 2365 /* 2366 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2367 * valid pte clear the ptebit from the valid pte. 2368 */ 2369 count = 0; 2370 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2371 pt = moea_pvo_to_pte(pvo, -1); 2372 if (pt != NULL) { 2373 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2374 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2375 count++; 2376 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2377 } 2378 mtx_unlock(&moea_table_mutex); 2379 } 2380 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2381 } 2382 2383 rw_wunlock(&pvh_global_lock); 2384 return (count); 2385} 2386 2387/* 2388 * Return true if the physical range is encompassed by the battable[idx] 2389 */ 2390static int 2391moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2392{ 2393 u_int prot; 2394 u_int32_t start; 2395 u_int32_t end; 2396 u_int32_t bat_ble; 2397 2398 /* 2399 * Return immediately if not a valid mapping 2400 */ 2401 if (!(battable[idx].batu & BAT_Vs)) 2402 return (EINVAL); 2403 2404 /* 2405 * The BAT entry must be cache-inhibited, guarded, and r/w 2406 * so it can function as an i/o page 2407 */ 2408 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2409 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2410 return (EPERM); 2411 2412 /* 2413 * The address should be within the BAT range. Assume that the 2414 * start address in the BAT has the correct alignment (thus 2415 * not requiring masking) 2416 */ 2417 start = battable[idx].batl & BAT_PBS; 2418 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2419 end = start | (bat_ble << 15) | 0x7fff; 2420 2421 if ((pa < start) || ((pa + size) > end)) 2422 return (ERANGE); 2423 2424 return (0); 2425} 2426 2427boolean_t 2428moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2429{ 2430 int i; 2431 2432 /* 2433 * This currently does not work for entries that 2434 * overlap 256M BAT segments. 2435 */ 2436 2437 for(i = 0; i < 16; i++) 2438 if (moea_bat_mapped(i, pa, size) == 0) 2439 return (0); 2440 2441 return (EFAULT); 2442} 2443 2444/* 2445 * Map a set of physical memory pages into the kernel virtual 2446 * address space. Return a pointer to where it is mapped. This 2447 * routine is intended to be used for mapping device memory, 2448 * NOT real memory. 2449 */ 2450void * 2451moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2452{ 2453 2454 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2455} 2456 2457void * 2458moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2459{ 2460 vm_offset_t va, tmpva, ppa, offset; 2461 int i; 2462 2463 ppa = trunc_page(pa); 2464 offset = pa & PAGE_MASK; 2465 size = roundup(offset + size, PAGE_SIZE); 2466 2467 /* 2468 * If the physical address lies within a valid BAT table entry, 2469 * return the 1:1 mapping. This currently doesn't work 2470 * for regions that overlap 256M BAT segments. 2471 */ 2472 for (i = 0; i < 16; i++) { 2473 if (moea_bat_mapped(i, pa, size) == 0) 2474 return ((void *) pa); 2475 } 2476 2477 va = kmem_alloc_nofault(kernel_map, size); 2478 if (!va) 2479 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2480 2481 for (tmpva = va; size > 0;) { 2482 moea_kenter_attr(mmu, tmpva, ppa, ma); 2483 tlbie(tmpva); 2484 size -= PAGE_SIZE; 2485 tmpva += PAGE_SIZE; 2486 ppa += PAGE_SIZE; 2487 } 2488 2489 return ((void *)(va + offset)); 2490} 2491 2492void 2493moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2494{ 2495 vm_offset_t base, offset; 2496 2497 /* 2498 * If this is outside kernel virtual space, then it's a 2499 * battable entry and doesn't require unmapping 2500 */ 2501 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2502 base = trunc_page(va); 2503 offset = va & PAGE_MASK; 2504 size = roundup(offset + size, PAGE_SIZE); 2505 kmem_free(kernel_map, base, size); 2506 } 2507} 2508 2509static void 2510moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2511{ 2512 struct pvo_entry *pvo; 2513 vm_offset_t lim; 2514 vm_paddr_t pa; 2515 vm_size_t len; 2516 2517 PMAP_LOCK(pm); 2518 while (sz > 0) { 2519 lim = round_page(va); 2520 len = MIN(lim - va, sz); 2521 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2522 if (pvo != NULL) { 2523 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2524 (va & ADDR_POFF); 2525 moea_syncicache(pa, len); 2526 } 2527 va += len; 2528 sz -= len; 2529 } 2530 PMAP_UNLOCK(pm); 2531} 2532