mmu_oea.c revision 213307
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 213307 2010-09-30 18:14:12Z nwhitehorn $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <dev/ofw/openfirm.h> 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/platform.h> 145#include <machine/bat.h> 146#include <machine/frame.h> 147#include <machine/md_var.h> 148#include <machine/psl.h> 149#include <machine/pte.h> 150#include <machine/smp.h> 151#include <machine/sr.h> 152#include <machine/mmuvar.h> 153 154#include "mmu_if.h" 155 156#define MOEA_DEBUG 157 158#define TODO panic("%s: not implemented", __func__); 159 160#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 161#define VSID_TO_SR(vsid) ((vsid) & 0xf) 162#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163 164#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 165#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 166#define PVO_WIRED 0x010 /* PVO entry is wired */ 167#define PVO_MANAGED 0x020 /* PVO entry is managed */ 168#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 169#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 170 bootstrap */ 171#define PVO_FAKE 0x100 /* fictitious phys page */ 172#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 173#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 175#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 176#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 177#define PVO_PTEGIDX_CLR(pvo) \ 178 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 179#define PVO_PTEGIDX_SET(pvo, i) \ 180 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 181 182#define MOEA_PVO_CHECK(pvo) 183 184struct ofw_map { 185 vm_offset_t om_va; 186 vm_size_t om_len; 187 vm_offset_t om_pa; 188 u_int om_mode; 189}; 190 191/* 192 * Map of physical memory regions. 193 */ 194static struct mem_region *regions; 195static struct mem_region *pregions; 196static u_int phys_avail_count; 197static int regions_sz, pregions_sz; 198static struct ofw_map *translations; 199 200extern struct pmap ofw_pmap; 201 202/* 203 * Lock for the pteg and pvo tables. 204 */ 205struct mtx moea_table_mutex; 206struct mtx moea_vsid_mutex; 207 208/* tlbie instruction synchronization */ 209static struct mtx tlbie_mtx; 210 211/* 212 * PTEG data. 213 */ 214static struct pteg *moea_pteg_table; 215u_int moea_pteg_count; 216u_int moea_pteg_mask; 217 218/* 219 * PVO data. 220 */ 221struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 222struct pvo_head moea_pvo_kunmanaged = 223 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 224struct pvo_head moea_pvo_unmanaged = 225 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 226 227uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 228uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 229 230#define BPVO_POOL_SIZE 32768 231static struct pvo_entry *moea_bpvo_pool; 232static int moea_bpvo_pool_index = 0; 233 234#define VSID_NBPW (sizeof(u_int32_t) * 8) 235static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 236 237static boolean_t moea_initialized = FALSE; 238 239/* 240 * Statistics. 241 */ 242u_int moea_pte_valid = 0; 243u_int moea_pte_overflow = 0; 244u_int moea_pte_replacements = 0; 245u_int moea_pvo_entries = 0; 246u_int moea_pvo_enter_calls = 0; 247u_int moea_pvo_remove_calls = 0; 248u_int moea_pte_spills = 0; 249SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 250 0, ""); 251SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 252 &moea_pte_overflow, 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 254 &moea_pte_replacements, 0, ""); 255SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 256 0, ""); 257SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 258 &moea_pvo_enter_calls, 0, ""); 259SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 260 &moea_pvo_remove_calls, 0, ""); 261SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 262 &moea_pte_spills, 0, ""); 263 264/* 265 * Allocate physical memory for use in moea_bootstrap. 266 */ 267static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 268 269/* 270 * PTE calls. 271 */ 272static int moea_pte_insert(u_int, struct pte *); 273 274/* 275 * PVO calls. 276 */ 277static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 278 vm_offset_t, vm_offset_t, u_int, int); 279static void moea_pvo_remove(struct pvo_entry *, int); 280static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 281static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 282 283/* 284 * Utility routines. 285 */ 286static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 287 vm_prot_t, boolean_t); 288static void moea_syncicache(vm_offset_t, vm_size_t); 289static boolean_t moea_query_bit(vm_page_t, int); 290static u_int moea_clear_bit(vm_page_t, int); 291static void moea_kremove(mmu_t, vm_offset_t); 292int moea_pte_spill(vm_offset_t); 293 294/* 295 * Kernel MMU interface 296 */ 297void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 298void moea_clear_modify(mmu_t, vm_page_t); 299void moea_clear_reference(mmu_t, vm_page_t); 300void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 301void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 302void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 303 vm_prot_t); 304void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 305vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 306vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 307void moea_init(mmu_t); 308boolean_t moea_is_modified(mmu_t, vm_page_t); 309boolean_t moea_is_referenced(mmu_t, vm_page_t); 310boolean_t moea_ts_referenced(mmu_t, vm_page_t); 311vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 312boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 313int moea_page_wired_mappings(mmu_t, vm_page_t); 314void moea_pinit(mmu_t, pmap_t); 315void moea_pinit0(mmu_t, pmap_t); 316void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 317void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 318void moea_qremove(mmu_t, vm_offset_t, int); 319void moea_release(mmu_t, pmap_t); 320void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 321void moea_remove_all(mmu_t, vm_page_t); 322void moea_remove_write(mmu_t, vm_page_t); 323void moea_zero_page(mmu_t, vm_page_t); 324void moea_zero_page_area(mmu_t, vm_page_t, int, int); 325void moea_zero_page_idle(mmu_t, vm_page_t); 326void moea_activate(mmu_t, struct thread *); 327void moea_deactivate(mmu_t, struct thread *); 328void moea_cpu_bootstrap(mmu_t, int); 329void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 330void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 331void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 332void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 333vm_offset_t moea_kextract(mmu_t, vm_offset_t); 334void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 335void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 336void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 337boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 338static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 339 340static mmu_method_t moea_methods[] = { 341 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 342 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 343 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 344 MMUMETHOD(mmu_copy_page, moea_copy_page), 345 MMUMETHOD(mmu_enter, moea_enter), 346 MMUMETHOD(mmu_enter_object, moea_enter_object), 347 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 348 MMUMETHOD(mmu_extract, moea_extract), 349 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 350 MMUMETHOD(mmu_init, moea_init), 351 MMUMETHOD(mmu_is_modified, moea_is_modified), 352 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 353 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 354 MMUMETHOD(mmu_map, moea_map), 355 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 356 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 357 MMUMETHOD(mmu_pinit, moea_pinit), 358 MMUMETHOD(mmu_pinit0, moea_pinit0), 359 MMUMETHOD(mmu_protect, moea_protect), 360 MMUMETHOD(mmu_qenter, moea_qenter), 361 MMUMETHOD(mmu_qremove, moea_qremove), 362 MMUMETHOD(mmu_release, moea_release), 363 MMUMETHOD(mmu_remove, moea_remove), 364 MMUMETHOD(mmu_remove_all, moea_remove_all), 365 MMUMETHOD(mmu_remove_write, moea_remove_write), 366 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 367 MMUMETHOD(mmu_zero_page, moea_zero_page), 368 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 369 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 370 MMUMETHOD(mmu_activate, moea_activate), 371 MMUMETHOD(mmu_deactivate, moea_deactivate), 372 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 373 374 /* Internal interfaces */ 375 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 376 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 377 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 378 MMUMETHOD(mmu_mapdev, moea_mapdev), 379 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 380 MMUMETHOD(mmu_kextract, moea_kextract), 381 MMUMETHOD(mmu_kenter, moea_kenter), 382 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 383 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 384 385 { 0, 0 } 386}; 387 388MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 389 390static __inline uint32_t 391moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 392{ 393 uint32_t pte_lo; 394 int i; 395 396 if (ma != VM_MEMATTR_DEFAULT) { 397 switch (ma) { 398 case VM_MEMATTR_UNCACHEABLE: 399 return (PTE_I | PTE_G); 400 case VM_MEMATTR_WRITE_COMBINING: 401 case VM_MEMATTR_WRITE_BACK: 402 case VM_MEMATTR_PREFETCHABLE: 403 return (PTE_I); 404 case VM_MEMATTR_WRITE_THROUGH: 405 return (PTE_W | PTE_M); 406 } 407 } 408 409 /* 410 * Assume the page is cache inhibited and access is guarded unless 411 * it's in our available memory array. 412 */ 413 pte_lo = PTE_I | PTE_G; 414 for (i = 0; i < pregions_sz; i++) { 415 if ((pa >= pregions[i].mr_start) && 416 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 417 pte_lo = PTE_M; 418 break; 419 } 420 } 421 422 return pte_lo; 423} 424 425static void 426tlbie(vm_offset_t va) 427{ 428 429 mtx_lock_spin(&tlbie_mtx); 430 __asm __volatile("tlbie %0" :: "r"(va)); 431 __asm __volatile("tlbsync"); 432 powerpc_sync(); 433 mtx_unlock_spin(&tlbie_mtx); 434} 435 436static void 437tlbia(void) 438{ 439 vm_offset_t va; 440 441 for (va = 0; va < 0x00040000; va += 0x00001000) { 442 __asm __volatile("tlbie %0" :: "r"(va)); 443 powerpc_sync(); 444 } 445 __asm __volatile("tlbsync"); 446 powerpc_sync(); 447} 448 449static __inline int 450va_to_sr(u_int *sr, vm_offset_t va) 451{ 452 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 453} 454 455static __inline u_int 456va_to_pteg(u_int sr, vm_offset_t addr) 457{ 458 u_int hash; 459 460 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 461 ADDR_PIDX_SHFT); 462 return (hash & moea_pteg_mask); 463} 464 465static __inline struct pvo_head * 466pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 467{ 468 struct vm_page *pg; 469 470 pg = PHYS_TO_VM_PAGE(pa); 471 472 if (pg_p != NULL) 473 *pg_p = pg; 474 475 if (pg == NULL) 476 return (&moea_pvo_unmanaged); 477 478 return (&pg->md.mdpg_pvoh); 479} 480 481static __inline struct pvo_head * 482vm_page_to_pvoh(vm_page_t m) 483{ 484 485 return (&m->md.mdpg_pvoh); 486} 487 488static __inline void 489moea_attr_clear(vm_page_t m, int ptebit) 490{ 491 492 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 493 m->md.mdpg_attrs &= ~ptebit; 494} 495 496static __inline int 497moea_attr_fetch(vm_page_t m) 498{ 499 500 return (m->md.mdpg_attrs); 501} 502 503static __inline void 504moea_attr_save(vm_page_t m, int ptebit) 505{ 506 507 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 508 m->md.mdpg_attrs |= ptebit; 509} 510 511static __inline int 512moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 513{ 514 if (pt->pte_hi == pvo_pt->pte_hi) 515 return (1); 516 517 return (0); 518} 519 520static __inline int 521moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 522{ 523 return (pt->pte_hi & ~PTE_VALID) == 524 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 525 ((va >> ADDR_API_SHFT) & PTE_API) | which); 526} 527 528static __inline void 529moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 530{ 531 532 mtx_assert(&moea_table_mutex, MA_OWNED); 533 534 /* 535 * Construct a PTE. Default to IMB initially. Valid bit only gets 536 * set when the real pte is set in memory. 537 * 538 * Note: Don't set the valid bit for correct operation of tlb update. 539 */ 540 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 541 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 542 pt->pte_lo = pte_lo; 543} 544 545static __inline void 546moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 547{ 548 549 mtx_assert(&moea_table_mutex, MA_OWNED); 550 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 551} 552 553static __inline void 554moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 555{ 556 557 mtx_assert(&moea_table_mutex, MA_OWNED); 558 559 /* 560 * As shown in Section 7.6.3.2.3 561 */ 562 pt->pte_lo &= ~ptebit; 563 tlbie(va); 564} 565 566static __inline void 567moea_pte_set(struct pte *pt, struct pte *pvo_pt) 568{ 569 570 mtx_assert(&moea_table_mutex, MA_OWNED); 571 pvo_pt->pte_hi |= PTE_VALID; 572 573 /* 574 * Update the PTE as defined in section 7.6.3.1. 575 * Note that the REF/CHG bits are from pvo_pt and thus should havce 576 * been saved so this routine can restore them (if desired). 577 */ 578 pt->pte_lo = pvo_pt->pte_lo; 579 powerpc_sync(); 580 pt->pte_hi = pvo_pt->pte_hi; 581 powerpc_sync(); 582 moea_pte_valid++; 583} 584 585static __inline void 586moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 587{ 588 589 mtx_assert(&moea_table_mutex, MA_OWNED); 590 pvo_pt->pte_hi &= ~PTE_VALID; 591 592 /* 593 * Force the reg & chg bits back into the PTEs. 594 */ 595 powerpc_sync(); 596 597 /* 598 * Invalidate the pte. 599 */ 600 pt->pte_hi &= ~PTE_VALID; 601 602 tlbie(va); 603 604 /* 605 * Save the reg & chg bits. 606 */ 607 moea_pte_synch(pt, pvo_pt); 608 moea_pte_valid--; 609} 610 611static __inline void 612moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 613{ 614 615 /* 616 * Invalidate the PTE 617 */ 618 moea_pte_unset(pt, pvo_pt, va); 619 moea_pte_set(pt, pvo_pt); 620} 621 622/* 623 * Quick sort callout for comparing memory regions. 624 */ 625static int mr_cmp(const void *a, const void *b); 626static int om_cmp(const void *a, const void *b); 627 628static int 629mr_cmp(const void *a, const void *b) 630{ 631 const struct mem_region *regiona; 632 const struct mem_region *regionb; 633 634 regiona = a; 635 regionb = b; 636 if (regiona->mr_start < regionb->mr_start) 637 return (-1); 638 else if (regiona->mr_start > regionb->mr_start) 639 return (1); 640 else 641 return (0); 642} 643 644static int 645om_cmp(const void *a, const void *b) 646{ 647 const struct ofw_map *mapa; 648 const struct ofw_map *mapb; 649 650 mapa = a; 651 mapb = b; 652 if (mapa->om_pa < mapb->om_pa) 653 return (-1); 654 else if (mapa->om_pa > mapb->om_pa) 655 return (1); 656 else 657 return (0); 658} 659 660void 661moea_cpu_bootstrap(mmu_t mmup, int ap) 662{ 663 u_int sdr; 664 int i; 665 666 if (ap) { 667 powerpc_sync(); 668 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 669 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 670 isync(); 671 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 672 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 673 isync(); 674 } 675 676 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 677 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 678 isync(); 679 680 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 681 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 682 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 683 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 684 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 685 isync(); 686 687 for (i = 0; i < 16; i++) 688 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 689 690 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 691 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 692 powerpc_sync(); 693 694 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 695 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 696 isync(); 697 698 tlbia(); 699} 700 701void 702moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 703{ 704 ihandle_t mmui; 705 phandle_t chosen, mmu; 706 int sz; 707 int i, j; 708 int ofw_mappings; 709 vm_size_t size, physsz, hwphyssz; 710 vm_offset_t pa, va, off; 711 void *dpcpu; 712 register_t msr; 713 714 /* 715 * Set up BAT0 to map the lowest 256 MB area 716 */ 717 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 718 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 719 720 /* 721 * Map PCI memory space. 722 */ 723 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 724 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 725 726 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 727 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 728 729 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 730 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 731 732 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 733 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 734 735 /* 736 * Map obio devices. 737 */ 738 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 739 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 740 741 /* 742 * Use an IBAT and a DBAT to map the bottom segment of memory 743 * where we are. Turn off instruction relocation temporarily 744 * to prevent faults while reprogramming the IBAT. 745 */ 746 msr = mfmsr(); 747 mtmsr(msr & ~PSL_IR); 748 __asm (".balign 32; \n" 749 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 750 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 751 :: "r"(battable[0].batu), "r"(battable[0].batl)); 752 mtmsr(msr); 753 754 /* map pci space */ 755 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 756 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 757 isync(); 758 759 /* set global direct map flag */ 760 hw_direct_map = 1; 761 762 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 763 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 764 765 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 766 for (i = 0; i < pregions_sz; i++) { 767 vm_offset_t pa; 768 vm_offset_t end; 769 770 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 771 pregions[i].mr_start, 772 pregions[i].mr_start + pregions[i].mr_size, 773 pregions[i].mr_size); 774 /* 775 * Install entries into the BAT table to allow all 776 * of physmem to be convered by on-demand BAT entries. 777 * The loop will sometimes set the same battable element 778 * twice, but that's fine since they won't be used for 779 * a while yet. 780 */ 781 pa = pregions[i].mr_start & 0xf0000000; 782 end = pregions[i].mr_start + pregions[i].mr_size; 783 do { 784 u_int n = pa >> ADDR_SR_SHFT; 785 786 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 787 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 788 pa += SEGMENT_LENGTH; 789 } while (pa < end); 790 } 791 792 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 793 panic("moea_bootstrap: phys_avail too small"); 794 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 795 phys_avail_count = 0; 796 physsz = 0; 797 hwphyssz = 0; 798 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 799 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 800 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 801 regions[i].mr_start + regions[i].mr_size, 802 regions[i].mr_size); 803 if (hwphyssz != 0 && 804 (physsz + regions[i].mr_size) >= hwphyssz) { 805 if (physsz < hwphyssz) { 806 phys_avail[j] = regions[i].mr_start; 807 phys_avail[j + 1] = regions[i].mr_start + 808 hwphyssz - physsz; 809 physsz = hwphyssz; 810 phys_avail_count++; 811 } 812 break; 813 } 814 phys_avail[j] = regions[i].mr_start; 815 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 816 phys_avail_count++; 817 physsz += regions[i].mr_size; 818 } 819 physmem = btoc(physsz); 820 821 /* 822 * Allocate PTEG table. 823 */ 824#ifdef PTEGCOUNT 825 moea_pteg_count = PTEGCOUNT; 826#else 827 moea_pteg_count = 0x1000; 828 829 while (moea_pteg_count < physmem) 830 moea_pteg_count <<= 1; 831 832 moea_pteg_count >>= 1; 833#endif /* PTEGCOUNT */ 834 835 size = moea_pteg_count * sizeof(struct pteg); 836 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 837 size); 838 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 839 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 840 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 841 moea_pteg_mask = moea_pteg_count - 1; 842 843 /* 844 * Allocate pv/overflow lists. 845 */ 846 size = sizeof(struct pvo_head) * moea_pteg_count; 847 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 848 PAGE_SIZE); 849 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 850 for (i = 0; i < moea_pteg_count; i++) 851 LIST_INIT(&moea_pvo_table[i]); 852 853 /* 854 * Initialize the lock that synchronizes access to the pteg and pvo 855 * tables. 856 */ 857 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 858 MTX_RECURSE); 859 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 860 861 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 862 863 /* 864 * Initialise the unmanaged pvo pool. 865 */ 866 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 867 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 868 moea_bpvo_pool_index = 0; 869 870 /* 871 * Make sure kernel vsid is allocated as well as VSID 0. 872 */ 873 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 874 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 875 moea_vsid_bitmap[0] |= 1; 876 877 /* 878 * Set up the Open Firmware pmap and add it's mappings. 879 */ 880 moea_pinit(mmup, &ofw_pmap); 881 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 882 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 883 if ((chosen = OF_finddevice("/chosen")) == -1) 884 panic("moea_bootstrap: can't find /chosen"); 885 OF_getprop(chosen, "mmu", &mmui, 4); 886 if ((mmu = OF_instance_to_package(mmui)) == -1) 887 panic("moea_bootstrap: can't get mmu package"); 888 if ((sz = OF_getproplen(mmu, "translations")) == -1) 889 panic("moea_bootstrap: can't get ofw translation count"); 890 translations = NULL; 891 for (i = 0; phys_avail[i] != 0; i += 2) { 892 if (phys_avail[i + 1] >= sz) { 893 translations = (struct ofw_map *)phys_avail[i]; 894 break; 895 } 896 } 897 if (translations == NULL) 898 panic("moea_bootstrap: no space to copy translations"); 899 bzero(translations, sz); 900 if (OF_getprop(mmu, "translations", translations, sz) == -1) 901 panic("moea_bootstrap: can't get ofw translations"); 902 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 903 sz /= sizeof(*translations); 904 qsort(translations, sz, sizeof (*translations), om_cmp); 905 for (i = 0, ofw_mappings = 0; i < sz; i++) { 906 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 907 translations[i].om_pa, translations[i].om_va, 908 translations[i].om_len); 909 910 /* 911 * If the mapping is 1:1, let the RAM and device on-demand 912 * BAT tables take care of the translation. 913 */ 914 if (translations[i].om_va == translations[i].om_pa) 915 continue; 916 917 /* Enter the pages */ 918 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 919 struct vm_page m; 920 921 m.phys_addr = translations[i].om_pa + off; 922 m.oflags = VPO_BUSY; 923 PMAP_LOCK(&ofw_pmap); 924 moea_enter_locked(&ofw_pmap, 925 translations[i].om_va + off, &m, 926 VM_PROT_ALL, 1); 927 PMAP_UNLOCK(&ofw_pmap); 928 ofw_mappings++; 929 } 930 } 931 932 /* 933 * Calculate the last available physical address. 934 */ 935 for (i = 0; phys_avail[i + 2] != 0; i += 2) 936 ; 937 Maxmem = powerpc_btop(phys_avail[i + 1]); 938 939 /* 940 * Initialize the kernel pmap (which is statically allocated). 941 */ 942 PMAP_LOCK_INIT(kernel_pmap); 943 for (i = 0; i < 16; i++) { 944 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 945 } 946 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 947 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 948 kernel_pmap->pm_active = ~0; 949 950 moea_cpu_bootstrap(mmup,0); 951 952 pmap_bootstrapped++; 953 954 /* 955 * Set the start and end of kva. 956 */ 957 virtual_avail = VM_MIN_KERNEL_ADDRESS; 958 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 959 960 /* 961 * Allocate a kernel stack with a guard page for thread0 and map it 962 * into the kernel page map. 963 */ 964 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 965 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 966 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 967 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 968 thread0.td_kstack = va; 969 thread0.td_kstack_pages = KSTACK_PAGES; 970 for (i = 0; i < KSTACK_PAGES; i++) { 971 moea_kenter(mmup, va, pa); 972 pa += PAGE_SIZE; 973 va += PAGE_SIZE; 974 } 975 976 /* 977 * Allocate virtual address space for the message buffer. 978 */ 979 pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 980 msgbufp = (struct msgbuf *)virtual_avail; 981 va = virtual_avail; 982 virtual_avail += round_page(MSGBUF_SIZE); 983 while (va < virtual_avail) { 984 moea_kenter(mmup, va, pa); 985 pa += PAGE_SIZE; 986 va += PAGE_SIZE; 987 } 988 989 /* 990 * Allocate virtual address space for the dynamic percpu area. 991 */ 992 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 993 dpcpu = (void *)virtual_avail; 994 va = virtual_avail; 995 virtual_avail += DPCPU_SIZE; 996 while (va < virtual_avail) { 997 moea_kenter(mmup, va, pa); 998 pa += PAGE_SIZE; 999 va += PAGE_SIZE; 1000 } 1001 dpcpu_init(dpcpu, 0); 1002} 1003 1004/* 1005 * Activate a user pmap. The pmap must be activated before it's address 1006 * space can be accessed in any way. 1007 */ 1008void 1009moea_activate(mmu_t mmu, struct thread *td) 1010{ 1011 pmap_t pm, pmr; 1012 1013 /* 1014 * Load all the data we need up front to encourage the compiler to 1015 * not issue any loads while we have interrupts disabled below. 1016 */ 1017 pm = &td->td_proc->p_vmspace->vm_pmap; 1018 pmr = pm->pmap_phys; 1019 1020 pm->pm_active |= PCPU_GET(cpumask); 1021 PCPU_SET(curpmap, pmr); 1022} 1023 1024void 1025moea_deactivate(mmu_t mmu, struct thread *td) 1026{ 1027 pmap_t pm; 1028 1029 pm = &td->td_proc->p_vmspace->vm_pmap; 1030 pm->pm_active &= ~PCPU_GET(cpumask); 1031 PCPU_SET(curpmap, NULL); 1032} 1033 1034void 1035moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1036{ 1037 struct pvo_entry *pvo; 1038 1039 PMAP_LOCK(pm); 1040 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1041 1042 if (pvo != NULL) { 1043 if (wired) { 1044 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1045 pm->pm_stats.wired_count++; 1046 pvo->pvo_vaddr |= PVO_WIRED; 1047 } else { 1048 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1049 pm->pm_stats.wired_count--; 1050 pvo->pvo_vaddr &= ~PVO_WIRED; 1051 } 1052 } 1053 PMAP_UNLOCK(pm); 1054} 1055 1056void 1057moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1058{ 1059 vm_offset_t dst; 1060 vm_offset_t src; 1061 1062 dst = VM_PAGE_TO_PHYS(mdst); 1063 src = VM_PAGE_TO_PHYS(msrc); 1064 1065 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1066} 1067 1068/* 1069 * Zero a page of physical memory by temporarily mapping it into the tlb. 1070 */ 1071void 1072moea_zero_page(mmu_t mmu, vm_page_t m) 1073{ 1074 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1075 void *va = (void *)pa; 1076 1077 bzero(va, PAGE_SIZE); 1078} 1079 1080void 1081moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1082{ 1083 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1084 void *va = (void *)(pa + off); 1085 1086 bzero(va, size); 1087} 1088 1089void 1090moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1091{ 1092 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1093 void *va = (void *)pa; 1094 1095 bzero(va, PAGE_SIZE); 1096} 1097 1098/* 1099 * Map the given physical page at the specified virtual address in the 1100 * target pmap with the protection requested. If specified the page 1101 * will be wired down. 1102 */ 1103void 1104moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1105 boolean_t wired) 1106{ 1107 1108 vm_page_lock_queues(); 1109 PMAP_LOCK(pmap); 1110 moea_enter_locked(pmap, va, m, prot, wired); 1111 vm_page_unlock_queues(); 1112 PMAP_UNLOCK(pmap); 1113} 1114 1115/* 1116 * Map the given physical page at the specified virtual address in the 1117 * target pmap with the protection requested. If specified the page 1118 * will be wired down. 1119 * 1120 * The page queues and pmap must be locked. 1121 */ 1122static void 1123moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1124 boolean_t wired) 1125{ 1126 struct pvo_head *pvo_head; 1127 uma_zone_t zone; 1128 vm_page_t pg; 1129 u_int pte_lo, pvo_flags, was_exec; 1130 int error; 1131 1132 if (!moea_initialized) { 1133 pvo_head = &moea_pvo_kunmanaged; 1134 zone = moea_upvo_zone; 1135 pvo_flags = 0; 1136 pg = NULL; 1137 was_exec = PTE_EXEC; 1138 } else { 1139 pvo_head = vm_page_to_pvoh(m); 1140 pg = m; 1141 zone = moea_mpvo_zone; 1142 pvo_flags = PVO_MANAGED; 1143 was_exec = 0; 1144 } 1145 if (pmap_bootstrapped) 1146 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1147 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1148 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1149 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1150 ("moea_enter_locked: page %p is not busy", m)); 1151 1152 /* XXX change the pvo head for fake pages */ 1153 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1154 pvo_flags &= ~PVO_MANAGED; 1155 pvo_head = &moea_pvo_kunmanaged; 1156 zone = moea_upvo_zone; 1157 } 1158 1159 /* 1160 * If this is a managed page, and it's the first reference to the page, 1161 * clear the execness of the page. Otherwise fetch the execness. 1162 */ 1163 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1164 if (LIST_EMPTY(pvo_head)) { 1165 moea_attr_clear(pg, PTE_EXEC); 1166 } else { 1167 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1168 } 1169 } 1170 1171 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), VM_MEMATTR_DEFAULT); 1172 1173 if (prot & VM_PROT_WRITE) { 1174 pte_lo |= PTE_BW; 1175 if (pmap_bootstrapped && 1176 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1177 vm_page_flag_set(m, PG_WRITEABLE); 1178 } else 1179 pte_lo |= PTE_BR; 1180 1181 if (prot & VM_PROT_EXECUTE) 1182 pvo_flags |= PVO_EXECUTABLE; 1183 1184 if (wired) 1185 pvo_flags |= PVO_WIRED; 1186 1187 if ((m->flags & PG_FICTITIOUS) != 0) 1188 pvo_flags |= PVO_FAKE; 1189 1190 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1191 pte_lo, pvo_flags); 1192 1193 /* 1194 * Flush the real page from the instruction cache if this page is 1195 * mapped executable and cacheable and was not previously mapped (or 1196 * was not mapped executable). 1197 */ 1198 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1199 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1200 /* 1201 * Flush the real memory from the cache. 1202 */ 1203 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1204 if (pg != NULL) 1205 moea_attr_save(pg, PTE_EXEC); 1206 } 1207 1208 /* XXX syncicache always until problems are sorted */ 1209 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1210} 1211 1212/* 1213 * Maps a sequence of resident pages belonging to the same object. 1214 * The sequence begins with the given page m_start. This page is 1215 * mapped at the given virtual address start. Each subsequent page is 1216 * mapped at a virtual address that is offset from start by the same 1217 * amount as the page is offset from m_start within the object. The 1218 * last page in the sequence is the page with the largest offset from 1219 * m_start that can be mapped at a virtual address less than the given 1220 * virtual address end. Not every virtual page between start and end 1221 * is mapped; only those for which a resident page exists with the 1222 * corresponding offset from m_start are mapped. 1223 */ 1224void 1225moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1226 vm_page_t m_start, vm_prot_t prot) 1227{ 1228 vm_page_t m; 1229 vm_pindex_t diff, psize; 1230 1231 psize = atop(end - start); 1232 m = m_start; 1233 vm_page_lock_queues(); 1234 PMAP_LOCK(pm); 1235 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1236 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1237 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1238 m = TAILQ_NEXT(m, listq); 1239 } 1240 vm_page_unlock_queues(); 1241 PMAP_UNLOCK(pm); 1242} 1243 1244void 1245moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1246 vm_prot_t prot) 1247{ 1248 1249 vm_page_lock_queues(); 1250 PMAP_LOCK(pm); 1251 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1252 FALSE); 1253 vm_page_unlock_queues(); 1254 PMAP_UNLOCK(pm); 1255} 1256 1257vm_paddr_t 1258moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1259{ 1260 struct pvo_entry *pvo; 1261 vm_paddr_t pa; 1262 1263 PMAP_LOCK(pm); 1264 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1265 if (pvo == NULL) 1266 pa = 0; 1267 else 1268 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1269 PMAP_UNLOCK(pm); 1270 return (pa); 1271} 1272 1273/* 1274 * Atomically extract and hold the physical page with the given 1275 * pmap and virtual address pair if that mapping permits the given 1276 * protection. 1277 */ 1278vm_page_t 1279moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1280{ 1281 struct pvo_entry *pvo; 1282 vm_page_t m; 1283 vm_paddr_t pa; 1284 1285 m = NULL; 1286 pa = 0; 1287 PMAP_LOCK(pmap); 1288retry: 1289 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1290 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1291 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1292 (prot & VM_PROT_WRITE) == 0)) { 1293 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1294 goto retry; 1295 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1296 vm_page_hold(m); 1297 } 1298 PA_UNLOCK_COND(pa); 1299 PMAP_UNLOCK(pmap); 1300 return (m); 1301} 1302 1303void 1304moea_init(mmu_t mmu) 1305{ 1306 1307 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1308 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1309 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1310 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1311 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1312 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1313 moea_initialized = TRUE; 1314} 1315 1316boolean_t 1317moea_is_referenced(mmu_t mmu, vm_page_t m) 1318{ 1319 1320 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1321 ("moea_is_referenced: page %p is not managed", m)); 1322 return (moea_query_bit(m, PTE_REF)); 1323} 1324 1325boolean_t 1326moea_is_modified(mmu_t mmu, vm_page_t m) 1327{ 1328 1329 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1330 ("moea_is_modified: page %p is not managed", m)); 1331 1332 /* 1333 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1334 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1335 * is clear, no PTEs can have PTE_CHG set. 1336 */ 1337 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1338 if ((m->oflags & VPO_BUSY) == 0 && 1339 (m->flags & PG_WRITEABLE) == 0) 1340 return (FALSE); 1341 return (moea_query_bit(m, PTE_CHG)); 1342} 1343 1344void 1345moea_clear_reference(mmu_t mmu, vm_page_t m) 1346{ 1347 1348 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1349 ("moea_clear_reference: page %p is not managed", m)); 1350 moea_clear_bit(m, PTE_REF); 1351} 1352 1353void 1354moea_clear_modify(mmu_t mmu, vm_page_t m) 1355{ 1356 1357 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1358 ("moea_clear_modify: page %p is not managed", m)); 1359 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1360 KASSERT((m->oflags & VPO_BUSY) == 0, 1361 ("moea_clear_modify: page %p is busy", m)); 1362 1363 /* 1364 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1365 * set. If the object containing the page is locked and the page is 1366 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1367 */ 1368 if ((m->flags & PG_WRITEABLE) == 0) 1369 return; 1370 moea_clear_bit(m, PTE_CHG); 1371} 1372 1373/* 1374 * Clear the write and modified bits in each of the given page's mappings. 1375 */ 1376void 1377moea_remove_write(mmu_t mmu, vm_page_t m) 1378{ 1379 struct pvo_entry *pvo; 1380 struct pte *pt; 1381 pmap_t pmap; 1382 u_int lo; 1383 1384 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1385 ("moea_remove_write: page %p is not managed", m)); 1386 1387 /* 1388 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1389 * another thread while the object is locked. Thus, if PG_WRITEABLE 1390 * is clear, no page table entries need updating. 1391 */ 1392 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1393 if ((m->oflags & VPO_BUSY) == 0 && 1394 (m->flags & PG_WRITEABLE) == 0) 1395 return; 1396 vm_page_lock_queues(); 1397 lo = moea_attr_fetch(m); 1398 powerpc_sync(); 1399 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1400 pmap = pvo->pvo_pmap; 1401 PMAP_LOCK(pmap); 1402 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1403 pt = moea_pvo_to_pte(pvo, -1); 1404 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1405 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1406 if (pt != NULL) { 1407 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1408 lo |= pvo->pvo_pte.pte.pte_lo; 1409 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1410 moea_pte_change(pt, &pvo->pvo_pte.pte, 1411 pvo->pvo_vaddr); 1412 mtx_unlock(&moea_table_mutex); 1413 } 1414 } 1415 PMAP_UNLOCK(pmap); 1416 } 1417 if ((lo & PTE_CHG) != 0) { 1418 moea_attr_clear(m, PTE_CHG); 1419 vm_page_dirty(m); 1420 } 1421 vm_page_flag_clear(m, PG_WRITEABLE); 1422 vm_page_unlock_queues(); 1423} 1424 1425/* 1426 * moea_ts_referenced: 1427 * 1428 * Return a count of reference bits for a page, clearing those bits. 1429 * It is not necessary for every reference bit to be cleared, but it 1430 * is necessary that 0 only be returned when there are truly no 1431 * reference bits set. 1432 * 1433 * XXX: The exact number of bits to check and clear is a matter that 1434 * should be tested and standardized at some point in the future for 1435 * optimal aging of shared pages. 1436 */ 1437boolean_t 1438moea_ts_referenced(mmu_t mmu, vm_page_t m) 1439{ 1440 1441 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1442 ("moea_ts_referenced: page %p is not managed", m)); 1443 return (moea_clear_bit(m, PTE_REF)); 1444} 1445 1446/* 1447 * Modify the WIMG settings of all mappings for a page. 1448 */ 1449void 1450moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1451{ 1452 struct pvo_entry *pvo; 1453 struct pte *pt; 1454 pmap_t pmap; 1455 u_int lo; 1456 1457 vm_page_lock_queues(); 1458 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1459 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1460 pmap = pvo->pvo_pmap; 1461 PMAP_LOCK(pmap); 1462 mtx_lock(&moea_table_mutex); 1463 pt = moea_pvo_to_pte(pvo, -1); 1464 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1465 pvo->pvo_pte.pte.pte_lo |= lo; 1466 if (pt != NULL) { 1467 moea_pte_change(pt, &pvo->pvo_pte.pte, 1468 pvo->pvo_vaddr); 1469 if (pvo->pvo_pmap == kernel_pmap) 1470 isync(); 1471 } 1472 mtx_unlock(&moea_table_mutex); 1473 PMAP_UNLOCK(pmap); 1474 } 1475 m->md.mdpg_cache_attrs = ma; 1476 vm_page_unlock_queues(); 1477} 1478 1479/* 1480 * Map a wired page into kernel virtual address space. 1481 */ 1482void 1483moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1484{ 1485 1486 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1487} 1488 1489void 1490moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1491{ 1492 u_int pte_lo; 1493 int error; 1494 1495#if 0 1496 if (va < VM_MIN_KERNEL_ADDRESS) 1497 panic("moea_kenter: attempt to enter non-kernel address %#x", 1498 va); 1499#endif 1500 1501 pte_lo = moea_calc_wimg(pa, ma); 1502 1503 PMAP_LOCK(kernel_pmap); 1504 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1505 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1506 1507 if (error != 0 && error != ENOENT) 1508 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1509 pa, error); 1510 1511 /* 1512 * Flush the real memory from the instruction cache. 1513 */ 1514 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1515 moea_syncicache(pa, PAGE_SIZE); 1516 } 1517 PMAP_UNLOCK(kernel_pmap); 1518} 1519 1520/* 1521 * Extract the physical page address associated with the given kernel virtual 1522 * address. 1523 */ 1524vm_offset_t 1525moea_kextract(mmu_t mmu, vm_offset_t va) 1526{ 1527 struct pvo_entry *pvo; 1528 vm_paddr_t pa; 1529 1530 /* 1531 * Allow direct mappings on 32-bit OEA 1532 */ 1533 if (va < VM_MIN_KERNEL_ADDRESS) { 1534 return (va); 1535 } 1536 1537 PMAP_LOCK(kernel_pmap); 1538 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1539 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1540 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1541 PMAP_UNLOCK(kernel_pmap); 1542 return (pa); 1543} 1544 1545/* 1546 * Remove a wired page from kernel virtual address space. 1547 */ 1548void 1549moea_kremove(mmu_t mmu, vm_offset_t va) 1550{ 1551 1552 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1553} 1554 1555/* 1556 * Map a range of physical addresses into kernel virtual address space. 1557 * 1558 * The value passed in *virt is a suggested virtual address for the mapping. 1559 * Architectures which can support a direct-mapped physical to virtual region 1560 * can return the appropriate address within that region, leaving '*virt' 1561 * unchanged. We cannot and therefore do not; *virt is updated with the 1562 * first usable address after the mapped region. 1563 */ 1564vm_offset_t 1565moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1566 vm_offset_t pa_end, int prot) 1567{ 1568 vm_offset_t sva, va; 1569 1570 sva = *virt; 1571 va = sva; 1572 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1573 moea_kenter(mmu, va, pa_start); 1574 *virt = va; 1575 return (sva); 1576} 1577 1578/* 1579 * Returns true if the pmap's pv is one of the first 1580 * 16 pvs linked to from this page. This count may 1581 * be changed upwards or downwards in the future; it 1582 * is only necessary that true be returned for a small 1583 * subset of pmaps for proper page aging. 1584 */ 1585boolean_t 1586moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1587{ 1588 int loops; 1589 struct pvo_entry *pvo; 1590 boolean_t rv; 1591 1592 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1593 ("moea_page_exists_quick: page %p is not managed", m)); 1594 loops = 0; 1595 rv = FALSE; 1596 vm_page_lock_queues(); 1597 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1598 if (pvo->pvo_pmap == pmap) { 1599 rv = TRUE; 1600 break; 1601 } 1602 if (++loops >= 16) 1603 break; 1604 } 1605 vm_page_unlock_queues(); 1606 return (rv); 1607} 1608 1609/* 1610 * Return the number of managed mappings to the given physical page 1611 * that are wired. 1612 */ 1613int 1614moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1615{ 1616 struct pvo_entry *pvo; 1617 int count; 1618 1619 count = 0; 1620 if ((m->flags & PG_FICTITIOUS) != 0) 1621 return (count); 1622 vm_page_lock_queues(); 1623 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1624 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1625 count++; 1626 vm_page_unlock_queues(); 1627 return (count); 1628} 1629 1630static u_int moea_vsidcontext; 1631 1632void 1633moea_pinit(mmu_t mmu, pmap_t pmap) 1634{ 1635 int i, mask; 1636 u_int entropy; 1637 1638 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1639 PMAP_LOCK_INIT(pmap); 1640 1641 entropy = 0; 1642 __asm __volatile("mftb %0" : "=r"(entropy)); 1643 1644 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1645 == NULL) { 1646 pmap->pmap_phys = pmap; 1647 } 1648 1649 1650 mtx_lock(&moea_vsid_mutex); 1651 /* 1652 * Allocate some segment registers for this pmap. 1653 */ 1654 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1655 u_int hash, n; 1656 1657 /* 1658 * Create a new value by mutiplying by a prime and adding in 1659 * entropy from the timebase register. This is to make the 1660 * VSID more random so that the PT hash function collides 1661 * less often. (Note that the prime casues gcc to do shifts 1662 * instead of a multiply.) 1663 */ 1664 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1665 hash = moea_vsidcontext & (NPMAPS - 1); 1666 if (hash == 0) /* 0 is special, avoid it */ 1667 continue; 1668 n = hash >> 5; 1669 mask = 1 << (hash & (VSID_NBPW - 1)); 1670 hash = (moea_vsidcontext & 0xfffff); 1671 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1672 /* anything free in this bucket? */ 1673 if (moea_vsid_bitmap[n] == 0xffffffff) { 1674 entropy = (moea_vsidcontext >> 20); 1675 continue; 1676 } 1677 i = ffs(~moea_vsid_bitmap[n]) - 1; 1678 mask = 1 << i; 1679 hash &= 0xfffff & ~(VSID_NBPW - 1); 1680 hash |= i; 1681 } 1682 moea_vsid_bitmap[n] |= mask; 1683 for (i = 0; i < 16; i++) 1684 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1685 mtx_unlock(&moea_vsid_mutex); 1686 return; 1687 } 1688 1689 mtx_unlock(&moea_vsid_mutex); 1690 panic("moea_pinit: out of segments"); 1691} 1692 1693/* 1694 * Initialize the pmap associated with process 0. 1695 */ 1696void 1697moea_pinit0(mmu_t mmu, pmap_t pm) 1698{ 1699 1700 moea_pinit(mmu, pm); 1701 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1702} 1703 1704/* 1705 * Set the physical protection on the specified range of this map as requested. 1706 */ 1707void 1708moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1709 vm_prot_t prot) 1710{ 1711 struct pvo_entry *pvo; 1712 struct pte *pt; 1713 int pteidx; 1714 1715 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1716 ("moea_protect: non current pmap")); 1717 1718 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1719 moea_remove(mmu, pm, sva, eva); 1720 return; 1721 } 1722 1723 vm_page_lock_queues(); 1724 PMAP_LOCK(pm); 1725 for (; sva < eva; sva += PAGE_SIZE) { 1726 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1727 if (pvo == NULL) 1728 continue; 1729 1730 if ((prot & VM_PROT_EXECUTE) == 0) 1731 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1732 1733 /* 1734 * Grab the PTE pointer before we diddle with the cached PTE 1735 * copy. 1736 */ 1737 pt = moea_pvo_to_pte(pvo, pteidx); 1738 /* 1739 * Change the protection of the page. 1740 */ 1741 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1742 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1743 1744 /* 1745 * If the PVO is in the page table, update that pte as well. 1746 */ 1747 if (pt != NULL) { 1748 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1749 mtx_unlock(&moea_table_mutex); 1750 } 1751 } 1752 vm_page_unlock_queues(); 1753 PMAP_UNLOCK(pm); 1754} 1755 1756/* 1757 * Map a list of wired pages into kernel virtual address space. This is 1758 * intended for temporary mappings which do not need page modification or 1759 * references recorded. Existing mappings in the region are overwritten. 1760 */ 1761void 1762moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1763{ 1764 vm_offset_t va; 1765 1766 va = sva; 1767 while (count-- > 0) { 1768 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1769 va += PAGE_SIZE; 1770 m++; 1771 } 1772} 1773 1774/* 1775 * Remove page mappings from kernel virtual address space. Intended for 1776 * temporary mappings entered by moea_qenter. 1777 */ 1778void 1779moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1780{ 1781 vm_offset_t va; 1782 1783 va = sva; 1784 while (count-- > 0) { 1785 moea_kremove(mmu, va); 1786 va += PAGE_SIZE; 1787 } 1788} 1789 1790void 1791moea_release(mmu_t mmu, pmap_t pmap) 1792{ 1793 int idx, mask; 1794 1795 /* 1796 * Free segment register's VSID 1797 */ 1798 if (pmap->pm_sr[0] == 0) 1799 panic("moea_release"); 1800 1801 mtx_lock(&moea_vsid_mutex); 1802 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1803 mask = 1 << (idx % VSID_NBPW); 1804 idx /= VSID_NBPW; 1805 moea_vsid_bitmap[idx] &= ~mask; 1806 mtx_unlock(&moea_vsid_mutex); 1807 PMAP_LOCK_DESTROY(pmap); 1808} 1809 1810/* 1811 * Remove the given range of addresses from the specified map. 1812 */ 1813void 1814moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1815{ 1816 struct pvo_entry *pvo; 1817 int pteidx; 1818 1819 vm_page_lock_queues(); 1820 PMAP_LOCK(pm); 1821 for (; sva < eva; sva += PAGE_SIZE) { 1822 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1823 if (pvo != NULL) { 1824 moea_pvo_remove(pvo, pteidx); 1825 } 1826 } 1827 PMAP_UNLOCK(pm); 1828 vm_page_unlock_queues(); 1829} 1830 1831/* 1832 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1833 * will reflect changes in pte's back to the vm_page. 1834 */ 1835void 1836moea_remove_all(mmu_t mmu, vm_page_t m) 1837{ 1838 struct pvo_head *pvo_head; 1839 struct pvo_entry *pvo, *next_pvo; 1840 pmap_t pmap; 1841 1842 vm_page_lock_queues(); 1843 pvo_head = vm_page_to_pvoh(m); 1844 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1845 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1846 1847 MOEA_PVO_CHECK(pvo); /* sanity check */ 1848 pmap = pvo->pvo_pmap; 1849 PMAP_LOCK(pmap); 1850 moea_pvo_remove(pvo, -1); 1851 PMAP_UNLOCK(pmap); 1852 } 1853 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1854 moea_attr_clear(m, PTE_CHG); 1855 vm_page_dirty(m); 1856 } 1857 vm_page_flag_clear(m, PG_WRITEABLE); 1858 vm_page_unlock_queues(); 1859} 1860 1861/* 1862 * Allocate a physical page of memory directly from the phys_avail map. 1863 * Can only be called from moea_bootstrap before avail start and end are 1864 * calculated. 1865 */ 1866static vm_offset_t 1867moea_bootstrap_alloc(vm_size_t size, u_int align) 1868{ 1869 vm_offset_t s, e; 1870 int i, j; 1871 1872 size = round_page(size); 1873 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1874 if (align != 0) 1875 s = (phys_avail[i] + align - 1) & ~(align - 1); 1876 else 1877 s = phys_avail[i]; 1878 e = s + size; 1879 1880 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1881 continue; 1882 1883 if (s == phys_avail[i]) { 1884 phys_avail[i] += size; 1885 } else if (e == phys_avail[i + 1]) { 1886 phys_avail[i + 1] -= size; 1887 } else { 1888 for (j = phys_avail_count * 2; j > i; j -= 2) { 1889 phys_avail[j] = phys_avail[j - 2]; 1890 phys_avail[j + 1] = phys_avail[j - 1]; 1891 } 1892 1893 phys_avail[i + 3] = phys_avail[i + 1]; 1894 phys_avail[i + 1] = s; 1895 phys_avail[i + 2] = e; 1896 phys_avail_count++; 1897 } 1898 1899 return (s); 1900 } 1901 panic("moea_bootstrap_alloc: could not allocate memory"); 1902} 1903 1904static void 1905moea_syncicache(vm_offset_t pa, vm_size_t len) 1906{ 1907 __syncicache((void *)pa, len); 1908} 1909 1910static int 1911moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1912 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1913{ 1914 struct pvo_entry *pvo; 1915 u_int sr; 1916 int first; 1917 u_int ptegidx; 1918 int i; 1919 int bootstrap; 1920 1921 moea_pvo_enter_calls++; 1922 first = 0; 1923 bootstrap = 0; 1924 1925 /* 1926 * Compute the PTE Group index. 1927 */ 1928 va &= ~ADDR_POFF; 1929 sr = va_to_sr(pm->pm_sr, va); 1930 ptegidx = va_to_pteg(sr, va); 1931 1932 /* 1933 * Remove any existing mapping for this page. Reuse the pvo entry if 1934 * there is a mapping. 1935 */ 1936 mtx_lock(&moea_table_mutex); 1937 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1938 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1939 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1940 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1941 (pte_lo & PTE_PP)) { 1942 mtx_unlock(&moea_table_mutex); 1943 return (0); 1944 } 1945 moea_pvo_remove(pvo, -1); 1946 break; 1947 } 1948 } 1949 1950 /* 1951 * If we aren't overwriting a mapping, try to allocate. 1952 */ 1953 if (moea_initialized) { 1954 pvo = uma_zalloc(zone, M_NOWAIT); 1955 } else { 1956 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1957 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1958 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1959 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1960 } 1961 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1962 moea_bpvo_pool_index++; 1963 bootstrap = 1; 1964 } 1965 1966 if (pvo == NULL) { 1967 mtx_unlock(&moea_table_mutex); 1968 return (ENOMEM); 1969 } 1970 1971 moea_pvo_entries++; 1972 pvo->pvo_vaddr = va; 1973 pvo->pvo_pmap = pm; 1974 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1975 pvo->pvo_vaddr &= ~ADDR_POFF; 1976 if (flags & VM_PROT_EXECUTE) 1977 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1978 if (flags & PVO_WIRED) 1979 pvo->pvo_vaddr |= PVO_WIRED; 1980 if (pvo_head != &moea_pvo_kunmanaged) 1981 pvo->pvo_vaddr |= PVO_MANAGED; 1982 if (bootstrap) 1983 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1984 if (flags & PVO_FAKE) 1985 pvo->pvo_vaddr |= PVO_FAKE; 1986 1987 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1988 1989 /* 1990 * Remember if the list was empty and therefore will be the first 1991 * item. 1992 */ 1993 if (LIST_FIRST(pvo_head) == NULL) 1994 first = 1; 1995 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1996 1997 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1998 pm->pm_stats.wired_count++; 1999 pm->pm_stats.resident_count++; 2000 2001 /* 2002 * We hope this succeeds but it isn't required. 2003 */ 2004 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2005 if (i >= 0) { 2006 PVO_PTEGIDX_SET(pvo, i); 2007 } else { 2008 panic("moea_pvo_enter: overflow"); 2009 moea_pte_overflow++; 2010 } 2011 mtx_unlock(&moea_table_mutex); 2012 2013 return (first ? ENOENT : 0); 2014} 2015 2016static void 2017moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2018{ 2019 struct pte *pt; 2020 2021 /* 2022 * If there is an active pte entry, we need to deactivate it (and 2023 * save the ref & cfg bits). 2024 */ 2025 pt = moea_pvo_to_pte(pvo, pteidx); 2026 if (pt != NULL) { 2027 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2028 mtx_unlock(&moea_table_mutex); 2029 PVO_PTEGIDX_CLR(pvo); 2030 } else { 2031 moea_pte_overflow--; 2032 } 2033 2034 /* 2035 * Update our statistics. 2036 */ 2037 pvo->pvo_pmap->pm_stats.resident_count--; 2038 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2039 pvo->pvo_pmap->pm_stats.wired_count--; 2040 2041 /* 2042 * Save the REF/CHG bits into their cache if the page is managed. 2043 */ 2044 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2045 struct vm_page *pg; 2046 2047 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2048 if (pg != NULL) { 2049 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2050 (PTE_REF | PTE_CHG)); 2051 } 2052 } 2053 2054 /* 2055 * Remove this PVO from the PV list. 2056 */ 2057 LIST_REMOVE(pvo, pvo_vlink); 2058 2059 /* 2060 * Remove this from the overflow list and return it to the pool 2061 * if we aren't going to reuse it. 2062 */ 2063 LIST_REMOVE(pvo, pvo_olink); 2064 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2065 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2066 moea_upvo_zone, pvo); 2067 moea_pvo_entries--; 2068 moea_pvo_remove_calls++; 2069} 2070 2071static __inline int 2072moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2073{ 2074 int pteidx; 2075 2076 /* 2077 * We can find the actual pte entry without searching by grabbing 2078 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2079 * noticing the HID bit. 2080 */ 2081 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2082 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2083 pteidx ^= moea_pteg_mask * 8; 2084 2085 return (pteidx); 2086} 2087 2088static struct pvo_entry * 2089moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2090{ 2091 struct pvo_entry *pvo; 2092 int ptegidx; 2093 u_int sr; 2094 2095 va &= ~ADDR_POFF; 2096 sr = va_to_sr(pm->pm_sr, va); 2097 ptegidx = va_to_pteg(sr, va); 2098 2099 mtx_lock(&moea_table_mutex); 2100 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2101 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2102 if (pteidx_p) 2103 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2104 break; 2105 } 2106 } 2107 mtx_unlock(&moea_table_mutex); 2108 2109 return (pvo); 2110} 2111 2112static struct pte * 2113moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2114{ 2115 struct pte *pt; 2116 2117 /* 2118 * If we haven't been supplied the ptegidx, calculate it. 2119 */ 2120 if (pteidx == -1) { 2121 int ptegidx; 2122 u_int sr; 2123 2124 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2125 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2126 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2127 } 2128 2129 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2130 mtx_lock(&moea_table_mutex); 2131 2132 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2133 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2134 "valid pte index", pvo); 2135 } 2136 2137 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2138 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2139 "pvo but no valid pte", pvo); 2140 } 2141 2142 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2143 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2144 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2145 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2146 } 2147 2148 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2149 != 0) { 2150 panic("moea_pvo_to_pte: pvo %p pte does not match " 2151 "pte %p in moea_pteg_table", pvo, pt); 2152 } 2153 2154 mtx_assert(&moea_table_mutex, MA_OWNED); 2155 return (pt); 2156 } 2157 2158 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2159 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2160 "moea_pteg_table but valid in pvo", pvo, pt); 2161 } 2162 2163 mtx_unlock(&moea_table_mutex); 2164 return (NULL); 2165} 2166 2167/* 2168 * XXX: THIS STUFF SHOULD BE IN pte.c? 2169 */ 2170int 2171moea_pte_spill(vm_offset_t addr) 2172{ 2173 struct pvo_entry *source_pvo, *victim_pvo; 2174 struct pvo_entry *pvo; 2175 int ptegidx, i, j; 2176 u_int sr; 2177 struct pteg *pteg; 2178 struct pte *pt; 2179 2180 moea_pte_spills++; 2181 2182 sr = mfsrin(addr); 2183 ptegidx = va_to_pteg(sr, addr); 2184 2185 /* 2186 * Have to substitute some entry. Use the primary hash for this. 2187 * Use low bits of timebase as random generator. 2188 */ 2189 pteg = &moea_pteg_table[ptegidx]; 2190 mtx_lock(&moea_table_mutex); 2191 __asm __volatile("mftb %0" : "=r"(i)); 2192 i &= 7; 2193 pt = &pteg->pt[i]; 2194 2195 source_pvo = NULL; 2196 victim_pvo = NULL; 2197 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2198 /* 2199 * We need to find a pvo entry for this address. 2200 */ 2201 MOEA_PVO_CHECK(pvo); 2202 if (source_pvo == NULL && 2203 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2204 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2205 /* 2206 * Now found an entry to be spilled into the pteg. 2207 * The PTE is now valid, so we know it's active. 2208 */ 2209 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2210 2211 if (j >= 0) { 2212 PVO_PTEGIDX_SET(pvo, j); 2213 moea_pte_overflow--; 2214 MOEA_PVO_CHECK(pvo); 2215 mtx_unlock(&moea_table_mutex); 2216 return (1); 2217 } 2218 2219 source_pvo = pvo; 2220 2221 if (victim_pvo != NULL) 2222 break; 2223 } 2224 2225 /* 2226 * We also need the pvo entry of the victim we are replacing 2227 * so save the R & C bits of the PTE. 2228 */ 2229 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2230 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2231 victim_pvo = pvo; 2232 if (source_pvo != NULL) 2233 break; 2234 } 2235 } 2236 2237 if (source_pvo == NULL) { 2238 mtx_unlock(&moea_table_mutex); 2239 return (0); 2240 } 2241 2242 if (victim_pvo == NULL) { 2243 if ((pt->pte_hi & PTE_HID) == 0) 2244 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2245 "entry", pt); 2246 2247 /* 2248 * If this is a secondary PTE, we need to search it's primary 2249 * pvo bucket for the matching PVO. 2250 */ 2251 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2252 pvo_olink) { 2253 MOEA_PVO_CHECK(pvo); 2254 /* 2255 * We also need the pvo entry of the victim we are 2256 * replacing so save the R & C bits of the PTE. 2257 */ 2258 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2259 victim_pvo = pvo; 2260 break; 2261 } 2262 } 2263 2264 if (victim_pvo == NULL) 2265 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2266 "entry", pt); 2267 } 2268 2269 /* 2270 * We are invalidating the TLB entry for the EA we are replacing even 2271 * though it's valid. If we don't, we lose any ref/chg bit changes 2272 * contained in the TLB entry. 2273 */ 2274 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2275 2276 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2277 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2278 2279 PVO_PTEGIDX_CLR(victim_pvo); 2280 PVO_PTEGIDX_SET(source_pvo, i); 2281 moea_pte_replacements++; 2282 2283 MOEA_PVO_CHECK(victim_pvo); 2284 MOEA_PVO_CHECK(source_pvo); 2285 2286 mtx_unlock(&moea_table_mutex); 2287 return (1); 2288} 2289 2290static int 2291moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2292{ 2293 struct pte *pt; 2294 int i; 2295 2296 mtx_assert(&moea_table_mutex, MA_OWNED); 2297 2298 /* 2299 * First try primary hash. 2300 */ 2301 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2302 if ((pt->pte_hi & PTE_VALID) == 0) { 2303 pvo_pt->pte_hi &= ~PTE_HID; 2304 moea_pte_set(pt, pvo_pt); 2305 return (i); 2306 } 2307 } 2308 2309 /* 2310 * Now try secondary hash. 2311 */ 2312 ptegidx ^= moea_pteg_mask; 2313 2314 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2315 if ((pt->pte_hi & PTE_VALID) == 0) { 2316 pvo_pt->pte_hi |= PTE_HID; 2317 moea_pte_set(pt, pvo_pt); 2318 return (i); 2319 } 2320 } 2321 2322 panic("moea_pte_insert: overflow"); 2323 return (-1); 2324} 2325 2326static boolean_t 2327moea_query_bit(vm_page_t m, int ptebit) 2328{ 2329 struct pvo_entry *pvo; 2330 struct pte *pt; 2331 2332 if (moea_attr_fetch(m) & ptebit) 2333 return (TRUE); 2334 2335 vm_page_lock_queues(); 2336 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2337 MOEA_PVO_CHECK(pvo); /* sanity check */ 2338 2339 /* 2340 * See if we saved the bit off. If so, cache it and return 2341 * success. 2342 */ 2343 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2344 moea_attr_save(m, ptebit); 2345 MOEA_PVO_CHECK(pvo); /* sanity check */ 2346 vm_page_unlock_queues(); 2347 return (TRUE); 2348 } 2349 } 2350 2351 /* 2352 * No luck, now go through the hard part of looking at the PTEs 2353 * themselves. Sync so that any pending REF/CHG bits are flushed to 2354 * the PTEs. 2355 */ 2356 powerpc_sync(); 2357 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2358 MOEA_PVO_CHECK(pvo); /* sanity check */ 2359 2360 /* 2361 * See if this pvo has a valid PTE. if so, fetch the 2362 * REF/CHG bits from the valid PTE. If the appropriate 2363 * ptebit is set, cache it and return success. 2364 */ 2365 pt = moea_pvo_to_pte(pvo, -1); 2366 if (pt != NULL) { 2367 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2368 mtx_unlock(&moea_table_mutex); 2369 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2370 moea_attr_save(m, ptebit); 2371 MOEA_PVO_CHECK(pvo); /* sanity check */ 2372 vm_page_unlock_queues(); 2373 return (TRUE); 2374 } 2375 } 2376 } 2377 2378 vm_page_unlock_queues(); 2379 return (FALSE); 2380} 2381 2382static u_int 2383moea_clear_bit(vm_page_t m, int ptebit) 2384{ 2385 u_int count; 2386 struct pvo_entry *pvo; 2387 struct pte *pt; 2388 2389 vm_page_lock_queues(); 2390 2391 /* 2392 * Clear the cached value. 2393 */ 2394 moea_attr_clear(m, ptebit); 2395 2396 /* 2397 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2398 * we can reset the right ones). note that since the pvo entries and 2399 * list heads are accessed via BAT0 and are never placed in the page 2400 * table, we don't have to worry about further accesses setting the 2401 * REF/CHG bits. 2402 */ 2403 powerpc_sync(); 2404 2405 /* 2406 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2407 * valid pte clear the ptebit from the valid pte. 2408 */ 2409 count = 0; 2410 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2411 MOEA_PVO_CHECK(pvo); /* sanity check */ 2412 pt = moea_pvo_to_pte(pvo, -1); 2413 if (pt != NULL) { 2414 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2415 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2416 count++; 2417 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2418 } 2419 mtx_unlock(&moea_table_mutex); 2420 } 2421 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2422 MOEA_PVO_CHECK(pvo); /* sanity check */ 2423 } 2424 2425 vm_page_unlock_queues(); 2426 return (count); 2427} 2428 2429/* 2430 * Return true if the physical range is encompassed by the battable[idx] 2431 */ 2432static int 2433moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2434{ 2435 u_int prot; 2436 u_int32_t start; 2437 u_int32_t end; 2438 u_int32_t bat_ble; 2439 2440 /* 2441 * Return immediately if not a valid mapping 2442 */ 2443 if (!battable[idx].batu & BAT_Vs) 2444 return (EINVAL); 2445 2446 /* 2447 * The BAT entry must be cache-inhibited, guarded, and r/w 2448 * so it can function as an i/o page 2449 */ 2450 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2451 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2452 return (EPERM); 2453 2454 /* 2455 * The address should be within the BAT range. Assume that the 2456 * start address in the BAT has the correct alignment (thus 2457 * not requiring masking) 2458 */ 2459 start = battable[idx].batl & BAT_PBS; 2460 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2461 end = start | (bat_ble << 15) | 0x7fff; 2462 2463 if ((pa < start) || ((pa + size) > end)) 2464 return (ERANGE); 2465 2466 return (0); 2467} 2468 2469boolean_t 2470moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2471{ 2472 int i; 2473 2474 /* 2475 * This currently does not work for entries that 2476 * overlap 256M BAT segments. 2477 */ 2478 2479 for(i = 0; i < 16; i++) 2480 if (moea_bat_mapped(i, pa, size) == 0) 2481 return (0); 2482 2483 return (EFAULT); 2484} 2485 2486/* 2487 * Map a set of physical memory pages into the kernel virtual 2488 * address space. Return a pointer to where it is mapped. This 2489 * routine is intended to be used for mapping device memory, 2490 * NOT real memory. 2491 */ 2492void * 2493moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2494{ 2495 2496 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2497} 2498 2499void * 2500moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2501{ 2502 vm_offset_t va, tmpva, ppa, offset; 2503 int i; 2504 2505 ppa = trunc_page(pa); 2506 offset = pa & PAGE_MASK; 2507 size = roundup(offset + size, PAGE_SIZE); 2508 2509 /* 2510 * If the physical address lies within a valid BAT table entry, 2511 * return the 1:1 mapping. This currently doesn't work 2512 * for regions that overlap 256M BAT segments. 2513 */ 2514 for (i = 0; i < 16; i++) { 2515 if (moea_bat_mapped(i, pa, size) == 0) 2516 return ((void *) pa); 2517 } 2518 2519 va = kmem_alloc_nofault(kernel_map, size); 2520 if (!va) 2521 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2522 2523 for (tmpva = va; size > 0;) { 2524 moea_kenter_attr(mmu, tmpva, ppa, ma); 2525 tlbie(tmpva); 2526 size -= PAGE_SIZE; 2527 tmpva += PAGE_SIZE; 2528 ppa += PAGE_SIZE; 2529 } 2530 2531 return ((void *)(va + offset)); 2532} 2533 2534void 2535moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2536{ 2537 vm_offset_t base, offset; 2538 2539 /* 2540 * If this is outside kernel virtual space, then it's a 2541 * battable entry and doesn't require unmapping 2542 */ 2543 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2544 base = trunc_page(va); 2545 offset = va & PAGE_MASK; 2546 size = roundup(offset + size, PAGE_SIZE); 2547 kmem_free(kernel_map, base, size); 2548 } 2549} 2550 2551static void 2552moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2553{ 2554 struct pvo_entry *pvo; 2555 vm_offset_t lim; 2556 vm_paddr_t pa; 2557 vm_size_t len; 2558 2559 PMAP_LOCK(pm); 2560 while (sz > 0) { 2561 lim = round_page(va); 2562 len = MIN(lim - va, sz); 2563 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2564 if (pvo != NULL) { 2565 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2566 (va & ADDR_POFF); 2567 moea_syncicache(pa, len); 2568 } 2569 va += len; 2570 sz -= len; 2571 } 2572 PMAP_UNLOCK(pm); 2573} 2574