mmu_oea.c revision 212627
1139825Simp/*- 290643Sbenno * Copyright (c) 2001 The NetBSD Foundation, Inc. 390643Sbenno * All rights reserved. 490643Sbenno * 590643Sbenno * This code is derived from software contributed to The NetBSD Foundation 690643Sbenno * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 790643Sbenno * 890643Sbenno * Redistribution and use in source and binary forms, with or without 990643Sbenno * modification, are permitted provided that the following conditions 1090643Sbenno * are met: 1190643Sbenno * 1. Redistributions of source code must retain the above copyright 1290643Sbenno * notice, this list of conditions and the following disclaimer. 1390643Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1490643Sbenno * notice, this list of conditions and the following disclaimer in the 1590643Sbenno * documentation and/or other materials provided with the distribution. 1690643Sbenno * 3. All advertising materials mentioning features or use of this software 1790643Sbenno * must display the following acknowledgement: 1890643Sbenno * This product includes software developed by the NetBSD 1990643Sbenno * Foundation, Inc. and its contributors. 2090643Sbenno * 4. Neither the name of The NetBSD Foundation nor the names of its 2190643Sbenno * contributors may be used to endorse or promote products derived 2290643Sbenno * from this software without specific prior written permission. 2390643Sbenno * 2490643Sbenno * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2590643Sbenno * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2690643Sbenno * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2790643Sbenno * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2890643Sbenno * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2990643Sbenno * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3090643Sbenno * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3190643Sbenno * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3290643Sbenno * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3390643Sbenno * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3490643Sbenno * POSSIBILITY OF SUCH DAMAGE. 3590643Sbenno */ 36139825Simp/*- 3777957Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3877957Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 3977957Sbenno * All rights reserved. 4077957Sbenno * 4177957Sbenno * Redistribution and use in source and binary forms, with or without 4277957Sbenno * modification, are permitted provided that the following conditions 4377957Sbenno * are met: 4477957Sbenno * 1. Redistributions of source code must retain the above copyright 4577957Sbenno * notice, this list of conditions and the following disclaimer. 4677957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 4777957Sbenno * notice, this list of conditions and the following disclaimer in the 4877957Sbenno * documentation and/or other materials provided with the distribution. 4977957Sbenno * 3. All advertising materials mentioning features or use of this software 5077957Sbenno * must display the following acknowledgement: 5177957Sbenno * This product includes software developed by TooLs GmbH. 5277957Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 5377957Sbenno * derived from this software without specific prior written permission. 5477957Sbenno * 5577957Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 5677957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 5777957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 5877957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 5977957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 6077957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 6177957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 6277957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 6377957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 6477957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 6577957Sbenno * 6678880Sbenno * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 6777957Sbenno */ 68139825Simp/*- 6977957Sbenno * Copyright (C) 2001 Benno Rice. 7077957Sbenno * All rights reserved. 7177957Sbenno * 7277957Sbenno * Redistribution and use in source and binary forms, with or without 7377957Sbenno * modification, are permitted provided that the following conditions 7477957Sbenno * are met: 7577957Sbenno * 1. Redistributions of source code must retain the above copyright 7677957Sbenno * notice, this list of conditions and the following disclaimer. 7777957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 7877957Sbenno * notice, this list of conditions and the following disclaimer in the 7977957Sbenno * documentation and/or other materials provided with the distribution. 8077957Sbenno * 8177957Sbenno * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 8277957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8377957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 8477957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 8577957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 8677957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 8777957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 8877957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 8977957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 9077957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9177957Sbenno */ 9277957Sbenno 93113038Sobrien#include <sys/cdefs.h> 94113038Sobrien__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 212627 2010-09-15 00:17:52Z grehan $"); 9577957Sbenno 9690643Sbenno/* 9790643Sbenno * Manages physical address maps. 9890643Sbenno * 9990643Sbenno * In addition to hardware address maps, this module is called upon to 10090643Sbenno * provide software-use-only maps which may or may not be stored in the 10190643Sbenno * same form as hardware maps. These pseudo-maps are used to store 10290643Sbenno * intermediate results from copy operations to and from address spaces. 10390643Sbenno * 10490643Sbenno * Since the information managed by this module is also stored by the 10590643Sbenno * logical address mapping module, this module may throw away valid virtual 10690643Sbenno * to physical mappings at almost any time. However, invalidations of 10790643Sbenno * mappings must be done as requested. 10890643Sbenno * 10990643Sbenno * In order to cope with hardware architectures which make virtual to 11090643Sbenno * physical map invalidates expensive, this module may delay invalidate 11190643Sbenno * reduced protection operations until such time as they are actually 11290643Sbenno * necessary. This module is given full information as to which processors 11390643Sbenno * are currently using which maps, and to when physical maps must be made 11490643Sbenno * correct. 11590643Sbenno */ 11690643Sbenno 117118239Speter#include "opt_kstack_pages.h" 118118239Speter 11977957Sbenno#include <sys/param.h> 12080431Speter#include <sys/kernel.h> 12190643Sbenno#include <sys/ktr.h> 12290643Sbenno#include <sys/lock.h> 12390643Sbenno#include <sys/msgbuf.h> 12490643Sbenno#include <sys/mutex.h> 12577957Sbenno#include <sys/proc.h> 12690643Sbenno#include <sys/sysctl.h> 12790643Sbenno#include <sys/systm.h> 12877957Sbenno#include <sys/vmmeter.h> 12977957Sbenno 13090643Sbenno#include <dev/ofw/openfirm.h> 13190643Sbenno 132152180Sgrehan#include <vm/vm.h> 13377957Sbenno#include <vm/vm_param.h> 13477957Sbenno#include <vm/vm_kern.h> 13577957Sbenno#include <vm/vm_page.h> 13677957Sbenno#include <vm/vm_map.h> 13777957Sbenno#include <vm/vm_object.h> 13877957Sbenno#include <vm/vm_extern.h> 13977957Sbenno#include <vm/vm_pageout.h> 14077957Sbenno#include <vm/vm_pager.h> 14192847Sjeff#include <vm/uma.h> 14277957Sbenno 143125687Sgrehan#include <machine/cpu.h> 144192067Snwhitehorn#include <machine/platform.h> 14583730Smp#include <machine/bat.h> 14690643Sbenno#include <machine/frame.h> 14790643Sbenno#include <machine/md_var.h> 14890643Sbenno#include <machine/psl.h> 14977957Sbenno#include <machine/pte.h> 150178628Smarcel#include <machine/smp.h> 15190643Sbenno#include <machine/sr.h> 152152180Sgrehan#include <machine/mmuvar.h> 15377957Sbenno 154152180Sgrehan#include "mmu_if.h" 15577957Sbenno 156152180Sgrehan#define MOEA_DEBUG 157152180Sgrehan 15890643Sbenno#define TODO panic("%s: not implemented", __func__); 15977957Sbenno 16090643Sbenno#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 16190643Sbenno#define VSID_TO_SR(vsid) ((vsid) & 0xf) 16290643Sbenno#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 16390643Sbenno 164142416Sgrehan#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 165142416Sgrehan#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 166142416Sgrehan#define PVO_WIRED 0x010 /* PVO entry is wired */ 167142416Sgrehan#define PVO_MANAGED 0x020 /* PVO entry is managed */ 168142416Sgrehan#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 169142416Sgrehan#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 17092521Sbenno bootstrap */ 171142416Sgrehan#define PVO_FAKE 0x100 /* fictitious phys page */ 17290643Sbenno#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 17390643Sbenno#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174142416Sgrehan#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 17590643Sbenno#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 17690643Sbenno#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 17790643Sbenno#define PVO_PTEGIDX_CLR(pvo) \ 17890643Sbenno ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 17990643Sbenno#define PVO_PTEGIDX_SET(pvo, i) \ 18090643Sbenno ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 18190643Sbenno 182152180Sgrehan#define MOEA_PVO_CHECK(pvo) 18390643Sbenno 18490643Sbennostruct ofw_map { 18590643Sbenno vm_offset_t om_va; 18690643Sbenno vm_size_t om_len; 18790643Sbenno vm_offset_t om_pa; 18890643Sbenno u_int om_mode; 18990643Sbenno}; 19077957Sbenno 19190643Sbenno/* 19290643Sbenno * Map of physical memory regions. 19390643Sbenno */ 19497346Sbennostatic struct mem_region *regions; 19597346Sbennostatic struct mem_region *pregions; 196209975Snwhitehornstatic u_int phys_avail_count; 197209975Snwhitehornstatic int regions_sz, pregions_sz; 198100319Sbennostatic struct ofw_map *translations; 19977957Sbenno 20090643Sbennoextern struct pmap ofw_pmap; 20177957Sbenno 20290643Sbenno/* 203134535Salc * Lock for the pteg and pvo tables. 204134535Salc */ 205152180Sgrehanstruct mtx moea_table_mutex; 206212278Snwhitehornstruct mtx moea_vsid_mutex; 207134535Salc 208183094Smarcel/* tlbie instruction synchronization */ 209183094Smarcelstatic struct mtx tlbie_mtx; 210183094Smarcel 211134535Salc/* 21290643Sbenno * PTEG data. 21390643Sbenno */ 214152180Sgrehanstatic struct pteg *moea_pteg_table; 215152180Sgrehanu_int moea_pteg_count; 216152180Sgrehanu_int moea_pteg_mask; 21777957Sbenno 21890643Sbenno/* 21990643Sbenno * PVO data. 22090643Sbenno */ 221152180Sgrehanstruct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 222152180Sgrehanstruct pvo_head moea_pvo_kunmanaged = 223152180Sgrehan LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 224152180Sgrehanstruct pvo_head moea_pvo_unmanaged = 225152180Sgrehan LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 22677957Sbenno 227152180Sgrehanuma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 228152180Sgrehanuma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 22977957Sbenno 23099037Sbenno#define BPVO_POOL_SIZE 32768 231152180Sgrehanstatic struct pvo_entry *moea_bpvo_pool; 232152180Sgrehanstatic int moea_bpvo_pool_index = 0; 23377957Sbenno 23490643Sbenno#define VSID_NBPW (sizeof(u_int32_t) * 8) 235152180Sgrehanstatic u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 23677957Sbenno 237152180Sgrehanstatic boolean_t moea_initialized = FALSE; 23877957Sbenno 23990643Sbenno/* 24090643Sbenno * Statistics. 24190643Sbenno */ 242152180Sgrehanu_int moea_pte_valid = 0; 243152180Sgrehanu_int moea_pte_overflow = 0; 244152180Sgrehanu_int moea_pte_replacements = 0; 245152180Sgrehanu_int moea_pvo_entries = 0; 246152180Sgrehanu_int moea_pvo_enter_calls = 0; 247152180Sgrehanu_int moea_pvo_remove_calls = 0; 248152180Sgrehanu_int moea_pte_spills = 0; 249152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 25090643Sbenno 0, ""); 251152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 252152180Sgrehan &moea_pte_overflow, 0, ""); 253152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 254152180Sgrehan &moea_pte_replacements, 0, ""); 255152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 25690643Sbenno 0, ""); 257152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 258152180Sgrehan &moea_pvo_enter_calls, 0, ""); 259152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 260152180Sgrehan &moea_pvo_remove_calls, 0, ""); 261152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 262152180Sgrehan &moea_pte_spills, 0, ""); 26377957Sbenno 26490643Sbenno/* 265152180Sgrehan * Allocate physical memory for use in moea_bootstrap. 26690643Sbenno */ 267152180Sgrehanstatic vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 26877957Sbenno 26990643Sbenno/* 27090643Sbenno * PTE calls. 27190643Sbenno */ 272152180Sgrehanstatic int moea_pte_insert(u_int, struct pte *); 27377957Sbenno 27477957Sbenno/* 27590643Sbenno * PVO calls. 27677957Sbenno */ 277152180Sgrehanstatic int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 27890643Sbenno vm_offset_t, vm_offset_t, u_int, int); 279152180Sgrehanstatic void moea_pvo_remove(struct pvo_entry *, int); 280152180Sgrehanstatic struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 281152180Sgrehanstatic struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 28290643Sbenno 28390643Sbenno/* 28490643Sbenno * Utility routines. 28590643Sbenno */ 286159303Salcstatic void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 287159303Salc vm_prot_t, boolean_t); 288152180Sgrehanstatic void moea_syncicache(vm_offset_t, vm_size_t); 289152180Sgrehanstatic boolean_t moea_query_bit(vm_page_t, int); 290208990Salcstatic u_int moea_clear_bit(vm_page_t, int); 291152180Sgrehanstatic void moea_kremove(mmu_t, vm_offset_t); 292152180Sgrehanint moea_pte_spill(vm_offset_t); 29390643Sbenno 294152180Sgrehan/* 295152180Sgrehan * Kernel MMU interface 296152180Sgrehan */ 297152180Sgrehanvoid moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 298152180Sgrehanvoid moea_clear_modify(mmu_t, vm_page_t); 299152180Sgrehanvoid moea_clear_reference(mmu_t, vm_page_t); 300152180Sgrehanvoid moea_copy_page(mmu_t, vm_page_t, vm_page_t); 301152180Sgrehanvoid moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 302159303Salcvoid moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 303159303Salc vm_prot_t); 304159627Supsvoid moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 305152180Sgrehanvm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 306152180Sgrehanvm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 307152180Sgrehanvoid moea_init(mmu_t); 308152180Sgrehanboolean_t moea_is_modified(mmu_t, vm_page_t); 309207155Salcboolean_t moea_is_referenced(mmu_t, vm_page_t); 310152180Sgrehanboolean_t moea_ts_referenced(mmu_t, vm_page_t); 311152180Sgrehanvm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 312152180Sgrehanboolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 313173708Salcint moea_page_wired_mappings(mmu_t, vm_page_t); 314152180Sgrehanvoid moea_pinit(mmu_t, pmap_t); 315152180Sgrehanvoid moea_pinit0(mmu_t, pmap_t); 316152180Sgrehanvoid moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 317152180Sgrehanvoid moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 318152180Sgrehanvoid moea_qremove(mmu_t, vm_offset_t, int); 319152180Sgrehanvoid moea_release(mmu_t, pmap_t); 320152180Sgrehanvoid moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 321152180Sgrehanvoid moea_remove_all(mmu_t, vm_page_t); 322160889Salcvoid moea_remove_write(mmu_t, vm_page_t); 323152180Sgrehanvoid moea_zero_page(mmu_t, vm_page_t); 324152180Sgrehanvoid moea_zero_page_area(mmu_t, vm_page_t, int, int); 325152180Sgrehanvoid moea_zero_page_idle(mmu_t, vm_page_t); 326152180Sgrehanvoid moea_activate(mmu_t, struct thread *); 327152180Sgrehanvoid moea_deactivate(mmu_t, struct thread *); 328190681Snwhitehornvoid moea_cpu_bootstrap(mmu_t, int); 329152180Sgrehanvoid moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 330152180Sgrehanvoid *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 331152180Sgrehanvoid moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 332152180Sgrehanvm_offset_t moea_kextract(mmu_t, vm_offset_t); 333152180Sgrehanvoid moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 334152180Sgrehanboolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 335198341Smarcelstatic void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 336152180Sgrehan 337152180Sgrehanstatic mmu_method_t moea_methods[] = { 338152180Sgrehan MMUMETHOD(mmu_change_wiring, moea_change_wiring), 339152180Sgrehan MMUMETHOD(mmu_clear_modify, moea_clear_modify), 340152180Sgrehan MMUMETHOD(mmu_clear_reference, moea_clear_reference), 341152180Sgrehan MMUMETHOD(mmu_copy_page, moea_copy_page), 342152180Sgrehan MMUMETHOD(mmu_enter, moea_enter), 343159303Salc MMUMETHOD(mmu_enter_object, moea_enter_object), 344152180Sgrehan MMUMETHOD(mmu_enter_quick, moea_enter_quick), 345152180Sgrehan MMUMETHOD(mmu_extract, moea_extract), 346152180Sgrehan MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 347152180Sgrehan MMUMETHOD(mmu_init, moea_init), 348152180Sgrehan MMUMETHOD(mmu_is_modified, moea_is_modified), 349207155Salc MMUMETHOD(mmu_is_referenced, moea_is_referenced), 350152180Sgrehan MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 351152180Sgrehan MMUMETHOD(mmu_map, moea_map), 352152180Sgrehan MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 353173708Salc MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 354152180Sgrehan MMUMETHOD(mmu_pinit, moea_pinit), 355152180Sgrehan MMUMETHOD(mmu_pinit0, moea_pinit0), 356152180Sgrehan MMUMETHOD(mmu_protect, moea_protect), 357152180Sgrehan MMUMETHOD(mmu_qenter, moea_qenter), 358152180Sgrehan MMUMETHOD(mmu_qremove, moea_qremove), 359152180Sgrehan MMUMETHOD(mmu_release, moea_release), 360152180Sgrehan MMUMETHOD(mmu_remove, moea_remove), 361152180Sgrehan MMUMETHOD(mmu_remove_all, moea_remove_all), 362160889Salc MMUMETHOD(mmu_remove_write, moea_remove_write), 363198341Smarcel MMUMETHOD(mmu_sync_icache, moea_sync_icache), 364152180Sgrehan MMUMETHOD(mmu_zero_page, moea_zero_page), 365152180Sgrehan MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 366152180Sgrehan MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 367152180Sgrehan MMUMETHOD(mmu_activate, moea_activate), 368152180Sgrehan MMUMETHOD(mmu_deactivate, moea_deactivate), 369152180Sgrehan 370152180Sgrehan /* Internal interfaces */ 371152180Sgrehan MMUMETHOD(mmu_bootstrap, moea_bootstrap), 372190681Snwhitehorn MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 373152180Sgrehan MMUMETHOD(mmu_mapdev, moea_mapdev), 374152180Sgrehan MMUMETHOD(mmu_unmapdev, moea_unmapdev), 375152180Sgrehan MMUMETHOD(mmu_kextract, moea_kextract), 376152180Sgrehan MMUMETHOD(mmu_kenter, moea_kenter), 377152180Sgrehan MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378152180Sgrehan 379152180Sgrehan { 0, 0 } 380152180Sgrehan}; 381152180Sgrehan 382212627SgrehanMMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 383152180Sgrehan 384212627Sgrehan 385183094Smarcelstatic void 386183094Smarceltlbie(vm_offset_t va) 387183094Smarcel{ 388152180Sgrehan 389183094Smarcel mtx_lock_spin(&tlbie_mtx); 390183094Smarcel __asm __volatile("tlbie %0" :: "r"(va)); 391183094Smarcel __asm __volatile("tlbsync"); 392183094Smarcel powerpc_sync(); 393183094Smarcel mtx_unlock_spin(&tlbie_mtx); 394183094Smarcel} 395183094Smarcel 396183094Smarcelstatic void 397183094Smarceltlbia(void) 398183094Smarcel{ 399183094Smarcel vm_offset_t va; 400183094Smarcel 401183094Smarcel for (va = 0; va < 0x00040000; va += 0x00001000) { 402183094Smarcel __asm __volatile("tlbie %0" :: "r"(va)); 403183094Smarcel powerpc_sync(); 404183094Smarcel } 405183094Smarcel __asm __volatile("tlbsync"); 406183094Smarcel powerpc_sync(); 407183094Smarcel} 408183094Smarcel 40990643Sbennostatic __inline int 41090643Sbennova_to_sr(u_int *sr, vm_offset_t va) 41177957Sbenno{ 41290643Sbenno return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 41390643Sbenno} 41477957Sbenno 41590643Sbennostatic __inline u_int 41690643Sbennova_to_pteg(u_int sr, vm_offset_t addr) 41790643Sbenno{ 41890643Sbenno u_int hash; 41990643Sbenno 42090643Sbenno hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 42190643Sbenno ADDR_PIDX_SHFT); 422152180Sgrehan return (hash & moea_pteg_mask); 42377957Sbenno} 42477957Sbenno 42590643Sbennostatic __inline struct pvo_head * 42696250Sbennopa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 42777957Sbenno{ 42890643Sbenno struct vm_page *pg; 42977957Sbenno 43090643Sbenno pg = PHYS_TO_VM_PAGE(pa); 43190643Sbenno 43296250Sbenno if (pg_p != NULL) 43396250Sbenno *pg_p = pg; 43496250Sbenno 43590643Sbenno if (pg == NULL) 436152180Sgrehan return (&moea_pvo_unmanaged); 43790643Sbenno 43890643Sbenno return (&pg->md.mdpg_pvoh); 43977957Sbenno} 44077957Sbenno 44190643Sbennostatic __inline struct pvo_head * 44290643Sbennovm_page_to_pvoh(vm_page_t m) 44390643Sbenno{ 44490643Sbenno 44590643Sbenno return (&m->md.mdpg_pvoh); 44690643Sbenno} 44790643Sbenno 44877957Sbennostatic __inline void 449152180Sgrehanmoea_attr_clear(vm_page_t m, int ptebit) 45077957Sbenno{ 45190643Sbenno 452159928Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 45390643Sbenno m->md.mdpg_attrs &= ~ptebit; 45477957Sbenno} 45577957Sbenno 45677957Sbennostatic __inline int 457152180Sgrehanmoea_attr_fetch(vm_page_t m) 45877957Sbenno{ 45977957Sbenno 46090643Sbenno return (m->md.mdpg_attrs); 46177957Sbenno} 46277957Sbenno 46390643Sbennostatic __inline void 464152180Sgrehanmoea_attr_save(vm_page_t m, int ptebit) 46590643Sbenno{ 46690643Sbenno 467159928Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 46890643Sbenno m->md.mdpg_attrs |= ptebit; 46990643Sbenno} 47090643Sbenno 47177957Sbennostatic __inline int 472152180Sgrehanmoea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 47377957Sbenno{ 47490643Sbenno if (pt->pte_hi == pvo_pt->pte_hi) 47590643Sbenno return (1); 47690643Sbenno 47790643Sbenno return (0); 47877957Sbenno} 47977957Sbenno 48077957Sbennostatic __inline int 481152180Sgrehanmoea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 48277957Sbenno{ 48390643Sbenno return (pt->pte_hi & ~PTE_VALID) == 48490643Sbenno (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 48590643Sbenno ((va >> ADDR_API_SHFT) & PTE_API) | which); 48690643Sbenno} 48777957Sbenno 48890643Sbennostatic __inline void 489152180Sgrehanmoea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 49090643Sbenno{ 491159928Salc 492159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 493159928Salc 49490643Sbenno /* 49590643Sbenno * Construct a PTE. Default to IMB initially. Valid bit only gets 49690643Sbenno * set when the real pte is set in memory. 49790643Sbenno * 49890643Sbenno * Note: Don't set the valid bit for correct operation of tlb update. 49990643Sbenno */ 50090643Sbenno pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 50190643Sbenno (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 50290643Sbenno pt->pte_lo = pte_lo; 50377957Sbenno} 50477957Sbenno 50590643Sbennostatic __inline void 506152180Sgrehanmoea_pte_synch(struct pte *pt, struct pte *pvo_pt) 50777957Sbenno{ 50877957Sbenno 509159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 51090643Sbenno pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 51177957Sbenno} 51277957Sbenno 51390643Sbennostatic __inline void 514152180Sgrehanmoea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 51577957Sbenno{ 51677957Sbenno 517159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 518159928Salc 51990643Sbenno /* 52090643Sbenno * As shown in Section 7.6.3.2.3 52190643Sbenno */ 52290643Sbenno pt->pte_lo &= ~ptebit; 523183094Smarcel tlbie(va); 52477957Sbenno} 52577957Sbenno 52690643Sbennostatic __inline void 527152180Sgrehanmoea_pte_set(struct pte *pt, struct pte *pvo_pt) 52877957Sbenno{ 52977957Sbenno 530159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 53190643Sbenno pvo_pt->pte_hi |= PTE_VALID; 53290643Sbenno 53377957Sbenno /* 53490643Sbenno * Update the PTE as defined in section 7.6.3.1. 53590643Sbenno * Note that the REF/CHG bits are from pvo_pt and thus should havce 53690643Sbenno * been saved so this routine can restore them (if desired). 53777957Sbenno */ 53890643Sbenno pt->pte_lo = pvo_pt->pte_lo; 539183094Smarcel powerpc_sync(); 54090643Sbenno pt->pte_hi = pvo_pt->pte_hi; 541183094Smarcel powerpc_sync(); 542152180Sgrehan moea_pte_valid++; 54390643Sbenno} 54477957Sbenno 54590643Sbennostatic __inline void 546152180Sgrehanmoea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 54790643Sbenno{ 54890643Sbenno 549159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 55090643Sbenno pvo_pt->pte_hi &= ~PTE_VALID; 55190643Sbenno 55277957Sbenno /* 55390643Sbenno * Force the reg & chg bits back into the PTEs. 55477957Sbenno */ 555183094Smarcel powerpc_sync(); 55677957Sbenno 55790643Sbenno /* 55890643Sbenno * Invalidate the pte. 55990643Sbenno */ 56090643Sbenno pt->pte_hi &= ~PTE_VALID; 56177957Sbenno 562183094Smarcel tlbie(va); 56377957Sbenno 56490643Sbenno /* 56590643Sbenno * Save the reg & chg bits. 56690643Sbenno */ 567152180Sgrehan moea_pte_synch(pt, pvo_pt); 568152180Sgrehan moea_pte_valid--; 56977957Sbenno} 57077957Sbenno 57190643Sbennostatic __inline void 572152180Sgrehanmoea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 57390643Sbenno{ 57490643Sbenno 57590643Sbenno /* 57690643Sbenno * Invalidate the PTE 57790643Sbenno */ 578152180Sgrehan moea_pte_unset(pt, pvo_pt, va); 579152180Sgrehan moea_pte_set(pt, pvo_pt); 58090643Sbenno} 58190643Sbenno 58277957Sbenno/* 58390643Sbenno * Quick sort callout for comparing memory regions. 58477957Sbenno */ 58590643Sbennostatic int mr_cmp(const void *a, const void *b); 58690643Sbennostatic int om_cmp(const void *a, const void *b); 58790643Sbenno 58890643Sbennostatic int 58990643Sbennomr_cmp(const void *a, const void *b) 59077957Sbenno{ 59190643Sbenno const struct mem_region *regiona; 59290643Sbenno const struct mem_region *regionb; 59377957Sbenno 59490643Sbenno regiona = a; 59590643Sbenno regionb = b; 59690643Sbenno if (regiona->mr_start < regionb->mr_start) 59790643Sbenno return (-1); 59890643Sbenno else if (regiona->mr_start > regionb->mr_start) 59990643Sbenno return (1); 60090643Sbenno else 60190643Sbenno return (0); 60290643Sbenno} 60377957Sbenno 60490643Sbennostatic int 60590643Sbennoom_cmp(const void *a, const void *b) 60690643Sbenno{ 60790643Sbenno const struct ofw_map *mapa; 60890643Sbenno const struct ofw_map *mapb; 60990643Sbenno 61090643Sbenno mapa = a; 61190643Sbenno mapb = b; 61290643Sbenno if (mapa->om_pa < mapb->om_pa) 61390643Sbenno return (-1); 61490643Sbenno else if (mapa->om_pa > mapb->om_pa) 61590643Sbenno return (1); 61690643Sbenno else 61790643Sbenno return (0); 61877957Sbenno} 61977957Sbenno 62077957Sbennovoid 621190681Snwhitehornmoea_cpu_bootstrap(mmu_t mmup, int ap) 622178628Smarcel{ 623178628Smarcel u_int sdr; 624178628Smarcel int i; 625178628Smarcel 626178628Smarcel if (ap) { 627183094Smarcel powerpc_sync(); 628178628Smarcel __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 629178628Smarcel __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 630178628Smarcel isync(); 631178628Smarcel __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 632178628Smarcel __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 633178628Smarcel isync(); 634178628Smarcel } 635178628Smarcel 636178629Smarcel __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 637178629Smarcel __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 638178629Smarcel isync(); 639178628Smarcel 640178629Smarcel __asm __volatile("mtibatu 1,%0" :: "r"(0)); 641178629Smarcel __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 642178629Smarcel __asm __volatile("mtibatu 2,%0" :: "r"(0)); 643178629Smarcel __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 644178629Smarcel __asm __volatile("mtibatu 3,%0" :: "r"(0)); 645178628Smarcel isync(); 646178628Smarcel 647178628Smarcel for (i = 0; i < 16; i++) 648178628Smarcel mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 649178628Smarcel 650178628Smarcel __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 651178628Smarcel __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 652183094Smarcel powerpc_sync(); 653178628Smarcel 654178628Smarcel sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 655178628Smarcel __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 656178628Smarcel isync(); 657178628Smarcel 658179254Smarcel tlbia(); 659178628Smarcel} 660178628Smarcel 661178628Smarcelvoid 662152180Sgrehanmoea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 66377957Sbenno{ 66497346Sbenno ihandle_t mmui; 66590643Sbenno phandle_t chosen, mmu; 66690643Sbenno int sz; 66790643Sbenno int i, j; 668103604Sgrehan int ofw_mappings; 669143200Sgrehan vm_size_t size, physsz, hwphyssz; 67090643Sbenno vm_offset_t pa, va, off; 671194784Sjeff void *dpcpu; 672209369Snwhitehorn register_t msr; 67377957Sbenno 67499037Sbenno /* 675103604Sgrehan * Set up BAT0 to map the lowest 256 MB area 67699037Sbenno */ 67799037Sbenno battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 67899037Sbenno battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 67999037Sbenno 68099037Sbenno /* 68199037Sbenno * Map PCI memory space. 68299037Sbenno */ 68399037Sbenno battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 68499037Sbenno battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 68599037Sbenno 68699037Sbenno battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 68799037Sbenno battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 68899037Sbenno 68999037Sbenno battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 69099037Sbenno battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 69199037Sbenno 69299037Sbenno battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 69399037Sbenno battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 69499037Sbenno 69599037Sbenno /* 69699037Sbenno * Map obio devices. 69799037Sbenno */ 69899037Sbenno battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 69999037Sbenno battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 70099037Sbenno 70177957Sbenno /* 70290643Sbenno * Use an IBAT and a DBAT to map the bottom segment of memory 703209369Snwhitehorn * where we are. Turn off instruction relocation temporarily 704209369Snwhitehorn * to prevent faults while reprogramming the IBAT. 70577957Sbenno */ 706209369Snwhitehorn msr = mfmsr(); 707209369Snwhitehorn mtmsr(msr & ~PSL_IR); 708152180Sgrehan __asm (".balign 32; \n" 709149958Sgrehan "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 710131808Sgrehan "mtdbatu 0,%0; mtdbatl 0,%1; isync" 711178628Smarcel :: "r"(battable[0].batu), "r"(battable[0].batl)); 712209369Snwhitehorn mtmsr(msr); 71399037Sbenno 71499037Sbenno /* map pci space */ 715178628Smarcel __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 716178628Smarcel __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 717178628Smarcel isync(); 71877957Sbenno 719190681Snwhitehorn /* set global direct map flag */ 720190681Snwhitehorn hw_direct_map = 1; 721190681Snwhitehorn 72297346Sbenno mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 723152180Sgrehan CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 72497346Sbenno 72597346Sbenno qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 72697346Sbenno for (i = 0; i < pregions_sz; i++) { 727103604Sgrehan vm_offset_t pa; 728103604Sgrehan vm_offset_t end; 729103604Sgrehan 73097346Sbenno CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 73197346Sbenno pregions[i].mr_start, 73297346Sbenno pregions[i].mr_start + pregions[i].mr_size, 73397346Sbenno pregions[i].mr_size); 734103604Sgrehan /* 735103604Sgrehan * Install entries into the BAT table to allow all 736103604Sgrehan * of physmem to be convered by on-demand BAT entries. 737103604Sgrehan * The loop will sometimes set the same battable element 738103604Sgrehan * twice, but that's fine since they won't be used for 739103604Sgrehan * a while yet. 740103604Sgrehan */ 741103604Sgrehan pa = pregions[i].mr_start & 0xf0000000; 742103604Sgrehan end = pregions[i].mr_start + pregions[i].mr_size; 743103604Sgrehan do { 744103604Sgrehan u_int n = pa >> ADDR_SR_SHFT; 745152180Sgrehan 746103604Sgrehan battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 747103604Sgrehan battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 748103604Sgrehan pa += SEGMENT_LENGTH; 749103604Sgrehan } while (pa < end); 75097346Sbenno } 75197346Sbenno 75297346Sbenno if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 753152180Sgrehan panic("moea_bootstrap: phys_avail too small"); 75497346Sbenno qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 75590643Sbenno phys_avail_count = 0; 75691793Sbenno physsz = 0; 757143234Sgrehan hwphyssz = 0; 758143234Sgrehan TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 75997346Sbenno for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 76090643Sbenno CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 76190643Sbenno regions[i].mr_start + regions[i].mr_size, 76290643Sbenno regions[i].mr_size); 763143200Sgrehan if (hwphyssz != 0 && 764143200Sgrehan (physsz + regions[i].mr_size) >= hwphyssz) { 765143200Sgrehan if (physsz < hwphyssz) { 766143200Sgrehan phys_avail[j] = regions[i].mr_start; 767143200Sgrehan phys_avail[j + 1] = regions[i].mr_start + 768143200Sgrehan hwphyssz - physsz; 769143200Sgrehan physsz = hwphyssz; 770143200Sgrehan phys_avail_count++; 771143200Sgrehan } 772143200Sgrehan break; 773143200Sgrehan } 77490643Sbenno phys_avail[j] = regions[i].mr_start; 77590643Sbenno phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 77690643Sbenno phys_avail_count++; 77791793Sbenno physsz += regions[i].mr_size; 77877957Sbenno } 77991793Sbenno physmem = btoc(physsz); 78077957Sbenno 78177957Sbenno /* 78290643Sbenno * Allocate PTEG table. 78377957Sbenno */ 78490643Sbenno#ifdef PTEGCOUNT 785152180Sgrehan moea_pteg_count = PTEGCOUNT; 78690643Sbenno#else 787152180Sgrehan moea_pteg_count = 0x1000; 78877957Sbenno 789152180Sgrehan while (moea_pteg_count < physmem) 790152180Sgrehan moea_pteg_count <<= 1; 79177957Sbenno 792152180Sgrehan moea_pteg_count >>= 1; 79390643Sbenno#endif /* PTEGCOUNT */ 79477957Sbenno 795152180Sgrehan size = moea_pteg_count * sizeof(struct pteg); 796152180Sgrehan CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 79790643Sbenno size); 798152180Sgrehan moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 799152180Sgrehan CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 800152180Sgrehan bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 801152180Sgrehan moea_pteg_mask = moea_pteg_count - 1; 80277957Sbenno 80390643Sbenno /* 80494839Sbenno * Allocate pv/overflow lists. 80590643Sbenno */ 806152180Sgrehan size = sizeof(struct pvo_head) * moea_pteg_count; 807152180Sgrehan moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 80890643Sbenno PAGE_SIZE); 809152180Sgrehan CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 810152180Sgrehan for (i = 0; i < moea_pteg_count; i++) 811152180Sgrehan LIST_INIT(&moea_pvo_table[i]); 81277957Sbenno 81390643Sbenno /* 814134535Salc * Initialize the lock that synchronizes access to the pteg and pvo 815134535Salc * tables. 816134535Salc */ 817159928Salc mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 818159928Salc MTX_RECURSE); 819212278Snwhitehorn mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 820134535Salc 821183094Smarcel mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 822183094Smarcel 823134535Salc /* 82490643Sbenno * Initialise the unmanaged pvo pool. 82590643Sbenno */ 826152180Sgrehan moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 82799037Sbenno BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 828152180Sgrehan moea_bpvo_pool_index = 0; 82977957Sbenno 83077957Sbenno /* 83190643Sbenno * Make sure kernel vsid is allocated as well as VSID 0. 83277957Sbenno */ 833152180Sgrehan moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 83490643Sbenno |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 835152180Sgrehan moea_vsid_bitmap[0] |= 1; 83677957Sbenno 83790643Sbenno /* 838133862Smarius * Set up the Open Firmware pmap and add it's mappings. 83990643Sbenno */ 840152180Sgrehan moea_pinit(mmup, &ofw_pmap); 84190643Sbenno ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 842126478Sgrehan ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 84390643Sbenno if ((chosen = OF_finddevice("/chosen")) == -1) 844152180Sgrehan panic("moea_bootstrap: can't find /chosen"); 84590643Sbenno OF_getprop(chosen, "mmu", &mmui, 4); 84690643Sbenno if ((mmu = OF_instance_to_package(mmui)) == -1) 847152180Sgrehan panic("moea_bootstrap: can't get mmu package"); 84890643Sbenno if ((sz = OF_getproplen(mmu, "translations")) == -1) 849152180Sgrehan panic("moea_bootstrap: can't get ofw translation count"); 850100319Sbenno translations = NULL; 851131401Sgrehan for (i = 0; phys_avail[i] != 0; i += 2) { 852131401Sgrehan if (phys_avail[i + 1] >= sz) { 853100319Sbenno translations = (struct ofw_map *)phys_avail[i]; 854131401Sgrehan break; 855131401Sgrehan } 856100319Sbenno } 857100319Sbenno if (translations == NULL) 858152180Sgrehan panic("moea_bootstrap: no space to copy translations"); 85990643Sbenno bzero(translations, sz); 86090643Sbenno if (OF_getprop(mmu, "translations", translations, sz) == -1) 861152180Sgrehan panic("moea_bootstrap: can't get ofw translations"); 862152180Sgrehan CTR0(KTR_PMAP, "moea_bootstrap: translations"); 86397346Sbenno sz /= sizeof(*translations); 86490643Sbenno qsort(translations, sz, sizeof (*translations), om_cmp); 865103604Sgrehan for (i = 0, ofw_mappings = 0; i < sz; i++) { 86690643Sbenno CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 86790643Sbenno translations[i].om_pa, translations[i].om_va, 86890643Sbenno translations[i].om_len); 86977957Sbenno 870103604Sgrehan /* 871103604Sgrehan * If the mapping is 1:1, let the RAM and device on-demand 872103604Sgrehan * BAT tables take care of the translation. 873103604Sgrehan */ 874103604Sgrehan if (translations[i].om_va == translations[i].om_pa) 875103604Sgrehan continue; 87677957Sbenno 877103604Sgrehan /* Enter the pages */ 87890643Sbenno for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 87990643Sbenno struct vm_page m; 88077957Sbenno 88190643Sbenno m.phys_addr = translations[i].om_pa + off; 882208175Salc m.oflags = VPO_BUSY; 883159705Srink PMAP_LOCK(&ofw_pmap); 884159303Salc moea_enter_locked(&ofw_pmap, 885152180Sgrehan translations[i].om_va + off, &m, 886103604Sgrehan VM_PROT_ALL, 1); 887159705Srink PMAP_UNLOCK(&ofw_pmap); 888103604Sgrehan ofw_mappings++; 88977957Sbenno } 89077957Sbenno } 89177957Sbenno 89290643Sbenno /* 893178261Smarcel * Calculate the last available physical address. 894178261Smarcel */ 895178261Smarcel for (i = 0; phys_avail[i + 2] != 0; i += 2) 896178261Smarcel ; 897178261Smarcel Maxmem = powerpc_btop(phys_avail[i + 1]); 898178261Smarcel 899178261Smarcel /* 90090643Sbenno * Initialize the kernel pmap (which is statically allocated). 90190643Sbenno */ 902134329Salc PMAP_LOCK_INIT(kernel_pmap); 90390643Sbenno for (i = 0; i < 16; i++) { 90490643Sbenno kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 90577957Sbenno } 90690643Sbenno kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 907139401Sgrehan kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 90890643Sbenno kernel_pmap->pm_active = ~0; 90977957Sbenno 910190681Snwhitehorn moea_cpu_bootstrap(mmup,0); 91177957Sbenno 91290643Sbenno pmap_bootstrapped++; 913178261Smarcel 914178261Smarcel /* 915178261Smarcel * Set the start and end of kva. 916178261Smarcel */ 917178261Smarcel virtual_avail = VM_MIN_KERNEL_ADDRESS; 918204128Snwhitehorn virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 919178261Smarcel 920178261Smarcel /* 921178261Smarcel * Allocate a kernel stack with a guard page for thread0 and map it 922178261Smarcel * into the kernel page map. 923178261Smarcel */ 924178261Smarcel pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 925178261Smarcel va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 926178261Smarcel virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 927178261Smarcel CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 928178261Smarcel thread0.td_kstack = va; 929178261Smarcel thread0.td_kstack_pages = KSTACK_PAGES; 930178261Smarcel for (i = 0; i < KSTACK_PAGES; i++) { 931201758Smbr moea_kenter(mmup, va, pa); 932178261Smarcel pa += PAGE_SIZE; 933178261Smarcel va += PAGE_SIZE; 934178261Smarcel } 935178261Smarcel 936178261Smarcel /* 937178261Smarcel * Allocate virtual address space for the message buffer. 938178261Smarcel */ 939178261Smarcel pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 940178261Smarcel msgbufp = (struct msgbuf *)virtual_avail; 941178261Smarcel va = virtual_avail; 942178261Smarcel virtual_avail += round_page(MSGBUF_SIZE); 943178261Smarcel while (va < virtual_avail) { 944201758Smbr moea_kenter(mmup, va, pa); 945178261Smarcel pa += PAGE_SIZE; 946178261Smarcel va += PAGE_SIZE; 947178261Smarcel } 948194784Sjeff 949194784Sjeff /* 950194784Sjeff * Allocate virtual address space for the dynamic percpu area. 951194784Sjeff */ 952194784Sjeff pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 953194784Sjeff dpcpu = (void *)virtual_avail; 954194784Sjeff va = virtual_avail; 955194784Sjeff virtual_avail += DPCPU_SIZE; 956194784Sjeff while (va < virtual_avail) { 957201758Smbr moea_kenter(mmup, va, pa); 958194784Sjeff pa += PAGE_SIZE; 959194784Sjeff va += PAGE_SIZE; 960194784Sjeff } 961194784Sjeff dpcpu_init(dpcpu, 0); 96277957Sbenno} 96377957Sbenno 96477957Sbenno/* 96590643Sbenno * Activate a user pmap. The pmap must be activated before it's address 96690643Sbenno * space can be accessed in any way. 96777957Sbenno */ 96877957Sbennovoid 969152180Sgrehanmoea_activate(mmu_t mmu, struct thread *td) 97077957Sbenno{ 97196250Sbenno pmap_t pm, pmr; 97277957Sbenno 97377957Sbenno /* 974103604Sgrehan * Load all the data we need up front to encourage the compiler to 97590643Sbenno * not issue any loads while we have interrupts disabled below. 97677957Sbenno */ 97790643Sbenno pm = &td->td_proc->p_vmspace->vm_pmap; 978183290Snwhitehorn pmr = pm->pmap_phys; 97977957Sbenno 98090643Sbenno pm->pm_active |= PCPU_GET(cpumask); 98196250Sbenno PCPU_SET(curpmap, pmr); 98277957Sbenno} 98377957Sbenno 98491483Sbennovoid 985152180Sgrehanmoea_deactivate(mmu_t mmu, struct thread *td) 98691483Sbenno{ 98791483Sbenno pmap_t pm; 98891483Sbenno 98991483Sbenno pm = &td->td_proc->p_vmspace->vm_pmap; 990183094Smarcel pm->pm_active &= ~PCPU_GET(cpumask); 99196250Sbenno PCPU_SET(curpmap, NULL); 99291483Sbenno} 99391483Sbenno 99477957Sbennovoid 995152180Sgrehanmoea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 99677957Sbenno{ 99796353Sbenno struct pvo_entry *pvo; 99896353Sbenno 999134329Salc PMAP_LOCK(pm); 1000152180Sgrehan pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 100196353Sbenno 100296353Sbenno if (pvo != NULL) { 100396353Sbenno if (wired) { 100496353Sbenno if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 100596353Sbenno pm->pm_stats.wired_count++; 100696353Sbenno pvo->pvo_vaddr |= PVO_WIRED; 100796353Sbenno } else { 100896353Sbenno if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 100996353Sbenno pm->pm_stats.wired_count--; 101096353Sbenno pvo->pvo_vaddr &= ~PVO_WIRED; 101196353Sbenno } 101296353Sbenno } 1013134329Salc PMAP_UNLOCK(pm); 101477957Sbenno} 101577957Sbenno 101677957Sbennovoid 1017152180Sgrehanmoea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 101877957Sbenno{ 101997385Sbenno vm_offset_t dst; 102097385Sbenno vm_offset_t src; 102197385Sbenno 102297385Sbenno dst = VM_PAGE_TO_PHYS(mdst); 102397385Sbenno src = VM_PAGE_TO_PHYS(msrc); 102497385Sbenno 102597385Sbenno kcopy((void *)src, (void *)dst, PAGE_SIZE); 102677957Sbenno} 102777957Sbenno 102877957Sbenno/* 102990643Sbenno * Zero a page of physical memory by temporarily mapping it into the tlb. 103077957Sbenno */ 103177957Sbennovoid 1032152180Sgrehanmoea_zero_page(mmu_t mmu, vm_page_t m) 103377957Sbenno{ 103494777Speter vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1035178265Smarcel void *va = (void *)pa; 103677957Sbenno 103790643Sbenno bzero(va, PAGE_SIZE); 103877957Sbenno} 103977957Sbenno 104077957Sbennovoid 1041152180Sgrehanmoea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 104277957Sbenno{ 104399666Sbenno vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1044178265Smarcel void *va = (void *)(pa + off); 104599666Sbenno 1046178265Smarcel bzero(va, size); 104777957Sbenno} 104877957Sbenno 104999571Spetervoid 1050152180Sgrehanmoea_zero_page_idle(mmu_t mmu, vm_page_t m) 105199571Speter{ 1052178265Smarcel vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1053178265Smarcel void *va = (void *)pa; 105499571Speter 1055178265Smarcel bzero(va, PAGE_SIZE); 105699571Speter} 105799571Speter 105877957Sbenno/* 105990643Sbenno * Map the given physical page at the specified virtual address in the 106090643Sbenno * target pmap with the protection requested. If specified the page 106190643Sbenno * will be wired down. 106277957Sbenno */ 106377957Sbennovoid 1064152180Sgrehanmoea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 106590643Sbenno boolean_t wired) 106677957Sbenno{ 1067159303Salc 1068159303Salc vm_page_lock_queues(); 1069159303Salc PMAP_LOCK(pmap); 1070159324Salc moea_enter_locked(pmap, va, m, prot, wired); 1071159303Salc vm_page_unlock_queues(); 1072159303Salc PMAP_UNLOCK(pmap); 1073159303Salc} 1074159303Salc 1075159303Salc/* 1076159303Salc * Map the given physical page at the specified virtual address in the 1077159303Salc * target pmap with the protection requested. If specified the page 1078159303Salc * will be wired down. 1079159303Salc * 1080159303Salc * The page queues and pmap must be locked. 1081159303Salc */ 1082159303Salcstatic void 1083159303Salcmoea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1084159303Salc boolean_t wired) 1085159303Salc{ 108690643Sbenno struct pvo_head *pvo_head; 108792847Sjeff uma_zone_t zone; 108896250Sbenno vm_page_t pg; 108996250Sbenno u_int pte_lo, pvo_flags, was_exec, i; 109090643Sbenno int error; 109177957Sbenno 1092152180Sgrehan if (!moea_initialized) { 1093152180Sgrehan pvo_head = &moea_pvo_kunmanaged; 1094152180Sgrehan zone = moea_upvo_zone; 109590643Sbenno pvo_flags = 0; 109696250Sbenno pg = NULL; 109796250Sbenno was_exec = PTE_EXEC; 109890643Sbenno } else { 1099110172Sgrehan pvo_head = vm_page_to_pvoh(m); 1100110172Sgrehan pg = m; 1101152180Sgrehan zone = moea_mpvo_zone; 110290643Sbenno pvo_flags = PVO_MANAGED; 110396250Sbenno was_exec = 0; 110490643Sbenno } 1105134535Salc if (pmap_bootstrapped) 1106159303Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1107159303Salc PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1108209048Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1109209048Salc (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1110208175Salc ("moea_enter_locked: page %p is not busy", m)); 111177957Sbenno 1112142416Sgrehan /* XXX change the pvo head for fake pages */ 1113189675Snwhitehorn if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1114189675Snwhitehorn pvo_flags &= ~PVO_MANAGED; 1115152180Sgrehan pvo_head = &moea_pvo_kunmanaged; 1116189675Snwhitehorn zone = moea_upvo_zone; 1117189675Snwhitehorn } 1118142416Sgrehan 111996250Sbenno /* 112096250Sbenno * If this is a managed page, and it's the first reference to the page, 112196250Sbenno * clear the execness of the page. Otherwise fetch the execness. 112296250Sbenno */ 1123142416Sgrehan if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 112496250Sbenno if (LIST_EMPTY(pvo_head)) { 1125152180Sgrehan moea_attr_clear(pg, PTE_EXEC); 112696250Sbenno } else { 1127152180Sgrehan was_exec = moea_attr_fetch(pg) & PTE_EXEC; 112896250Sbenno } 112996250Sbenno } 113096250Sbenno 113196250Sbenno /* 113296250Sbenno * Assume the page is cache inhibited and access is guarded unless 113396250Sbenno * it's in our available memory array. 113496250Sbenno */ 113590643Sbenno pte_lo = PTE_I | PTE_G; 113697346Sbenno for (i = 0; i < pregions_sz; i++) { 113797346Sbenno if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 113897346Sbenno (VM_PAGE_TO_PHYS(m) < 113997346Sbenno (pregions[i].mr_start + pregions[i].mr_size))) { 1140183094Smarcel pte_lo = PTE_M; 114196250Sbenno break; 114296250Sbenno } 114396250Sbenno } 114477957Sbenno 1145164229Salc if (prot & VM_PROT_WRITE) { 114690643Sbenno pte_lo |= PTE_BW; 1147208810Salc if (pmap_bootstrapped && 1148208810Salc (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1149164765Sgrehan vm_page_flag_set(m, PG_WRITEABLE); 1150164229Salc } else 115190643Sbenno pte_lo |= PTE_BR; 115277957Sbenno 1153142416Sgrehan if (prot & VM_PROT_EXECUTE) 1154142416Sgrehan pvo_flags |= PVO_EXECUTABLE; 115577957Sbenno 115690643Sbenno if (wired) 115790643Sbenno pvo_flags |= PVO_WIRED; 115877957Sbenno 1159142416Sgrehan if ((m->flags & PG_FICTITIOUS) != 0) 1160142416Sgrehan pvo_flags |= PVO_FAKE; 1161142416Sgrehan 1162152180Sgrehan error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 116396250Sbenno pte_lo, pvo_flags); 116490643Sbenno 116596250Sbenno /* 116696250Sbenno * Flush the real page from the instruction cache if this page is 116796250Sbenno * mapped executable and cacheable and was not previously mapped (or 116896250Sbenno * was not mapped executable). 116996250Sbenno */ 117096250Sbenno if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 117196250Sbenno (pte_lo & PTE_I) == 0 && was_exec == 0) { 117277957Sbenno /* 117390643Sbenno * Flush the real memory from the cache. 117477957Sbenno */ 1175152180Sgrehan moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 117696250Sbenno if (pg != NULL) 1177152180Sgrehan moea_attr_save(pg, PTE_EXEC); 117877957Sbenno } 1179103604Sgrehan 1180103604Sgrehan /* XXX syncicache always until problems are sorted */ 1181152180Sgrehan moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 118277957Sbenno} 118377957Sbenno 1184159303Salc/* 1185159303Salc * Maps a sequence of resident pages belonging to the same object. 1186159303Salc * The sequence begins with the given page m_start. This page is 1187159303Salc * mapped at the given virtual address start. Each subsequent page is 1188159303Salc * mapped at a virtual address that is offset from start by the same 1189159303Salc * amount as the page is offset from m_start within the object. The 1190159303Salc * last page in the sequence is the page with the largest offset from 1191159303Salc * m_start that can be mapped at a virtual address less than the given 1192159303Salc * virtual address end. Not every virtual page between start and end 1193159303Salc * is mapped; only those for which a resident page exists with the 1194159303Salc * corresponding offset from m_start are mapped. 1195159303Salc */ 1196159303Salcvoid 1197159303Salcmoea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1198159303Salc vm_page_t m_start, vm_prot_t prot) 1199159303Salc{ 1200159303Salc vm_page_t m; 1201159303Salc vm_pindex_t diff, psize; 1202159303Salc 1203159303Salc psize = atop(end - start); 1204159303Salc m = m_start; 1205208574Salc vm_page_lock_queues(); 1206159303Salc PMAP_LOCK(pm); 1207159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1208159303Salc moea_enter_locked(pm, start + ptoa(diff), m, prot & 1209159303Salc (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1210159303Salc m = TAILQ_NEXT(m, listq); 1211159303Salc } 1212208574Salc vm_page_unlock_queues(); 1213159303Salc PMAP_UNLOCK(pm); 1214159303Salc} 1215159303Salc 1216159627Supsvoid 1217152180Sgrehanmoea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1218159627Sups vm_prot_t prot) 1219117045Salc{ 1220117045Salc 1221207796Salc vm_page_lock_queues(); 1222159303Salc PMAP_LOCK(pm); 1223159303Salc moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1224152180Sgrehan FALSE); 1225207796Salc vm_page_unlock_queues(); 1226159303Salc PMAP_UNLOCK(pm); 1227117045Salc} 1228117045Salc 1229131658Salcvm_paddr_t 1230152180Sgrehanmoea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 123177957Sbenno{ 123296353Sbenno struct pvo_entry *pvo; 1233134329Salc vm_paddr_t pa; 123496353Sbenno 1235134329Salc PMAP_LOCK(pm); 1236152180Sgrehan pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1237134329Salc if (pvo == NULL) 1238134329Salc pa = 0; 1239134329Salc else 1240183290Snwhitehorn pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1241134329Salc PMAP_UNLOCK(pm); 1242134329Salc return (pa); 124377957Sbenno} 124477957Sbenno 124577957Sbenno/* 1246120336Sgrehan * Atomically extract and hold the physical page with the given 1247120336Sgrehan * pmap and virtual address pair if that mapping permits the given 1248120336Sgrehan * protection. 1249120336Sgrehan */ 1250120336Sgrehanvm_page_t 1251152180Sgrehanmoea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1252120336Sgrehan{ 1253132666Salc struct pvo_entry *pvo; 1254120336Sgrehan vm_page_t m; 1255207410Skmacy vm_paddr_t pa; 1256207410Skmacy 1257120336Sgrehan m = NULL; 1258207410Skmacy pa = 0; 1259134329Salc PMAP_LOCK(pmap); 1260207410Skmacyretry: 1261152180Sgrehan pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1262183290Snwhitehorn if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1263183290Snwhitehorn ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1264132666Salc (prot & VM_PROT_WRITE) == 0)) { 1265207410Skmacy if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1266207410Skmacy goto retry; 1267183290Snwhitehorn m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1268120336Sgrehan vm_page_hold(m); 1269120336Sgrehan } 1270207410Skmacy PA_UNLOCK_COND(pa); 1271134329Salc PMAP_UNLOCK(pmap); 1272120336Sgrehan return (m); 1273120336Sgrehan} 1274120336Sgrehan 127590643Sbennovoid 1276152180Sgrehanmoea_init(mmu_t mmu) 127777957Sbenno{ 127877957Sbenno 1279152180Sgrehan moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1280125442Sgrehan NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1281125442Sgrehan UMA_ZONE_VM | UMA_ZONE_NOFREE); 1282152180Sgrehan moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1283125442Sgrehan NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1284125442Sgrehan UMA_ZONE_VM | UMA_ZONE_NOFREE); 1285152180Sgrehan moea_initialized = TRUE; 128677957Sbenno} 128777957Sbenno 128890643Sbennoboolean_t 1289207155Salcmoea_is_referenced(mmu_t mmu, vm_page_t m) 1290207155Salc{ 1291207155Salc 1292208574Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1293208574Salc ("moea_is_referenced: page %p is not managed", m)); 1294207155Salc return (moea_query_bit(m, PTE_REF)); 1295207155Salc} 1296207155Salc 1297207155Salcboolean_t 1298152180Sgrehanmoea_is_modified(mmu_t mmu, vm_page_t m) 129990643Sbenno{ 130096353Sbenno 1301208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1302208504Salc ("moea_is_modified: page %p is not managed", m)); 1303208504Salc 1304208504Salc /* 1305208504Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1306208504Salc * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1307208504Salc * is clear, no PTEs can have PTE_CHG set. 1308208504Salc */ 1309208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1310208504Salc if ((m->oflags & VPO_BUSY) == 0 && 1311208504Salc (m->flags & PG_WRITEABLE) == 0) 131296353Sbenno return (FALSE); 1313208574Salc return (moea_query_bit(m, PTE_CHG)); 131490643Sbenno} 131590643Sbenno 131690643Sbennovoid 1317152180Sgrehanmoea_clear_reference(mmu_t mmu, vm_page_t m) 131890643Sbenno{ 1319110172Sgrehan 1320208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1321208504Salc ("moea_clear_reference: page %p is not managed", m)); 1322208990Salc moea_clear_bit(m, PTE_REF); 132390643Sbenno} 132490643Sbenno 1325110172Sgrehanvoid 1326152180Sgrehanmoea_clear_modify(mmu_t mmu, vm_page_t m) 1327110172Sgrehan{ 1328110172Sgrehan 1329208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1330208504Salc ("moea_clear_modify: page %p is not managed", m)); 1331208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1332208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 1333208504Salc ("moea_clear_modify: page %p is busy", m)); 1334208504Salc 1335208504Salc /* 1336208504Salc * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1337208504Salc * set. If the object containing the page is locked and the page is 1338208504Salc * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1339208504Salc */ 1340208504Salc if ((m->flags & PG_WRITEABLE) == 0) 1341110172Sgrehan return; 1342208990Salc moea_clear_bit(m, PTE_CHG); 1343110172Sgrehan} 1344110172Sgrehan 134591403Ssilby/* 1346160889Salc * Clear the write and modified bits in each of the given page's mappings. 1347160889Salc */ 1348160889Salcvoid 1349160889Salcmoea_remove_write(mmu_t mmu, vm_page_t m) 1350160889Salc{ 1351160889Salc struct pvo_entry *pvo; 1352160889Salc struct pte *pt; 1353160889Salc pmap_t pmap; 1354160889Salc u_int lo; 1355160889Salc 1356208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1357208175Salc ("moea_remove_write: page %p is not managed", m)); 1358208175Salc 1359208175Salc /* 1360208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1361208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 1362208175Salc * is clear, no page table entries need updating. 1363208175Salc */ 1364208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1365208175Salc if ((m->oflags & VPO_BUSY) == 0 && 1366160889Salc (m->flags & PG_WRITEABLE) == 0) 1367160889Salc return; 1368207796Salc vm_page_lock_queues(); 1369160889Salc lo = moea_attr_fetch(m); 1370183094Smarcel powerpc_sync(); 1371160889Salc LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1372160889Salc pmap = pvo->pvo_pmap; 1373160889Salc PMAP_LOCK(pmap); 1374183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1375160889Salc pt = moea_pvo_to_pte(pvo, -1); 1376183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1377183290Snwhitehorn pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1378160889Salc if (pt != NULL) { 1379183290Snwhitehorn moea_pte_synch(pt, &pvo->pvo_pte.pte); 1380183290Snwhitehorn lo |= pvo->pvo_pte.pte.pte_lo; 1381183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1382183290Snwhitehorn moea_pte_change(pt, &pvo->pvo_pte.pte, 1383160889Salc pvo->pvo_vaddr); 1384160889Salc mtx_unlock(&moea_table_mutex); 1385160889Salc } 1386160889Salc } 1387160889Salc PMAP_UNLOCK(pmap); 1388160889Salc } 1389160889Salc if ((lo & PTE_CHG) != 0) { 1390160889Salc moea_attr_clear(m, PTE_CHG); 1391160889Salc vm_page_dirty(m); 1392160889Salc } 1393160889Salc vm_page_flag_clear(m, PG_WRITEABLE); 1394207796Salc vm_page_unlock_queues(); 1395160889Salc} 1396160889Salc 1397160889Salc/* 1398152180Sgrehan * moea_ts_referenced: 139991403Ssilby * 140091403Ssilby * Return a count of reference bits for a page, clearing those bits. 140191403Ssilby * It is not necessary for every reference bit to be cleared, but it 140291403Ssilby * is necessary that 0 only be returned when there are truly no 140391403Ssilby * reference bits set. 140491403Ssilby * 140591403Ssilby * XXX: The exact number of bits to check and clear is a matter that 140691403Ssilby * should be tested and standardized at some point in the future for 140791403Ssilby * optimal aging of shared pages. 140891403Ssilby */ 1409152180Sgrehanboolean_t 1410152180Sgrehanmoea_ts_referenced(mmu_t mmu, vm_page_t m) 141190643Sbenno{ 1412110172Sgrehan 1413208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1414208990Salc ("moea_ts_referenced: page %p is not managed", m)); 1415208990Salc return (moea_clear_bit(m, PTE_REF)); 141690643Sbenno} 141790643Sbenno 141877957Sbenno/* 141990643Sbenno * Map a wired page into kernel virtual address space. 142077957Sbenno */ 142177957Sbennovoid 1422152180Sgrehanmoea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 142377957Sbenno{ 142490643Sbenno u_int pte_lo; 142590643Sbenno int error; 142690643Sbenno int i; 142777957Sbenno 142890643Sbenno#if 0 142990643Sbenno if (va < VM_MIN_KERNEL_ADDRESS) 1430152180Sgrehan panic("moea_kenter: attempt to enter non-kernel address %#x", 143190643Sbenno va); 143290643Sbenno#endif 143377957Sbenno 1434103604Sgrehan pte_lo = PTE_I | PTE_G; 1435103604Sgrehan for (i = 0; i < pregions_sz; i++) { 1436103604Sgrehan if ((pa >= pregions[i].mr_start) && 1437103604Sgrehan (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1438183094Smarcel pte_lo = PTE_M; 143977957Sbenno break; 144077957Sbenno } 1441103604Sgrehan } 144277957Sbenno 1443135172Salc PMAP_LOCK(kernel_pmap); 1444152180Sgrehan error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1445152180Sgrehan &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 144690643Sbenno 144790643Sbenno if (error != 0 && error != ENOENT) 1448152180Sgrehan panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 144990643Sbenno pa, error); 145090643Sbenno 145177957Sbenno /* 145290643Sbenno * Flush the real memory from the instruction cache. 145377957Sbenno */ 145490643Sbenno if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1455152180Sgrehan moea_syncicache(pa, PAGE_SIZE); 145677957Sbenno } 1457135172Salc PMAP_UNLOCK(kernel_pmap); 145877957Sbenno} 145977957Sbenno 146094838Sbenno/* 146194838Sbenno * Extract the physical page address associated with the given kernel virtual 146294838Sbenno * address. 146394838Sbenno */ 146490643Sbennovm_offset_t 1465152180Sgrehanmoea_kextract(mmu_t mmu, vm_offset_t va) 146677957Sbenno{ 146794838Sbenno struct pvo_entry *pvo; 1468134329Salc vm_paddr_t pa; 146994838Sbenno 1470125185Sgrehan /* 1471183290Snwhitehorn * Allow direct mappings on 32-bit OEA 1472125185Sgrehan */ 1473125185Sgrehan if (va < VM_MIN_KERNEL_ADDRESS) { 1474125185Sgrehan return (va); 1475125185Sgrehan } 1476125185Sgrehan 1477134329Salc PMAP_LOCK(kernel_pmap); 1478152180Sgrehan pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1479152180Sgrehan KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1480183290Snwhitehorn pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1481134329Salc PMAP_UNLOCK(kernel_pmap); 1482134329Salc return (pa); 148377957Sbenno} 148477957Sbenno 148591456Sbenno/* 148691456Sbenno * Remove a wired page from kernel virtual address space. 148791456Sbenno */ 148877957Sbennovoid 1489152180Sgrehanmoea_kremove(mmu_t mmu, vm_offset_t va) 149077957Sbenno{ 149191456Sbenno 1492152180Sgrehan moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 149377957Sbenno} 149477957Sbenno 149577957Sbenno/* 149690643Sbenno * Map a range of physical addresses into kernel virtual address space. 149790643Sbenno * 149890643Sbenno * The value passed in *virt is a suggested virtual address for the mapping. 149990643Sbenno * Architectures which can support a direct-mapped physical to virtual region 150090643Sbenno * can return the appropriate address within that region, leaving '*virt' 150190643Sbenno * unchanged. We cannot and therefore do not; *virt is updated with the 150290643Sbenno * first usable address after the mapped region. 150377957Sbenno */ 150490643Sbennovm_offset_t 1505152180Sgrehanmoea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1506152180Sgrehan vm_offset_t pa_end, int prot) 150777957Sbenno{ 150890643Sbenno vm_offset_t sva, va; 150977957Sbenno 151090643Sbenno sva = *virt; 151190643Sbenno va = sva; 151290643Sbenno for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1513152180Sgrehan moea_kenter(mmu, va, pa_start); 151490643Sbenno *virt = va; 151590643Sbenno return (sva); 151677957Sbenno} 151777957Sbenno 151877957Sbenno/* 151991403Ssilby * Returns true if the pmap's pv is one of the first 152091403Ssilby * 16 pvs linked to from this page. This count may 152191403Ssilby * be changed upwards or downwards in the future; it 152291403Ssilby * is only necessary that true be returned for a small 152391403Ssilby * subset of pmaps for proper page aging. 152491403Ssilby */ 152590643Sbennoboolean_t 1526152180Sgrehanmoea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 152790643Sbenno{ 1528110172Sgrehan int loops; 1529110172Sgrehan struct pvo_entry *pvo; 1530208990Salc boolean_t rv; 1531110172Sgrehan 1532208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1533208990Salc ("moea_page_exists_quick: page %p is not managed", m)); 1534110172Sgrehan loops = 0; 1535208990Salc rv = FALSE; 1536208990Salc vm_page_lock_queues(); 1537110172Sgrehan LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1538208990Salc if (pvo->pvo_pmap == pmap) { 1539208990Salc rv = TRUE; 1540208990Salc break; 1541208990Salc } 1542110172Sgrehan if (++loops >= 16) 1543110172Sgrehan break; 1544110172Sgrehan } 1545208990Salc vm_page_unlock_queues(); 1546208990Salc return (rv); 154790643Sbenno} 154877957Sbenno 1549173708Salc/* 1550173708Salc * Return the number of managed mappings to the given physical page 1551173708Salc * that are wired. 1552173708Salc */ 1553173708Salcint 1554173708Salcmoea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1555173708Salc{ 1556173708Salc struct pvo_entry *pvo; 1557173708Salc int count; 1558173708Salc 1559173708Salc count = 0; 1560208990Salc if ((m->flags & PG_FICTITIOUS) != 0) 1561173708Salc return (count); 1562207796Salc vm_page_lock_queues(); 1563173708Salc LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1564173708Salc if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1565173708Salc count++; 1566207796Salc vm_page_unlock_queues(); 1567173708Salc return (count); 1568173708Salc} 1569173708Salc 1570152180Sgrehanstatic u_int moea_vsidcontext; 157177957Sbenno 157290643Sbennovoid 1573152180Sgrehanmoea_pinit(mmu_t mmu, pmap_t pmap) 157490643Sbenno{ 157590643Sbenno int i, mask; 157690643Sbenno u_int entropy; 157777957Sbenno 1578152180Sgrehan KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1579134329Salc PMAP_LOCK_INIT(pmap); 1580126478Sgrehan 158190643Sbenno entropy = 0; 158290643Sbenno __asm __volatile("mftb %0" : "=r"(entropy)); 158377957Sbenno 1584183290Snwhitehorn if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1585183290Snwhitehorn == NULL) { 1586183290Snwhitehorn pmap->pmap_phys = pmap; 1587183290Snwhitehorn } 1588183290Snwhitehorn 1589183290Snwhitehorn 1590212278Snwhitehorn mtx_lock(&moea_vsid_mutex); 159190643Sbenno /* 159290643Sbenno * Allocate some segment registers for this pmap. 159390643Sbenno */ 159490643Sbenno for (i = 0; i < NPMAPS; i += VSID_NBPW) { 159590643Sbenno u_int hash, n; 159677957Sbenno 159777957Sbenno /* 159890643Sbenno * Create a new value by mutiplying by a prime and adding in 159990643Sbenno * entropy from the timebase register. This is to make the 160090643Sbenno * VSID more random so that the PT hash function collides 160190643Sbenno * less often. (Note that the prime casues gcc to do shifts 160290643Sbenno * instead of a multiply.) 160377957Sbenno */ 1604152180Sgrehan moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1605152180Sgrehan hash = moea_vsidcontext & (NPMAPS - 1); 160690643Sbenno if (hash == 0) /* 0 is special, avoid it */ 160790643Sbenno continue; 160890643Sbenno n = hash >> 5; 160990643Sbenno mask = 1 << (hash & (VSID_NBPW - 1)); 1610152180Sgrehan hash = (moea_vsidcontext & 0xfffff); 1611152180Sgrehan if (moea_vsid_bitmap[n] & mask) { /* collision? */ 161290643Sbenno /* anything free in this bucket? */ 1613152180Sgrehan if (moea_vsid_bitmap[n] == 0xffffffff) { 1614152180Sgrehan entropy = (moea_vsidcontext >> 20); 161590643Sbenno continue; 161690643Sbenno } 1617212322Snwhitehorn i = ffs(~moea_vsid_bitmap[n]) - 1; 161890643Sbenno mask = 1 << i; 161990643Sbenno hash &= 0xfffff & ~(VSID_NBPW - 1); 162090643Sbenno hash |= i; 162177957Sbenno } 1622152180Sgrehan moea_vsid_bitmap[n] |= mask; 162390643Sbenno for (i = 0; i < 16; i++) 162490643Sbenno pmap->pm_sr[i] = VSID_MAKE(i, hash); 1625212278Snwhitehorn mtx_unlock(&moea_vsid_mutex); 162690643Sbenno return; 162790643Sbenno } 162877957Sbenno 1629212278Snwhitehorn mtx_unlock(&moea_vsid_mutex); 1630152180Sgrehan panic("moea_pinit: out of segments"); 163177957Sbenno} 163277957Sbenno 163377957Sbenno/* 163490643Sbenno * Initialize the pmap associated with process 0. 163577957Sbenno */ 163677957Sbennovoid 1637152180Sgrehanmoea_pinit0(mmu_t mmu, pmap_t pm) 163877957Sbenno{ 163977957Sbenno 1640152180Sgrehan moea_pinit(mmu, pm); 164190643Sbenno bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 164277957Sbenno} 164377957Sbenno 164494838Sbenno/* 164594838Sbenno * Set the physical protection on the specified range of this map as requested. 164694838Sbenno */ 164790643Sbennovoid 1648152180Sgrehanmoea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1649152180Sgrehan vm_prot_t prot) 165090643Sbenno{ 165194838Sbenno struct pvo_entry *pvo; 165294838Sbenno struct pte *pt; 165394838Sbenno int pteidx; 165494838Sbenno 165594838Sbenno KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1656152180Sgrehan ("moea_protect: non current pmap")); 165794838Sbenno 165894838Sbenno if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1659152180Sgrehan moea_remove(mmu, pm, sva, eva); 166094838Sbenno return; 166194838Sbenno } 166294838Sbenno 1663132220Salc vm_page_lock_queues(); 1664134329Salc PMAP_LOCK(pm); 166594838Sbenno for (; sva < eva; sva += PAGE_SIZE) { 1666152180Sgrehan pvo = moea_pvo_find_va(pm, sva, &pteidx); 166794838Sbenno if (pvo == NULL) 166894838Sbenno continue; 166994838Sbenno 167094838Sbenno if ((prot & VM_PROT_EXECUTE) == 0) 167194838Sbenno pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 167294838Sbenno 167394838Sbenno /* 167494838Sbenno * Grab the PTE pointer before we diddle with the cached PTE 167594838Sbenno * copy. 167694838Sbenno */ 1677152180Sgrehan pt = moea_pvo_to_pte(pvo, pteidx); 167894838Sbenno /* 167994838Sbenno * Change the protection of the page. 168094838Sbenno */ 1681183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1682183290Snwhitehorn pvo->pvo_pte.pte.pte_lo |= PTE_BR; 168394838Sbenno 168494838Sbenno /* 168594838Sbenno * If the PVO is in the page table, update that pte as well. 168694838Sbenno */ 1687159928Salc if (pt != NULL) { 1688183290Snwhitehorn moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1689159928Salc mtx_unlock(&moea_table_mutex); 1690159928Salc } 169194838Sbenno } 1692132220Salc vm_page_unlock_queues(); 1693134329Salc PMAP_UNLOCK(pm); 169477957Sbenno} 169577957Sbenno 169691456Sbenno/* 169791456Sbenno * Map a list of wired pages into kernel virtual address space. This is 169891456Sbenno * intended for temporary mappings which do not need page modification or 169991456Sbenno * references recorded. Existing mappings in the region are overwritten. 170091456Sbenno */ 170190643Sbennovoid 1702152180Sgrehanmoea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 170377957Sbenno{ 1704110172Sgrehan vm_offset_t va; 170577957Sbenno 1706110172Sgrehan va = sva; 1707110172Sgrehan while (count-- > 0) { 1708152180Sgrehan moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1709110172Sgrehan va += PAGE_SIZE; 1710110172Sgrehan m++; 1711110172Sgrehan } 171290643Sbenno} 171377957Sbenno 171491456Sbenno/* 171591456Sbenno * Remove page mappings from kernel virtual address space. Intended for 1716152180Sgrehan * temporary mappings entered by moea_qenter. 171791456Sbenno */ 171890643Sbennovoid 1719152180Sgrehanmoea_qremove(mmu_t mmu, vm_offset_t sva, int count) 172090643Sbenno{ 1721110172Sgrehan vm_offset_t va; 172291456Sbenno 1723110172Sgrehan va = sva; 1724110172Sgrehan while (count-- > 0) { 1725152180Sgrehan moea_kremove(mmu, va); 1726110172Sgrehan va += PAGE_SIZE; 1727110172Sgrehan } 172877957Sbenno} 172977957Sbenno 173090643Sbennovoid 1731152180Sgrehanmoea_release(mmu_t mmu, pmap_t pmap) 173290643Sbenno{ 1733103604Sgrehan int idx, mask; 1734103604Sgrehan 1735103604Sgrehan /* 1736103604Sgrehan * Free segment register's VSID 1737103604Sgrehan */ 1738103604Sgrehan if (pmap->pm_sr[0] == 0) 1739152180Sgrehan panic("moea_release"); 1740103604Sgrehan 1741212278Snwhitehorn mtx_lock(&moea_vsid_mutex); 1742103604Sgrehan idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1743103604Sgrehan mask = 1 << (idx % VSID_NBPW); 1744103604Sgrehan idx /= VSID_NBPW; 1745152180Sgrehan moea_vsid_bitmap[idx] &= ~mask; 1746212278Snwhitehorn mtx_unlock(&moea_vsid_mutex); 1747134329Salc PMAP_LOCK_DESTROY(pmap); 174877957Sbenno} 174977957Sbenno 175091456Sbenno/* 175191456Sbenno * Remove the given range of addresses from the specified map. 175291456Sbenno */ 175390643Sbennovoid 1754152180Sgrehanmoea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 175577957Sbenno{ 175691456Sbenno struct pvo_entry *pvo; 175791456Sbenno int pteidx; 175891456Sbenno 1759132220Salc vm_page_lock_queues(); 1760134329Salc PMAP_LOCK(pm); 176191456Sbenno for (; sva < eva; sva += PAGE_SIZE) { 1762152180Sgrehan pvo = moea_pvo_find_va(pm, sva, &pteidx); 176391456Sbenno if (pvo != NULL) { 1764152180Sgrehan moea_pvo_remove(pvo, pteidx); 176591456Sbenno } 176691456Sbenno } 1767140538Sgrehan PMAP_UNLOCK(pm); 1768132220Salc vm_page_unlock_queues(); 176977957Sbenno} 177077957Sbenno 177194838Sbenno/* 1772152180Sgrehan * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1773110172Sgrehan * will reflect changes in pte's back to the vm_page. 1774110172Sgrehan */ 1775110172Sgrehanvoid 1776152180Sgrehanmoea_remove_all(mmu_t mmu, vm_page_t m) 1777110172Sgrehan{ 1778110172Sgrehan struct pvo_head *pvo_head; 1779110172Sgrehan struct pvo_entry *pvo, *next_pvo; 1780134329Salc pmap_t pmap; 1781110172Sgrehan 1782207796Salc vm_page_lock_queues(); 1783110172Sgrehan pvo_head = vm_page_to_pvoh(m); 1784110172Sgrehan for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1785110172Sgrehan next_pvo = LIST_NEXT(pvo, pvo_vlink); 1786133166Sgrehan 1787152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 1788134329Salc pmap = pvo->pvo_pmap; 1789134329Salc PMAP_LOCK(pmap); 1790152180Sgrehan moea_pvo_remove(pvo, -1); 1791134329Salc PMAP_UNLOCK(pmap); 1792110172Sgrehan } 1793204042Snwhitehorn if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1794208847Snwhitehorn moea_attr_clear(m, PTE_CHG); 1795204042Snwhitehorn vm_page_dirty(m); 1796204042Snwhitehorn } 1797110172Sgrehan vm_page_flag_clear(m, PG_WRITEABLE); 1798207796Salc vm_page_unlock_queues(); 1799110172Sgrehan} 1800110172Sgrehan 1801110172Sgrehan/* 180290643Sbenno * Allocate a physical page of memory directly from the phys_avail map. 1803152180Sgrehan * Can only be called from moea_bootstrap before avail start and end are 180490643Sbenno * calculated. 180583682Smp */ 180690643Sbennostatic vm_offset_t 1807152180Sgrehanmoea_bootstrap_alloc(vm_size_t size, u_int align) 180883682Smp{ 180990643Sbenno vm_offset_t s, e; 181090643Sbenno int i, j; 181183682Smp 181290643Sbenno size = round_page(size); 181390643Sbenno for (i = 0; phys_avail[i + 1] != 0; i += 2) { 181490643Sbenno if (align != 0) 181590643Sbenno s = (phys_avail[i] + align - 1) & ~(align - 1); 181690643Sbenno else 181790643Sbenno s = phys_avail[i]; 181890643Sbenno e = s + size; 181990643Sbenno 182090643Sbenno if (s < phys_avail[i] || e > phys_avail[i + 1]) 182190643Sbenno continue; 182290643Sbenno 182390643Sbenno if (s == phys_avail[i]) { 182490643Sbenno phys_avail[i] += size; 182590643Sbenno } else if (e == phys_avail[i + 1]) { 182690643Sbenno phys_avail[i + 1] -= size; 182790643Sbenno } else { 182890643Sbenno for (j = phys_avail_count * 2; j > i; j -= 2) { 182990643Sbenno phys_avail[j] = phys_avail[j - 2]; 183090643Sbenno phys_avail[j + 1] = phys_avail[j - 1]; 183190643Sbenno } 183290643Sbenno 183390643Sbenno phys_avail[i + 3] = phys_avail[i + 1]; 183490643Sbenno phys_avail[i + 1] = s; 183590643Sbenno phys_avail[i + 2] = e; 183690643Sbenno phys_avail_count++; 183790643Sbenno } 183890643Sbenno 183990643Sbenno return (s); 184083682Smp } 1841152180Sgrehan panic("moea_bootstrap_alloc: could not allocate memory"); 184283682Smp} 184383682Smp 184490643Sbennostatic void 1845152180Sgrehanmoea_syncicache(vm_offset_t pa, vm_size_t len) 184677957Sbenno{ 184790643Sbenno __syncicache((void *)pa, len); 184890643Sbenno} 184977957Sbenno 185090643Sbennostatic int 1851152180Sgrehanmoea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 185290643Sbenno vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 185377957Sbenno{ 185490643Sbenno struct pvo_entry *pvo; 185590643Sbenno u_int sr; 185690643Sbenno int first; 185790643Sbenno u_int ptegidx; 185890643Sbenno int i; 1859103604Sgrehan int bootstrap; 186077957Sbenno 1861152180Sgrehan moea_pvo_enter_calls++; 186296250Sbenno first = 0; 1863103604Sgrehan bootstrap = 0; 186490643Sbenno 186590643Sbenno /* 186690643Sbenno * Compute the PTE Group index. 186790643Sbenno */ 186890643Sbenno va &= ~ADDR_POFF; 186990643Sbenno sr = va_to_sr(pm->pm_sr, va); 187090643Sbenno ptegidx = va_to_pteg(sr, va); 187190643Sbenno 187290643Sbenno /* 187390643Sbenno * Remove any existing mapping for this page. Reuse the pvo entry if 187490643Sbenno * there is a mapping. 187590643Sbenno */ 1876152180Sgrehan mtx_lock(&moea_table_mutex); 1877152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 187890643Sbenno if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1879183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1880183290Snwhitehorn (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 188196334Sbenno (pte_lo & PTE_PP)) { 1882152180Sgrehan mtx_unlock(&moea_table_mutex); 188392521Sbenno return (0); 188496334Sbenno } 1885152180Sgrehan moea_pvo_remove(pvo, -1); 188690643Sbenno break; 188790643Sbenno } 188890643Sbenno } 188990643Sbenno 189090643Sbenno /* 189190643Sbenno * If we aren't overwriting a mapping, try to allocate. 189290643Sbenno */ 1893152180Sgrehan if (moea_initialized) { 189492847Sjeff pvo = uma_zalloc(zone, M_NOWAIT); 189592521Sbenno } else { 1896152180Sgrehan if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1897152180Sgrehan panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1898152180Sgrehan moea_bpvo_pool_index, BPVO_POOL_SIZE, 189999037Sbenno BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 190092521Sbenno } 1901152180Sgrehan pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1902152180Sgrehan moea_bpvo_pool_index++; 1903103604Sgrehan bootstrap = 1; 190492521Sbenno } 190590643Sbenno 190690643Sbenno if (pvo == NULL) { 1907152180Sgrehan mtx_unlock(&moea_table_mutex); 190890643Sbenno return (ENOMEM); 190990643Sbenno } 191090643Sbenno 1911152180Sgrehan moea_pvo_entries++; 191290643Sbenno pvo->pvo_vaddr = va; 191390643Sbenno pvo->pvo_pmap = pm; 1914152180Sgrehan LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 191590643Sbenno pvo->pvo_vaddr &= ~ADDR_POFF; 191690643Sbenno if (flags & VM_PROT_EXECUTE) 191790643Sbenno pvo->pvo_vaddr |= PVO_EXECUTABLE; 191890643Sbenno if (flags & PVO_WIRED) 191990643Sbenno pvo->pvo_vaddr |= PVO_WIRED; 1920152180Sgrehan if (pvo_head != &moea_pvo_kunmanaged) 192190643Sbenno pvo->pvo_vaddr |= PVO_MANAGED; 1922103604Sgrehan if (bootstrap) 1923103604Sgrehan pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1924142416Sgrehan if (flags & PVO_FAKE) 1925142416Sgrehan pvo->pvo_vaddr |= PVO_FAKE; 1926142416Sgrehan 1927183290Snwhitehorn moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 192890643Sbenno 192990643Sbenno /* 193090643Sbenno * Remember if the list was empty and therefore will be the first 193190643Sbenno * item. 193290643Sbenno */ 193396250Sbenno if (LIST_FIRST(pvo_head) == NULL) 193496250Sbenno first = 1; 1935142416Sgrehan LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 193690643Sbenno 1937183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1938134453Salc pm->pm_stats.wired_count++; 1939134453Salc pm->pm_stats.resident_count++; 194090643Sbenno 194190643Sbenno /* 194290643Sbenno * We hope this succeeds but it isn't required. 194390643Sbenno */ 1944183290Snwhitehorn i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 194590643Sbenno if (i >= 0) { 194690643Sbenno PVO_PTEGIDX_SET(pvo, i); 194790643Sbenno } else { 1948152180Sgrehan panic("moea_pvo_enter: overflow"); 1949152180Sgrehan moea_pte_overflow++; 195090643Sbenno } 1951152180Sgrehan mtx_unlock(&moea_table_mutex); 195290643Sbenno 195390643Sbenno return (first ? ENOENT : 0); 195477957Sbenno} 195577957Sbenno 195690643Sbennostatic void 1957152180Sgrehanmoea_pvo_remove(struct pvo_entry *pvo, int pteidx) 195877957Sbenno{ 195990643Sbenno struct pte *pt; 196077957Sbenno 196190643Sbenno /* 196290643Sbenno * If there is an active pte entry, we need to deactivate it (and 196390643Sbenno * save the ref & cfg bits). 196490643Sbenno */ 1965152180Sgrehan pt = moea_pvo_to_pte(pvo, pteidx); 196690643Sbenno if (pt != NULL) { 1967183290Snwhitehorn moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1968159928Salc mtx_unlock(&moea_table_mutex); 196990643Sbenno PVO_PTEGIDX_CLR(pvo); 197090643Sbenno } else { 1971152180Sgrehan moea_pte_overflow--; 1972142416Sgrehan } 197390643Sbenno 197490643Sbenno /* 197590643Sbenno * Update our statistics. 197690643Sbenno */ 197790643Sbenno pvo->pvo_pmap->pm_stats.resident_count--; 1978183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 197990643Sbenno pvo->pvo_pmap->pm_stats.wired_count--; 198090643Sbenno 198190643Sbenno /* 198290643Sbenno * Save the REF/CHG bits into their cache if the page is managed. 198390643Sbenno */ 1984142416Sgrehan if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 198590643Sbenno struct vm_page *pg; 198690643Sbenno 1987183290Snwhitehorn pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 198890643Sbenno if (pg != NULL) { 1989183290Snwhitehorn moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 199090643Sbenno (PTE_REF | PTE_CHG)); 199190643Sbenno } 199290643Sbenno } 199390643Sbenno 199490643Sbenno /* 199590643Sbenno * Remove this PVO from the PV list. 199690643Sbenno */ 199790643Sbenno LIST_REMOVE(pvo, pvo_vlink); 199890643Sbenno 199990643Sbenno /* 200090643Sbenno * Remove this from the overflow list and return it to the pool 200190643Sbenno * if we aren't going to reuse it. 200290643Sbenno */ 200390643Sbenno LIST_REMOVE(pvo, pvo_olink); 200492521Sbenno if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2005152180Sgrehan uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2006152180Sgrehan moea_upvo_zone, pvo); 2007152180Sgrehan moea_pvo_entries--; 2008152180Sgrehan moea_pvo_remove_calls++; 200977957Sbenno} 201077957Sbenno 201190643Sbennostatic __inline int 2012152180Sgrehanmoea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 201377957Sbenno{ 201490643Sbenno int pteidx; 201577957Sbenno 201690643Sbenno /* 201790643Sbenno * We can find the actual pte entry without searching by grabbing 201890643Sbenno * the PTEG index from 3 unused bits in pte_lo[11:9] and by 201990643Sbenno * noticing the HID bit. 202090643Sbenno */ 202190643Sbenno pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2022183290Snwhitehorn if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2023152180Sgrehan pteidx ^= moea_pteg_mask * 8; 202490643Sbenno 202590643Sbenno return (pteidx); 202677957Sbenno} 202777957Sbenno 202890643Sbennostatic struct pvo_entry * 2029152180Sgrehanmoea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 203077957Sbenno{ 203190643Sbenno struct pvo_entry *pvo; 203290643Sbenno int ptegidx; 203390643Sbenno u_int sr; 203477957Sbenno 203590643Sbenno va &= ~ADDR_POFF; 203690643Sbenno sr = va_to_sr(pm->pm_sr, va); 203790643Sbenno ptegidx = va_to_pteg(sr, va); 203890643Sbenno 2039152180Sgrehan mtx_lock(&moea_table_mutex); 2040152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 204190643Sbenno if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 204290643Sbenno if (pteidx_p) 2043152180Sgrehan *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2044134535Salc break; 204590643Sbenno } 204690643Sbenno } 2047152180Sgrehan mtx_unlock(&moea_table_mutex); 204890643Sbenno 2049134535Salc return (pvo); 205077957Sbenno} 205177957Sbenno 205290643Sbennostatic struct pte * 2053152180Sgrehanmoea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 205477957Sbenno{ 205590643Sbenno struct pte *pt; 205677957Sbenno 205790643Sbenno /* 205890643Sbenno * If we haven't been supplied the ptegidx, calculate it. 205990643Sbenno */ 206090643Sbenno if (pteidx == -1) { 206190643Sbenno int ptegidx; 206290643Sbenno u_int sr; 206377957Sbenno 206490643Sbenno sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 206590643Sbenno ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2066152180Sgrehan pteidx = moea_pvo_pte_index(pvo, ptegidx); 206790643Sbenno } 206890643Sbenno 2069152180Sgrehan pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2070159928Salc mtx_lock(&moea_table_mutex); 207190643Sbenno 2072183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2073152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 207490643Sbenno "valid pte index", pvo); 207590643Sbenno } 207690643Sbenno 2077183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2078152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 207990643Sbenno "pvo but no valid pte", pvo); 208090643Sbenno } 208190643Sbenno 2082183290Snwhitehorn if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2083183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2084152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte in " 2085152180Sgrehan "moea_pteg_table %p but invalid in pvo", pvo, pt); 208677957Sbenno } 208790643Sbenno 2088183290Snwhitehorn if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 208990643Sbenno != 0) { 2090152180Sgrehan panic("moea_pvo_to_pte: pvo %p pte does not match " 2091152180Sgrehan "pte %p in moea_pteg_table", pvo, pt); 209290643Sbenno } 209390643Sbenno 2094159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 209590643Sbenno return (pt); 209677957Sbenno } 209777957Sbenno 2098183290Snwhitehorn if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2099152180Sgrehan panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2100152180Sgrehan "moea_pteg_table but valid in pvo", pvo, pt); 210190643Sbenno } 210277957Sbenno 2103159928Salc mtx_unlock(&moea_table_mutex); 210490643Sbenno return (NULL); 210577957Sbenno} 210678880Sbenno 210778880Sbenno/* 210890643Sbenno * XXX: THIS STUFF SHOULD BE IN pte.c? 210978880Sbenno */ 211090643Sbennoint 2111152180Sgrehanmoea_pte_spill(vm_offset_t addr) 211278880Sbenno{ 211390643Sbenno struct pvo_entry *source_pvo, *victim_pvo; 211490643Sbenno struct pvo_entry *pvo; 211590643Sbenno int ptegidx, i, j; 211690643Sbenno u_int sr; 211790643Sbenno struct pteg *pteg; 211890643Sbenno struct pte *pt; 211978880Sbenno 2120152180Sgrehan moea_pte_spills++; 212190643Sbenno 212294836Sbenno sr = mfsrin(addr); 212390643Sbenno ptegidx = va_to_pteg(sr, addr); 212490643Sbenno 212578880Sbenno /* 212690643Sbenno * Have to substitute some entry. Use the primary hash for this. 212790643Sbenno * Use low bits of timebase as random generator. 212878880Sbenno */ 2129152180Sgrehan pteg = &moea_pteg_table[ptegidx]; 2130152180Sgrehan mtx_lock(&moea_table_mutex); 213190643Sbenno __asm __volatile("mftb %0" : "=r"(i)); 213290643Sbenno i &= 7; 213390643Sbenno pt = &pteg->pt[i]; 213478880Sbenno 213590643Sbenno source_pvo = NULL; 213690643Sbenno victim_pvo = NULL; 2137152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 213878880Sbenno /* 213990643Sbenno * We need to find a pvo entry for this address. 214078880Sbenno */ 2141152180Sgrehan MOEA_PVO_CHECK(pvo); 214290643Sbenno if (source_pvo == NULL && 2143183290Snwhitehorn moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2144183290Snwhitehorn pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 214590643Sbenno /* 214690643Sbenno * Now found an entry to be spilled into the pteg. 214790643Sbenno * The PTE is now valid, so we know it's active. 214890643Sbenno */ 2149183290Snwhitehorn j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 215078880Sbenno 215190643Sbenno if (j >= 0) { 215290643Sbenno PVO_PTEGIDX_SET(pvo, j); 2153152180Sgrehan moea_pte_overflow--; 2154152180Sgrehan MOEA_PVO_CHECK(pvo); 2155152180Sgrehan mtx_unlock(&moea_table_mutex); 215690643Sbenno return (1); 215790643Sbenno } 215890643Sbenno 215990643Sbenno source_pvo = pvo; 216090643Sbenno 216190643Sbenno if (victim_pvo != NULL) 216290643Sbenno break; 216390643Sbenno } 216490643Sbenno 216578880Sbenno /* 216690643Sbenno * We also need the pvo entry of the victim we are replacing 216790643Sbenno * so save the R & C bits of the PTE. 216878880Sbenno */ 216990643Sbenno if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2170183290Snwhitehorn moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 217190643Sbenno victim_pvo = pvo; 217290643Sbenno if (source_pvo != NULL) 217390643Sbenno break; 217490643Sbenno } 217590643Sbenno } 217678880Sbenno 2177134535Salc if (source_pvo == NULL) { 2178152180Sgrehan mtx_unlock(&moea_table_mutex); 217990643Sbenno return (0); 2180134535Salc } 218190643Sbenno 218290643Sbenno if (victim_pvo == NULL) { 218390643Sbenno if ((pt->pte_hi & PTE_HID) == 0) 2184152180Sgrehan panic("moea_pte_spill: victim p-pte (%p) has no pvo" 218590643Sbenno "entry", pt); 218690643Sbenno 218778880Sbenno /* 218890643Sbenno * If this is a secondary PTE, we need to search it's primary 218990643Sbenno * pvo bucket for the matching PVO. 219078880Sbenno */ 2191152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 219290643Sbenno pvo_olink) { 2193152180Sgrehan MOEA_PVO_CHECK(pvo); 219490643Sbenno /* 219590643Sbenno * We also need the pvo entry of the victim we are 219690643Sbenno * replacing so save the R & C bits of the PTE. 219790643Sbenno */ 2198183290Snwhitehorn if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 219990643Sbenno victim_pvo = pvo; 220090643Sbenno break; 220190643Sbenno } 220290643Sbenno } 220378880Sbenno 220490643Sbenno if (victim_pvo == NULL) 2205152180Sgrehan panic("moea_pte_spill: victim s-pte (%p) has no pvo" 220690643Sbenno "entry", pt); 220790643Sbenno } 220878880Sbenno 220990643Sbenno /* 221090643Sbenno * We are invalidating the TLB entry for the EA we are replacing even 221190643Sbenno * though it's valid. If we don't, we lose any ref/chg bit changes 221290643Sbenno * contained in the TLB entry. 221390643Sbenno */ 2214183290Snwhitehorn source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 221578880Sbenno 2216183290Snwhitehorn moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2217183290Snwhitehorn moea_pte_set(pt, &source_pvo->pvo_pte.pte); 221890643Sbenno 221990643Sbenno PVO_PTEGIDX_CLR(victim_pvo); 222090643Sbenno PVO_PTEGIDX_SET(source_pvo, i); 2221152180Sgrehan moea_pte_replacements++; 222290643Sbenno 2223152180Sgrehan MOEA_PVO_CHECK(victim_pvo); 2224152180Sgrehan MOEA_PVO_CHECK(source_pvo); 222590643Sbenno 2226152180Sgrehan mtx_unlock(&moea_table_mutex); 222790643Sbenno return (1); 222890643Sbenno} 222990643Sbenno 223090643Sbennostatic int 2231152180Sgrehanmoea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 223290643Sbenno{ 223390643Sbenno struct pte *pt; 223490643Sbenno int i; 223590643Sbenno 2236159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 2237159928Salc 223890643Sbenno /* 223990643Sbenno * First try primary hash. 224090643Sbenno */ 2241152180Sgrehan for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 224290643Sbenno if ((pt->pte_hi & PTE_VALID) == 0) { 224390643Sbenno pvo_pt->pte_hi &= ~PTE_HID; 2244152180Sgrehan moea_pte_set(pt, pvo_pt); 224590643Sbenno return (i); 224678880Sbenno } 224790643Sbenno } 224878880Sbenno 224990643Sbenno /* 225090643Sbenno * Now try secondary hash. 225190643Sbenno */ 2252152180Sgrehan ptegidx ^= moea_pteg_mask; 2253165362Sgrehan 2254152180Sgrehan for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 225590643Sbenno if ((pt->pte_hi & PTE_VALID) == 0) { 225690643Sbenno pvo_pt->pte_hi |= PTE_HID; 2257152180Sgrehan moea_pte_set(pt, pvo_pt); 225890643Sbenno return (i); 225990643Sbenno } 226090643Sbenno } 226178880Sbenno 2262152180Sgrehan panic("moea_pte_insert: overflow"); 226390643Sbenno return (-1); 226478880Sbenno} 226584921Sbenno 226690643Sbennostatic boolean_t 2267152180Sgrehanmoea_query_bit(vm_page_t m, int ptebit) 226884921Sbenno{ 226990643Sbenno struct pvo_entry *pvo; 227090643Sbenno struct pte *pt; 227184921Sbenno 2272152180Sgrehan if (moea_attr_fetch(m) & ptebit) 227390643Sbenno return (TRUE); 227484921Sbenno 2275208574Salc vm_page_lock_queues(); 227690643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2277152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 227884921Sbenno 227990643Sbenno /* 228090643Sbenno * See if we saved the bit off. If so, cache it and return 228190643Sbenno * success. 228290643Sbenno */ 2283183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2284152180Sgrehan moea_attr_save(m, ptebit); 2285152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2286208574Salc vm_page_unlock_queues(); 228790643Sbenno return (TRUE); 228890643Sbenno } 228990643Sbenno } 229084921Sbenno 229190643Sbenno /* 229290643Sbenno * No luck, now go through the hard part of looking at the PTEs 229390643Sbenno * themselves. Sync so that any pending REF/CHG bits are flushed to 229490643Sbenno * the PTEs. 229590643Sbenno */ 2296183094Smarcel powerpc_sync(); 229790643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2298152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 229990643Sbenno 230090643Sbenno /* 230190643Sbenno * See if this pvo has a valid PTE. if so, fetch the 230290643Sbenno * REF/CHG bits from the valid PTE. If the appropriate 230390643Sbenno * ptebit is set, cache it and return success. 230490643Sbenno */ 2305152180Sgrehan pt = moea_pvo_to_pte(pvo, -1); 230690643Sbenno if (pt != NULL) { 2307183290Snwhitehorn moea_pte_synch(pt, &pvo->pvo_pte.pte); 2308159928Salc mtx_unlock(&moea_table_mutex); 2309183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2310152180Sgrehan moea_attr_save(m, ptebit); 2311152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2312208574Salc vm_page_unlock_queues(); 231390643Sbenno return (TRUE); 231490643Sbenno } 231590643Sbenno } 231684921Sbenno } 231784921Sbenno 2318208574Salc vm_page_unlock_queues(); 2319123354Sgallatin return (FALSE); 232084921Sbenno} 232190643Sbenno 2322110172Sgrehanstatic u_int 2323208990Salcmoea_clear_bit(vm_page_t m, int ptebit) 232490643Sbenno{ 2325110172Sgrehan u_int count; 232690643Sbenno struct pvo_entry *pvo; 232790643Sbenno struct pte *pt; 232890643Sbenno 2329208990Salc vm_page_lock_queues(); 2330208990Salc 233190643Sbenno /* 233290643Sbenno * Clear the cached value. 233390643Sbenno */ 2334152180Sgrehan moea_attr_clear(m, ptebit); 233590643Sbenno 233690643Sbenno /* 233790643Sbenno * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 233890643Sbenno * we can reset the right ones). note that since the pvo entries and 233990643Sbenno * list heads are accessed via BAT0 and are never placed in the page 234090643Sbenno * table, we don't have to worry about further accesses setting the 234190643Sbenno * REF/CHG bits. 234290643Sbenno */ 2343183094Smarcel powerpc_sync(); 234490643Sbenno 234590643Sbenno /* 234690643Sbenno * For each pvo entry, clear the pvo's ptebit. If this pvo has a 234790643Sbenno * valid pte clear the ptebit from the valid pte. 234890643Sbenno */ 2349110172Sgrehan count = 0; 235090643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2351152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2352152180Sgrehan pt = moea_pvo_to_pte(pvo, -1); 235390643Sbenno if (pt != NULL) { 2354183290Snwhitehorn moea_pte_synch(pt, &pvo->pvo_pte.pte); 2355183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2356110172Sgrehan count++; 2357152180Sgrehan moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2358110172Sgrehan } 2359159928Salc mtx_unlock(&moea_table_mutex); 236090643Sbenno } 2361183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2362152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 236390643Sbenno } 236490643Sbenno 2365208990Salc vm_page_unlock_queues(); 2366110172Sgrehan return (count); 236790643Sbenno} 236899038Sbenno 236999038Sbenno/* 2370103604Sgrehan * Return true if the physical range is encompassed by the battable[idx] 2371103604Sgrehan */ 2372103604Sgrehanstatic int 2373152180Sgrehanmoea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2374103604Sgrehan{ 2375103604Sgrehan u_int prot; 2376103604Sgrehan u_int32_t start; 2377103604Sgrehan u_int32_t end; 2378103604Sgrehan u_int32_t bat_ble; 2379103604Sgrehan 2380103604Sgrehan /* 2381103604Sgrehan * Return immediately if not a valid mapping 2382103604Sgrehan */ 2383103604Sgrehan if (!battable[idx].batu & BAT_Vs) 2384103604Sgrehan return (EINVAL); 2385103604Sgrehan 2386103604Sgrehan /* 2387103604Sgrehan * The BAT entry must be cache-inhibited, guarded, and r/w 2388103604Sgrehan * so it can function as an i/o page 2389103604Sgrehan */ 2390103604Sgrehan prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2391103604Sgrehan if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2392103604Sgrehan return (EPERM); 2393103604Sgrehan 2394103604Sgrehan /* 2395103604Sgrehan * The address should be within the BAT range. Assume that the 2396103604Sgrehan * start address in the BAT has the correct alignment (thus 2397103604Sgrehan * not requiring masking) 2398103604Sgrehan */ 2399103604Sgrehan start = battable[idx].batl & BAT_PBS; 2400103604Sgrehan bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2401103604Sgrehan end = start | (bat_ble << 15) | 0x7fff; 2402103604Sgrehan 2403103604Sgrehan if ((pa < start) || ((pa + size) > end)) 2404103604Sgrehan return (ERANGE); 2405103604Sgrehan 2406103604Sgrehan return (0); 2407103604Sgrehan} 2408103604Sgrehan 2409152180Sgrehanboolean_t 2410152180Sgrehanmoea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2411133855Sssouhlal{ 2412133855Sssouhlal int i; 2413103604Sgrehan 2414133855Sssouhlal /* 2415133855Sssouhlal * This currently does not work for entries that 2416133855Sssouhlal * overlap 256M BAT segments. 2417133855Sssouhlal */ 2418133855Sssouhlal 2419133855Sssouhlal for(i = 0; i < 16; i++) 2420152180Sgrehan if (moea_bat_mapped(i, pa, size) == 0) 2421133855Sssouhlal return (0); 2422133855Sssouhlal 2423133855Sssouhlal return (EFAULT); 2424133855Sssouhlal} 2425133855Sssouhlal 2426103604Sgrehan/* 242799038Sbenno * Map a set of physical memory pages into the kernel virtual 242899038Sbenno * address space. Return a pointer to where it is mapped. This 242999038Sbenno * routine is intended to be used for mapping device memory, 243099038Sbenno * NOT real memory. 243199038Sbenno */ 243299038Sbennovoid * 2433152180Sgrehanmoea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 243499038Sbenno{ 2435103604Sgrehan vm_offset_t va, tmpva, ppa, offset; 2436103604Sgrehan int i; 2437103604Sgrehan 2438103604Sgrehan ppa = trunc_page(pa); 243999038Sbenno offset = pa & PAGE_MASK; 244099038Sbenno size = roundup(offset + size, PAGE_SIZE); 244199038Sbenno 2442103604Sgrehan /* 2443103604Sgrehan * If the physical address lies within a valid BAT table entry, 2444103604Sgrehan * return the 1:1 mapping. This currently doesn't work 2445103604Sgrehan * for regions that overlap 256M BAT segments. 2446103604Sgrehan */ 2447103604Sgrehan for (i = 0; i < 16; i++) { 2448152180Sgrehan if (moea_bat_mapped(i, pa, size) == 0) 2449103604Sgrehan return ((void *) pa); 2450103604Sgrehan } 2451103604Sgrehan 2452118365Salc va = kmem_alloc_nofault(kernel_map, size); 245399038Sbenno if (!va) 2454152180Sgrehan panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 245599038Sbenno 245699038Sbenno for (tmpva = va; size > 0;) { 2457152180Sgrehan moea_kenter(mmu, tmpva, ppa); 2458183094Smarcel tlbie(tmpva); 245999038Sbenno size -= PAGE_SIZE; 246099038Sbenno tmpva += PAGE_SIZE; 2461103604Sgrehan ppa += PAGE_SIZE; 246299038Sbenno } 246399038Sbenno 246499038Sbenno return ((void *)(va + offset)); 246599038Sbenno} 246699038Sbenno 246799038Sbennovoid 2468152180Sgrehanmoea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 246999038Sbenno{ 247099038Sbenno vm_offset_t base, offset; 247199038Sbenno 2472103604Sgrehan /* 2473103604Sgrehan * If this is outside kernel virtual space, then it's a 2474103604Sgrehan * battable entry and doesn't require unmapping 2475103604Sgrehan */ 2476204128Snwhitehorn if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2477103604Sgrehan base = trunc_page(va); 2478103604Sgrehan offset = va & PAGE_MASK; 2479103604Sgrehan size = roundup(offset + size, PAGE_SIZE); 2480103604Sgrehan kmem_free(kernel_map, base, size); 2481103604Sgrehan } 248299038Sbenno} 2483198341Smarcel 2484198341Smarcelstatic void 2485198341Smarcelmoea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2486198341Smarcel{ 2487198341Smarcel struct pvo_entry *pvo; 2488198341Smarcel vm_offset_t lim; 2489198341Smarcel vm_paddr_t pa; 2490198341Smarcel vm_size_t len; 2491198341Smarcel 2492198341Smarcel PMAP_LOCK(pm); 2493198341Smarcel while (sz > 0) { 2494198341Smarcel lim = round_page(va); 2495198341Smarcel len = MIN(lim - va, sz); 2496198341Smarcel pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2497198341Smarcel if (pvo != NULL) { 2498198341Smarcel pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2499198341Smarcel (va & ADDR_POFF); 2500198341Smarcel moea_syncicache(pa, len); 2501198341Smarcel } 2502198341Smarcel va += len; 2503198341Smarcel sz -= len; 2504198341Smarcel } 2505198341Smarcel PMAP_UNLOCK(pm); 2506198341Smarcel} 2507