mmu_oea.c revision 212278
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 212278 2010-09-06 23:07:58Z nwhitehorn $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <dev/ofw/openfirm.h> 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/platform.h> 145#include <machine/bat.h> 146#include <machine/frame.h> 147#include <machine/md_var.h> 148#include <machine/psl.h> 149#include <machine/pte.h> 150#include <machine/smp.h> 151#include <machine/sr.h> 152#include <machine/mmuvar.h> 153 154#include "mmu_if.h" 155 156#define MOEA_DEBUG 157 158#define TODO panic("%s: not implemented", __func__); 159 160#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 161#define VSID_TO_SR(vsid) ((vsid) & 0xf) 162#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163 164#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 165#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 166#define PVO_WIRED 0x010 /* PVO entry is wired */ 167#define PVO_MANAGED 0x020 /* PVO entry is managed */ 168#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 169#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 170 bootstrap */ 171#define PVO_FAKE 0x100 /* fictitious phys page */ 172#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 173#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 175#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 176#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 177#define PVO_PTEGIDX_CLR(pvo) \ 178 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 179#define PVO_PTEGIDX_SET(pvo, i) \ 180 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 181 182#define MOEA_PVO_CHECK(pvo) 183 184struct ofw_map { 185 vm_offset_t om_va; 186 vm_size_t om_len; 187 vm_offset_t om_pa; 188 u_int om_mode; 189}; 190 191/* 192 * Map of physical memory regions. 193 */ 194static struct mem_region *regions; 195static struct mem_region *pregions; 196static u_int phys_avail_count; 197static int regions_sz, pregions_sz; 198static struct ofw_map *translations; 199 200extern struct pmap ofw_pmap; 201 202/* 203 * Lock for the pteg and pvo tables. 204 */ 205struct mtx moea_table_mutex; 206struct mtx moea_vsid_mutex; 207 208/* tlbie instruction synchronization */ 209static struct mtx tlbie_mtx; 210 211/* 212 * PTEG data. 213 */ 214static struct pteg *moea_pteg_table; 215u_int moea_pteg_count; 216u_int moea_pteg_mask; 217 218/* 219 * PVO data. 220 */ 221struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 222struct pvo_head moea_pvo_kunmanaged = 223 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 224struct pvo_head moea_pvo_unmanaged = 225 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 226 227uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 228uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 229 230#define BPVO_POOL_SIZE 32768 231static struct pvo_entry *moea_bpvo_pool; 232static int moea_bpvo_pool_index = 0; 233 234#define VSID_NBPW (sizeof(u_int32_t) * 8) 235static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 236 237static boolean_t moea_initialized = FALSE; 238 239/* 240 * Statistics. 241 */ 242u_int moea_pte_valid = 0; 243u_int moea_pte_overflow = 0; 244u_int moea_pte_replacements = 0; 245u_int moea_pvo_entries = 0; 246u_int moea_pvo_enter_calls = 0; 247u_int moea_pvo_remove_calls = 0; 248u_int moea_pte_spills = 0; 249SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 250 0, ""); 251SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 252 &moea_pte_overflow, 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 254 &moea_pte_replacements, 0, ""); 255SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 256 0, ""); 257SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 258 &moea_pvo_enter_calls, 0, ""); 259SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 260 &moea_pvo_remove_calls, 0, ""); 261SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 262 &moea_pte_spills, 0, ""); 263 264/* 265 * Allocate physical memory for use in moea_bootstrap. 266 */ 267static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 268 269/* 270 * PTE calls. 271 */ 272static int moea_pte_insert(u_int, struct pte *); 273 274/* 275 * PVO calls. 276 */ 277static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 278 vm_offset_t, vm_offset_t, u_int, int); 279static void moea_pvo_remove(struct pvo_entry *, int); 280static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 281static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 282 283/* 284 * Utility routines. 285 */ 286static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 287 vm_prot_t, boolean_t); 288static void moea_syncicache(vm_offset_t, vm_size_t); 289static boolean_t moea_query_bit(vm_page_t, int); 290static u_int moea_clear_bit(vm_page_t, int); 291static void moea_kremove(mmu_t, vm_offset_t); 292int moea_pte_spill(vm_offset_t); 293 294/* 295 * Kernel MMU interface 296 */ 297void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 298void moea_clear_modify(mmu_t, vm_page_t); 299void moea_clear_reference(mmu_t, vm_page_t); 300void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 301void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 302void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 303 vm_prot_t); 304void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 305vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 306vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 307void moea_init(mmu_t); 308boolean_t moea_is_modified(mmu_t, vm_page_t); 309boolean_t moea_is_referenced(mmu_t, vm_page_t); 310boolean_t moea_ts_referenced(mmu_t, vm_page_t); 311vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 312boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 313int moea_page_wired_mappings(mmu_t, vm_page_t); 314void moea_pinit(mmu_t, pmap_t); 315void moea_pinit0(mmu_t, pmap_t); 316void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 317void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 318void moea_qremove(mmu_t, vm_offset_t, int); 319void moea_release(mmu_t, pmap_t); 320void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 321void moea_remove_all(mmu_t, vm_page_t); 322void moea_remove_write(mmu_t, vm_page_t); 323void moea_zero_page(mmu_t, vm_page_t); 324void moea_zero_page_area(mmu_t, vm_page_t, int, int); 325void moea_zero_page_idle(mmu_t, vm_page_t); 326void moea_activate(mmu_t, struct thread *); 327void moea_deactivate(mmu_t, struct thread *); 328void moea_cpu_bootstrap(mmu_t, int); 329void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 330void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 331void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 332vm_offset_t moea_kextract(mmu_t, vm_offset_t); 333void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 334boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 335static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 336 337static mmu_method_t moea_methods[] = { 338 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 339 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 340 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 341 MMUMETHOD(mmu_copy_page, moea_copy_page), 342 MMUMETHOD(mmu_enter, moea_enter), 343 MMUMETHOD(mmu_enter_object, moea_enter_object), 344 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 345 MMUMETHOD(mmu_extract, moea_extract), 346 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 347 MMUMETHOD(mmu_init, moea_init), 348 MMUMETHOD(mmu_is_modified, moea_is_modified), 349 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 350 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 351 MMUMETHOD(mmu_map, moea_map), 352 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 353 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 354 MMUMETHOD(mmu_pinit, moea_pinit), 355 MMUMETHOD(mmu_pinit0, moea_pinit0), 356 MMUMETHOD(mmu_protect, moea_protect), 357 MMUMETHOD(mmu_qenter, moea_qenter), 358 MMUMETHOD(mmu_qremove, moea_qremove), 359 MMUMETHOD(mmu_release, moea_release), 360 MMUMETHOD(mmu_remove, moea_remove), 361 MMUMETHOD(mmu_remove_all, moea_remove_all), 362 MMUMETHOD(mmu_remove_write, moea_remove_write), 363 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 364 MMUMETHOD(mmu_zero_page, moea_zero_page), 365 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 366 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 367 MMUMETHOD(mmu_activate, moea_activate), 368 MMUMETHOD(mmu_deactivate, moea_deactivate), 369 370 /* Internal interfaces */ 371 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 372 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 373 MMUMETHOD(mmu_mapdev, moea_mapdev), 374 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 375 MMUMETHOD(mmu_kextract, moea_kextract), 376 MMUMETHOD(mmu_kenter, moea_kenter), 377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378 379 { 0, 0 } 380}; 381 382static mmu_def_t oea_mmu = { 383 MMU_TYPE_OEA, 384 moea_methods, 385 0 386}; 387MMU_DEF(oea_mmu); 388 389static void 390tlbie(vm_offset_t va) 391{ 392 393 mtx_lock_spin(&tlbie_mtx); 394 __asm __volatile("tlbie %0" :: "r"(va)); 395 __asm __volatile("tlbsync"); 396 powerpc_sync(); 397 mtx_unlock_spin(&tlbie_mtx); 398} 399 400static void 401tlbia(void) 402{ 403 vm_offset_t va; 404 405 for (va = 0; va < 0x00040000; va += 0x00001000) { 406 __asm __volatile("tlbie %0" :: "r"(va)); 407 powerpc_sync(); 408 } 409 __asm __volatile("tlbsync"); 410 powerpc_sync(); 411} 412 413static __inline int 414va_to_sr(u_int *sr, vm_offset_t va) 415{ 416 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 417} 418 419static __inline u_int 420va_to_pteg(u_int sr, vm_offset_t addr) 421{ 422 u_int hash; 423 424 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 425 ADDR_PIDX_SHFT); 426 return (hash & moea_pteg_mask); 427} 428 429static __inline struct pvo_head * 430pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 431{ 432 struct vm_page *pg; 433 434 pg = PHYS_TO_VM_PAGE(pa); 435 436 if (pg_p != NULL) 437 *pg_p = pg; 438 439 if (pg == NULL) 440 return (&moea_pvo_unmanaged); 441 442 return (&pg->md.mdpg_pvoh); 443} 444 445static __inline struct pvo_head * 446vm_page_to_pvoh(vm_page_t m) 447{ 448 449 return (&m->md.mdpg_pvoh); 450} 451 452static __inline void 453moea_attr_clear(vm_page_t m, int ptebit) 454{ 455 456 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 457 m->md.mdpg_attrs &= ~ptebit; 458} 459 460static __inline int 461moea_attr_fetch(vm_page_t m) 462{ 463 464 return (m->md.mdpg_attrs); 465} 466 467static __inline void 468moea_attr_save(vm_page_t m, int ptebit) 469{ 470 471 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 472 m->md.mdpg_attrs |= ptebit; 473} 474 475static __inline int 476moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 477{ 478 if (pt->pte_hi == pvo_pt->pte_hi) 479 return (1); 480 481 return (0); 482} 483 484static __inline int 485moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 486{ 487 return (pt->pte_hi & ~PTE_VALID) == 488 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 489 ((va >> ADDR_API_SHFT) & PTE_API) | which); 490} 491 492static __inline void 493moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 494{ 495 496 mtx_assert(&moea_table_mutex, MA_OWNED); 497 498 /* 499 * Construct a PTE. Default to IMB initially. Valid bit only gets 500 * set when the real pte is set in memory. 501 * 502 * Note: Don't set the valid bit for correct operation of tlb update. 503 */ 504 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 505 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 506 pt->pte_lo = pte_lo; 507} 508 509static __inline void 510moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 511{ 512 513 mtx_assert(&moea_table_mutex, MA_OWNED); 514 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 515} 516 517static __inline void 518moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 519{ 520 521 mtx_assert(&moea_table_mutex, MA_OWNED); 522 523 /* 524 * As shown in Section 7.6.3.2.3 525 */ 526 pt->pte_lo &= ~ptebit; 527 tlbie(va); 528} 529 530static __inline void 531moea_pte_set(struct pte *pt, struct pte *pvo_pt) 532{ 533 534 mtx_assert(&moea_table_mutex, MA_OWNED); 535 pvo_pt->pte_hi |= PTE_VALID; 536 537 /* 538 * Update the PTE as defined in section 7.6.3.1. 539 * Note that the REF/CHG bits are from pvo_pt and thus should havce 540 * been saved so this routine can restore them (if desired). 541 */ 542 pt->pte_lo = pvo_pt->pte_lo; 543 powerpc_sync(); 544 pt->pte_hi = pvo_pt->pte_hi; 545 powerpc_sync(); 546 moea_pte_valid++; 547} 548 549static __inline void 550moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 551{ 552 553 mtx_assert(&moea_table_mutex, MA_OWNED); 554 pvo_pt->pte_hi &= ~PTE_VALID; 555 556 /* 557 * Force the reg & chg bits back into the PTEs. 558 */ 559 powerpc_sync(); 560 561 /* 562 * Invalidate the pte. 563 */ 564 pt->pte_hi &= ~PTE_VALID; 565 566 tlbie(va); 567 568 /* 569 * Save the reg & chg bits. 570 */ 571 moea_pte_synch(pt, pvo_pt); 572 moea_pte_valid--; 573} 574 575static __inline void 576moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 577{ 578 579 /* 580 * Invalidate the PTE 581 */ 582 moea_pte_unset(pt, pvo_pt, va); 583 moea_pte_set(pt, pvo_pt); 584} 585 586/* 587 * Quick sort callout for comparing memory regions. 588 */ 589static int mr_cmp(const void *a, const void *b); 590static int om_cmp(const void *a, const void *b); 591 592static int 593mr_cmp(const void *a, const void *b) 594{ 595 const struct mem_region *regiona; 596 const struct mem_region *regionb; 597 598 regiona = a; 599 regionb = b; 600 if (regiona->mr_start < regionb->mr_start) 601 return (-1); 602 else if (regiona->mr_start > regionb->mr_start) 603 return (1); 604 else 605 return (0); 606} 607 608static int 609om_cmp(const void *a, const void *b) 610{ 611 const struct ofw_map *mapa; 612 const struct ofw_map *mapb; 613 614 mapa = a; 615 mapb = b; 616 if (mapa->om_pa < mapb->om_pa) 617 return (-1); 618 else if (mapa->om_pa > mapb->om_pa) 619 return (1); 620 else 621 return (0); 622} 623 624void 625moea_cpu_bootstrap(mmu_t mmup, int ap) 626{ 627 u_int sdr; 628 int i; 629 630 if (ap) { 631 powerpc_sync(); 632 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 633 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 634 isync(); 635 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 636 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 637 isync(); 638 } 639 640 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 641 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 642 isync(); 643 644 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 645 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 646 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 647 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 648 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 649 isync(); 650 651 for (i = 0; i < 16; i++) 652 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 653 654 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 655 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 656 powerpc_sync(); 657 658 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 659 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 660 isync(); 661 662 tlbia(); 663} 664 665void 666moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 667{ 668 ihandle_t mmui; 669 phandle_t chosen, mmu; 670 int sz; 671 int i, j; 672 int ofw_mappings; 673 vm_size_t size, physsz, hwphyssz; 674 vm_offset_t pa, va, off; 675 void *dpcpu; 676 register_t msr; 677 678 /* 679 * Set up BAT0 to map the lowest 256 MB area 680 */ 681 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 682 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 683 684 /* 685 * Map PCI memory space. 686 */ 687 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 689 690 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 692 693 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 694 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 695 696 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 697 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 698 699 /* 700 * Map obio devices. 701 */ 702 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 703 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 704 705 /* 706 * Use an IBAT and a DBAT to map the bottom segment of memory 707 * where we are. Turn off instruction relocation temporarily 708 * to prevent faults while reprogramming the IBAT. 709 */ 710 msr = mfmsr(); 711 mtmsr(msr & ~PSL_IR); 712 __asm (".balign 32; \n" 713 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 714 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 715 :: "r"(battable[0].batu), "r"(battable[0].batl)); 716 mtmsr(msr); 717 718 /* map pci space */ 719 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 720 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 721 isync(); 722 723 /* set global direct map flag */ 724 hw_direct_map = 1; 725 726 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 727 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 728 729 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 730 for (i = 0; i < pregions_sz; i++) { 731 vm_offset_t pa; 732 vm_offset_t end; 733 734 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 735 pregions[i].mr_start, 736 pregions[i].mr_start + pregions[i].mr_size, 737 pregions[i].mr_size); 738 /* 739 * Install entries into the BAT table to allow all 740 * of physmem to be convered by on-demand BAT entries. 741 * The loop will sometimes set the same battable element 742 * twice, but that's fine since they won't be used for 743 * a while yet. 744 */ 745 pa = pregions[i].mr_start & 0xf0000000; 746 end = pregions[i].mr_start + pregions[i].mr_size; 747 do { 748 u_int n = pa >> ADDR_SR_SHFT; 749 750 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 751 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 752 pa += SEGMENT_LENGTH; 753 } while (pa < end); 754 } 755 756 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 757 panic("moea_bootstrap: phys_avail too small"); 758 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 759 phys_avail_count = 0; 760 physsz = 0; 761 hwphyssz = 0; 762 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 763 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 764 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 765 regions[i].mr_start + regions[i].mr_size, 766 regions[i].mr_size); 767 if (hwphyssz != 0 && 768 (physsz + regions[i].mr_size) >= hwphyssz) { 769 if (physsz < hwphyssz) { 770 phys_avail[j] = regions[i].mr_start; 771 phys_avail[j + 1] = regions[i].mr_start + 772 hwphyssz - physsz; 773 physsz = hwphyssz; 774 phys_avail_count++; 775 } 776 break; 777 } 778 phys_avail[j] = regions[i].mr_start; 779 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 780 phys_avail_count++; 781 physsz += regions[i].mr_size; 782 } 783 physmem = btoc(physsz); 784 785 /* 786 * Allocate PTEG table. 787 */ 788#ifdef PTEGCOUNT 789 moea_pteg_count = PTEGCOUNT; 790#else 791 moea_pteg_count = 0x1000; 792 793 while (moea_pteg_count < physmem) 794 moea_pteg_count <<= 1; 795 796 moea_pteg_count >>= 1; 797#endif /* PTEGCOUNT */ 798 799 size = moea_pteg_count * sizeof(struct pteg); 800 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 801 size); 802 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 803 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 804 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 805 moea_pteg_mask = moea_pteg_count - 1; 806 807 /* 808 * Allocate pv/overflow lists. 809 */ 810 size = sizeof(struct pvo_head) * moea_pteg_count; 811 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 812 PAGE_SIZE); 813 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 814 for (i = 0; i < moea_pteg_count; i++) 815 LIST_INIT(&moea_pvo_table[i]); 816 817 /* 818 * Initialize the lock that synchronizes access to the pteg and pvo 819 * tables. 820 */ 821 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 822 MTX_RECURSE); 823 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 824 825 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 826 827 /* 828 * Initialise the unmanaged pvo pool. 829 */ 830 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 831 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 832 moea_bpvo_pool_index = 0; 833 834 /* 835 * Make sure kernel vsid is allocated as well as VSID 0. 836 */ 837 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 838 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 839 moea_vsid_bitmap[0] |= 1; 840 841 /* 842 * Set up the Open Firmware pmap and add it's mappings. 843 */ 844 moea_pinit(mmup, &ofw_pmap); 845 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 846 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 847 if ((chosen = OF_finddevice("/chosen")) == -1) 848 panic("moea_bootstrap: can't find /chosen"); 849 OF_getprop(chosen, "mmu", &mmui, 4); 850 if ((mmu = OF_instance_to_package(mmui)) == -1) 851 panic("moea_bootstrap: can't get mmu package"); 852 if ((sz = OF_getproplen(mmu, "translations")) == -1) 853 panic("moea_bootstrap: can't get ofw translation count"); 854 translations = NULL; 855 for (i = 0; phys_avail[i] != 0; i += 2) { 856 if (phys_avail[i + 1] >= sz) { 857 translations = (struct ofw_map *)phys_avail[i]; 858 break; 859 } 860 } 861 if (translations == NULL) 862 panic("moea_bootstrap: no space to copy translations"); 863 bzero(translations, sz); 864 if (OF_getprop(mmu, "translations", translations, sz) == -1) 865 panic("moea_bootstrap: can't get ofw translations"); 866 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 867 sz /= sizeof(*translations); 868 qsort(translations, sz, sizeof (*translations), om_cmp); 869 for (i = 0, ofw_mappings = 0; i < sz; i++) { 870 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 871 translations[i].om_pa, translations[i].om_va, 872 translations[i].om_len); 873 874 /* 875 * If the mapping is 1:1, let the RAM and device on-demand 876 * BAT tables take care of the translation. 877 */ 878 if (translations[i].om_va == translations[i].om_pa) 879 continue; 880 881 /* Enter the pages */ 882 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 883 struct vm_page m; 884 885 m.phys_addr = translations[i].om_pa + off; 886 m.oflags = VPO_BUSY; 887 PMAP_LOCK(&ofw_pmap); 888 moea_enter_locked(&ofw_pmap, 889 translations[i].om_va + off, &m, 890 VM_PROT_ALL, 1); 891 PMAP_UNLOCK(&ofw_pmap); 892 ofw_mappings++; 893 } 894 } 895 896 /* 897 * Calculate the last available physical address. 898 */ 899 for (i = 0; phys_avail[i + 2] != 0; i += 2) 900 ; 901 Maxmem = powerpc_btop(phys_avail[i + 1]); 902 903 /* 904 * Initialize the kernel pmap (which is statically allocated). 905 */ 906 PMAP_LOCK_INIT(kernel_pmap); 907 for (i = 0; i < 16; i++) { 908 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 909 } 910 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 911 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 912 kernel_pmap->pm_active = ~0; 913 914 moea_cpu_bootstrap(mmup,0); 915 916 pmap_bootstrapped++; 917 918 /* 919 * Set the start and end of kva. 920 */ 921 virtual_avail = VM_MIN_KERNEL_ADDRESS; 922 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 923 924 /* 925 * Allocate a kernel stack with a guard page for thread0 and map it 926 * into the kernel page map. 927 */ 928 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 929 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 930 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 931 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 932 thread0.td_kstack = va; 933 thread0.td_kstack_pages = KSTACK_PAGES; 934 for (i = 0; i < KSTACK_PAGES; i++) { 935 moea_kenter(mmup, va, pa); 936 pa += PAGE_SIZE; 937 va += PAGE_SIZE; 938 } 939 940 /* 941 * Allocate virtual address space for the message buffer. 942 */ 943 pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 944 msgbufp = (struct msgbuf *)virtual_avail; 945 va = virtual_avail; 946 virtual_avail += round_page(MSGBUF_SIZE); 947 while (va < virtual_avail) { 948 moea_kenter(mmup, va, pa); 949 pa += PAGE_SIZE; 950 va += PAGE_SIZE; 951 } 952 953 /* 954 * Allocate virtual address space for the dynamic percpu area. 955 */ 956 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 957 dpcpu = (void *)virtual_avail; 958 va = virtual_avail; 959 virtual_avail += DPCPU_SIZE; 960 while (va < virtual_avail) { 961 moea_kenter(mmup, va, pa); 962 pa += PAGE_SIZE; 963 va += PAGE_SIZE; 964 } 965 dpcpu_init(dpcpu, 0); 966} 967 968/* 969 * Activate a user pmap. The pmap must be activated before it's address 970 * space can be accessed in any way. 971 */ 972void 973moea_activate(mmu_t mmu, struct thread *td) 974{ 975 pmap_t pm, pmr; 976 977 /* 978 * Load all the data we need up front to encourage the compiler to 979 * not issue any loads while we have interrupts disabled below. 980 */ 981 pm = &td->td_proc->p_vmspace->vm_pmap; 982 pmr = pm->pmap_phys; 983 984 pm->pm_active |= PCPU_GET(cpumask); 985 PCPU_SET(curpmap, pmr); 986} 987 988void 989moea_deactivate(mmu_t mmu, struct thread *td) 990{ 991 pmap_t pm; 992 993 pm = &td->td_proc->p_vmspace->vm_pmap; 994 pm->pm_active &= ~PCPU_GET(cpumask); 995 PCPU_SET(curpmap, NULL); 996} 997 998void 999moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 1000{ 1001 struct pvo_entry *pvo; 1002 1003 PMAP_LOCK(pm); 1004 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1005 1006 if (pvo != NULL) { 1007 if (wired) { 1008 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1009 pm->pm_stats.wired_count++; 1010 pvo->pvo_vaddr |= PVO_WIRED; 1011 } else { 1012 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1013 pm->pm_stats.wired_count--; 1014 pvo->pvo_vaddr &= ~PVO_WIRED; 1015 } 1016 } 1017 PMAP_UNLOCK(pm); 1018} 1019 1020void 1021moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1022{ 1023 vm_offset_t dst; 1024 vm_offset_t src; 1025 1026 dst = VM_PAGE_TO_PHYS(mdst); 1027 src = VM_PAGE_TO_PHYS(msrc); 1028 1029 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1030} 1031 1032/* 1033 * Zero a page of physical memory by temporarily mapping it into the tlb. 1034 */ 1035void 1036moea_zero_page(mmu_t mmu, vm_page_t m) 1037{ 1038 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1039 void *va = (void *)pa; 1040 1041 bzero(va, PAGE_SIZE); 1042} 1043 1044void 1045moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1046{ 1047 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1048 void *va = (void *)(pa + off); 1049 1050 bzero(va, size); 1051} 1052 1053void 1054moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1055{ 1056 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1057 void *va = (void *)pa; 1058 1059 bzero(va, PAGE_SIZE); 1060} 1061 1062/* 1063 * Map the given physical page at the specified virtual address in the 1064 * target pmap with the protection requested. If specified the page 1065 * will be wired down. 1066 */ 1067void 1068moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1069 boolean_t wired) 1070{ 1071 1072 vm_page_lock_queues(); 1073 PMAP_LOCK(pmap); 1074 moea_enter_locked(pmap, va, m, prot, wired); 1075 vm_page_unlock_queues(); 1076 PMAP_UNLOCK(pmap); 1077} 1078 1079/* 1080 * Map the given physical page at the specified virtual address in the 1081 * target pmap with the protection requested. If specified the page 1082 * will be wired down. 1083 * 1084 * The page queues and pmap must be locked. 1085 */ 1086static void 1087moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1088 boolean_t wired) 1089{ 1090 struct pvo_head *pvo_head; 1091 uma_zone_t zone; 1092 vm_page_t pg; 1093 u_int pte_lo, pvo_flags, was_exec, i; 1094 int error; 1095 1096 if (!moea_initialized) { 1097 pvo_head = &moea_pvo_kunmanaged; 1098 zone = moea_upvo_zone; 1099 pvo_flags = 0; 1100 pg = NULL; 1101 was_exec = PTE_EXEC; 1102 } else { 1103 pvo_head = vm_page_to_pvoh(m); 1104 pg = m; 1105 zone = moea_mpvo_zone; 1106 pvo_flags = PVO_MANAGED; 1107 was_exec = 0; 1108 } 1109 if (pmap_bootstrapped) 1110 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1111 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1112 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1113 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1114 ("moea_enter_locked: page %p is not busy", m)); 1115 1116 /* XXX change the pvo head for fake pages */ 1117 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1118 pvo_flags &= ~PVO_MANAGED; 1119 pvo_head = &moea_pvo_kunmanaged; 1120 zone = moea_upvo_zone; 1121 } 1122 1123 /* 1124 * If this is a managed page, and it's the first reference to the page, 1125 * clear the execness of the page. Otherwise fetch the execness. 1126 */ 1127 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1128 if (LIST_EMPTY(pvo_head)) { 1129 moea_attr_clear(pg, PTE_EXEC); 1130 } else { 1131 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1132 } 1133 } 1134 1135 /* 1136 * Assume the page is cache inhibited and access is guarded unless 1137 * it's in our available memory array. 1138 */ 1139 pte_lo = PTE_I | PTE_G; 1140 for (i = 0; i < pregions_sz; i++) { 1141 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1142 (VM_PAGE_TO_PHYS(m) < 1143 (pregions[i].mr_start + pregions[i].mr_size))) { 1144 pte_lo = PTE_M; 1145 break; 1146 } 1147 } 1148 1149 if (prot & VM_PROT_WRITE) { 1150 pte_lo |= PTE_BW; 1151 if (pmap_bootstrapped && 1152 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1153 vm_page_flag_set(m, PG_WRITEABLE); 1154 } else 1155 pte_lo |= PTE_BR; 1156 1157 if (prot & VM_PROT_EXECUTE) 1158 pvo_flags |= PVO_EXECUTABLE; 1159 1160 if (wired) 1161 pvo_flags |= PVO_WIRED; 1162 1163 if ((m->flags & PG_FICTITIOUS) != 0) 1164 pvo_flags |= PVO_FAKE; 1165 1166 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1167 pte_lo, pvo_flags); 1168 1169 /* 1170 * Flush the real page from the instruction cache if this page is 1171 * mapped executable and cacheable and was not previously mapped (or 1172 * was not mapped executable). 1173 */ 1174 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1175 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1176 /* 1177 * Flush the real memory from the cache. 1178 */ 1179 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1180 if (pg != NULL) 1181 moea_attr_save(pg, PTE_EXEC); 1182 } 1183 1184 /* XXX syncicache always until problems are sorted */ 1185 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1186} 1187 1188/* 1189 * Maps a sequence of resident pages belonging to the same object. 1190 * The sequence begins with the given page m_start. This page is 1191 * mapped at the given virtual address start. Each subsequent page is 1192 * mapped at a virtual address that is offset from start by the same 1193 * amount as the page is offset from m_start within the object. The 1194 * last page in the sequence is the page with the largest offset from 1195 * m_start that can be mapped at a virtual address less than the given 1196 * virtual address end. Not every virtual page between start and end 1197 * is mapped; only those for which a resident page exists with the 1198 * corresponding offset from m_start are mapped. 1199 */ 1200void 1201moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1202 vm_page_t m_start, vm_prot_t prot) 1203{ 1204 vm_page_t m; 1205 vm_pindex_t diff, psize; 1206 1207 psize = atop(end - start); 1208 m = m_start; 1209 vm_page_lock_queues(); 1210 PMAP_LOCK(pm); 1211 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1212 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1213 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1214 m = TAILQ_NEXT(m, listq); 1215 } 1216 vm_page_unlock_queues(); 1217 PMAP_UNLOCK(pm); 1218} 1219 1220void 1221moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1222 vm_prot_t prot) 1223{ 1224 1225 vm_page_lock_queues(); 1226 PMAP_LOCK(pm); 1227 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1228 FALSE); 1229 vm_page_unlock_queues(); 1230 PMAP_UNLOCK(pm); 1231} 1232 1233vm_paddr_t 1234moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1235{ 1236 struct pvo_entry *pvo; 1237 vm_paddr_t pa; 1238 1239 PMAP_LOCK(pm); 1240 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1241 if (pvo == NULL) 1242 pa = 0; 1243 else 1244 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1245 PMAP_UNLOCK(pm); 1246 return (pa); 1247} 1248 1249/* 1250 * Atomically extract and hold the physical page with the given 1251 * pmap and virtual address pair if that mapping permits the given 1252 * protection. 1253 */ 1254vm_page_t 1255moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1256{ 1257 struct pvo_entry *pvo; 1258 vm_page_t m; 1259 vm_paddr_t pa; 1260 1261 m = NULL; 1262 pa = 0; 1263 PMAP_LOCK(pmap); 1264retry: 1265 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1266 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1267 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1268 (prot & VM_PROT_WRITE) == 0)) { 1269 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1270 goto retry; 1271 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1272 vm_page_hold(m); 1273 } 1274 PA_UNLOCK_COND(pa); 1275 PMAP_UNLOCK(pmap); 1276 return (m); 1277} 1278 1279void 1280moea_init(mmu_t mmu) 1281{ 1282 1283 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1284 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1285 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1286 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1287 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1288 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1289 moea_initialized = TRUE; 1290} 1291 1292boolean_t 1293moea_is_referenced(mmu_t mmu, vm_page_t m) 1294{ 1295 1296 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1297 ("moea_is_referenced: page %p is not managed", m)); 1298 return (moea_query_bit(m, PTE_REF)); 1299} 1300 1301boolean_t 1302moea_is_modified(mmu_t mmu, vm_page_t m) 1303{ 1304 1305 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1306 ("moea_is_modified: page %p is not managed", m)); 1307 1308 /* 1309 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1310 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1311 * is clear, no PTEs can have PTE_CHG set. 1312 */ 1313 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1314 if ((m->oflags & VPO_BUSY) == 0 && 1315 (m->flags & PG_WRITEABLE) == 0) 1316 return (FALSE); 1317 return (moea_query_bit(m, PTE_CHG)); 1318} 1319 1320void 1321moea_clear_reference(mmu_t mmu, vm_page_t m) 1322{ 1323 1324 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1325 ("moea_clear_reference: page %p is not managed", m)); 1326 moea_clear_bit(m, PTE_REF); 1327} 1328 1329void 1330moea_clear_modify(mmu_t mmu, vm_page_t m) 1331{ 1332 1333 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1334 ("moea_clear_modify: page %p is not managed", m)); 1335 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1336 KASSERT((m->oflags & VPO_BUSY) == 0, 1337 ("moea_clear_modify: page %p is busy", m)); 1338 1339 /* 1340 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1341 * set. If the object containing the page is locked and the page is 1342 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1343 */ 1344 if ((m->flags & PG_WRITEABLE) == 0) 1345 return; 1346 moea_clear_bit(m, PTE_CHG); 1347} 1348 1349/* 1350 * Clear the write and modified bits in each of the given page's mappings. 1351 */ 1352void 1353moea_remove_write(mmu_t mmu, vm_page_t m) 1354{ 1355 struct pvo_entry *pvo; 1356 struct pte *pt; 1357 pmap_t pmap; 1358 u_int lo; 1359 1360 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1361 ("moea_remove_write: page %p is not managed", m)); 1362 1363 /* 1364 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1365 * another thread while the object is locked. Thus, if PG_WRITEABLE 1366 * is clear, no page table entries need updating. 1367 */ 1368 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1369 if ((m->oflags & VPO_BUSY) == 0 && 1370 (m->flags & PG_WRITEABLE) == 0) 1371 return; 1372 vm_page_lock_queues(); 1373 lo = moea_attr_fetch(m); 1374 powerpc_sync(); 1375 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1376 pmap = pvo->pvo_pmap; 1377 PMAP_LOCK(pmap); 1378 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1379 pt = moea_pvo_to_pte(pvo, -1); 1380 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1381 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1382 if (pt != NULL) { 1383 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1384 lo |= pvo->pvo_pte.pte.pte_lo; 1385 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1386 moea_pte_change(pt, &pvo->pvo_pte.pte, 1387 pvo->pvo_vaddr); 1388 mtx_unlock(&moea_table_mutex); 1389 } 1390 } 1391 PMAP_UNLOCK(pmap); 1392 } 1393 if ((lo & PTE_CHG) != 0) { 1394 moea_attr_clear(m, PTE_CHG); 1395 vm_page_dirty(m); 1396 } 1397 vm_page_flag_clear(m, PG_WRITEABLE); 1398 vm_page_unlock_queues(); 1399} 1400 1401/* 1402 * moea_ts_referenced: 1403 * 1404 * Return a count of reference bits for a page, clearing those bits. 1405 * It is not necessary for every reference bit to be cleared, but it 1406 * is necessary that 0 only be returned when there are truly no 1407 * reference bits set. 1408 * 1409 * XXX: The exact number of bits to check and clear is a matter that 1410 * should be tested and standardized at some point in the future for 1411 * optimal aging of shared pages. 1412 */ 1413boolean_t 1414moea_ts_referenced(mmu_t mmu, vm_page_t m) 1415{ 1416 1417 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1418 ("moea_ts_referenced: page %p is not managed", m)); 1419 return (moea_clear_bit(m, PTE_REF)); 1420} 1421 1422/* 1423 * Map a wired page into kernel virtual address space. 1424 */ 1425void 1426moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1427{ 1428 u_int pte_lo; 1429 int error; 1430 int i; 1431 1432#if 0 1433 if (va < VM_MIN_KERNEL_ADDRESS) 1434 panic("moea_kenter: attempt to enter non-kernel address %#x", 1435 va); 1436#endif 1437 1438 pte_lo = PTE_I | PTE_G; 1439 for (i = 0; i < pregions_sz; i++) { 1440 if ((pa >= pregions[i].mr_start) && 1441 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1442 pte_lo = PTE_M; 1443 break; 1444 } 1445 } 1446 1447 PMAP_LOCK(kernel_pmap); 1448 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1449 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1450 1451 if (error != 0 && error != ENOENT) 1452 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1453 pa, error); 1454 1455 /* 1456 * Flush the real memory from the instruction cache. 1457 */ 1458 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1459 moea_syncicache(pa, PAGE_SIZE); 1460 } 1461 PMAP_UNLOCK(kernel_pmap); 1462} 1463 1464/* 1465 * Extract the physical page address associated with the given kernel virtual 1466 * address. 1467 */ 1468vm_offset_t 1469moea_kextract(mmu_t mmu, vm_offset_t va) 1470{ 1471 struct pvo_entry *pvo; 1472 vm_paddr_t pa; 1473 1474 /* 1475 * Allow direct mappings on 32-bit OEA 1476 */ 1477 if (va < VM_MIN_KERNEL_ADDRESS) { 1478 return (va); 1479 } 1480 1481 PMAP_LOCK(kernel_pmap); 1482 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1483 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1484 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1485 PMAP_UNLOCK(kernel_pmap); 1486 return (pa); 1487} 1488 1489/* 1490 * Remove a wired page from kernel virtual address space. 1491 */ 1492void 1493moea_kremove(mmu_t mmu, vm_offset_t va) 1494{ 1495 1496 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1497} 1498 1499/* 1500 * Map a range of physical addresses into kernel virtual address space. 1501 * 1502 * The value passed in *virt is a suggested virtual address for the mapping. 1503 * Architectures which can support a direct-mapped physical to virtual region 1504 * can return the appropriate address within that region, leaving '*virt' 1505 * unchanged. We cannot and therefore do not; *virt is updated with the 1506 * first usable address after the mapped region. 1507 */ 1508vm_offset_t 1509moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1510 vm_offset_t pa_end, int prot) 1511{ 1512 vm_offset_t sva, va; 1513 1514 sva = *virt; 1515 va = sva; 1516 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1517 moea_kenter(mmu, va, pa_start); 1518 *virt = va; 1519 return (sva); 1520} 1521 1522/* 1523 * Returns true if the pmap's pv is one of the first 1524 * 16 pvs linked to from this page. This count may 1525 * be changed upwards or downwards in the future; it 1526 * is only necessary that true be returned for a small 1527 * subset of pmaps for proper page aging. 1528 */ 1529boolean_t 1530moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1531{ 1532 int loops; 1533 struct pvo_entry *pvo; 1534 boolean_t rv; 1535 1536 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1537 ("moea_page_exists_quick: page %p is not managed", m)); 1538 loops = 0; 1539 rv = FALSE; 1540 vm_page_lock_queues(); 1541 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1542 if (pvo->pvo_pmap == pmap) { 1543 rv = TRUE; 1544 break; 1545 } 1546 if (++loops >= 16) 1547 break; 1548 } 1549 vm_page_unlock_queues(); 1550 return (rv); 1551} 1552 1553/* 1554 * Return the number of managed mappings to the given physical page 1555 * that are wired. 1556 */ 1557int 1558moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1559{ 1560 struct pvo_entry *pvo; 1561 int count; 1562 1563 count = 0; 1564 if ((m->flags & PG_FICTITIOUS) != 0) 1565 return (count); 1566 vm_page_lock_queues(); 1567 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1568 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1569 count++; 1570 vm_page_unlock_queues(); 1571 return (count); 1572} 1573 1574static u_int moea_vsidcontext; 1575 1576void 1577moea_pinit(mmu_t mmu, pmap_t pmap) 1578{ 1579 int i, mask; 1580 u_int entropy; 1581 1582 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1583 PMAP_LOCK_INIT(pmap); 1584 1585 entropy = 0; 1586 __asm __volatile("mftb %0" : "=r"(entropy)); 1587 1588 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1589 == NULL) { 1590 pmap->pmap_phys = pmap; 1591 } 1592 1593 1594 mtx_lock(&moea_vsid_mutex); 1595 /* 1596 * Allocate some segment registers for this pmap. 1597 */ 1598 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1599 u_int hash, n; 1600 1601 /* 1602 * Create a new value by mutiplying by a prime and adding in 1603 * entropy from the timebase register. This is to make the 1604 * VSID more random so that the PT hash function collides 1605 * less often. (Note that the prime casues gcc to do shifts 1606 * instead of a multiply.) 1607 */ 1608 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1609 hash = moea_vsidcontext & (NPMAPS - 1); 1610 if (hash == 0) /* 0 is special, avoid it */ 1611 continue; 1612 n = hash >> 5; 1613 mask = 1 << (hash & (VSID_NBPW - 1)); 1614 hash = (moea_vsidcontext & 0xfffff); 1615 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1616 /* anything free in this bucket? */ 1617 if (moea_vsid_bitmap[n] == 0xffffffff) { 1618 entropy = (moea_vsidcontext >> 20); 1619 continue; 1620 } 1621 i = ffs(~moea_vsid_bitmap[i]) - 1; 1622 mask = 1 << i; 1623 hash &= 0xfffff & ~(VSID_NBPW - 1); 1624 hash |= i; 1625 } 1626 moea_vsid_bitmap[n] |= mask; 1627 for (i = 0; i < 16; i++) 1628 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1629 mtx_unlock(&moea_vsid_mutex); 1630 return; 1631 } 1632 1633 mtx_unlock(&moea_vsid_mutex); 1634 panic("moea_pinit: out of segments"); 1635} 1636 1637/* 1638 * Initialize the pmap associated with process 0. 1639 */ 1640void 1641moea_pinit0(mmu_t mmu, pmap_t pm) 1642{ 1643 1644 moea_pinit(mmu, pm); 1645 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1646} 1647 1648/* 1649 * Set the physical protection on the specified range of this map as requested. 1650 */ 1651void 1652moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1653 vm_prot_t prot) 1654{ 1655 struct pvo_entry *pvo; 1656 struct pte *pt; 1657 int pteidx; 1658 1659 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1660 ("moea_protect: non current pmap")); 1661 1662 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1663 moea_remove(mmu, pm, sva, eva); 1664 return; 1665 } 1666 1667 vm_page_lock_queues(); 1668 PMAP_LOCK(pm); 1669 for (; sva < eva; sva += PAGE_SIZE) { 1670 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1671 if (pvo == NULL) 1672 continue; 1673 1674 if ((prot & VM_PROT_EXECUTE) == 0) 1675 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1676 1677 /* 1678 * Grab the PTE pointer before we diddle with the cached PTE 1679 * copy. 1680 */ 1681 pt = moea_pvo_to_pte(pvo, pteidx); 1682 /* 1683 * Change the protection of the page. 1684 */ 1685 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1686 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1687 1688 /* 1689 * If the PVO is in the page table, update that pte as well. 1690 */ 1691 if (pt != NULL) { 1692 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1693 mtx_unlock(&moea_table_mutex); 1694 } 1695 } 1696 vm_page_unlock_queues(); 1697 PMAP_UNLOCK(pm); 1698} 1699 1700/* 1701 * Map a list of wired pages into kernel virtual address space. This is 1702 * intended for temporary mappings which do not need page modification or 1703 * references recorded. Existing mappings in the region are overwritten. 1704 */ 1705void 1706moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1707{ 1708 vm_offset_t va; 1709 1710 va = sva; 1711 while (count-- > 0) { 1712 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1713 va += PAGE_SIZE; 1714 m++; 1715 } 1716} 1717 1718/* 1719 * Remove page mappings from kernel virtual address space. Intended for 1720 * temporary mappings entered by moea_qenter. 1721 */ 1722void 1723moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1724{ 1725 vm_offset_t va; 1726 1727 va = sva; 1728 while (count-- > 0) { 1729 moea_kremove(mmu, va); 1730 va += PAGE_SIZE; 1731 } 1732} 1733 1734void 1735moea_release(mmu_t mmu, pmap_t pmap) 1736{ 1737 int idx, mask; 1738 1739 /* 1740 * Free segment register's VSID 1741 */ 1742 if (pmap->pm_sr[0] == 0) 1743 panic("moea_release"); 1744 1745 mtx_lock(&moea_vsid_mutex); 1746 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1747 mask = 1 << (idx % VSID_NBPW); 1748 idx /= VSID_NBPW; 1749 moea_vsid_bitmap[idx] &= ~mask; 1750 mtx_unlock(&moea_vsid_mutex); 1751 PMAP_LOCK_DESTROY(pmap); 1752} 1753 1754/* 1755 * Remove the given range of addresses from the specified map. 1756 */ 1757void 1758moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1759{ 1760 struct pvo_entry *pvo; 1761 int pteidx; 1762 1763 vm_page_lock_queues(); 1764 PMAP_LOCK(pm); 1765 for (; sva < eva; sva += PAGE_SIZE) { 1766 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1767 if (pvo != NULL) { 1768 moea_pvo_remove(pvo, pteidx); 1769 } 1770 } 1771 PMAP_UNLOCK(pm); 1772 vm_page_unlock_queues(); 1773} 1774 1775/* 1776 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1777 * will reflect changes in pte's back to the vm_page. 1778 */ 1779void 1780moea_remove_all(mmu_t mmu, vm_page_t m) 1781{ 1782 struct pvo_head *pvo_head; 1783 struct pvo_entry *pvo, *next_pvo; 1784 pmap_t pmap; 1785 1786 vm_page_lock_queues(); 1787 pvo_head = vm_page_to_pvoh(m); 1788 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1789 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1790 1791 MOEA_PVO_CHECK(pvo); /* sanity check */ 1792 pmap = pvo->pvo_pmap; 1793 PMAP_LOCK(pmap); 1794 moea_pvo_remove(pvo, -1); 1795 PMAP_UNLOCK(pmap); 1796 } 1797 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1798 moea_attr_clear(m, PTE_CHG); 1799 vm_page_dirty(m); 1800 } 1801 vm_page_flag_clear(m, PG_WRITEABLE); 1802 vm_page_unlock_queues(); 1803} 1804 1805/* 1806 * Allocate a physical page of memory directly from the phys_avail map. 1807 * Can only be called from moea_bootstrap before avail start and end are 1808 * calculated. 1809 */ 1810static vm_offset_t 1811moea_bootstrap_alloc(vm_size_t size, u_int align) 1812{ 1813 vm_offset_t s, e; 1814 int i, j; 1815 1816 size = round_page(size); 1817 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1818 if (align != 0) 1819 s = (phys_avail[i] + align - 1) & ~(align - 1); 1820 else 1821 s = phys_avail[i]; 1822 e = s + size; 1823 1824 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1825 continue; 1826 1827 if (s == phys_avail[i]) { 1828 phys_avail[i] += size; 1829 } else if (e == phys_avail[i + 1]) { 1830 phys_avail[i + 1] -= size; 1831 } else { 1832 for (j = phys_avail_count * 2; j > i; j -= 2) { 1833 phys_avail[j] = phys_avail[j - 2]; 1834 phys_avail[j + 1] = phys_avail[j - 1]; 1835 } 1836 1837 phys_avail[i + 3] = phys_avail[i + 1]; 1838 phys_avail[i + 1] = s; 1839 phys_avail[i + 2] = e; 1840 phys_avail_count++; 1841 } 1842 1843 return (s); 1844 } 1845 panic("moea_bootstrap_alloc: could not allocate memory"); 1846} 1847 1848static void 1849moea_syncicache(vm_offset_t pa, vm_size_t len) 1850{ 1851 __syncicache((void *)pa, len); 1852} 1853 1854static int 1855moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1856 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1857{ 1858 struct pvo_entry *pvo; 1859 u_int sr; 1860 int first; 1861 u_int ptegidx; 1862 int i; 1863 int bootstrap; 1864 1865 moea_pvo_enter_calls++; 1866 first = 0; 1867 bootstrap = 0; 1868 1869 /* 1870 * Compute the PTE Group index. 1871 */ 1872 va &= ~ADDR_POFF; 1873 sr = va_to_sr(pm->pm_sr, va); 1874 ptegidx = va_to_pteg(sr, va); 1875 1876 /* 1877 * Remove any existing mapping for this page. Reuse the pvo entry if 1878 * there is a mapping. 1879 */ 1880 mtx_lock(&moea_table_mutex); 1881 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1882 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1883 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1884 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1885 (pte_lo & PTE_PP)) { 1886 mtx_unlock(&moea_table_mutex); 1887 return (0); 1888 } 1889 moea_pvo_remove(pvo, -1); 1890 break; 1891 } 1892 } 1893 1894 /* 1895 * If we aren't overwriting a mapping, try to allocate. 1896 */ 1897 if (moea_initialized) { 1898 pvo = uma_zalloc(zone, M_NOWAIT); 1899 } else { 1900 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1901 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1902 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1903 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1904 } 1905 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1906 moea_bpvo_pool_index++; 1907 bootstrap = 1; 1908 } 1909 1910 if (pvo == NULL) { 1911 mtx_unlock(&moea_table_mutex); 1912 return (ENOMEM); 1913 } 1914 1915 moea_pvo_entries++; 1916 pvo->pvo_vaddr = va; 1917 pvo->pvo_pmap = pm; 1918 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1919 pvo->pvo_vaddr &= ~ADDR_POFF; 1920 if (flags & VM_PROT_EXECUTE) 1921 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1922 if (flags & PVO_WIRED) 1923 pvo->pvo_vaddr |= PVO_WIRED; 1924 if (pvo_head != &moea_pvo_kunmanaged) 1925 pvo->pvo_vaddr |= PVO_MANAGED; 1926 if (bootstrap) 1927 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1928 if (flags & PVO_FAKE) 1929 pvo->pvo_vaddr |= PVO_FAKE; 1930 1931 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1932 1933 /* 1934 * Remember if the list was empty and therefore will be the first 1935 * item. 1936 */ 1937 if (LIST_FIRST(pvo_head) == NULL) 1938 first = 1; 1939 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1940 1941 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1942 pm->pm_stats.wired_count++; 1943 pm->pm_stats.resident_count++; 1944 1945 /* 1946 * We hope this succeeds but it isn't required. 1947 */ 1948 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1949 if (i >= 0) { 1950 PVO_PTEGIDX_SET(pvo, i); 1951 } else { 1952 panic("moea_pvo_enter: overflow"); 1953 moea_pte_overflow++; 1954 } 1955 mtx_unlock(&moea_table_mutex); 1956 1957 return (first ? ENOENT : 0); 1958} 1959 1960static void 1961moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1962{ 1963 struct pte *pt; 1964 1965 /* 1966 * If there is an active pte entry, we need to deactivate it (and 1967 * save the ref & cfg bits). 1968 */ 1969 pt = moea_pvo_to_pte(pvo, pteidx); 1970 if (pt != NULL) { 1971 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1972 mtx_unlock(&moea_table_mutex); 1973 PVO_PTEGIDX_CLR(pvo); 1974 } else { 1975 moea_pte_overflow--; 1976 } 1977 1978 /* 1979 * Update our statistics. 1980 */ 1981 pvo->pvo_pmap->pm_stats.resident_count--; 1982 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1983 pvo->pvo_pmap->pm_stats.wired_count--; 1984 1985 /* 1986 * Save the REF/CHG bits into their cache if the page is managed. 1987 */ 1988 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 1989 struct vm_page *pg; 1990 1991 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1992 if (pg != NULL) { 1993 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 1994 (PTE_REF | PTE_CHG)); 1995 } 1996 } 1997 1998 /* 1999 * Remove this PVO from the PV list. 2000 */ 2001 LIST_REMOVE(pvo, pvo_vlink); 2002 2003 /* 2004 * Remove this from the overflow list and return it to the pool 2005 * if we aren't going to reuse it. 2006 */ 2007 LIST_REMOVE(pvo, pvo_olink); 2008 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2009 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2010 moea_upvo_zone, pvo); 2011 moea_pvo_entries--; 2012 moea_pvo_remove_calls++; 2013} 2014 2015static __inline int 2016moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2017{ 2018 int pteidx; 2019 2020 /* 2021 * We can find the actual pte entry without searching by grabbing 2022 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2023 * noticing the HID bit. 2024 */ 2025 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2026 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2027 pteidx ^= moea_pteg_mask * 8; 2028 2029 return (pteidx); 2030} 2031 2032static struct pvo_entry * 2033moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2034{ 2035 struct pvo_entry *pvo; 2036 int ptegidx; 2037 u_int sr; 2038 2039 va &= ~ADDR_POFF; 2040 sr = va_to_sr(pm->pm_sr, va); 2041 ptegidx = va_to_pteg(sr, va); 2042 2043 mtx_lock(&moea_table_mutex); 2044 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2045 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2046 if (pteidx_p) 2047 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2048 break; 2049 } 2050 } 2051 mtx_unlock(&moea_table_mutex); 2052 2053 return (pvo); 2054} 2055 2056static struct pte * 2057moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2058{ 2059 struct pte *pt; 2060 2061 /* 2062 * If we haven't been supplied the ptegidx, calculate it. 2063 */ 2064 if (pteidx == -1) { 2065 int ptegidx; 2066 u_int sr; 2067 2068 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2069 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2070 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2071 } 2072 2073 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2074 mtx_lock(&moea_table_mutex); 2075 2076 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2077 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2078 "valid pte index", pvo); 2079 } 2080 2081 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2082 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2083 "pvo but no valid pte", pvo); 2084 } 2085 2086 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2087 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2088 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2089 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2090 } 2091 2092 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2093 != 0) { 2094 panic("moea_pvo_to_pte: pvo %p pte does not match " 2095 "pte %p in moea_pteg_table", pvo, pt); 2096 } 2097 2098 mtx_assert(&moea_table_mutex, MA_OWNED); 2099 return (pt); 2100 } 2101 2102 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2103 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2104 "moea_pteg_table but valid in pvo", pvo, pt); 2105 } 2106 2107 mtx_unlock(&moea_table_mutex); 2108 return (NULL); 2109} 2110 2111/* 2112 * XXX: THIS STUFF SHOULD BE IN pte.c? 2113 */ 2114int 2115moea_pte_spill(vm_offset_t addr) 2116{ 2117 struct pvo_entry *source_pvo, *victim_pvo; 2118 struct pvo_entry *pvo; 2119 int ptegidx, i, j; 2120 u_int sr; 2121 struct pteg *pteg; 2122 struct pte *pt; 2123 2124 moea_pte_spills++; 2125 2126 sr = mfsrin(addr); 2127 ptegidx = va_to_pteg(sr, addr); 2128 2129 /* 2130 * Have to substitute some entry. Use the primary hash for this. 2131 * Use low bits of timebase as random generator. 2132 */ 2133 pteg = &moea_pteg_table[ptegidx]; 2134 mtx_lock(&moea_table_mutex); 2135 __asm __volatile("mftb %0" : "=r"(i)); 2136 i &= 7; 2137 pt = &pteg->pt[i]; 2138 2139 source_pvo = NULL; 2140 victim_pvo = NULL; 2141 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2142 /* 2143 * We need to find a pvo entry for this address. 2144 */ 2145 MOEA_PVO_CHECK(pvo); 2146 if (source_pvo == NULL && 2147 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2148 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2149 /* 2150 * Now found an entry to be spilled into the pteg. 2151 * The PTE is now valid, so we know it's active. 2152 */ 2153 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2154 2155 if (j >= 0) { 2156 PVO_PTEGIDX_SET(pvo, j); 2157 moea_pte_overflow--; 2158 MOEA_PVO_CHECK(pvo); 2159 mtx_unlock(&moea_table_mutex); 2160 return (1); 2161 } 2162 2163 source_pvo = pvo; 2164 2165 if (victim_pvo != NULL) 2166 break; 2167 } 2168 2169 /* 2170 * We also need the pvo entry of the victim we are replacing 2171 * so save the R & C bits of the PTE. 2172 */ 2173 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2174 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2175 victim_pvo = pvo; 2176 if (source_pvo != NULL) 2177 break; 2178 } 2179 } 2180 2181 if (source_pvo == NULL) { 2182 mtx_unlock(&moea_table_mutex); 2183 return (0); 2184 } 2185 2186 if (victim_pvo == NULL) { 2187 if ((pt->pte_hi & PTE_HID) == 0) 2188 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2189 "entry", pt); 2190 2191 /* 2192 * If this is a secondary PTE, we need to search it's primary 2193 * pvo bucket for the matching PVO. 2194 */ 2195 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2196 pvo_olink) { 2197 MOEA_PVO_CHECK(pvo); 2198 /* 2199 * We also need the pvo entry of the victim we are 2200 * replacing so save the R & C bits of the PTE. 2201 */ 2202 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2203 victim_pvo = pvo; 2204 break; 2205 } 2206 } 2207 2208 if (victim_pvo == NULL) 2209 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2210 "entry", pt); 2211 } 2212 2213 /* 2214 * We are invalidating the TLB entry for the EA we are replacing even 2215 * though it's valid. If we don't, we lose any ref/chg bit changes 2216 * contained in the TLB entry. 2217 */ 2218 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2219 2220 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2221 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2222 2223 PVO_PTEGIDX_CLR(victim_pvo); 2224 PVO_PTEGIDX_SET(source_pvo, i); 2225 moea_pte_replacements++; 2226 2227 MOEA_PVO_CHECK(victim_pvo); 2228 MOEA_PVO_CHECK(source_pvo); 2229 2230 mtx_unlock(&moea_table_mutex); 2231 return (1); 2232} 2233 2234static int 2235moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2236{ 2237 struct pte *pt; 2238 int i; 2239 2240 mtx_assert(&moea_table_mutex, MA_OWNED); 2241 2242 /* 2243 * First try primary hash. 2244 */ 2245 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2246 if ((pt->pte_hi & PTE_VALID) == 0) { 2247 pvo_pt->pte_hi &= ~PTE_HID; 2248 moea_pte_set(pt, pvo_pt); 2249 return (i); 2250 } 2251 } 2252 2253 /* 2254 * Now try secondary hash. 2255 */ 2256 ptegidx ^= moea_pteg_mask; 2257 2258 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2259 if ((pt->pte_hi & PTE_VALID) == 0) { 2260 pvo_pt->pte_hi |= PTE_HID; 2261 moea_pte_set(pt, pvo_pt); 2262 return (i); 2263 } 2264 } 2265 2266 panic("moea_pte_insert: overflow"); 2267 return (-1); 2268} 2269 2270static boolean_t 2271moea_query_bit(vm_page_t m, int ptebit) 2272{ 2273 struct pvo_entry *pvo; 2274 struct pte *pt; 2275 2276 if (moea_attr_fetch(m) & ptebit) 2277 return (TRUE); 2278 2279 vm_page_lock_queues(); 2280 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2281 MOEA_PVO_CHECK(pvo); /* sanity check */ 2282 2283 /* 2284 * See if we saved the bit off. If so, cache it and return 2285 * success. 2286 */ 2287 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2288 moea_attr_save(m, ptebit); 2289 MOEA_PVO_CHECK(pvo); /* sanity check */ 2290 vm_page_unlock_queues(); 2291 return (TRUE); 2292 } 2293 } 2294 2295 /* 2296 * No luck, now go through the hard part of looking at the PTEs 2297 * themselves. Sync so that any pending REF/CHG bits are flushed to 2298 * the PTEs. 2299 */ 2300 powerpc_sync(); 2301 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2302 MOEA_PVO_CHECK(pvo); /* sanity check */ 2303 2304 /* 2305 * See if this pvo has a valid PTE. if so, fetch the 2306 * REF/CHG bits from the valid PTE. If the appropriate 2307 * ptebit is set, cache it and return success. 2308 */ 2309 pt = moea_pvo_to_pte(pvo, -1); 2310 if (pt != NULL) { 2311 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2312 mtx_unlock(&moea_table_mutex); 2313 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2314 moea_attr_save(m, ptebit); 2315 MOEA_PVO_CHECK(pvo); /* sanity check */ 2316 vm_page_unlock_queues(); 2317 return (TRUE); 2318 } 2319 } 2320 } 2321 2322 vm_page_unlock_queues(); 2323 return (FALSE); 2324} 2325 2326static u_int 2327moea_clear_bit(vm_page_t m, int ptebit) 2328{ 2329 u_int count; 2330 struct pvo_entry *pvo; 2331 struct pte *pt; 2332 2333 vm_page_lock_queues(); 2334 2335 /* 2336 * Clear the cached value. 2337 */ 2338 moea_attr_clear(m, ptebit); 2339 2340 /* 2341 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2342 * we can reset the right ones). note that since the pvo entries and 2343 * list heads are accessed via BAT0 and are never placed in the page 2344 * table, we don't have to worry about further accesses setting the 2345 * REF/CHG bits. 2346 */ 2347 powerpc_sync(); 2348 2349 /* 2350 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2351 * valid pte clear the ptebit from the valid pte. 2352 */ 2353 count = 0; 2354 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2355 MOEA_PVO_CHECK(pvo); /* sanity check */ 2356 pt = moea_pvo_to_pte(pvo, -1); 2357 if (pt != NULL) { 2358 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2359 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2360 count++; 2361 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2362 } 2363 mtx_unlock(&moea_table_mutex); 2364 } 2365 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2366 MOEA_PVO_CHECK(pvo); /* sanity check */ 2367 } 2368 2369 vm_page_unlock_queues(); 2370 return (count); 2371} 2372 2373/* 2374 * Return true if the physical range is encompassed by the battable[idx] 2375 */ 2376static int 2377moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2378{ 2379 u_int prot; 2380 u_int32_t start; 2381 u_int32_t end; 2382 u_int32_t bat_ble; 2383 2384 /* 2385 * Return immediately if not a valid mapping 2386 */ 2387 if (!battable[idx].batu & BAT_Vs) 2388 return (EINVAL); 2389 2390 /* 2391 * The BAT entry must be cache-inhibited, guarded, and r/w 2392 * so it can function as an i/o page 2393 */ 2394 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2395 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2396 return (EPERM); 2397 2398 /* 2399 * The address should be within the BAT range. Assume that the 2400 * start address in the BAT has the correct alignment (thus 2401 * not requiring masking) 2402 */ 2403 start = battable[idx].batl & BAT_PBS; 2404 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2405 end = start | (bat_ble << 15) | 0x7fff; 2406 2407 if ((pa < start) || ((pa + size) > end)) 2408 return (ERANGE); 2409 2410 return (0); 2411} 2412 2413boolean_t 2414moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2415{ 2416 int i; 2417 2418 /* 2419 * This currently does not work for entries that 2420 * overlap 256M BAT segments. 2421 */ 2422 2423 for(i = 0; i < 16; i++) 2424 if (moea_bat_mapped(i, pa, size) == 0) 2425 return (0); 2426 2427 return (EFAULT); 2428} 2429 2430/* 2431 * Map a set of physical memory pages into the kernel virtual 2432 * address space. Return a pointer to where it is mapped. This 2433 * routine is intended to be used for mapping device memory, 2434 * NOT real memory. 2435 */ 2436void * 2437moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2438{ 2439 vm_offset_t va, tmpva, ppa, offset; 2440 int i; 2441 2442 ppa = trunc_page(pa); 2443 offset = pa & PAGE_MASK; 2444 size = roundup(offset + size, PAGE_SIZE); 2445 2446 /* 2447 * If the physical address lies within a valid BAT table entry, 2448 * return the 1:1 mapping. This currently doesn't work 2449 * for regions that overlap 256M BAT segments. 2450 */ 2451 for (i = 0; i < 16; i++) { 2452 if (moea_bat_mapped(i, pa, size) == 0) 2453 return ((void *) pa); 2454 } 2455 2456 va = kmem_alloc_nofault(kernel_map, size); 2457 if (!va) 2458 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2459 2460 for (tmpva = va; size > 0;) { 2461 moea_kenter(mmu, tmpva, ppa); 2462 tlbie(tmpva); 2463 size -= PAGE_SIZE; 2464 tmpva += PAGE_SIZE; 2465 ppa += PAGE_SIZE; 2466 } 2467 2468 return ((void *)(va + offset)); 2469} 2470 2471void 2472moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2473{ 2474 vm_offset_t base, offset; 2475 2476 /* 2477 * If this is outside kernel virtual space, then it's a 2478 * battable entry and doesn't require unmapping 2479 */ 2480 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2481 base = trunc_page(va); 2482 offset = va & PAGE_MASK; 2483 size = roundup(offset + size, PAGE_SIZE); 2484 kmem_free(kernel_map, base, size); 2485 } 2486} 2487 2488static void 2489moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2490{ 2491 struct pvo_entry *pvo; 2492 vm_offset_t lim; 2493 vm_paddr_t pa; 2494 vm_size_t len; 2495 2496 PMAP_LOCK(pm); 2497 while (sz > 0) { 2498 lim = round_page(va); 2499 len = MIN(lim - va, sz); 2500 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2501 if (pvo != NULL) { 2502 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2503 (va & ADDR_POFF); 2504 moea_syncicache(pa, len); 2505 } 2506 va += len; 2507 sz -= len; 2508 } 2509 PMAP_UNLOCK(pm); 2510} 2511