mmu_oea.c revision 209975
1139825Simp/*- 290643Sbenno * Copyright (c) 2001 The NetBSD Foundation, Inc. 390643Sbenno * All rights reserved. 490643Sbenno * 590643Sbenno * This code is derived from software contributed to The NetBSD Foundation 690643Sbenno * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 790643Sbenno * 890643Sbenno * Redistribution and use in source and binary forms, with or without 990643Sbenno * modification, are permitted provided that the following conditions 1090643Sbenno * are met: 1190643Sbenno * 1. Redistributions of source code must retain the above copyright 1290643Sbenno * notice, this list of conditions and the following disclaimer. 1390643Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1490643Sbenno * notice, this list of conditions and the following disclaimer in the 1590643Sbenno * documentation and/or other materials provided with the distribution. 1690643Sbenno * 3. All advertising materials mentioning features or use of this software 1790643Sbenno * must display the following acknowledgement: 1890643Sbenno * This product includes software developed by the NetBSD 1990643Sbenno * Foundation, Inc. and its contributors. 2090643Sbenno * 4. Neither the name of The NetBSD Foundation nor the names of its 2190643Sbenno * contributors may be used to endorse or promote products derived 2290643Sbenno * from this software without specific prior written permission. 2390643Sbenno * 2490643Sbenno * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2590643Sbenno * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2690643Sbenno * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2790643Sbenno * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2890643Sbenno * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2990643Sbenno * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3090643Sbenno * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3190643Sbenno * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3290643Sbenno * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3390643Sbenno * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3490643Sbenno * POSSIBILITY OF SUCH DAMAGE. 3590643Sbenno */ 36139825Simp/*- 3777957Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3877957Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 3977957Sbenno * All rights reserved. 4077957Sbenno * 4177957Sbenno * Redistribution and use in source and binary forms, with or without 4277957Sbenno * modification, are permitted provided that the following conditions 4377957Sbenno * are met: 4477957Sbenno * 1. Redistributions of source code must retain the above copyright 4577957Sbenno * notice, this list of conditions and the following disclaimer. 4677957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 4777957Sbenno * notice, this list of conditions and the following disclaimer in the 4877957Sbenno * documentation and/or other materials provided with the distribution. 4977957Sbenno * 3. All advertising materials mentioning features or use of this software 5077957Sbenno * must display the following acknowledgement: 5177957Sbenno * This product includes software developed by TooLs GmbH. 5277957Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 5377957Sbenno * derived from this software without specific prior written permission. 5477957Sbenno * 5577957Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 5677957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 5777957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 5877957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 5977957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 6077957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 6177957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 6277957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 6377957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 6477957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 6577957Sbenno * 6678880Sbenno * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 6777957Sbenno */ 68139825Simp/*- 6977957Sbenno * Copyright (C) 2001 Benno Rice. 7077957Sbenno * All rights reserved. 7177957Sbenno * 7277957Sbenno * Redistribution and use in source and binary forms, with or without 7377957Sbenno * modification, are permitted provided that the following conditions 7477957Sbenno * are met: 7577957Sbenno * 1. Redistributions of source code must retain the above copyright 7677957Sbenno * notice, this list of conditions and the following disclaimer. 7777957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 7877957Sbenno * notice, this list of conditions and the following disclaimer in the 7977957Sbenno * documentation and/or other materials provided with the distribution. 8077957Sbenno * 8177957Sbenno * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 8277957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8377957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 8477957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 8577957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 8677957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 8777957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 8877957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 8977957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 9077957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9177957Sbenno */ 9277957Sbenno 93113038Sobrien#include <sys/cdefs.h> 94113038Sobrien__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 209975 2010-07-13 05:32:19Z nwhitehorn $"); 9577957Sbenno 9690643Sbenno/* 9790643Sbenno * Manages physical address maps. 9890643Sbenno * 9990643Sbenno * In addition to hardware address maps, this module is called upon to 10090643Sbenno * provide software-use-only maps which may or may not be stored in the 10190643Sbenno * same form as hardware maps. These pseudo-maps are used to store 10290643Sbenno * intermediate results from copy operations to and from address spaces. 10390643Sbenno * 10490643Sbenno * Since the information managed by this module is also stored by the 10590643Sbenno * logical address mapping module, this module may throw away valid virtual 10690643Sbenno * to physical mappings at almost any time. However, invalidations of 10790643Sbenno * mappings must be done as requested. 10890643Sbenno * 10990643Sbenno * In order to cope with hardware architectures which make virtual to 11090643Sbenno * physical map invalidates expensive, this module may delay invalidate 11190643Sbenno * reduced protection operations until such time as they are actually 11290643Sbenno * necessary. This module is given full information as to which processors 11390643Sbenno * are currently using which maps, and to when physical maps must be made 11490643Sbenno * correct. 11590643Sbenno */ 11690643Sbenno 117118239Speter#include "opt_kstack_pages.h" 118118239Speter 11977957Sbenno#include <sys/param.h> 12080431Speter#include <sys/kernel.h> 12190643Sbenno#include <sys/ktr.h> 12290643Sbenno#include <sys/lock.h> 12390643Sbenno#include <sys/msgbuf.h> 12490643Sbenno#include <sys/mutex.h> 12577957Sbenno#include <sys/proc.h> 12690643Sbenno#include <sys/sysctl.h> 12790643Sbenno#include <sys/systm.h> 12877957Sbenno#include <sys/vmmeter.h> 12977957Sbenno 13090643Sbenno#include <dev/ofw/openfirm.h> 13190643Sbenno 132152180Sgrehan#include <vm/vm.h> 13377957Sbenno#include <vm/vm_param.h> 13477957Sbenno#include <vm/vm_kern.h> 13577957Sbenno#include <vm/vm_page.h> 13677957Sbenno#include <vm/vm_map.h> 13777957Sbenno#include <vm/vm_object.h> 13877957Sbenno#include <vm/vm_extern.h> 13977957Sbenno#include <vm/vm_pageout.h> 14077957Sbenno#include <vm/vm_pager.h> 14192847Sjeff#include <vm/uma.h> 14277957Sbenno 143125687Sgrehan#include <machine/cpu.h> 144192067Snwhitehorn#include <machine/platform.h> 14583730Smp#include <machine/bat.h> 14690643Sbenno#include <machine/frame.h> 14790643Sbenno#include <machine/md_var.h> 14890643Sbenno#include <machine/psl.h> 14977957Sbenno#include <machine/pte.h> 150178628Smarcel#include <machine/smp.h> 15190643Sbenno#include <machine/sr.h> 152152180Sgrehan#include <machine/mmuvar.h> 15377957Sbenno 154152180Sgrehan#include "mmu_if.h" 15577957Sbenno 156152180Sgrehan#define MOEA_DEBUG 157152180Sgrehan 15890643Sbenno#define TODO panic("%s: not implemented", __func__); 15977957Sbenno 16090643Sbenno#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 16190643Sbenno#define VSID_TO_SR(vsid) ((vsid) & 0xf) 16290643Sbenno#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 16390643Sbenno 164142416Sgrehan#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 165142416Sgrehan#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 166142416Sgrehan#define PVO_WIRED 0x010 /* PVO entry is wired */ 167142416Sgrehan#define PVO_MANAGED 0x020 /* PVO entry is managed */ 168142416Sgrehan#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 169142416Sgrehan#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 17092521Sbenno bootstrap */ 171142416Sgrehan#define PVO_FAKE 0x100 /* fictitious phys page */ 17290643Sbenno#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 17390643Sbenno#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174142416Sgrehan#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 17590643Sbenno#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 17690643Sbenno#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 17790643Sbenno#define PVO_PTEGIDX_CLR(pvo) \ 17890643Sbenno ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 17990643Sbenno#define PVO_PTEGIDX_SET(pvo, i) \ 18090643Sbenno ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 18190643Sbenno 182152180Sgrehan#define MOEA_PVO_CHECK(pvo) 18390643Sbenno 18490643Sbennostruct ofw_map { 18590643Sbenno vm_offset_t om_va; 18690643Sbenno vm_size_t om_len; 18790643Sbenno vm_offset_t om_pa; 18890643Sbenno u_int om_mode; 18990643Sbenno}; 19077957Sbenno 19190643Sbenno/* 19290643Sbenno * Map of physical memory regions. 19390643Sbenno */ 19497346Sbennostatic struct mem_region *regions; 19597346Sbennostatic struct mem_region *pregions; 196209975Snwhitehornstatic u_int phys_avail_count; 197209975Snwhitehornstatic int regions_sz, pregions_sz; 198100319Sbennostatic struct ofw_map *translations; 19977957Sbenno 20090643Sbennoextern struct pmap ofw_pmap; 20177957Sbenno 20290643Sbenno/* 203134535Salc * Lock for the pteg and pvo tables. 204134535Salc */ 205152180Sgrehanstruct mtx moea_table_mutex; 206134535Salc 207183094Smarcel/* tlbie instruction synchronization */ 208183094Smarcelstatic struct mtx tlbie_mtx; 209183094Smarcel 210134535Salc/* 21190643Sbenno * PTEG data. 21290643Sbenno */ 213152180Sgrehanstatic struct pteg *moea_pteg_table; 214152180Sgrehanu_int moea_pteg_count; 215152180Sgrehanu_int moea_pteg_mask; 21677957Sbenno 21790643Sbenno/* 21890643Sbenno * PVO data. 21990643Sbenno */ 220152180Sgrehanstruct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 221152180Sgrehanstruct pvo_head moea_pvo_kunmanaged = 222152180Sgrehan LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 223152180Sgrehanstruct pvo_head moea_pvo_unmanaged = 224152180Sgrehan LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 22577957Sbenno 226152180Sgrehanuma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 227152180Sgrehanuma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 22877957Sbenno 22999037Sbenno#define BPVO_POOL_SIZE 32768 230152180Sgrehanstatic struct pvo_entry *moea_bpvo_pool; 231152180Sgrehanstatic int moea_bpvo_pool_index = 0; 23277957Sbenno 23390643Sbenno#define VSID_NBPW (sizeof(u_int32_t) * 8) 234152180Sgrehanstatic u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 23577957Sbenno 236152180Sgrehanstatic boolean_t moea_initialized = FALSE; 23777957Sbenno 23890643Sbenno/* 23990643Sbenno * Statistics. 24090643Sbenno */ 241152180Sgrehanu_int moea_pte_valid = 0; 242152180Sgrehanu_int moea_pte_overflow = 0; 243152180Sgrehanu_int moea_pte_replacements = 0; 244152180Sgrehanu_int moea_pvo_entries = 0; 245152180Sgrehanu_int moea_pvo_enter_calls = 0; 246152180Sgrehanu_int moea_pvo_remove_calls = 0; 247152180Sgrehanu_int moea_pte_spills = 0; 248152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 24990643Sbenno 0, ""); 250152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 251152180Sgrehan &moea_pte_overflow, 0, ""); 252152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 253152180Sgrehan &moea_pte_replacements, 0, ""); 254152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 25590643Sbenno 0, ""); 256152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 257152180Sgrehan &moea_pvo_enter_calls, 0, ""); 258152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 259152180Sgrehan &moea_pvo_remove_calls, 0, ""); 260152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 261152180Sgrehan &moea_pte_spills, 0, ""); 26277957Sbenno 26390643Sbenno/* 264152180Sgrehan * Allocate physical memory for use in moea_bootstrap. 26590643Sbenno */ 266152180Sgrehanstatic vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 26777957Sbenno 26890643Sbenno/* 26990643Sbenno * PTE calls. 27090643Sbenno */ 271152180Sgrehanstatic int moea_pte_insert(u_int, struct pte *); 27277957Sbenno 27377957Sbenno/* 27490643Sbenno * PVO calls. 27577957Sbenno */ 276152180Sgrehanstatic int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 27790643Sbenno vm_offset_t, vm_offset_t, u_int, int); 278152180Sgrehanstatic void moea_pvo_remove(struct pvo_entry *, int); 279152180Sgrehanstatic struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 280152180Sgrehanstatic struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 28190643Sbenno 28290643Sbenno/* 28390643Sbenno * Utility routines. 28490643Sbenno */ 285159303Salcstatic void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 286159303Salc vm_prot_t, boolean_t); 287152180Sgrehanstatic void moea_syncicache(vm_offset_t, vm_size_t); 288152180Sgrehanstatic boolean_t moea_query_bit(vm_page_t, int); 289208990Salcstatic u_int moea_clear_bit(vm_page_t, int); 290152180Sgrehanstatic void moea_kremove(mmu_t, vm_offset_t); 291152180Sgrehanint moea_pte_spill(vm_offset_t); 29290643Sbenno 293152180Sgrehan/* 294152180Sgrehan * Kernel MMU interface 295152180Sgrehan */ 296152180Sgrehanvoid moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 297152180Sgrehanvoid moea_clear_modify(mmu_t, vm_page_t); 298152180Sgrehanvoid moea_clear_reference(mmu_t, vm_page_t); 299152180Sgrehanvoid moea_copy_page(mmu_t, vm_page_t, vm_page_t); 300152180Sgrehanvoid moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 301159303Salcvoid moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 302159303Salc vm_prot_t); 303159627Supsvoid moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 304152180Sgrehanvm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 305152180Sgrehanvm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 306152180Sgrehanvoid moea_init(mmu_t); 307152180Sgrehanboolean_t moea_is_modified(mmu_t, vm_page_t); 308207155Salcboolean_t moea_is_referenced(mmu_t, vm_page_t); 309152180Sgrehanboolean_t moea_ts_referenced(mmu_t, vm_page_t); 310152180Sgrehanvm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 311152180Sgrehanboolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 312173708Salcint moea_page_wired_mappings(mmu_t, vm_page_t); 313152180Sgrehanvoid moea_pinit(mmu_t, pmap_t); 314152180Sgrehanvoid moea_pinit0(mmu_t, pmap_t); 315152180Sgrehanvoid moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 316152180Sgrehanvoid moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 317152180Sgrehanvoid moea_qremove(mmu_t, vm_offset_t, int); 318152180Sgrehanvoid moea_release(mmu_t, pmap_t); 319152180Sgrehanvoid moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 320152180Sgrehanvoid moea_remove_all(mmu_t, vm_page_t); 321160889Salcvoid moea_remove_write(mmu_t, vm_page_t); 322152180Sgrehanvoid moea_zero_page(mmu_t, vm_page_t); 323152180Sgrehanvoid moea_zero_page_area(mmu_t, vm_page_t, int, int); 324152180Sgrehanvoid moea_zero_page_idle(mmu_t, vm_page_t); 325152180Sgrehanvoid moea_activate(mmu_t, struct thread *); 326152180Sgrehanvoid moea_deactivate(mmu_t, struct thread *); 327190681Snwhitehornvoid moea_cpu_bootstrap(mmu_t, int); 328152180Sgrehanvoid moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 329152180Sgrehanvoid *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 330152180Sgrehanvoid moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 331152180Sgrehanvm_offset_t moea_kextract(mmu_t, vm_offset_t); 332152180Sgrehanvoid moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 333152180Sgrehanboolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 334198341Smarcelstatic void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 335152180Sgrehan 336152180Sgrehanstatic mmu_method_t moea_methods[] = { 337152180Sgrehan MMUMETHOD(mmu_change_wiring, moea_change_wiring), 338152180Sgrehan MMUMETHOD(mmu_clear_modify, moea_clear_modify), 339152180Sgrehan MMUMETHOD(mmu_clear_reference, moea_clear_reference), 340152180Sgrehan MMUMETHOD(mmu_copy_page, moea_copy_page), 341152180Sgrehan MMUMETHOD(mmu_enter, moea_enter), 342159303Salc MMUMETHOD(mmu_enter_object, moea_enter_object), 343152180Sgrehan MMUMETHOD(mmu_enter_quick, moea_enter_quick), 344152180Sgrehan MMUMETHOD(mmu_extract, moea_extract), 345152180Sgrehan MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 346152180Sgrehan MMUMETHOD(mmu_init, moea_init), 347152180Sgrehan MMUMETHOD(mmu_is_modified, moea_is_modified), 348207155Salc MMUMETHOD(mmu_is_referenced, moea_is_referenced), 349152180Sgrehan MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 350152180Sgrehan MMUMETHOD(mmu_map, moea_map), 351152180Sgrehan MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 352173708Salc MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 353152180Sgrehan MMUMETHOD(mmu_pinit, moea_pinit), 354152180Sgrehan MMUMETHOD(mmu_pinit0, moea_pinit0), 355152180Sgrehan MMUMETHOD(mmu_protect, moea_protect), 356152180Sgrehan MMUMETHOD(mmu_qenter, moea_qenter), 357152180Sgrehan MMUMETHOD(mmu_qremove, moea_qremove), 358152180Sgrehan MMUMETHOD(mmu_release, moea_release), 359152180Sgrehan MMUMETHOD(mmu_remove, moea_remove), 360152180Sgrehan MMUMETHOD(mmu_remove_all, moea_remove_all), 361160889Salc MMUMETHOD(mmu_remove_write, moea_remove_write), 362198341Smarcel MMUMETHOD(mmu_sync_icache, moea_sync_icache), 363152180Sgrehan MMUMETHOD(mmu_zero_page, moea_zero_page), 364152180Sgrehan MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 365152180Sgrehan MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 366152180Sgrehan MMUMETHOD(mmu_activate, moea_activate), 367152180Sgrehan MMUMETHOD(mmu_deactivate, moea_deactivate), 368152180Sgrehan 369152180Sgrehan /* Internal interfaces */ 370152180Sgrehan MMUMETHOD(mmu_bootstrap, moea_bootstrap), 371190681Snwhitehorn MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 372152180Sgrehan MMUMETHOD(mmu_mapdev, moea_mapdev), 373152180Sgrehan MMUMETHOD(mmu_unmapdev, moea_unmapdev), 374152180Sgrehan MMUMETHOD(mmu_kextract, moea_kextract), 375152180Sgrehan MMUMETHOD(mmu_kenter, moea_kenter), 376152180Sgrehan MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 377152180Sgrehan 378152180Sgrehan { 0, 0 } 379152180Sgrehan}; 380152180Sgrehan 381152180Sgrehanstatic mmu_def_t oea_mmu = { 382152180Sgrehan MMU_TYPE_OEA, 383152180Sgrehan moea_methods, 384152180Sgrehan 0 385152180Sgrehan}; 386152180SgrehanMMU_DEF(oea_mmu); 387152180Sgrehan 388183094Smarcelstatic void 389183094Smarceltlbie(vm_offset_t va) 390183094Smarcel{ 391152180Sgrehan 392183094Smarcel mtx_lock_spin(&tlbie_mtx); 393183094Smarcel __asm __volatile("tlbie %0" :: "r"(va)); 394183094Smarcel __asm __volatile("tlbsync"); 395183094Smarcel powerpc_sync(); 396183094Smarcel mtx_unlock_spin(&tlbie_mtx); 397183094Smarcel} 398183094Smarcel 399183094Smarcelstatic void 400183094Smarceltlbia(void) 401183094Smarcel{ 402183094Smarcel vm_offset_t va; 403183094Smarcel 404183094Smarcel for (va = 0; va < 0x00040000; va += 0x00001000) { 405183094Smarcel __asm __volatile("tlbie %0" :: "r"(va)); 406183094Smarcel powerpc_sync(); 407183094Smarcel } 408183094Smarcel __asm __volatile("tlbsync"); 409183094Smarcel powerpc_sync(); 410183094Smarcel} 411183094Smarcel 41290643Sbennostatic __inline int 41390643Sbennova_to_sr(u_int *sr, vm_offset_t va) 41477957Sbenno{ 41590643Sbenno return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 41690643Sbenno} 41777957Sbenno 41890643Sbennostatic __inline u_int 41990643Sbennova_to_pteg(u_int sr, vm_offset_t addr) 42090643Sbenno{ 42190643Sbenno u_int hash; 42290643Sbenno 42390643Sbenno hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 42490643Sbenno ADDR_PIDX_SHFT); 425152180Sgrehan return (hash & moea_pteg_mask); 42677957Sbenno} 42777957Sbenno 42890643Sbennostatic __inline struct pvo_head * 42996250Sbennopa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 43077957Sbenno{ 43190643Sbenno struct vm_page *pg; 43277957Sbenno 43390643Sbenno pg = PHYS_TO_VM_PAGE(pa); 43490643Sbenno 43596250Sbenno if (pg_p != NULL) 43696250Sbenno *pg_p = pg; 43796250Sbenno 43890643Sbenno if (pg == NULL) 439152180Sgrehan return (&moea_pvo_unmanaged); 44090643Sbenno 44190643Sbenno return (&pg->md.mdpg_pvoh); 44277957Sbenno} 44377957Sbenno 44490643Sbennostatic __inline struct pvo_head * 44590643Sbennovm_page_to_pvoh(vm_page_t m) 44690643Sbenno{ 44790643Sbenno 44890643Sbenno return (&m->md.mdpg_pvoh); 44990643Sbenno} 45090643Sbenno 45177957Sbennostatic __inline void 452152180Sgrehanmoea_attr_clear(vm_page_t m, int ptebit) 45377957Sbenno{ 45490643Sbenno 455159928Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 45690643Sbenno m->md.mdpg_attrs &= ~ptebit; 45777957Sbenno} 45877957Sbenno 45977957Sbennostatic __inline int 460152180Sgrehanmoea_attr_fetch(vm_page_t m) 46177957Sbenno{ 46277957Sbenno 46390643Sbenno return (m->md.mdpg_attrs); 46477957Sbenno} 46577957Sbenno 46690643Sbennostatic __inline void 467152180Sgrehanmoea_attr_save(vm_page_t m, int ptebit) 46890643Sbenno{ 46990643Sbenno 470159928Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 47190643Sbenno m->md.mdpg_attrs |= ptebit; 47290643Sbenno} 47390643Sbenno 47477957Sbennostatic __inline int 475152180Sgrehanmoea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 47677957Sbenno{ 47790643Sbenno if (pt->pte_hi == pvo_pt->pte_hi) 47890643Sbenno return (1); 47990643Sbenno 48090643Sbenno return (0); 48177957Sbenno} 48277957Sbenno 48377957Sbennostatic __inline int 484152180Sgrehanmoea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 48577957Sbenno{ 48690643Sbenno return (pt->pte_hi & ~PTE_VALID) == 48790643Sbenno (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 48890643Sbenno ((va >> ADDR_API_SHFT) & PTE_API) | which); 48990643Sbenno} 49077957Sbenno 49190643Sbennostatic __inline void 492152180Sgrehanmoea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 49390643Sbenno{ 494159928Salc 495159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 496159928Salc 49790643Sbenno /* 49890643Sbenno * Construct a PTE. Default to IMB initially. Valid bit only gets 49990643Sbenno * set when the real pte is set in memory. 50090643Sbenno * 50190643Sbenno * Note: Don't set the valid bit for correct operation of tlb update. 50290643Sbenno */ 50390643Sbenno pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 50490643Sbenno (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 50590643Sbenno pt->pte_lo = pte_lo; 50677957Sbenno} 50777957Sbenno 50890643Sbennostatic __inline void 509152180Sgrehanmoea_pte_synch(struct pte *pt, struct pte *pvo_pt) 51077957Sbenno{ 51177957Sbenno 512159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 51390643Sbenno pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 51477957Sbenno} 51577957Sbenno 51690643Sbennostatic __inline void 517152180Sgrehanmoea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 51877957Sbenno{ 51977957Sbenno 520159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 521159928Salc 52290643Sbenno /* 52390643Sbenno * As shown in Section 7.6.3.2.3 52490643Sbenno */ 52590643Sbenno pt->pte_lo &= ~ptebit; 526183094Smarcel tlbie(va); 52777957Sbenno} 52877957Sbenno 52990643Sbennostatic __inline void 530152180Sgrehanmoea_pte_set(struct pte *pt, struct pte *pvo_pt) 53177957Sbenno{ 53277957Sbenno 533159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 53490643Sbenno pvo_pt->pte_hi |= PTE_VALID; 53590643Sbenno 53677957Sbenno /* 53790643Sbenno * Update the PTE as defined in section 7.6.3.1. 53890643Sbenno * Note that the REF/CHG bits are from pvo_pt and thus should havce 53990643Sbenno * been saved so this routine can restore them (if desired). 54077957Sbenno */ 54190643Sbenno pt->pte_lo = pvo_pt->pte_lo; 542183094Smarcel powerpc_sync(); 54390643Sbenno pt->pte_hi = pvo_pt->pte_hi; 544183094Smarcel powerpc_sync(); 545152180Sgrehan moea_pte_valid++; 54690643Sbenno} 54777957Sbenno 54890643Sbennostatic __inline void 549152180Sgrehanmoea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 55090643Sbenno{ 55190643Sbenno 552159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 55390643Sbenno pvo_pt->pte_hi &= ~PTE_VALID; 55490643Sbenno 55577957Sbenno /* 55690643Sbenno * Force the reg & chg bits back into the PTEs. 55777957Sbenno */ 558183094Smarcel powerpc_sync(); 55977957Sbenno 56090643Sbenno /* 56190643Sbenno * Invalidate the pte. 56290643Sbenno */ 56390643Sbenno pt->pte_hi &= ~PTE_VALID; 56477957Sbenno 565183094Smarcel tlbie(va); 56677957Sbenno 56790643Sbenno /* 56890643Sbenno * Save the reg & chg bits. 56990643Sbenno */ 570152180Sgrehan moea_pte_synch(pt, pvo_pt); 571152180Sgrehan moea_pte_valid--; 57277957Sbenno} 57377957Sbenno 57490643Sbennostatic __inline void 575152180Sgrehanmoea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 57690643Sbenno{ 57790643Sbenno 57890643Sbenno /* 57990643Sbenno * Invalidate the PTE 58090643Sbenno */ 581152180Sgrehan moea_pte_unset(pt, pvo_pt, va); 582152180Sgrehan moea_pte_set(pt, pvo_pt); 58390643Sbenno} 58490643Sbenno 58577957Sbenno/* 58690643Sbenno * Quick sort callout for comparing memory regions. 58777957Sbenno */ 58890643Sbennostatic int mr_cmp(const void *a, const void *b); 58990643Sbennostatic int om_cmp(const void *a, const void *b); 59090643Sbenno 59190643Sbennostatic int 59290643Sbennomr_cmp(const void *a, const void *b) 59377957Sbenno{ 59490643Sbenno const struct mem_region *regiona; 59590643Sbenno const struct mem_region *regionb; 59677957Sbenno 59790643Sbenno regiona = a; 59890643Sbenno regionb = b; 59990643Sbenno if (regiona->mr_start < regionb->mr_start) 60090643Sbenno return (-1); 60190643Sbenno else if (regiona->mr_start > regionb->mr_start) 60290643Sbenno return (1); 60390643Sbenno else 60490643Sbenno return (0); 60590643Sbenno} 60677957Sbenno 60790643Sbennostatic int 60890643Sbennoom_cmp(const void *a, const void *b) 60990643Sbenno{ 61090643Sbenno const struct ofw_map *mapa; 61190643Sbenno const struct ofw_map *mapb; 61290643Sbenno 61390643Sbenno mapa = a; 61490643Sbenno mapb = b; 61590643Sbenno if (mapa->om_pa < mapb->om_pa) 61690643Sbenno return (-1); 61790643Sbenno else if (mapa->om_pa > mapb->om_pa) 61890643Sbenno return (1); 61990643Sbenno else 62090643Sbenno return (0); 62177957Sbenno} 62277957Sbenno 62377957Sbennovoid 624190681Snwhitehornmoea_cpu_bootstrap(mmu_t mmup, int ap) 625178628Smarcel{ 626178628Smarcel u_int sdr; 627178628Smarcel int i; 628178628Smarcel 629178628Smarcel if (ap) { 630183094Smarcel powerpc_sync(); 631178628Smarcel __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 632178628Smarcel __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 633178628Smarcel isync(); 634178628Smarcel __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 635178628Smarcel __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 636178628Smarcel isync(); 637178628Smarcel } 638178628Smarcel 639178629Smarcel __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 640178629Smarcel __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 641178629Smarcel isync(); 642178628Smarcel 643178629Smarcel __asm __volatile("mtibatu 1,%0" :: "r"(0)); 644178629Smarcel __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 645178629Smarcel __asm __volatile("mtibatu 2,%0" :: "r"(0)); 646178629Smarcel __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 647178629Smarcel __asm __volatile("mtibatu 3,%0" :: "r"(0)); 648178628Smarcel isync(); 649178628Smarcel 650178628Smarcel for (i = 0; i < 16; i++) 651178628Smarcel mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 652178628Smarcel 653178628Smarcel __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 654178628Smarcel __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 655183094Smarcel powerpc_sync(); 656178628Smarcel 657178628Smarcel sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 658178628Smarcel __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 659178628Smarcel isync(); 660178628Smarcel 661179254Smarcel tlbia(); 662178628Smarcel} 663178628Smarcel 664178628Smarcelvoid 665152180Sgrehanmoea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 66677957Sbenno{ 66797346Sbenno ihandle_t mmui; 66890643Sbenno phandle_t chosen, mmu; 66990643Sbenno int sz; 67090643Sbenno int i, j; 671103604Sgrehan int ofw_mappings; 672143200Sgrehan vm_size_t size, physsz, hwphyssz; 67390643Sbenno vm_offset_t pa, va, off; 674194784Sjeff void *dpcpu; 675209369Snwhitehorn register_t msr; 67677957Sbenno 67799037Sbenno /* 678103604Sgrehan * Set up BAT0 to map the lowest 256 MB area 67999037Sbenno */ 68099037Sbenno battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 68199037Sbenno battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 68299037Sbenno 68399037Sbenno /* 68499037Sbenno * Map PCI memory space. 68599037Sbenno */ 68699037Sbenno battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 68799037Sbenno battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 68899037Sbenno 68999037Sbenno battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 69099037Sbenno battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 69199037Sbenno 69299037Sbenno battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 69399037Sbenno battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 69499037Sbenno 69599037Sbenno battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 69699037Sbenno battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 69799037Sbenno 69899037Sbenno /* 69999037Sbenno * Map obio devices. 70099037Sbenno */ 70199037Sbenno battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 70299037Sbenno battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 70399037Sbenno 70477957Sbenno /* 70590643Sbenno * Use an IBAT and a DBAT to map the bottom segment of memory 706209369Snwhitehorn * where we are. Turn off instruction relocation temporarily 707209369Snwhitehorn * to prevent faults while reprogramming the IBAT. 70877957Sbenno */ 709209369Snwhitehorn msr = mfmsr(); 710209369Snwhitehorn mtmsr(msr & ~PSL_IR); 711152180Sgrehan __asm (".balign 32; \n" 712149958Sgrehan "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 713131808Sgrehan "mtdbatu 0,%0; mtdbatl 0,%1; isync" 714178628Smarcel :: "r"(battable[0].batu), "r"(battable[0].batl)); 715209369Snwhitehorn mtmsr(msr); 71699037Sbenno 71799037Sbenno /* map pci space */ 718178628Smarcel __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 719178628Smarcel __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 720178628Smarcel isync(); 72177957Sbenno 722190681Snwhitehorn /* set global direct map flag */ 723190681Snwhitehorn hw_direct_map = 1; 724190681Snwhitehorn 72597346Sbenno mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 726152180Sgrehan CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 72797346Sbenno 72897346Sbenno qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 72997346Sbenno for (i = 0; i < pregions_sz; i++) { 730103604Sgrehan vm_offset_t pa; 731103604Sgrehan vm_offset_t end; 732103604Sgrehan 73397346Sbenno CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 73497346Sbenno pregions[i].mr_start, 73597346Sbenno pregions[i].mr_start + pregions[i].mr_size, 73697346Sbenno pregions[i].mr_size); 737103604Sgrehan /* 738103604Sgrehan * Install entries into the BAT table to allow all 739103604Sgrehan * of physmem to be convered by on-demand BAT entries. 740103604Sgrehan * The loop will sometimes set the same battable element 741103604Sgrehan * twice, but that's fine since they won't be used for 742103604Sgrehan * a while yet. 743103604Sgrehan */ 744103604Sgrehan pa = pregions[i].mr_start & 0xf0000000; 745103604Sgrehan end = pregions[i].mr_start + pregions[i].mr_size; 746103604Sgrehan do { 747103604Sgrehan u_int n = pa >> ADDR_SR_SHFT; 748152180Sgrehan 749103604Sgrehan battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 750103604Sgrehan battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 751103604Sgrehan pa += SEGMENT_LENGTH; 752103604Sgrehan } while (pa < end); 75397346Sbenno } 75497346Sbenno 75597346Sbenno if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 756152180Sgrehan panic("moea_bootstrap: phys_avail too small"); 75797346Sbenno qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 75890643Sbenno phys_avail_count = 0; 75991793Sbenno physsz = 0; 760143234Sgrehan hwphyssz = 0; 761143234Sgrehan TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 76297346Sbenno for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 76390643Sbenno CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 76490643Sbenno regions[i].mr_start + regions[i].mr_size, 76590643Sbenno regions[i].mr_size); 766143200Sgrehan if (hwphyssz != 0 && 767143200Sgrehan (physsz + regions[i].mr_size) >= hwphyssz) { 768143200Sgrehan if (physsz < hwphyssz) { 769143200Sgrehan phys_avail[j] = regions[i].mr_start; 770143200Sgrehan phys_avail[j + 1] = regions[i].mr_start + 771143200Sgrehan hwphyssz - physsz; 772143200Sgrehan physsz = hwphyssz; 773143200Sgrehan phys_avail_count++; 774143200Sgrehan } 775143200Sgrehan break; 776143200Sgrehan } 77790643Sbenno phys_avail[j] = regions[i].mr_start; 77890643Sbenno phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 77990643Sbenno phys_avail_count++; 78091793Sbenno physsz += regions[i].mr_size; 78177957Sbenno } 78291793Sbenno physmem = btoc(physsz); 78377957Sbenno 78477957Sbenno /* 78590643Sbenno * Allocate PTEG table. 78677957Sbenno */ 78790643Sbenno#ifdef PTEGCOUNT 788152180Sgrehan moea_pteg_count = PTEGCOUNT; 78990643Sbenno#else 790152180Sgrehan moea_pteg_count = 0x1000; 79177957Sbenno 792152180Sgrehan while (moea_pteg_count < physmem) 793152180Sgrehan moea_pteg_count <<= 1; 79477957Sbenno 795152180Sgrehan moea_pteg_count >>= 1; 79690643Sbenno#endif /* PTEGCOUNT */ 79777957Sbenno 798152180Sgrehan size = moea_pteg_count * sizeof(struct pteg); 799152180Sgrehan CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 80090643Sbenno size); 801152180Sgrehan moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 802152180Sgrehan CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 803152180Sgrehan bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 804152180Sgrehan moea_pteg_mask = moea_pteg_count - 1; 80577957Sbenno 80690643Sbenno /* 80794839Sbenno * Allocate pv/overflow lists. 80890643Sbenno */ 809152180Sgrehan size = sizeof(struct pvo_head) * moea_pteg_count; 810152180Sgrehan moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 81190643Sbenno PAGE_SIZE); 812152180Sgrehan CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 813152180Sgrehan for (i = 0; i < moea_pteg_count; i++) 814152180Sgrehan LIST_INIT(&moea_pvo_table[i]); 81577957Sbenno 81690643Sbenno /* 817134535Salc * Initialize the lock that synchronizes access to the pteg and pvo 818134535Salc * tables. 819134535Salc */ 820159928Salc mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 821159928Salc MTX_RECURSE); 822134535Salc 823183094Smarcel mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 824183094Smarcel 825134535Salc /* 82690643Sbenno * Initialise the unmanaged pvo pool. 82790643Sbenno */ 828152180Sgrehan moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 82999037Sbenno BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 830152180Sgrehan moea_bpvo_pool_index = 0; 83177957Sbenno 83277957Sbenno /* 83390643Sbenno * Make sure kernel vsid is allocated as well as VSID 0. 83477957Sbenno */ 835152180Sgrehan moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 83690643Sbenno |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 837152180Sgrehan moea_vsid_bitmap[0] |= 1; 83877957Sbenno 83990643Sbenno /* 840133862Smarius * Set up the Open Firmware pmap and add it's mappings. 84190643Sbenno */ 842152180Sgrehan moea_pinit(mmup, &ofw_pmap); 84390643Sbenno ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 844126478Sgrehan ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 84590643Sbenno if ((chosen = OF_finddevice("/chosen")) == -1) 846152180Sgrehan panic("moea_bootstrap: can't find /chosen"); 84790643Sbenno OF_getprop(chosen, "mmu", &mmui, 4); 84890643Sbenno if ((mmu = OF_instance_to_package(mmui)) == -1) 849152180Sgrehan panic("moea_bootstrap: can't get mmu package"); 85090643Sbenno if ((sz = OF_getproplen(mmu, "translations")) == -1) 851152180Sgrehan panic("moea_bootstrap: can't get ofw translation count"); 852100319Sbenno translations = NULL; 853131401Sgrehan for (i = 0; phys_avail[i] != 0; i += 2) { 854131401Sgrehan if (phys_avail[i + 1] >= sz) { 855100319Sbenno translations = (struct ofw_map *)phys_avail[i]; 856131401Sgrehan break; 857131401Sgrehan } 858100319Sbenno } 859100319Sbenno if (translations == NULL) 860152180Sgrehan panic("moea_bootstrap: no space to copy translations"); 86190643Sbenno bzero(translations, sz); 86290643Sbenno if (OF_getprop(mmu, "translations", translations, sz) == -1) 863152180Sgrehan panic("moea_bootstrap: can't get ofw translations"); 864152180Sgrehan CTR0(KTR_PMAP, "moea_bootstrap: translations"); 86597346Sbenno sz /= sizeof(*translations); 86690643Sbenno qsort(translations, sz, sizeof (*translations), om_cmp); 867103604Sgrehan for (i = 0, ofw_mappings = 0; i < sz; i++) { 86890643Sbenno CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 86990643Sbenno translations[i].om_pa, translations[i].om_va, 87090643Sbenno translations[i].om_len); 87177957Sbenno 872103604Sgrehan /* 873103604Sgrehan * If the mapping is 1:1, let the RAM and device on-demand 874103604Sgrehan * BAT tables take care of the translation. 875103604Sgrehan */ 876103604Sgrehan if (translations[i].om_va == translations[i].om_pa) 877103604Sgrehan continue; 87877957Sbenno 879103604Sgrehan /* Enter the pages */ 88090643Sbenno for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 88190643Sbenno struct vm_page m; 88277957Sbenno 88390643Sbenno m.phys_addr = translations[i].om_pa + off; 884208175Salc m.oflags = VPO_BUSY; 885159705Srink PMAP_LOCK(&ofw_pmap); 886159303Salc moea_enter_locked(&ofw_pmap, 887152180Sgrehan translations[i].om_va + off, &m, 888103604Sgrehan VM_PROT_ALL, 1); 889159705Srink PMAP_UNLOCK(&ofw_pmap); 890103604Sgrehan ofw_mappings++; 89177957Sbenno } 89277957Sbenno } 89377957Sbenno 89490643Sbenno /* 895178261Smarcel * Calculate the last available physical address. 896178261Smarcel */ 897178261Smarcel for (i = 0; phys_avail[i + 2] != 0; i += 2) 898178261Smarcel ; 899178261Smarcel Maxmem = powerpc_btop(phys_avail[i + 1]); 900178261Smarcel 901178261Smarcel /* 90290643Sbenno * Initialize the kernel pmap (which is statically allocated). 90390643Sbenno */ 904134329Salc PMAP_LOCK_INIT(kernel_pmap); 90590643Sbenno for (i = 0; i < 16; i++) { 90690643Sbenno kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 90777957Sbenno } 90890643Sbenno kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 909139401Sgrehan kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 91090643Sbenno kernel_pmap->pm_active = ~0; 91177957Sbenno 912190681Snwhitehorn moea_cpu_bootstrap(mmup,0); 91377957Sbenno 91490643Sbenno pmap_bootstrapped++; 915178261Smarcel 916178261Smarcel /* 917178261Smarcel * Set the start and end of kva. 918178261Smarcel */ 919178261Smarcel virtual_avail = VM_MIN_KERNEL_ADDRESS; 920204128Snwhitehorn virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 921178261Smarcel 922178261Smarcel /* 923178261Smarcel * Allocate a kernel stack with a guard page for thread0 and map it 924178261Smarcel * into the kernel page map. 925178261Smarcel */ 926178261Smarcel pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 927178261Smarcel va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 928178261Smarcel virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 929178261Smarcel CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 930178261Smarcel thread0.td_kstack = va; 931178261Smarcel thread0.td_kstack_pages = KSTACK_PAGES; 932178261Smarcel for (i = 0; i < KSTACK_PAGES; i++) { 933201758Smbr moea_kenter(mmup, va, pa); 934178261Smarcel pa += PAGE_SIZE; 935178261Smarcel va += PAGE_SIZE; 936178261Smarcel } 937178261Smarcel 938178261Smarcel /* 939178261Smarcel * Allocate virtual address space for the message buffer. 940178261Smarcel */ 941178261Smarcel pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 942178261Smarcel msgbufp = (struct msgbuf *)virtual_avail; 943178261Smarcel va = virtual_avail; 944178261Smarcel virtual_avail += round_page(MSGBUF_SIZE); 945178261Smarcel while (va < virtual_avail) { 946201758Smbr moea_kenter(mmup, va, pa); 947178261Smarcel pa += PAGE_SIZE; 948178261Smarcel va += PAGE_SIZE; 949178261Smarcel } 950194784Sjeff 951194784Sjeff /* 952194784Sjeff * Allocate virtual address space for the dynamic percpu area. 953194784Sjeff */ 954194784Sjeff pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 955194784Sjeff dpcpu = (void *)virtual_avail; 956194784Sjeff va = virtual_avail; 957194784Sjeff virtual_avail += DPCPU_SIZE; 958194784Sjeff while (va < virtual_avail) { 959201758Smbr moea_kenter(mmup, va, pa); 960194784Sjeff pa += PAGE_SIZE; 961194784Sjeff va += PAGE_SIZE; 962194784Sjeff } 963194784Sjeff dpcpu_init(dpcpu, 0); 96477957Sbenno} 96577957Sbenno 96677957Sbenno/* 96790643Sbenno * Activate a user pmap. The pmap must be activated before it's address 96890643Sbenno * space can be accessed in any way. 96977957Sbenno */ 97077957Sbennovoid 971152180Sgrehanmoea_activate(mmu_t mmu, struct thread *td) 97277957Sbenno{ 97396250Sbenno pmap_t pm, pmr; 97477957Sbenno 97577957Sbenno /* 976103604Sgrehan * Load all the data we need up front to encourage the compiler to 97790643Sbenno * not issue any loads while we have interrupts disabled below. 97877957Sbenno */ 97990643Sbenno pm = &td->td_proc->p_vmspace->vm_pmap; 980183290Snwhitehorn pmr = pm->pmap_phys; 98177957Sbenno 98290643Sbenno pm->pm_active |= PCPU_GET(cpumask); 98396250Sbenno PCPU_SET(curpmap, pmr); 98477957Sbenno} 98577957Sbenno 98691483Sbennovoid 987152180Sgrehanmoea_deactivate(mmu_t mmu, struct thread *td) 98891483Sbenno{ 98991483Sbenno pmap_t pm; 99091483Sbenno 99191483Sbenno pm = &td->td_proc->p_vmspace->vm_pmap; 992183094Smarcel pm->pm_active &= ~PCPU_GET(cpumask); 99396250Sbenno PCPU_SET(curpmap, NULL); 99491483Sbenno} 99591483Sbenno 99677957Sbennovoid 997152180Sgrehanmoea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 99877957Sbenno{ 99996353Sbenno struct pvo_entry *pvo; 100096353Sbenno 1001134329Salc PMAP_LOCK(pm); 1002152180Sgrehan pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 100396353Sbenno 100496353Sbenno if (pvo != NULL) { 100596353Sbenno if (wired) { 100696353Sbenno if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 100796353Sbenno pm->pm_stats.wired_count++; 100896353Sbenno pvo->pvo_vaddr |= PVO_WIRED; 100996353Sbenno } else { 101096353Sbenno if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 101196353Sbenno pm->pm_stats.wired_count--; 101296353Sbenno pvo->pvo_vaddr &= ~PVO_WIRED; 101396353Sbenno } 101496353Sbenno } 1015134329Salc PMAP_UNLOCK(pm); 101677957Sbenno} 101777957Sbenno 101877957Sbennovoid 1019152180Sgrehanmoea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 102077957Sbenno{ 102197385Sbenno vm_offset_t dst; 102297385Sbenno vm_offset_t src; 102397385Sbenno 102497385Sbenno dst = VM_PAGE_TO_PHYS(mdst); 102597385Sbenno src = VM_PAGE_TO_PHYS(msrc); 102697385Sbenno 102797385Sbenno kcopy((void *)src, (void *)dst, PAGE_SIZE); 102877957Sbenno} 102977957Sbenno 103077957Sbenno/* 103190643Sbenno * Zero a page of physical memory by temporarily mapping it into the tlb. 103277957Sbenno */ 103377957Sbennovoid 1034152180Sgrehanmoea_zero_page(mmu_t mmu, vm_page_t m) 103577957Sbenno{ 103694777Speter vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1037178265Smarcel void *va = (void *)pa; 103877957Sbenno 103990643Sbenno bzero(va, PAGE_SIZE); 104077957Sbenno} 104177957Sbenno 104277957Sbennovoid 1043152180Sgrehanmoea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 104477957Sbenno{ 104599666Sbenno vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1046178265Smarcel void *va = (void *)(pa + off); 104799666Sbenno 1048178265Smarcel bzero(va, size); 104977957Sbenno} 105077957Sbenno 105199571Spetervoid 1052152180Sgrehanmoea_zero_page_idle(mmu_t mmu, vm_page_t m) 105399571Speter{ 1054178265Smarcel vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1055178265Smarcel void *va = (void *)pa; 105699571Speter 1057178265Smarcel bzero(va, PAGE_SIZE); 105899571Speter} 105999571Speter 106077957Sbenno/* 106190643Sbenno * Map the given physical page at the specified virtual address in the 106290643Sbenno * target pmap with the protection requested. If specified the page 106390643Sbenno * will be wired down. 106477957Sbenno */ 106577957Sbennovoid 1066152180Sgrehanmoea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 106790643Sbenno boolean_t wired) 106877957Sbenno{ 1069159303Salc 1070159303Salc vm_page_lock_queues(); 1071159303Salc PMAP_LOCK(pmap); 1072159324Salc moea_enter_locked(pmap, va, m, prot, wired); 1073159303Salc vm_page_unlock_queues(); 1074159303Salc PMAP_UNLOCK(pmap); 1075159303Salc} 1076159303Salc 1077159303Salc/* 1078159303Salc * Map the given physical page at the specified virtual address in the 1079159303Salc * target pmap with the protection requested. If specified the page 1080159303Salc * will be wired down. 1081159303Salc * 1082159303Salc * The page queues and pmap must be locked. 1083159303Salc */ 1084159303Salcstatic void 1085159303Salcmoea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1086159303Salc boolean_t wired) 1087159303Salc{ 108890643Sbenno struct pvo_head *pvo_head; 108992847Sjeff uma_zone_t zone; 109096250Sbenno vm_page_t pg; 109196250Sbenno u_int pte_lo, pvo_flags, was_exec, i; 109290643Sbenno int error; 109377957Sbenno 1094152180Sgrehan if (!moea_initialized) { 1095152180Sgrehan pvo_head = &moea_pvo_kunmanaged; 1096152180Sgrehan zone = moea_upvo_zone; 109790643Sbenno pvo_flags = 0; 109896250Sbenno pg = NULL; 109996250Sbenno was_exec = PTE_EXEC; 110090643Sbenno } else { 1101110172Sgrehan pvo_head = vm_page_to_pvoh(m); 1102110172Sgrehan pg = m; 1103152180Sgrehan zone = moea_mpvo_zone; 110490643Sbenno pvo_flags = PVO_MANAGED; 110596250Sbenno was_exec = 0; 110690643Sbenno } 1107134535Salc if (pmap_bootstrapped) 1108159303Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1109159303Salc PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1110209048Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1111209048Salc (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1112208175Salc ("moea_enter_locked: page %p is not busy", m)); 111377957Sbenno 1114142416Sgrehan /* XXX change the pvo head for fake pages */ 1115189675Snwhitehorn if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1116189675Snwhitehorn pvo_flags &= ~PVO_MANAGED; 1117152180Sgrehan pvo_head = &moea_pvo_kunmanaged; 1118189675Snwhitehorn zone = moea_upvo_zone; 1119189675Snwhitehorn } 1120142416Sgrehan 112196250Sbenno /* 112296250Sbenno * If this is a managed page, and it's the first reference to the page, 112396250Sbenno * clear the execness of the page. Otherwise fetch the execness. 112496250Sbenno */ 1125142416Sgrehan if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 112696250Sbenno if (LIST_EMPTY(pvo_head)) { 1127152180Sgrehan moea_attr_clear(pg, PTE_EXEC); 112896250Sbenno } else { 1129152180Sgrehan was_exec = moea_attr_fetch(pg) & PTE_EXEC; 113096250Sbenno } 113196250Sbenno } 113296250Sbenno 113396250Sbenno /* 113496250Sbenno * Assume the page is cache inhibited and access is guarded unless 113596250Sbenno * it's in our available memory array. 113696250Sbenno */ 113790643Sbenno pte_lo = PTE_I | PTE_G; 113897346Sbenno for (i = 0; i < pregions_sz; i++) { 113997346Sbenno if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 114097346Sbenno (VM_PAGE_TO_PHYS(m) < 114197346Sbenno (pregions[i].mr_start + pregions[i].mr_size))) { 1142183094Smarcel pte_lo = PTE_M; 114396250Sbenno break; 114496250Sbenno } 114596250Sbenno } 114677957Sbenno 1147164229Salc if (prot & VM_PROT_WRITE) { 114890643Sbenno pte_lo |= PTE_BW; 1149208810Salc if (pmap_bootstrapped && 1150208810Salc (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1151164765Sgrehan vm_page_flag_set(m, PG_WRITEABLE); 1152164229Salc } else 115390643Sbenno pte_lo |= PTE_BR; 115477957Sbenno 1155142416Sgrehan if (prot & VM_PROT_EXECUTE) 1156142416Sgrehan pvo_flags |= PVO_EXECUTABLE; 115777957Sbenno 115890643Sbenno if (wired) 115990643Sbenno pvo_flags |= PVO_WIRED; 116077957Sbenno 1161142416Sgrehan if ((m->flags & PG_FICTITIOUS) != 0) 1162142416Sgrehan pvo_flags |= PVO_FAKE; 1163142416Sgrehan 1164152180Sgrehan error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 116596250Sbenno pte_lo, pvo_flags); 116690643Sbenno 116796250Sbenno /* 116896250Sbenno * Flush the real page from the instruction cache if this page is 116996250Sbenno * mapped executable and cacheable and was not previously mapped (or 117096250Sbenno * was not mapped executable). 117196250Sbenno */ 117296250Sbenno if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 117396250Sbenno (pte_lo & PTE_I) == 0 && was_exec == 0) { 117477957Sbenno /* 117590643Sbenno * Flush the real memory from the cache. 117677957Sbenno */ 1177152180Sgrehan moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 117896250Sbenno if (pg != NULL) 1179152180Sgrehan moea_attr_save(pg, PTE_EXEC); 118077957Sbenno } 1181103604Sgrehan 1182103604Sgrehan /* XXX syncicache always until problems are sorted */ 1183152180Sgrehan moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 118477957Sbenno} 118577957Sbenno 1186159303Salc/* 1187159303Salc * Maps a sequence of resident pages belonging to the same object. 1188159303Salc * The sequence begins with the given page m_start. This page is 1189159303Salc * mapped at the given virtual address start. Each subsequent page is 1190159303Salc * mapped at a virtual address that is offset from start by the same 1191159303Salc * amount as the page is offset from m_start within the object. The 1192159303Salc * last page in the sequence is the page with the largest offset from 1193159303Salc * m_start that can be mapped at a virtual address less than the given 1194159303Salc * virtual address end. Not every virtual page between start and end 1195159303Salc * is mapped; only those for which a resident page exists with the 1196159303Salc * corresponding offset from m_start are mapped. 1197159303Salc */ 1198159303Salcvoid 1199159303Salcmoea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1200159303Salc vm_page_t m_start, vm_prot_t prot) 1201159303Salc{ 1202159303Salc vm_page_t m; 1203159303Salc vm_pindex_t diff, psize; 1204159303Salc 1205159303Salc psize = atop(end - start); 1206159303Salc m = m_start; 1207208574Salc vm_page_lock_queues(); 1208159303Salc PMAP_LOCK(pm); 1209159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1210159303Salc moea_enter_locked(pm, start + ptoa(diff), m, prot & 1211159303Salc (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1212159303Salc m = TAILQ_NEXT(m, listq); 1213159303Salc } 1214208574Salc vm_page_unlock_queues(); 1215159303Salc PMAP_UNLOCK(pm); 1216159303Salc} 1217159303Salc 1218159627Supsvoid 1219152180Sgrehanmoea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1220159627Sups vm_prot_t prot) 1221117045Salc{ 1222117045Salc 1223207796Salc vm_page_lock_queues(); 1224159303Salc PMAP_LOCK(pm); 1225159303Salc moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1226152180Sgrehan FALSE); 1227207796Salc vm_page_unlock_queues(); 1228159303Salc PMAP_UNLOCK(pm); 1229117045Salc} 1230117045Salc 1231131658Salcvm_paddr_t 1232152180Sgrehanmoea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 123377957Sbenno{ 123496353Sbenno struct pvo_entry *pvo; 1235134329Salc vm_paddr_t pa; 123696353Sbenno 1237134329Salc PMAP_LOCK(pm); 1238152180Sgrehan pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1239134329Salc if (pvo == NULL) 1240134329Salc pa = 0; 1241134329Salc else 1242183290Snwhitehorn pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1243134329Salc PMAP_UNLOCK(pm); 1244134329Salc return (pa); 124577957Sbenno} 124677957Sbenno 124777957Sbenno/* 1248120336Sgrehan * Atomically extract and hold the physical page with the given 1249120336Sgrehan * pmap and virtual address pair if that mapping permits the given 1250120336Sgrehan * protection. 1251120336Sgrehan */ 1252120336Sgrehanvm_page_t 1253152180Sgrehanmoea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1254120336Sgrehan{ 1255132666Salc struct pvo_entry *pvo; 1256120336Sgrehan vm_page_t m; 1257207410Skmacy vm_paddr_t pa; 1258207410Skmacy 1259120336Sgrehan m = NULL; 1260207410Skmacy pa = 0; 1261134329Salc PMAP_LOCK(pmap); 1262207410Skmacyretry: 1263152180Sgrehan pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1264183290Snwhitehorn if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1265183290Snwhitehorn ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1266132666Salc (prot & VM_PROT_WRITE) == 0)) { 1267207410Skmacy if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1268207410Skmacy goto retry; 1269183290Snwhitehorn m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1270120336Sgrehan vm_page_hold(m); 1271120336Sgrehan } 1272207410Skmacy PA_UNLOCK_COND(pa); 1273134329Salc PMAP_UNLOCK(pmap); 1274120336Sgrehan return (m); 1275120336Sgrehan} 1276120336Sgrehan 127790643Sbennovoid 1278152180Sgrehanmoea_init(mmu_t mmu) 127977957Sbenno{ 128077957Sbenno 1281152180Sgrehan moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1282125442Sgrehan NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1283125442Sgrehan UMA_ZONE_VM | UMA_ZONE_NOFREE); 1284152180Sgrehan moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1285125442Sgrehan NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1286125442Sgrehan UMA_ZONE_VM | UMA_ZONE_NOFREE); 1287152180Sgrehan moea_initialized = TRUE; 128877957Sbenno} 128977957Sbenno 129090643Sbennoboolean_t 1291207155Salcmoea_is_referenced(mmu_t mmu, vm_page_t m) 1292207155Salc{ 1293207155Salc 1294208574Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1295208574Salc ("moea_is_referenced: page %p is not managed", m)); 1296207155Salc return (moea_query_bit(m, PTE_REF)); 1297207155Salc} 1298207155Salc 1299207155Salcboolean_t 1300152180Sgrehanmoea_is_modified(mmu_t mmu, vm_page_t m) 130190643Sbenno{ 130296353Sbenno 1303208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1304208504Salc ("moea_is_modified: page %p is not managed", m)); 1305208504Salc 1306208504Salc /* 1307208504Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1308208504Salc * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1309208504Salc * is clear, no PTEs can have PTE_CHG set. 1310208504Salc */ 1311208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1312208504Salc if ((m->oflags & VPO_BUSY) == 0 && 1313208504Salc (m->flags & PG_WRITEABLE) == 0) 131496353Sbenno return (FALSE); 1315208574Salc return (moea_query_bit(m, PTE_CHG)); 131690643Sbenno} 131790643Sbenno 131890643Sbennovoid 1319152180Sgrehanmoea_clear_reference(mmu_t mmu, vm_page_t m) 132090643Sbenno{ 1321110172Sgrehan 1322208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1323208504Salc ("moea_clear_reference: page %p is not managed", m)); 1324208990Salc moea_clear_bit(m, PTE_REF); 132590643Sbenno} 132690643Sbenno 1327110172Sgrehanvoid 1328152180Sgrehanmoea_clear_modify(mmu_t mmu, vm_page_t m) 1329110172Sgrehan{ 1330110172Sgrehan 1331208504Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1332208504Salc ("moea_clear_modify: page %p is not managed", m)); 1333208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1334208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 1335208504Salc ("moea_clear_modify: page %p is busy", m)); 1336208504Salc 1337208504Salc /* 1338208504Salc * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1339208504Salc * set. If the object containing the page is locked and the page is 1340208504Salc * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1341208504Salc */ 1342208504Salc if ((m->flags & PG_WRITEABLE) == 0) 1343110172Sgrehan return; 1344208990Salc moea_clear_bit(m, PTE_CHG); 1345110172Sgrehan} 1346110172Sgrehan 134791403Ssilby/* 1348160889Salc * Clear the write and modified bits in each of the given page's mappings. 1349160889Salc */ 1350160889Salcvoid 1351160889Salcmoea_remove_write(mmu_t mmu, vm_page_t m) 1352160889Salc{ 1353160889Salc struct pvo_entry *pvo; 1354160889Salc struct pte *pt; 1355160889Salc pmap_t pmap; 1356160889Salc u_int lo; 1357160889Salc 1358208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1359208175Salc ("moea_remove_write: page %p is not managed", m)); 1360208175Salc 1361208175Salc /* 1362208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1363208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 1364208175Salc * is clear, no page table entries need updating. 1365208175Salc */ 1366208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1367208175Salc if ((m->oflags & VPO_BUSY) == 0 && 1368160889Salc (m->flags & PG_WRITEABLE) == 0) 1369160889Salc return; 1370207796Salc vm_page_lock_queues(); 1371160889Salc lo = moea_attr_fetch(m); 1372183094Smarcel powerpc_sync(); 1373160889Salc LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1374160889Salc pmap = pvo->pvo_pmap; 1375160889Salc PMAP_LOCK(pmap); 1376183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1377160889Salc pt = moea_pvo_to_pte(pvo, -1); 1378183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1379183290Snwhitehorn pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1380160889Salc if (pt != NULL) { 1381183290Snwhitehorn moea_pte_synch(pt, &pvo->pvo_pte.pte); 1382183290Snwhitehorn lo |= pvo->pvo_pte.pte.pte_lo; 1383183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1384183290Snwhitehorn moea_pte_change(pt, &pvo->pvo_pte.pte, 1385160889Salc pvo->pvo_vaddr); 1386160889Salc mtx_unlock(&moea_table_mutex); 1387160889Salc } 1388160889Salc } 1389160889Salc PMAP_UNLOCK(pmap); 1390160889Salc } 1391160889Salc if ((lo & PTE_CHG) != 0) { 1392160889Salc moea_attr_clear(m, PTE_CHG); 1393160889Salc vm_page_dirty(m); 1394160889Salc } 1395160889Salc vm_page_flag_clear(m, PG_WRITEABLE); 1396207796Salc vm_page_unlock_queues(); 1397160889Salc} 1398160889Salc 1399160889Salc/* 1400152180Sgrehan * moea_ts_referenced: 140191403Ssilby * 140291403Ssilby * Return a count of reference bits for a page, clearing those bits. 140391403Ssilby * It is not necessary for every reference bit to be cleared, but it 140491403Ssilby * is necessary that 0 only be returned when there are truly no 140591403Ssilby * reference bits set. 140691403Ssilby * 140791403Ssilby * XXX: The exact number of bits to check and clear is a matter that 140891403Ssilby * should be tested and standardized at some point in the future for 140991403Ssilby * optimal aging of shared pages. 141091403Ssilby */ 1411152180Sgrehanboolean_t 1412152180Sgrehanmoea_ts_referenced(mmu_t mmu, vm_page_t m) 141390643Sbenno{ 1414110172Sgrehan 1415208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1416208990Salc ("moea_ts_referenced: page %p is not managed", m)); 1417208990Salc return (moea_clear_bit(m, PTE_REF)); 141890643Sbenno} 141990643Sbenno 142077957Sbenno/* 142190643Sbenno * Map a wired page into kernel virtual address space. 142277957Sbenno */ 142377957Sbennovoid 1424152180Sgrehanmoea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 142577957Sbenno{ 142690643Sbenno u_int pte_lo; 142790643Sbenno int error; 142890643Sbenno int i; 142977957Sbenno 143090643Sbenno#if 0 143190643Sbenno if (va < VM_MIN_KERNEL_ADDRESS) 1432152180Sgrehan panic("moea_kenter: attempt to enter non-kernel address %#x", 143390643Sbenno va); 143490643Sbenno#endif 143577957Sbenno 1436103604Sgrehan pte_lo = PTE_I | PTE_G; 1437103604Sgrehan for (i = 0; i < pregions_sz; i++) { 1438103604Sgrehan if ((pa >= pregions[i].mr_start) && 1439103604Sgrehan (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1440183094Smarcel pte_lo = PTE_M; 144177957Sbenno break; 144277957Sbenno } 1443103604Sgrehan } 144477957Sbenno 1445135172Salc PMAP_LOCK(kernel_pmap); 1446152180Sgrehan error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1447152180Sgrehan &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 144890643Sbenno 144990643Sbenno if (error != 0 && error != ENOENT) 1450152180Sgrehan panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 145190643Sbenno pa, error); 145290643Sbenno 145377957Sbenno /* 145490643Sbenno * Flush the real memory from the instruction cache. 145577957Sbenno */ 145690643Sbenno if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1457152180Sgrehan moea_syncicache(pa, PAGE_SIZE); 145877957Sbenno } 1459135172Salc PMAP_UNLOCK(kernel_pmap); 146077957Sbenno} 146177957Sbenno 146294838Sbenno/* 146394838Sbenno * Extract the physical page address associated with the given kernel virtual 146494838Sbenno * address. 146594838Sbenno */ 146690643Sbennovm_offset_t 1467152180Sgrehanmoea_kextract(mmu_t mmu, vm_offset_t va) 146877957Sbenno{ 146994838Sbenno struct pvo_entry *pvo; 1470134329Salc vm_paddr_t pa; 147194838Sbenno 1472125185Sgrehan /* 1473183290Snwhitehorn * Allow direct mappings on 32-bit OEA 1474125185Sgrehan */ 1475125185Sgrehan if (va < VM_MIN_KERNEL_ADDRESS) { 1476125185Sgrehan return (va); 1477125185Sgrehan } 1478125185Sgrehan 1479134329Salc PMAP_LOCK(kernel_pmap); 1480152180Sgrehan pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1481152180Sgrehan KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1482183290Snwhitehorn pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1483134329Salc PMAP_UNLOCK(kernel_pmap); 1484134329Salc return (pa); 148577957Sbenno} 148677957Sbenno 148791456Sbenno/* 148891456Sbenno * Remove a wired page from kernel virtual address space. 148991456Sbenno */ 149077957Sbennovoid 1491152180Sgrehanmoea_kremove(mmu_t mmu, vm_offset_t va) 149277957Sbenno{ 149391456Sbenno 1494152180Sgrehan moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 149577957Sbenno} 149677957Sbenno 149777957Sbenno/* 149890643Sbenno * Map a range of physical addresses into kernel virtual address space. 149990643Sbenno * 150090643Sbenno * The value passed in *virt is a suggested virtual address for the mapping. 150190643Sbenno * Architectures which can support a direct-mapped physical to virtual region 150290643Sbenno * can return the appropriate address within that region, leaving '*virt' 150390643Sbenno * unchanged. We cannot and therefore do not; *virt is updated with the 150490643Sbenno * first usable address after the mapped region. 150577957Sbenno */ 150690643Sbennovm_offset_t 1507152180Sgrehanmoea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1508152180Sgrehan vm_offset_t pa_end, int prot) 150977957Sbenno{ 151090643Sbenno vm_offset_t sva, va; 151177957Sbenno 151290643Sbenno sva = *virt; 151390643Sbenno va = sva; 151490643Sbenno for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1515152180Sgrehan moea_kenter(mmu, va, pa_start); 151690643Sbenno *virt = va; 151790643Sbenno return (sva); 151877957Sbenno} 151977957Sbenno 152077957Sbenno/* 152191403Ssilby * Returns true if the pmap's pv is one of the first 152291403Ssilby * 16 pvs linked to from this page. This count may 152391403Ssilby * be changed upwards or downwards in the future; it 152491403Ssilby * is only necessary that true be returned for a small 152591403Ssilby * subset of pmaps for proper page aging. 152691403Ssilby */ 152790643Sbennoboolean_t 1528152180Sgrehanmoea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 152990643Sbenno{ 1530110172Sgrehan int loops; 1531110172Sgrehan struct pvo_entry *pvo; 1532208990Salc boolean_t rv; 1533110172Sgrehan 1534208990Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1535208990Salc ("moea_page_exists_quick: page %p is not managed", m)); 1536110172Sgrehan loops = 0; 1537208990Salc rv = FALSE; 1538208990Salc vm_page_lock_queues(); 1539110172Sgrehan LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1540208990Salc if (pvo->pvo_pmap == pmap) { 1541208990Salc rv = TRUE; 1542208990Salc break; 1543208990Salc } 1544110172Sgrehan if (++loops >= 16) 1545110172Sgrehan break; 1546110172Sgrehan } 1547208990Salc vm_page_unlock_queues(); 1548208990Salc return (rv); 154990643Sbenno} 155077957Sbenno 1551173708Salc/* 1552173708Salc * Return the number of managed mappings to the given physical page 1553173708Salc * that are wired. 1554173708Salc */ 1555173708Salcint 1556173708Salcmoea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1557173708Salc{ 1558173708Salc struct pvo_entry *pvo; 1559173708Salc int count; 1560173708Salc 1561173708Salc count = 0; 1562208990Salc if ((m->flags & PG_FICTITIOUS) != 0) 1563173708Salc return (count); 1564207796Salc vm_page_lock_queues(); 1565173708Salc LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1566173708Salc if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1567173708Salc count++; 1568207796Salc vm_page_unlock_queues(); 1569173708Salc return (count); 1570173708Salc} 1571173708Salc 1572152180Sgrehanstatic u_int moea_vsidcontext; 157377957Sbenno 157490643Sbennovoid 1575152180Sgrehanmoea_pinit(mmu_t mmu, pmap_t pmap) 157690643Sbenno{ 157790643Sbenno int i, mask; 157890643Sbenno u_int entropy; 157977957Sbenno 1580152180Sgrehan KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1581134329Salc PMAP_LOCK_INIT(pmap); 1582126478Sgrehan 158390643Sbenno entropy = 0; 158490643Sbenno __asm __volatile("mftb %0" : "=r"(entropy)); 158577957Sbenno 1586183290Snwhitehorn if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1587183290Snwhitehorn == NULL) { 1588183290Snwhitehorn pmap->pmap_phys = pmap; 1589183290Snwhitehorn } 1590183290Snwhitehorn 1591183290Snwhitehorn 159290643Sbenno /* 159390643Sbenno * Allocate some segment registers for this pmap. 159490643Sbenno */ 159590643Sbenno for (i = 0; i < NPMAPS; i += VSID_NBPW) { 159690643Sbenno u_int hash, n; 159777957Sbenno 159877957Sbenno /* 159990643Sbenno * Create a new value by mutiplying by a prime and adding in 160090643Sbenno * entropy from the timebase register. This is to make the 160190643Sbenno * VSID more random so that the PT hash function collides 160290643Sbenno * less often. (Note that the prime casues gcc to do shifts 160390643Sbenno * instead of a multiply.) 160477957Sbenno */ 1605152180Sgrehan moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1606152180Sgrehan hash = moea_vsidcontext & (NPMAPS - 1); 160790643Sbenno if (hash == 0) /* 0 is special, avoid it */ 160890643Sbenno continue; 160990643Sbenno n = hash >> 5; 161090643Sbenno mask = 1 << (hash & (VSID_NBPW - 1)); 1611152180Sgrehan hash = (moea_vsidcontext & 0xfffff); 1612152180Sgrehan if (moea_vsid_bitmap[n] & mask) { /* collision? */ 161390643Sbenno /* anything free in this bucket? */ 1614152180Sgrehan if (moea_vsid_bitmap[n] == 0xffffffff) { 1615152180Sgrehan entropy = (moea_vsidcontext >> 20); 161690643Sbenno continue; 161790643Sbenno } 1618152180Sgrehan i = ffs(~moea_vsid_bitmap[i]) - 1; 161990643Sbenno mask = 1 << i; 162090643Sbenno hash &= 0xfffff & ~(VSID_NBPW - 1); 162190643Sbenno hash |= i; 162277957Sbenno } 1623152180Sgrehan moea_vsid_bitmap[n] |= mask; 162490643Sbenno for (i = 0; i < 16; i++) 162590643Sbenno pmap->pm_sr[i] = VSID_MAKE(i, hash); 162690643Sbenno return; 162790643Sbenno } 162877957Sbenno 1629152180Sgrehan panic("moea_pinit: out of segments"); 163077957Sbenno} 163177957Sbenno 163277957Sbenno/* 163390643Sbenno * Initialize the pmap associated with process 0. 163477957Sbenno */ 163577957Sbennovoid 1636152180Sgrehanmoea_pinit0(mmu_t mmu, pmap_t pm) 163777957Sbenno{ 163877957Sbenno 1639152180Sgrehan moea_pinit(mmu, pm); 164090643Sbenno bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 164177957Sbenno} 164277957Sbenno 164394838Sbenno/* 164494838Sbenno * Set the physical protection on the specified range of this map as requested. 164594838Sbenno */ 164690643Sbennovoid 1647152180Sgrehanmoea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1648152180Sgrehan vm_prot_t prot) 164990643Sbenno{ 165094838Sbenno struct pvo_entry *pvo; 165194838Sbenno struct pte *pt; 165294838Sbenno int pteidx; 165394838Sbenno 165494838Sbenno KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1655152180Sgrehan ("moea_protect: non current pmap")); 165694838Sbenno 165794838Sbenno if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1658152180Sgrehan moea_remove(mmu, pm, sva, eva); 165994838Sbenno return; 166094838Sbenno } 166194838Sbenno 1662132220Salc vm_page_lock_queues(); 1663134329Salc PMAP_LOCK(pm); 166494838Sbenno for (; sva < eva; sva += PAGE_SIZE) { 1665152180Sgrehan pvo = moea_pvo_find_va(pm, sva, &pteidx); 166694838Sbenno if (pvo == NULL) 166794838Sbenno continue; 166894838Sbenno 166994838Sbenno if ((prot & VM_PROT_EXECUTE) == 0) 167094838Sbenno pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 167194838Sbenno 167294838Sbenno /* 167394838Sbenno * Grab the PTE pointer before we diddle with the cached PTE 167494838Sbenno * copy. 167594838Sbenno */ 1676152180Sgrehan pt = moea_pvo_to_pte(pvo, pteidx); 167794838Sbenno /* 167894838Sbenno * Change the protection of the page. 167994838Sbenno */ 1680183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1681183290Snwhitehorn pvo->pvo_pte.pte.pte_lo |= PTE_BR; 168294838Sbenno 168394838Sbenno /* 168494838Sbenno * If the PVO is in the page table, update that pte as well. 168594838Sbenno */ 1686159928Salc if (pt != NULL) { 1687183290Snwhitehorn moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1688159928Salc mtx_unlock(&moea_table_mutex); 1689159928Salc } 169094838Sbenno } 1691132220Salc vm_page_unlock_queues(); 1692134329Salc PMAP_UNLOCK(pm); 169377957Sbenno} 169477957Sbenno 169591456Sbenno/* 169691456Sbenno * Map a list of wired pages into kernel virtual address space. This is 169791456Sbenno * intended for temporary mappings which do not need page modification or 169891456Sbenno * references recorded. Existing mappings in the region are overwritten. 169991456Sbenno */ 170090643Sbennovoid 1701152180Sgrehanmoea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 170277957Sbenno{ 1703110172Sgrehan vm_offset_t va; 170477957Sbenno 1705110172Sgrehan va = sva; 1706110172Sgrehan while (count-- > 0) { 1707152180Sgrehan moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1708110172Sgrehan va += PAGE_SIZE; 1709110172Sgrehan m++; 1710110172Sgrehan } 171190643Sbenno} 171277957Sbenno 171391456Sbenno/* 171491456Sbenno * Remove page mappings from kernel virtual address space. Intended for 1715152180Sgrehan * temporary mappings entered by moea_qenter. 171691456Sbenno */ 171790643Sbennovoid 1718152180Sgrehanmoea_qremove(mmu_t mmu, vm_offset_t sva, int count) 171990643Sbenno{ 1720110172Sgrehan vm_offset_t va; 172191456Sbenno 1722110172Sgrehan va = sva; 1723110172Sgrehan while (count-- > 0) { 1724152180Sgrehan moea_kremove(mmu, va); 1725110172Sgrehan va += PAGE_SIZE; 1726110172Sgrehan } 172777957Sbenno} 172877957Sbenno 172990643Sbennovoid 1730152180Sgrehanmoea_release(mmu_t mmu, pmap_t pmap) 173190643Sbenno{ 1732103604Sgrehan int idx, mask; 1733103604Sgrehan 1734103604Sgrehan /* 1735103604Sgrehan * Free segment register's VSID 1736103604Sgrehan */ 1737103604Sgrehan if (pmap->pm_sr[0] == 0) 1738152180Sgrehan panic("moea_release"); 1739103604Sgrehan 1740103604Sgrehan idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1741103604Sgrehan mask = 1 << (idx % VSID_NBPW); 1742103604Sgrehan idx /= VSID_NBPW; 1743152180Sgrehan moea_vsid_bitmap[idx] &= ~mask; 1744134329Salc PMAP_LOCK_DESTROY(pmap); 174577957Sbenno} 174677957Sbenno 174791456Sbenno/* 174891456Sbenno * Remove the given range of addresses from the specified map. 174991456Sbenno */ 175090643Sbennovoid 1751152180Sgrehanmoea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 175277957Sbenno{ 175391456Sbenno struct pvo_entry *pvo; 175491456Sbenno int pteidx; 175591456Sbenno 1756132220Salc vm_page_lock_queues(); 1757134329Salc PMAP_LOCK(pm); 175891456Sbenno for (; sva < eva; sva += PAGE_SIZE) { 1759152180Sgrehan pvo = moea_pvo_find_va(pm, sva, &pteidx); 176091456Sbenno if (pvo != NULL) { 1761152180Sgrehan moea_pvo_remove(pvo, pteidx); 176291456Sbenno } 176391456Sbenno } 1764140538Sgrehan PMAP_UNLOCK(pm); 1765132220Salc vm_page_unlock_queues(); 176677957Sbenno} 176777957Sbenno 176894838Sbenno/* 1769152180Sgrehan * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1770110172Sgrehan * will reflect changes in pte's back to the vm_page. 1771110172Sgrehan */ 1772110172Sgrehanvoid 1773152180Sgrehanmoea_remove_all(mmu_t mmu, vm_page_t m) 1774110172Sgrehan{ 1775110172Sgrehan struct pvo_head *pvo_head; 1776110172Sgrehan struct pvo_entry *pvo, *next_pvo; 1777134329Salc pmap_t pmap; 1778110172Sgrehan 1779207796Salc vm_page_lock_queues(); 1780110172Sgrehan pvo_head = vm_page_to_pvoh(m); 1781110172Sgrehan for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1782110172Sgrehan next_pvo = LIST_NEXT(pvo, pvo_vlink); 1783133166Sgrehan 1784152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 1785134329Salc pmap = pvo->pvo_pmap; 1786134329Salc PMAP_LOCK(pmap); 1787152180Sgrehan moea_pvo_remove(pvo, -1); 1788134329Salc PMAP_UNLOCK(pmap); 1789110172Sgrehan } 1790204042Snwhitehorn if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1791208847Snwhitehorn moea_attr_clear(m, PTE_CHG); 1792204042Snwhitehorn vm_page_dirty(m); 1793204042Snwhitehorn } 1794110172Sgrehan vm_page_flag_clear(m, PG_WRITEABLE); 1795207796Salc vm_page_unlock_queues(); 1796110172Sgrehan} 1797110172Sgrehan 1798110172Sgrehan/* 179990643Sbenno * Allocate a physical page of memory directly from the phys_avail map. 1800152180Sgrehan * Can only be called from moea_bootstrap before avail start and end are 180190643Sbenno * calculated. 180283682Smp */ 180390643Sbennostatic vm_offset_t 1804152180Sgrehanmoea_bootstrap_alloc(vm_size_t size, u_int align) 180583682Smp{ 180690643Sbenno vm_offset_t s, e; 180790643Sbenno int i, j; 180883682Smp 180990643Sbenno size = round_page(size); 181090643Sbenno for (i = 0; phys_avail[i + 1] != 0; i += 2) { 181190643Sbenno if (align != 0) 181290643Sbenno s = (phys_avail[i] + align - 1) & ~(align - 1); 181390643Sbenno else 181490643Sbenno s = phys_avail[i]; 181590643Sbenno e = s + size; 181690643Sbenno 181790643Sbenno if (s < phys_avail[i] || e > phys_avail[i + 1]) 181890643Sbenno continue; 181990643Sbenno 182090643Sbenno if (s == phys_avail[i]) { 182190643Sbenno phys_avail[i] += size; 182290643Sbenno } else if (e == phys_avail[i + 1]) { 182390643Sbenno phys_avail[i + 1] -= size; 182490643Sbenno } else { 182590643Sbenno for (j = phys_avail_count * 2; j > i; j -= 2) { 182690643Sbenno phys_avail[j] = phys_avail[j - 2]; 182790643Sbenno phys_avail[j + 1] = phys_avail[j - 1]; 182890643Sbenno } 182990643Sbenno 183090643Sbenno phys_avail[i + 3] = phys_avail[i + 1]; 183190643Sbenno phys_avail[i + 1] = s; 183290643Sbenno phys_avail[i + 2] = e; 183390643Sbenno phys_avail_count++; 183490643Sbenno } 183590643Sbenno 183690643Sbenno return (s); 183783682Smp } 1838152180Sgrehan panic("moea_bootstrap_alloc: could not allocate memory"); 183983682Smp} 184083682Smp 184190643Sbennostatic void 1842152180Sgrehanmoea_syncicache(vm_offset_t pa, vm_size_t len) 184377957Sbenno{ 184490643Sbenno __syncicache((void *)pa, len); 184590643Sbenno} 184677957Sbenno 184790643Sbennostatic int 1848152180Sgrehanmoea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 184990643Sbenno vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 185077957Sbenno{ 185190643Sbenno struct pvo_entry *pvo; 185290643Sbenno u_int sr; 185390643Sbenno int first; 185490643Sbenno u_int ptegidx; 185590643Sbenno int i; 1856103604Sgrehan int bootstrap; 185777957Sbenno 1858152180Sgrehan moea_pvo_enter_calls++; 185996250Sbenno first = 0; 1860103604Sgrehan bootstrap = 0; 186190643Sbenno 186290643Sbenno /* 186390643Sbenno * Compute the PTE Group index. 186490643Sbenno */ 186590643Sbenno va &= ~ADDR_POFF; 186690643Sbenno sr = va_to_sr(pm->pm_sr, va); 186790643Sbenno ptegidx = va_to_pteg(sr, va); 186890643Sbenno 186990643Sbenno /* 187090643Sbenno * Remove any existing mapping for this page. Reuse the pvo entry if 187190643Sbenno * there is a mapping. 187290643Sbenno */ 1873152180Sgrehan mtx_lock(&moea_table_mutex); 1874152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 187590643Sbenno if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1876183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1877183290Snwhitehorn (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 187896334Sbenno (pte_lo & PTE_PP)) { 1879152180Sgrehan mtx_unlock(&moea_table_mutex); 188092521Sbenno return (0); 188196334Sbenno } 1882152180Sgrehan moea_pvo_remove(pvo, -1); 188390643Sbenno break; 188490643Sbenno } 188590643Sbenno } 188690643Sbenno 188790643Sbenno /* 188890643Sbenno * If we aren't overwriting a mapping, try to allocate. 188990643Sbenno */ 1890152180Sgrehan if (moea_initialized) { 189192847Sjeff pvo = uma_zalloc(zone, M_NOWAIT); 189292521Sbenno } else { 1893152180Sgrehan if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1894152180Sgrehan panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1895152180Sgrehan moea_bpvo_pool_index, BPVO_POOL_SIZE, 189699037Sbenno BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 189792521Sbenno } 1898152180Sgrehan pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1899152180Sgrehan moea_bpvo_pool_index++; 1900103604Sgrehan bootstrap = 1; 190192521Sbenno } 190290643Sbenno 190390643Sbenno if (pvo == NULL) { 1904152180Sgrehan mtx_unlock(&moea_table_mutex); 190590643Sbenno return (ENOMEM); 190690643Sbenno } 190790643Sbenno 1908152180Sgrehan moea_pvo_entries++; 190990643Sbenno pvo->pvo_vaddr = va; 191090643Sbenno pvo->pvo_pmap = pm; 1911152180Sgrehan LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 191290643Sbenno pvo->pvo_vaddr &= ~ADDR_POFF; 191390643Sbenno if (flags & VM_PROT_EXECUTE) 191490643Sbenno pvo->pvo_vaddr |= PVO_EXECUTABLE; 191590643Sbenno if (flags & PVO_WIRED) 191690643Sbenno pvo->pvo_vaddr |= PVO_WIRED; 1917152180Sgrehan if (pvo_head != &moea_pvo_kunmanaged) 191890643Sbenno pvo->pvo_vaddr |= PVO_MANAGED; 1919103604Sgrehan if (bootstrap) 1920103604Sgrehan pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1921142416Sgrehan if (flags & PVO_FAKE) 1922142416Sgrehan pvo->pvo_vaddr |= PVO_FAKE; 1923142416Sgrehan 1924183290Snwhitehorn moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 192590643Sbenno 192690643Sbenno /* 192790643Sbenno * Remember if the list was empty and therefore will be the first 192890643Sbenno * item. 192990643Sbenno */ 193096250Sbenno if (LIST_FIRST(pvo_head) == NULL) 193196250Sbenno first = 1; 1932142416Sgrehan LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 193390643Sbenno 1934183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1935134453Salc pm->pm_stats.wired_count++; 1936134453Salc pm->pm_stats.resident_count++; 193790643Sbenno 193890643Sbenno /* 193990643Sbenno * We hope this succeeds but it isn't required. 194090643Sbenno */ 1941183290Snwhitehorn i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 194290643Sbenno if (i >= 0) { 194390643Sbenno PVO_PTEGIDX_SET(pvo, i); 194490643Sbenno } else { 1945152180Sgrehan panic("moea_pvo_enter: overflow"); 1946152180Sgrehan moea_pte_overflow++; 194790643Sbenno } 1948152180Sgrehan mtx_unlock(&moea_table_mutex); 194990643Sbenno 195090643Sbenno return (first ? ENOENT : 0); 195177957Sbenno} 195277957Sbenno 195390643Sbennostatic void 1954152180Sgrehanmoea_pvo_remove(struct pvo_entry *pvo, int pteidx) 195577957Sbenno{ 195690643Sbenno struct pte *pt; 195777957Sbenno 195890643Sbenno /* 195990643Sbenno * If there is an active pte entry, we need to deactivate it (and 196090643Sbenno * save the ref & cfg bits). 196190643Sbenno */ 1962152180Sgrehan pt = moea_pvo_to_pte(pvo, pteidx); 196390643Sbenno if (pt != NULL) { 1964183290Snwhitehorn moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1965159928Salc mtx_unlock(&moea_table_mutex); 196690643Sbenno PVO_PTEGIDX_CLR(pvo); 196790643Sbenno } else { 1968152180Sgrehan moea_pte_overflow--; 1969142416Sgrehan } 197090643Sbenno 197190643Sbenno /* 197290643Sbenno * Update our statistics. 197390643Sbenno */ 197490643Sbenno pvo->pvo_pmap->pm_stats.resident_count--; 1975183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 197690643Sbenno pvo->pvo_pmap->pm_stats.wired_count--; 197790643Sbenno 197890643Sbenno /* 197990643Sbenno * Save the REF/CHG bits into their cache if the page is managed. 198090643Sbenno */ 1981142416Sgrehan if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 198290643Sbenno struct vm_page *pg; 198390643Sbenno 1984183290Snwhitehorn pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 198590643Sbenno if (pg != NULL) { 1986183290Snwhitehorn moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 198790643Sbenno (PTE_REF | PTE_CHG)); 198890643Sbenno } 198990643Sbenno } 199090643Sbenno 199190643Sbenno /* 199290643Sbenno * Remove this PVO from the PV list. 199390643Sbenno */ 199490643Sbenno LIST_REMOVE(pvo, pvo_vlink); 199590643Sbenno 199690643Sbenno /* 199790643Sbenno * Remove this from the overflow list and return it to the pool 199890643Sbenno * if we aren't going to reuse it. 199990643Sbenno */ 200090643Sbenno LIST_REMOVE(pvo, pvo_olink); 200192521Sbenno if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2002152180Sgrehan uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2003152180Sgrehan moea_upvo_zone, pvo); 2004152180Sgrehan moea_pvo_entries--; 2005152180Sgrehan moea_pvo_remove_calls++; 200677957Sbenno} 200777957Sbenno 200890643Sbennostatic __inline int 2009152180Sgrehanmoea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 201077957Sbenno{ 201190643Sbenno int pteidx; 201277957Sbenno 201390643Sbenno /* 201490643Sbenno * We can find the actual pte entry without searching by grabbing 201590643Sbenno * the PTEG index from 3 unused bits in pte_lo[11:9] and by 201690643Sbenno * noticing the HID bit. 201790643Sbenno */ 201890643Sbenno pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2019183290Snwhitehorn if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2020152180Sgrehan pteidx ^= moea_pteg_mask * 8; 202190643Sbenno 202290643Sbenno return (pteidx); 202377957Sbenno} 202477957Sbenno 202590643Sbennostatic struct pvo_entry * 2026152180Sgrehanmoea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 202777957Sbenno{ 202890643Sbenno struct pvo_entry *pvo; 202990643Sbenno int ptegidx; 203090643Sbenno u_int sr; 203177957Sbenno 203290643Sbenno va &= ~ADDR_POFF; 203390643Sbenno sr = va_to_sr(pm->pm_sr, va); 203490643Sbenno ptegidx = va_to_pteg(sr, va); 203590643Sbenno 2036152180Sgrehan mtx_lock(&moea_table_mutex); 2037152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 203890643Sbenno if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 203990643Sbenno if (pteidx_p) 2040152180Sgrehan *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2041134535Salc break; 204290643Sbenno } 204390643Sbenno } 2044152180Sgrehan mtx_unlock(&moea_table_mutex); 204590643Sbenno 2046134535Salc return (pvo); 204777957Sbenno} 204877957Sbenno 204990643Sbennostatic struct pte * 2050152180Sgrehanmoea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 205177957Sbenno{ 205290643Sbenno struct pte *pt; 205377957Sbenno 205490643Sbenno /* 205590643Sbenno * If we haven't been supplied the ptegidx, calculate it. 205690643Sbenno */ 205790643Sbenno if (pteidx == -1) { 205890643Sbenno int ptegidx; 205990643Sbenno u_int sr; 206077957Sbenno 206190643Sbenno sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 206290643Sbenno ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2063152180Sgrehan pteidx = moea_pvo_pte_index(pvo, ptegidx); 206490643Sbenno } 206590643Sbenno 2066152180Sgrehan pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2067159928Salc mtx_lock(&moea_table_mutex); 206890643Sbenno 2069183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2070152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 207190643Sbenno "valid pte index", pvo); 207290643Sbenno } 207390643Sbenno 2074183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2075152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 207690643Sbenno "pvo but no valid pte", pvo); 207790643Sbenno } 207890643Sbenno 2079183290Snwhitehorn if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2080183290Snwhitehorn if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2081152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte in " 2082152180Sgrehan "moea_pteg_table %p but invalid in pvo", pvo, pt); 208377957Sbenno } 208490643Sbenno 2085183290Snwhitehorn if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 208690643Sbenno != 0) { 2087152180Sgrehan panic("moea_pvo_to_pte: pvo %p pte does not match " 2088152180Sgrehan "pte %p in moea_pteg_table", pvo, pt); 208990643Sbenno } 209090643Sbenno 2091159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 209290643Sbenno return (pt); 209377957Sbenno } 209477957Sbenno 2095183290Snwhitehorn if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2096152180Sgrehan panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2097152180Sgrehan "moea_pteg_table but valid in pvo", pvo, pt); 209890643Sbenno } 209977957Sbenno 2100159928Salc mtx_unlock(&moea_table_mutex); 210190643Sbenno return (NULL); 210277957Sbenno} 210378880Sbenno 210478880Sbenno/* 210590643Sbenno * XXX: THIS STUFF SHOULD BE IN pte.c? 210678880Sbenno */ 210790643Sbennoint 2108152180Sgrehanmoea_pte_spill(vm_offset_t addr) 210978880Sbenno{ 211090643Sbenno struct pvo_entry *source_pvo, *victim_pvo; 211190643Sbenno struct pvo_entry *pvo; 211290643Sbenno int ptegidx, i, j; 211390643Sbenno u_int sr; 211490643Sbenno struct pteg *pteg; 211590643Sbenno struct pte *pt; 211678880Sbenno 2117152180Sgrehan moea_pte_spills++; 211890643Sbenno 211994836Sbenno sr = mfsrin(addr); 212090643Sbenno ptegidx = va_to_pteg(sr, addr); 212190643Sbenno 212278880Sbenno /* 212390643Sbenno * Have to substitute some entry. Use the primary hash for this. 212490643Sbenno * Use low bits of timebase as random generator. 212578880Sbenno */ 2126152180Sgrehan pteg = &moea_pteg_table[ptegidx]; 2127152180Sgrehan mtx_lock(&moea_table_mutex); 212890643Sbenno __asm __volatile("mftb %0" : "=r"(i)); 212990643Sbenno i &= 7; 213090643Sbenno pt = &pteg->pt[i]; 213178880Sbenno 213290643Sbenno source_pvo = NULL; 213390643Sbenno victim_pvo = NULL; 2134152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 213578880Sbenno /* 213690643Sbenno * We need to find a pvo entry for this address. 213778880Sbenno */ 2138152180Sgrehan MOEA_PVO_CHECK(pvo); 213990643Sbenno if (source_pvo == NULL && 2140183290Snwhitehorn moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2141183290Snwhitehorn pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 214290643Sbenno /* 214390643Sbenno * Now found an entry to be spilled into the pteg. 214490643Sbenno * The PTE is now valid, so we know it's active. 214590643Sbenno */ 2146183290Snwhitehorn j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 214778880Sbenno 214890643Sbenno if (j >= 0) { 214990643Sbenno PVO_PTEGIDX_SET(pvo, j); 2150152180Sgrehan moea_pte_overflow--; 2151152180Sgrehan MOEA_PVO_CHECK(pvo); 2152152180Sgrehan mtx_unlock(&moea_table_mutex); 215390643Sbenno return (1); 215490643Sbenno } 215590643Sbenno 215690643Sbenno source_pvo = pvo; 215790643Sbenno 215890643Sbenno if (victim_pvo != NULL) 215990643Sbenno break; 216090643Sbenno } 216190643Sbenno 216278880Sbenno /* 216390643Sbenno * We also need the pvo entry of the victim we are replacing 216490643Sbenno * so save the R & C bits of the PTE. 216578880Sbenno */ 216690643Sbenno if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2167183290Snwhitehorn moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 216890643Sbenno victim_pvo = pvo; 216990643Sbenno if (source_pvo != NULL) 217090643Sbenno break; 217190643Sbenno } 217290643Sbenno } 217378880Sbenno 2174134535Salc if (source_pvo == NULL) { 2175152180Sgrehan mtx_unlock(&moea_table_mutex); 217690643Sbenno return (0); 2177134535Salc } 217890643Sbenno 217990643Sbenno if (victim_pvo == NULL) { 218090643Sbenno if ((pt->pte_hi & PTE_HID) == 0) 2181152180Sgrehan panic("moea_pte_spill: victim p-pte (%p) has no pvo" 218290643Sbenno "entry", pt); 218390643Sbenno 218478880Sbenno /* 218590643Sbenno * If this is a secondary PTE, we need to search it's primary 218690643Sbenno * pvo bucket for the matching PVO. 218778880Sbenno */ 2188152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 218990643Sbenno pvo_olink) { 2190152180Sgrehan MOEA_PVO_CHECK(pvo); 219190643Sbenno /* 219290643Sbenno * We also need the pvo entry of the victim we are 219390643Sbenno * replacing so save the R & C bits of the PTE. 219490643Sbenno */ 2195183290Snwhitehorn if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 219690643Sbenno victim_pvo = pvo; 219790643Sbenno break; 219890643Sbenno } 219990643Sbenno } 220078880Sbenno 220190643Sbenno if (victim_pvo == NULL) 2202152180Sgrehan panic("moea_pte_spill: victim s-pte (%p) has no pvo" 220390643Sbenno "entry", pt); 220490643Sbenno } 220578880Sbenno 220690643Sbenno /* 220790643Sbenno * We are invalidating the TLB entry for the EA we are replacing even 220890643Sbenno * though it's valid. If we don't, we lose any ref/chg bit changes 220990643Sbenno * contained in the TLB entry. 221090643Sbenno */ 2211183290Snwhitehorn source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 221278880Sbenno 2213183290Snwhitehorn moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2214183290Snwhitehorn moea_pte_set(pt, &source_pvo->pvo_pte.pte); 221590643Sbenno 221690643Sbenno PVO_PTEGIDX_CLR(victim_pvo); 221790643Sbenno PVO_PTEGIDX_SET(source_pvo, i); 2218152180Sgrehan moea_pte_replacements++; 221990643Sbenno 2220152180Sgrehan MOEA_PVO_CHECK(victim_pvo); 2221152180Sgrehan MOEA_PVO_CHECK(source_pvo); 222290643Sbenno 2223152180Sgrehan mtx_unlock(&moea_table_mutex); 222490643Sbenno return (1); 222590643Sbenno} 222690643Sbenno 222790643Sbennostatic int 2228152180Sgrehanmoea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 222990643Sbenno{ 223090643Sbenno struct pte *pt; 223190643Sbenno int i; 223290643Sbenno 2233159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 2234159928Salc 223590643Sbenno /* 223690643Sbenno * First try primary hash. 223790643Sbenno */ 2238152180Sgrehan for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 223990643Sbenno if ((pt->pte_hi & PTE_VALID) == 0) { 224090643Sbenno pvo_pt->pte_hi &= ~PTE_HID; 2241152180Sgrehan moea_pte_set(pt, pvo_pt); 224290643Sbenno return (i); 224378880Sbenno } 224490643Sbenno } 224578880Sbenno 224690643Sbenno /* 224790643Sbenno * Now try secondary hash. 224890643Sbenno */ 2249152180Sgrehan ptegidx ^= moea_pteg_mask; 2250165362Sgrehan 2251152180Sgrehan for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 225290643Sbenno if ((pt->pte_hi & PTE_VALID) == 0) { 225390643Sbenno pvo_pt->pte_hi |= PTE_HID; 2254152180Sgrehan moea_pte_set(pt, pvo_pt); 225590643Sbenno return (i); 225690643Sbenno } 225790643Sbenno } 225878880Sbenno 2259152180Sgrehan panic("moea_pte_insert: overflow"); 226090643Sbenno return (-1); 226178880Sbenno} 226284921Sbenno 226390643Sbennostatic boolean_t 2264152180Sgrehanmoea_query_bit(vm_page_t m, int ptebit) 226584921Sbenno{ 226690643Sbenno struct pvo_entry *pvo; 226790643Sbenno struct pte *pt; 226884921Sbenno 2269152180Sgrehan if (moea_attr_fetch(m) & ptebit) 227090643Sbenno return (TRUE); 227184921Sbenno 2272208574Salc vm_page_lock_queues(); 227390643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2274152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 227584921Sbenno 227690643Sbenno /* 227790643Sbenno * See if we saved the bit off. If so, cache it and return 227890643Sbenno * success. 227990643Sbenno */ 2280183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2281152180Sgrehan moea_attr_save(m, ptebit); 2282152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2283208574Salc vm_page_unlock_queues(); 228490643Sbenno return (TRUE); 228590643Sbenno } 228690643Sbenno } 228784921Sbenno 228890643Sbenno /* 228990643Sbenno * No luck, now go through the hard part of looking at the PTEs 229090643Sbenno * themselves. Sync so that any pending REF/CHG bits are flushed to 229190643Sbenno * the PTEs. 229290643Sbenno */ 2293183094Smarcel powerpc_sync(); 229490643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2295152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 229690643Sbenno 229790643Sbenno /* 229890643Sbenno * See if this pvo has a valid PTE. if so, fetch the 229990643Sbenno * REF/CHG bits from the valid PTE. If the appropriate 230090643Sbenno * ptebit is set, cache it and return success. 230190643Sbenno */ 2302152180Sgrehan pt = moea_pvo_to_pte(pvo, -1); 230390643Sbenno if (pt != NULL) { 2304183290Snwhitehorn moea_pte_synch(pt, &pvo->pvo_pte.pte); 2305159928Salc mtx_unlock(&moea_table_mutex); 2306183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2307152180Sgrehan moea_attr_save(m, ptebit); 2308152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2309208574Salc vm_page_unlock_queues(); 231090643Sbenno return (TRUE); 231190643Sbenno } 231290643Sbenno } 231384921Sbenno } 231484921Sbenno 2315208574Salc vm_page_unlock_queues(); 2316123354Sgallatin return (FALSE); 231784921Sbenno} 231890643Sbenno 2319110172Sgrehanstatic u_int 2320208990Salcmoea_clear_bit(vm_page_t m, int ptebit) 232190643Sbenno{ 2322110172Sgrehan u_int count; 232390643Sbenno struct pvo_entry *pvo; 232490643Sbenno struct pte *pt; 232590643Sbenno 2326208990Salc vm_page_lock_queues(); 2327208990Salc 232890643Sbenno /* 232990643Sbenno * Clear the cached value. 233090643Sbenno */ 2331152180Sgrehan moea_attr_clear(m, ptebit); 233290643Sbenno 233390643Sbenno /* 233490643Sbenno * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 233590643Sbenno * we can reset the right ones). note that since the pvo entries and 233690643Sbenno * list heads are accessed via BAT0 and are never placed in the page 233790643Sbenno * table, we don't have to worry about further accesses setting the 233890643Sbenno * REF/CHG bits. 233990643Sbenno */ 2340183094Smarcel powerpc_sync(); 234190643Sbenno 234290643Sbenno /* 234390643Sbenno * For each pvo entry, clear the pvo's ptebit. If this pvo has a 234490643Sbenno * valid pte clear the ptebit from the valid pte. 234590643Sbenno */ 2346110172Sgrehan count = 0; 234790643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2348152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2349152180Sgrehan pt = moea_pvo_to_pte(pvo, -1); 235090643Sbenno if (pt != NULL) { 2351183290Snwhitehorn moea_pte_synch(pt, &pvo->pvo_pte.pte); 2352183290Snwhitehorn if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2353110172Sgrehan count++; 2354152180Sgrehan moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2355110172Sgrehan } 2356159928Salc mtx_unlock(&moea_table_mutex); 235790643Sbenno } 2358183290Snwhitehorn pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2359152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 236090643Sbenno } 236190643Sbenno 2362208990Salc vm_page_unlock_queues(); 2363110172Sgrehan return (count); 236490643Sbenno} 236599038Sbenno 236699038Sbenno/* 2367103604Sgrehan * Return true if the physical range is encompassed by the battable[idx] 2368103604Sgrehan */ 2369103604Sgrehanstatic int 2370152180Sgrehanmoea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2371103604Sgrehan{ 2372103604Sgrehan u_int prot; 2373103604Sgrehan u_int32_t start; 2374103604Sgrehan u_int32_t end; 2375103604Sgrehan u_int32_t bat_ble; 2376103604Sgrehan 2377103604Sgrehan /* 2378103604Sgrehan * Return immediately if not a valid mapping 2379103604Sgrehan */ 2380103604Sgrehan if (!battable[idx].batu & BAT_Vs) 2381103604Sgrehan return (EINVAL); 2382103604Sgrehan 2383103604Sgrehan /* 2384103604Sgrehan * The BAT entry must be cache-inhibited, guarded, and r/w 2385103604Sgrehan * so it can function as an i/o page 2386103604Sgrehan */ 2387103604Sgrehan prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2388103604Sgrehan if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2389103604Sgrehan return (EPERM); 2390103604Sgrehan 2391103604Sgrehan /* 2392103604Sgrehan * The address should be within the BAT range. Assume that the 2393103604Sgrehan * start address in the BAT has the correct alignment (thus 2394103604Sgrehan * not requiring masking) 2395103604Sgrehan */ 2396103604Sgrehan start = battable[idx].batl & BAT_PBS; 2397103604Sgrehan bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2398103604Sgrehan end = start | (bat_ble << 15) | 0x7fff; 2399103604Sgrehan 2400103604Sgrehan if ((pa < start) || ((pa + size) > end)) 2401103604Sgrehan return (ERANGE); 2402103604Sgrehan 2403103604Sgrehan return (0); 2404103604Sgrehan} 2405103604Sgrehan 2406152180Sgrehanboolean_t 2407152180Sgrehanmoea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2408133855Sssouhlal{ 2409133855Sssouhlal int i; 2410103604Sgrehan 2411133855Sssouhlal /* 2412133855Sssouhlal * This currently does not work for entries that 2413133855Sssouhlal * overlap 256M BAT segments. 2414133855Sssouhlal */ 2415133855Sssouhlal 2416133855Sssouhlal for(i = 0; i < 16; i++) 2417152180Sgrehan if (moea_bat_mapped(i, pa, size) == 0) 2418133855Sssouhlal return (0); 2419133855Sssouhlal 2420133855Sssouhlal return (EFAULT); 2421133855Sssouhlal} 2422133855Sssouhlal 2423103604Sgrehan/* 242499038Sbenno * Map a set of physical memory pages into the kernel virtual 242599038Sbenno * address space. Return a pointer to where it is mapped. This 242699038Sbenno * routine is intended to be used for mapping device memory, 242799038Sbenno * NOT real memory. 242899038Sbenno */ 242999038Sbennovoid * 2430152180Sgrehanmoea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 243199038Sbenno{ 2432103604Sgrehan vm_offset_t va, tmpva, ppa, offset; 2433103604Sgrehan int i; 2434103604Sgrehan 2435103604Sgrehan ppa = trunc_page(pa); 243699038Sbenno offset = pa & PAGE_MASK; 243799038Sbenno size = roundup(offset + size, PAGE_SIZE); 243899038Sbenno 243999038Sbenno GIANT_REQUIRED; 244099038Sbenno 2441103604Sgrehan /* 2442103604Sgrehan * If the physical address lies within a valid BAT table entry, 2443103604Sgrehan * return the 1:1 mapping. This currently doesn't work 2444103604Sgrehan * for regions that overlap 256M BAT segments. 2445103604Sgrehan */ 2446103604Sgrehan for (i = 0; i < 16; i++) { 2447152180Sgrehan if (moea_bat_mapped(i, pa, size) == 0) 2448103604Sgrehan return ((void *) pa); 2449103604Sgrehan } 2450103604Sgrehan 2451118365Salc va = kmem_alloc_nofault(kernel_map, size); 245299038Sbenno if (!va) 2453152180Sgrehan panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 245499038Sbenno 245599038Sbenno for (tmpva = va; size > 0;) { 2456152180Sgrehan moea_kenter(mmu, tmpva, ppa); 2457183094Smarcel tlbie(tmpva); 245899038Sbenno size -= PAGE_SIZE; 245999038Sbenno tmpva += PAGE_SIZE; 2460103604Sgrehan ppa += PAGE_SIZE; 246199038Sbenno } 246299038Sbenno 246399038Sbenno return ((void *)(va + offset)); 246499038Sbenno} 246599038Sbenno 246699038Sbennovoid 2467152180Sgrehanmoea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 246899038Sbenno{ 246999038Sbenno vm_offset_t base, offset; 247099038Sbenno 2471103604Sgrehan /* 2472103604Sgrehan * If this is outside kernel virtual space, then it's a 2473103604Sgrehan * battable entry and doesn't require unmapping 2474103604Sgrehan */ 2475204128Snwhitehorn if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2476103604Sgrehan base = trunc_page(va); 2477103604Sgrehan offset = va & PAGE_MASK; 2478103604Sgrehan size = roundup(offset + size, PAGE_SIZE); 2479103604Sgrehan kmem_free(kernel_map, base, size); 2480103604Sgrehan } 248199038Sbenno} 2482198341Smarcel 2483198341Smarcelstatic void 2484198341Smarcelmoea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2485198341Smarcel{ 2486198341Smarcel struct pvo_entry *pvo; 2487198341Smarcel vm_offset_t lim; 2488198341Smarcel vm_paddr_t pa; 2489198341Smarcel vm_size_t len; 2490198341Smarcel 2491198341Smarcel PMAP_LOCK(pm); 2492198341Smarcel while (sz > 0) { 2493198341Smarcel lim = round_page(va); 2494198341Smarcel len = MIN(lim - va, sz); 2495198341Smarcel pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2496198341Smarcel if (pvo != NULL) { 2497198341Smarcel pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2498198341Smarcel (va & ADDR_POFF); 2499198341Smarcel moea_syncicache(pa, len); 2500198341Smarcel } 2501198341Smarcel va += len; 2502198341Smarcel sz -= len; 2503198341Smarcel } 2504198341Smarcel PMAP_UNLOCK(pm); 2505198341Smarcel} 2506