mmu_oea.c revision 208810
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 208810 2010-06-05 06:56:06Z alc $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <dev/ofw/openfirm.h> 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/platform.h> 145#include <machine/bat.h> 146#include <machine/frame.h> 147#include <machine/md_var.h> 148#include <machine/psl.h> 149#include <machine/pte.h> 150#include <machine/smp.h> 151#include <machine/sr.h> 152#include <machine/mmuvar.h> 153 154#include "mmu_if.h" 155 156#define MOEA_DEBUG 157 158#define TODO panic("%s: not implemented", __func__); 159 160#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 161#define VSID_TO_SR(vsid) ((vsid) & 0xf) 162#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163 164#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 165#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 166#define PVO_WIRED 0x010 /* PVO entry is wired */ 167#define PVO_MANAGED 0x020 /* PVO entry is managed */ 168#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 169#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 170 bootstrap */ 171#define PVO_FAKE 0x100 /* fictitious phys page */ 172#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 173#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 174#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 175#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 176#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 177#define PVO_PTEGIDX_CLR(pvo) \ 178 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 179#define PVO_PTEGIDX_SET(pvo, i) \ 180 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 181 182#define MOEA_PVO_CHECK(pvo) 183 184struct ofw_map { 185 vm_offset_t om_va; 186 vm_size_t om_len; 187 vm_offset_t om_pa; 188 u_int om_mode; 189}; 190 191/* 192 * Map of physical memory regions. 193 */ 194static struct mem_region *regions; 195static struct mem_region *pregions; 196u_int phys_avail_count; 197int regions_sz, pregions_sz; 198static struct ofw_map *translations; 199 200extern struct pmap ofw_pmap; 201 202/* 203 * Lock for the pteg and pvo tables. 204 */ 205struct mtx moea_table_mutex; 206 207/* tlbie instruction synchronization */ 208static struct mtx tlbie_mtx; 209 210/* 211 * PTEG data. 212 */ 213static struct pteg *moea_pteg_table; 214u_int moea_pteg_count; 215u_int moea_pteg_mask; 216 217/* 218 * PVO data. 219 */ 220struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 221struct pvo_head moea_pvo_kunmanaged = 222 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 223struct pvo_head moea_pvo_unmanaged = 224 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 225 226uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 227uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 228 229#define BPVO_POOL_SIZE 32768 230static struct pvo_entry *moea_bpvo_pool; 231static int moea_bpvo_pool_index = 0; 232 233#define VSID_NBPW (sizeof(u_int32_t) * 8) 234static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 235 236static boolean_t moea_initialized = FALSE; 237 238/* 239 * Statistics. 240 */ 241u_int moea_pte_valid = 0; 242u_int moea_pte_overflow = 0; 243u_int moea_pte_replacements = 0; 244u_int moea_pvo_entries = 0; 245u_int moea_pvo_enter_calls = 0; 246u_int moea_pvo_remove_calls = 0; 247u_int moea_pte_spills = 0; 248SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 249 0, ""); 250SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 251 &moea_pte_overflow, 0, ""); 252SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 253 &moea_pte_replacements, 0, ""); 254SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 255 0, ""); 256SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 257 &moea_pvo_enter_calls, 0, ""); 258SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 259 &moea_pvo_remove_calls, 0, ""); 260SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 261 &moea_pte_spills, 0, ""); 262 263/* 264 * Allocate physical memory for use in moea_bootstrap. 265 */ 266static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 267 268/* 269 * PTE calls. 270 */ 271static int moea_pte_insert(u_int, struct pte *); 272 273/* 274 * PVO calls. 275 */ 276static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 277 vm_offset_t, vm_offset_t, u_int, int); 278static void moea_pvo_remove(struct pvo_entry *, int); 279static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 280static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 281 282/* 283 * Utility routines. 284 */ 285static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 286 vm_prot_t, boolean_t); 287static void moea_syncicache(vm_offset_t, vm_size_t); 288static boolean_t moea_query_bit(vm_page_t, int); 289static u_int moea_clear_bit(vm_page_t, int, int *); 290static void moea_kremove(mmu_t, vm_offset_t); 291int moea_pte_spill(vm_offset_t); 292 293/* 294 * Kernel MMU interface 295 */ 296void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 297void moea_clear_modify(mmu_t, vm_page_t); 298void moea_clear_reference(mmu_t, vm_page_t); 299void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 300void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 301void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 302 vm_prot_t); 303void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 304vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 305vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 306void moea_init(mmu_t); 307boolean_t moea_is_modified(mmu_t, vm_page_t); 308boolean_t moea_is_referenced(mmu_t, vm_page_t); 309boolean_t moea_ts_referenced(mmu_t, vm_page_t); 310vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 311boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 312int moea_page_wired_mappings(mmu_t, vm_page_t); 313void moea_pinit(mmu_t, pmap_t); 314void moea_pinit0(mmu_t, pmap_t); 315void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 316void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 317void moea_qremove(mmu_t, vm_offset_t, int); 318void moea_release(mmu_t, pmap_t); 319void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 320void moea_remove_all(mmu_t, vm_page_t); 321void moea_remove_write(mmu_t, vm_page_t); 322void moea_zero_page(mmu_t, vm_page_t); 323void moea_zero_page_area(mmu_t, vm_page_t, int, int); 324void moea_zero_page_idle(mmu_t, vm_page_t); 325void moea_activate(mmu_t, struct thread *); 326void moea_deactivate(mmu_t, struct thread *); 327void moea_cpu_bootstrap(mmu_t, int); 328void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 329void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 330void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 331vm_offset_t moea_kextract(mmu_t, vm_offset_t); 332void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 333boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 334static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 335 336static mmu_method_t moea_methods[] = { 337 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 338 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 339 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 340 MMUMETHOD(mmu_copy_page, moea_copy_page), 341 MMUMETHOD(mmu_enter, moea_enter), 342 MMUMETHOD(mmu_enter_object, moea_enter_object), 343 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 344 MMUMETHOD(mmu_extract, moea_extract), 345 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 346 MMUMETHOD(mmu_init, moea_init), 347 MMUMETHOD(mmu_is_modified, moea_is_modified), 348 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 350 MMUMETHOD(mmu_map, moea_map), 351 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 352 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 353 MMUMETHOD(mmu_pinit, moea_pinit), 354 MMUMETHOD(mmu_pinit0, moea_pinit0), 355 MMUMETHOD(mmu_protect, moea_protect), 356 MMUMETHOD(mmu_qenter, moea_qenter), 357 MMUMETHOD(mmu_qremove, moea_qremove), 358 MMUMETHOD(mmu_release, moea_release), 359 MMUMETHOD(mmu_remove, moea_remove), 360 MMUMETHOD(mmu_remove_all, moea_remove_all), 361 MMUMETHOD(mmu_remove_write, moea_remove_write), 362 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 363 MMUMETHOD(mmu_zero_page, moea_zero_page), 364 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 365 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 366 MMUMETHOD(mmu_activate, moea_activate), 367 MMUMETHOD(mmu_deactivate, moea_deactivate), 368 369 /* Internal interfaces */ 370 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 371 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 372 MMUMETHOD(mmu_mapdev, moea_mapdev), 373 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 374 MMUMETHOD(mmu_kextract, moea_kextract), 375 MMUMETHOD(mmu_kenter, moea_kenter), 376 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 377 378 { 0, 0 } 379}; 380 381static mmu_def_t oea_mmu = { 382 MMU_TYPE_OEA, 383 moea_methods, 384 0 385}; 386MMU_DEF(oea_mmu); 387 388static void 389tlbie(vm_offset_t va) 390{ 391 392 mtx_lock_spin(&tlbie_mtx); 393 __asm __volatile("tlbie %0" :: "r"(va)); 394 __asm __volatile("tlbsync"); 395 powerpc_sync(); 396 mtx_unlock_spin(&tlbie_mtx); 397} 398 399static void 400tlbia(void) 401{ 402 vm_offset_t va; 403 404 for (va = 0; va < 0x00040000; va += 0x00001000) { 405 __asm __volatile("tlbie %0" :: "r"(va)); 406 powerpc_sync(); 407 } 408 __asm __volatile("tlbsync"); 409 powerpc_sync(); 410} 411 412static __inline int 413va_to_sr(u_int *sr, vm_offset_t va) 414{ 415 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 416} 417 418static __inline u_int 419va_to_pteg(u_int sr, vm_offset_t addr) 420{ 421 u_int hash; 422 423 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 424 ADDR_PIDX_SHFT); 425 return (hash & moea_pteg_mask); 426} 427 428static __inline struct pvo_head * 429pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 430{ 431 struct vm_page *pg; 432 433 pg = PHYS_TO_VM_PAGE(pa); 434 435 if (pg_p != NULL) 436 *pg_p = pg; 437 438 if (pg == NULL) 439 return (&moea_pvo_unmanaged); 440 441 return (&pg->md.mdpg_pvoh); 442} 443 444static __inline struct pvo_head * 445vm_page_to_pvoh(vm_page_t m) 446{ 447 448 return (&m->md.mdpg_pvoh); 449} 450 451static __inline void 452moea_attr_clear(vm_page_t m, int ptebit) 453{ 454 455 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 456 m->md.mdpg_attrs &= ~ptebit; 457} 458 459static __inline int 460moea_attr_fetch(vm_page_t m) 461{ 462 463 return (m->md.mdpg_attrs); 464} 465 466static __inline void 467moea_attr_save(vm_page_t m, int ptebit) 468{ 469 470 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 471 m->md.mdpg_attrs |= ptebit; 472} 473 474static __inline int 475moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 476{ 477 if (pt->pte_hi == pvo_pt->pte_hi) 478 return (1); 479 480 return (0); 481} 482 483static __inline int 484moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 485{ 486 return (pt->pte_hi & ~PTE_VALID) == 487 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 488 ((va >> ADDR_API_SHFT) & PTE_API) | which); 489} 490 491static __inline void 492moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 493{ 494 495 mtx_assert(&moea_table_mutex, MA_OWNED); 496 497 /* 498 * Construct a PTE. Default to IMB initially. Valid bit only gets 499 * set when the real pte is set in memory. 500 * 501 * Note: Don't set the valid bit for correct operation of tlb update. 502 */ 503 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 504 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 505 pt->pte_lo = pte_lo; 506} 507 508static __inline void 509moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 510{ 511 512 mtx_assert(&moea_table_mutex, MA_OWNED); 513 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 514} 515 516static __inline void 517moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 518{ 519 520 mtx_assert(&moea_table_mutex, MA_OWNED); 521 522 /* 523 * As shown in Section 7.6.3.2.3 524 */ 525 pt->pte_lo &= ~ptebit; 526 tlbie(va); 527} 528 529static __inline void 530moea_pte_set(struct pte *pt, struct pte *pvo_pt) 531{ 532 533 mtx_assert(&moea_table_mutex, MA_OWNED); 534 pvo_pt->pte_hi |= PTE_VALID; 535 536 /* 537 * Update the PTE as defined in section 7.6.3.1. 538 * Note that the REF/CHG bits are from pvo_pt and thus should havce 539 * been saved so this routine can restore them (if desired). 540 */ 541 pt->pte_lo = pvo_pt->pte_lo; 542 powerpc_sync(); 543 pt->pte_hi = pvo_pt->pte_hi; 544 powerpc_sync(); 545 moea_pte_valid++; 546} 547 548static __inline void 549moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 550{ 551 552 mtx_assert(&moea_table_mutex, MA_OWNED); 553 pvo_pt->pte_hi &= ~PTE_VALID; 554 555 /* 556 * Force the reg & chg bits back into the PTEs. 557 */ 558 powerpc_sync(); 559 560 /* 561 * Invalidate the pte. 562 */ 563 pt->pte_hi &= ~PTE_VALID; 564 565 tlbie(va); 566 567 /* 568 * Save the reg & chg bits. 569 */ 570 moea_pte_synch(pt, pvo_pt); 571 moea_pte_valid--; 572} 573 574static __inline void 575moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 576{ 577 578 /* 579 * Invalidate the PTE 580 */ 581 moea_pte_unset(pt, pvo_pt, va); 582 moea_pte_set(pt, pvo_pt); 583} 584 585/* 586 * Quick sort callout for comparing memory regions. 587 */ 588static int mr_cmp(const void *a, const void *b); 589static int om_cmp(const void *a, const void *b); 590 591static int 592mr_cmp(const void *a, const void *b) 593{ 594 const struct mem_region *regiona; 595 const struct mem_region *regionb; 596 597 regiona = a; 598 regionb = b; 599 if (regiona->mr_start < regionb->mr_start) 600 return (-1); 601 else if (regiona->mr_start > regionb->mr_start) 602 return (1); 603 else 604 return (0); 605} 606 607static int 608om_cmp(const void *a, const void *b) 609{ 610 const struct ofw_map *mapa; 611 const struct ofw_map *mapb; 612 613 mapa = a; 614 mapb = b; 615 if (mapa->om_pa < mapb->om_pa) 616 return (-1); 617 else if (mapa->om_pa > mapb->om_pa) 618 return (1); 619 else 620 return (0); 621} 622 623void 624moea_cpu_bootstrap(mmu_t mmup, int ap) 625{ 626 u_int sdr; 627 int i; 628 629 if (ap) { 630 powerpc_sync(); 631 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 632 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 633 isync(); 634 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 635 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 636 isync(); 637 } 638 639 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 640 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 641 isync(); 642 643 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 644 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 645 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 646 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 647 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 648 isync(); 649 650 for (i = 0; i < 16; i++) 651 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 652 653 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 654 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 655 powerpc_sync(); 656 657 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 658 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 659 isync(); 660 661 tlbia(); 662} 663 664void 665moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 666{ 667 ihandle_t mmui; 668 phandle_t chosen, mmu; 669 int sz; 670 int i, j; 671 int ofw_mappings; 672 vm_size_t size, physsz, hwphyssz; 673 vm_offset_t pa, va, off; 674 void *dpcpu; 675 676 /* 677 * Set up BAT0 to map the lowest 256 MB area 678 */ 679 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 680 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 681 682 /* 683 * Map PCI memory space. 684 */ 685 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 686 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 687 688 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 689 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 690 691 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 692 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 693 694 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 695 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 696 697 /* 698 * Map obio devices. 699 */ 700 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 701 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 702 703 /* 704 * Use an IBAT and a DBAT to map the bottom segment of memory 705 * where we are. 706 */ 707 __asm (".balign 32; \n" 708 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 709 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 710 :: "r"(battable[0].batu), "r"(battable[0].batl)); 711 712 /* map pci space */ 713 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 714 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 715 isync(); 716 717 /* set global direct map flag */ 718 hw_direct_map = 1; 719 720 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 721 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 722 723 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 724 for (i = 0; i < pregions_sz; i++) { 725 vm_offset_t pa; 726 vm_offset_t end; 727 728 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 729 pregions[i].mr_start, 730 pregions[i].mr_start + pregions[i].mr_size, 731 pregions[i].mr_size); 732 /* 733 * Install entries into the BAT table to allow all 734 * of physmem to be convered by on-demand BAT entries. 735 * The loop will sometimes set the same battable element 736 * twice, but that's fine since they won't be used for 737 * a while yet. 738 */ 739 pa = pregions[i].mr_start & 0xf0000000; 740 end = pregions[i].mr_start + pregions[i].mr_size; 741 do { 742 u_int n = pa >> ADDR_SR_SHFT; 743 744 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 745 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 746 pa += SEGMENT_LENGTH; 747 } while (pa < end); 748 } 749 750 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 751 panic("moea_bootstrap: phys_avail too small"); 752 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 753 phys_avail_count = 0; 754 physsz = 0; 755 hwphyssz = 0; 756 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 757 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 758 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 759 regions[i].mr_start + regions[i].mr_size, 760 regions[i].mr_size); 761 if (hwphyssz != 0 && 762 (physsz + regions[i].mr_size) >= hwphyssz) { 763 if (physsz < hwphyssz) { 764 phys_avail[j] = regions[i].mr_start; 765 phys_avail[j + 1] = regions[i].mr_start + 766 hwphyssz - physsz; 767 physsz = hwphyssz; 768 phys_avail_count++; 769 } 770 break; 771 } 772 phys_avail[j] = regions[i].mr_start; 773 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 774 phys_avail_count++; 775 physsz += regions[i].mr_size; 776 } 777 physmem = btoc(physsz); 778 779 /* 780 * Allocate PTEG table. 781 */ 782#ifdef PTEGCOUNT 783 moea_pteg_count = PTEGCOUNT; 784#else 785 moea_pteg_count = 0x1000; 786 787 while (moea_pteg_count < physmem) 788 moea_pteg_count <<= 1; 789 790 moea_pteg_count >>= 1; 791#endif /* PTEGCOUNT */ 792 793 size = moea_pteg_count * sizeof(struct pteg); 794 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 795 size); 796 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 797 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 798 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 799 moea_pteg_mask = moea_pteg_count - 1; 800 801 /* 802 * Allocate pv/overflow lists. 803 */ 804 size = sizeof(struct pvo_head) * moea_pteg_count; 805 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 806 PAGE_SIZE); 807 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 808 for (i = 0; i < moea_pteg_count; i++) 809 LIST_INIT(&moea_pvo_table[i]); 810 811 /* 812 * Initialize the lock that synchronizes access to the pteg and pvo 813 * tables. 814 */ 815 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 816 MTX_RECURSE); 817 818 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 819 820 /* 821 * Initialise the unmanaged pvo pool. 822 */ 823 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 824 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 825 moea_bpvo_pool_index = 0; 826 827 /* 828 * Make sure kernel vsid is allocated as well as VSID 0. 829 */ 830 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 831 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 832 moea_vsid_bitmap[0] |= 1; 833 834 /* 835 * Set up the Open Firmware pmap and add it's mappings. 836 */ 837 moea_pinit(mmup, &ofw_pmap); 838 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 839 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 840 if ((chosen = OF_finddevice("/chosen")) == -1) 841 panic("moea_bootstrap: can't find /chosen"); 842 OF_getprop(chosen, "mmu", &mmui, 4); 843 if ((mmu = OF_instance_to_package(mmui)) == -1) 844 panic("moea_bootstrap: can't get mmu package"); 845 if ((sz = OF_getproplen(mmu, "translations")) == -1) 846 panic("moea_bootstrap: can't get ofw translation count"); 847 translations = NULL; 848 for (i = 0; phys_avail[i] != 0; i += 2) { 849 if (phys_avail[i + 1] >= sz) { 850 translations = (struct ofw_map *)phys_avail[i]; 851 break; 852 } 853 } 854 if (translations == NULL) 855 panic("moea_bootstrap: no space to copy translations"); 856 bzero(translations, sz); 857 if (OF_getprop(mmu, "translations", translations, sz) == -1) 858 panic("moea_bootstrap: can't get ofw translations"); 859 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 860 sz /= sizeof(*translations); 861 qsort(translations, sz, sizeof (*translations), om_cmp); 862 for (i = 0, ofw_mappings = 0; i < sz; i++) { 863 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 864 translations[i].om_pa, translations[i].om_va, 865 translations[i].om_len); 866 867 /* 868 * If the mapping is 1:1, let the RAM and device on-demand 869 * BAT tables take care of the translation. 870 */ 871 if (translations[i].om_va == translations[i].om_pa) 872 continue; 873 874 /* Enter the pages */ 875 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 876 struct vm_page m; 877 878 m.phys_addr = translations[i].om_pa + off; 879 m.oflags = VPO_BUSY; 880 PMAP_LOCK(&ofw_pmap); 881 moea_enter_locked(&ofw_pmap, 882 translations[i].om_va + off, &m, 883 VM_PROT_ALL, 1); 884 PMAP_UNLOCK(&ofw_pmap); 885 ofw_mappings++; 886 } 887 } 888 889 /* 890 * Calculate the last available physical address. 891 */ 892 for (i = 0; phys_avail[i + 2] != 0; i += 2) 893 ; 894 Maxmem = powerpc_btop(phys_avail[i + 1]); 895 896 /* 897 * Initialize the kernel pmap (which is statically allocated). 898 */ 899 PMAP_LOCK_INIT(kernel_pmap); 900 for (i = 0; i < 16; i++) { 901 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 902 } 903 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 904 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 905 kernel_pmap->pm_active = ~0; 906 907 moea_cpu_bootstrap(mmup,0); 908 909 pmap_bootstrapped++; 910 911 /* 912 * Set the start and end of kva. 913 */ 914 virtual_avail = VM_MIN_KERNEL_ADDRESS; 915 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 916 917 /* 918 * Allocate a kernel stack with a guard page for thread0 and map it 919 * into the kernel page map. 920 */ 921 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 922 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 923 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 924 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 925 thread0.td_kstack = va; 926 thread0.td_kstack_pages = KSTACK_PAGES; 927 for (i = 0; i < KSTACK_PAGES; i++) { 928 moea_kenter(mmup, va, pa); 929 pa += PAGE_SIZE; 930 va += PAGE_SIZE; 931 } 932 933 /* 934 * Allocate virtual address space for the message buffer. 935 */ 936 pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 937 msgbufp = (struct msgbuf *)virtual_avail; 938 va = virtual_avail; 939 virtual_avail += round_page(MSGBUF_SIZE); 940 while (va < virtual_avail) { 941 moea_kenter(mmup, va, pa); 942 pa += PAGE_SIZE; 943 va += PAGE_SIZE; 944 } 945 946 /* 947 * Allocate virtual address space for the dynamic percpu area. 948 */ 949 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 950 dpcpu = (void *)virtual_avail; 951 va = virtual_avail; 952 virtual_avail += DPCPU_SIZE; 953 while (va < virtual_avail) { 954 moea_kenter(mmup, va, pa); 955 pa += PAGE_SIZE; 956 va += PAGE_SIZE; 957 } 958 dpcpu_init(dpcpu, 0); 959} 960 961/* 962 * Activate a user pmap. The pmap must be activated before it's address 963 * space can be accessed in any way. 964 */ 965void 966moea_activate(mmu_t mmu, struct thread *td) 967{ 968 pmap_t pm, pmr; 969 970 /* 971 * Load all the data we need up front to encourage the compiler to 972 * not issue any loads while we have interrupts disabled below. 973 */ 974 pm = &td->td_proc->p_vmspace->vm_pmap; 975 pmr = pm->pmap_phys; 976 977 pm->pm_active |= PCPU_GET(cpumask); 978 PCPU_SET(curpmap, pmr); 979} 980 981void 982moea_deactivate(mmu_t mmu, struct thread *td) 983{ 984 pmap_t pm; 985 986 pm = &td->td_proc->p_vmspace->vm_pmap; 987 pm->pm_active &= ~PCPU_GET(cpumask); 988 PCPU_SET(curpmap, NULL); 989} 990 991void 992moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 993{ 994 struct pvo_entry *pvo; 995 996 PMAP_LOCK(pm); 997 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 998 999 if (pvo != NULL) { 1000 if (wired) { 1001 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1002 pm->pm_stats.wired_count++; 1003 pvo->pvo_vaddr |= PVO_WIRED; 1004 } else { 1005 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1006 pm->pm_stats.wired_count--; 1007 pvo->pvo_vaddr &= ~PVO_WIRED; 1008 } 1009 } 1010 PMAP_UNLOCK(pm); 1011} 1012 1013void 1014moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1015{ 1016 vm_offset_t dst; 1017 vm_offset_t src; 1018 1019 dst = VM_PAGE_TO_PHYS(mdst); 1020 src = VM_PAGE_TO_PHYS(msrc); 1021 1022 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1023} 1024 1025/* 1026 * Zero a page of physical memory by temporarily mapping it into the tlb. 1027 */ 1028void 1029moea_zero_page(mmu_t mmu, vm_page_t m) 1030{ 1031 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1032 void *va = (void *)pa; 1033 1034 bzero(va, PAGE_SIZE); 1035} 1036 1037void 1038moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1039{ 1040 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1041 void *va = (void *)(pa + off); 1042 1043 bzero(va, size); 1044} 1045 1046void 1047moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1048{ 1049 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1050 void *va = (void *)pa; 1051 1052 bzero(va, PAGE_SIZE); 1053} 1054 1055/* 1056 * Map the given physical page at the specified virtual address in the 1057 * target pmap with the protection requested. If specified the page 1058 * will be wired down. 1059 */ 1060void 1061moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1062 boolean_t wired) 1063{ 1064 1065 vm_page_lock_queues(); 1066 PMAP_LOCK(pmap); 1067 moea_enter_locked(pmap, va, m, prot, wired); 1068 vm_page_unlock_queues(); 1069 PMAP_UNLOCK(pmap); 1070} 1071 1072/* 1073 * Map the given physical page at the specified virtual address in the 1074 * target pmap with the protection requested. If specified the page 1075 * will be wired down. 1076 * 1077 * The page queues and pmap must be locked. 1078 */ 1079static void 1080moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1081 boolean_t wired) 1082{ 1083 struct pvo_head *pvo_head; 1084 uma_zone_t zone; 1085 vm_page_t pg; 1086 u_int pte_lo, pvo_flags, was_exec, i; 1087 int error; 1088 1089 if (!moea_initialized) { 1090 pvo_head = &moea_pvo_kunmanaged; 1091 zone = moea_upvo_zone; 1092 pvo_flags = 0; 1093 pg = NULL; 1094 was_exec = PTE_EXEC; 1095 } else { 1096 pvo_head = vm_page_to_pvoh(m); 1097 pg = m; 1098 zone = moea_mpvo_zone; 1099 pvo_flags = PVO_MANAGED; 1100 was_exec = 0; 1101 } 1102 if (pmap_bootstrapped) 1103 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1104 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1105 KASSERT((m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1106 ("moea_enter_locked: page %p is not busy", m)); 1107 1108 /* XXX change the pvo head for fake pages */ 1109 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1110 pvo_flags &= ~PVO_MANAGED; 1111 pvo_head = &moea_pvo_kunmanaged; 1112 zone = moea_upvo_zone; 1113 } 1114 1115 /* 1116 * If this is a managed page, and it's the first reference to the page, 1117 * clear the execness of the page. Otherwise fetch the execness. 1118 */ 1119 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1120 if (LIST_EMPTY(pvo_head)) { 1121 moea_attr_clear(pg, PTE_EXEC); 1122 } else { 1123 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1124 } 1125 } 1126 1127 /* 1128 * Assume the page is cache inhibited and access is guarded unless 1129 * it's in our available memory array. 1130 */ 1131 pte_lo = PTE_I | PTE_G; 1132 for (i = 0; i < pregions_sz; i++) { 1133 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1134 (VM_PAGE_TO_PHYS(m) < 1135 (pregions[i].mr_start + pregions[i].mr_size))) { 1136 pte_lo = PTE_M; 1137 break; 1138 } 1139 } 1140 1141 if (prot & VM_PROT_WRITE) { 1142 pte_lo |= PTE_BW; 1143 if (pmap_bootstrapped && 1144 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1145 vm_page_flag_set(m, PG_WRITEABLE); 1146 } else 1147 pte_lo |= PTE_BR; 1148 1149 if (prot & VM_PROT_EXECUTE) 1150 pvo_flags |= PVO_EXECUTABLE; 1151 1152 if (wired) 1153 pvo_flags |= PVO_WIRED; 1154 1155 if ((m->flags & PG_FICTITIOUS) != 0) 1156 pvo_flags |= PVO_FAKE; 1157 1158 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1159 pte_lo, pvo_flags); 1160 1161 /* 1162 * Flush the real page from the instruction cache if this page is 1163 * mapped executable and cacheable and was not previously mapped (or 1164 * was not mapped executable). 1165 */ 1166 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1167 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1168 /* 1169 * Flush the real memory from the cache. 1170 */ 1171 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1172 if (pg != NULL) 1173 moea_attr_save(pg, PTE_EXEC); 1174 } 1175 1176 /* XXX syncicache always until problems are sorted */ 1177 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1178} 1179 1180/* 1181 * Maps a sequence of resident pages belonging to the same object. 1182 * The sequence begins with the given page m_start. This page is 1183 * mapped at the given virtual address start. Each subsequent page is 1184 * mapped at a virtual address that is offset from start by the same 1185 * amount as the page is offset from m_start within the object. The 1186 * last page in the sequence is the page with the largest offset from 1187 * m_start that can be mapped at a virtual address less than the given 1188 * virtual address end. Not every virtual page between start and end 1189 * is mapped; only those for which a resident page exists with the 1190 * corresponding offset from m_start are mapped. 1191 */ 1192void 1193moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1194 vm_page_t m_start, vm_prot_t prot) 1195{ 1196 vm_page_t m; 1197 vm_pindex_t diff, psize; 1198 1199 psize = atop(end - start); 1200 m = m_start; 1201 vm_page_lock_queues(); 1202 PMAP_LOCK(pm); 1203 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1204 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1205 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1206 m = TAILQ_NEXT(m, listq); 1207 } 1208 vm_page_unlock_queues(); 1209 PMAP_UNLOCK(pm); 1210} 1211 1212void 1213moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1214 vm_prot_t prot) 1215{ 1216 1217 vm_page_lock_queues(); 1218 PMAP_LOCK(pm); 1219 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1220 FALSE); 1221 vm_page_unlock_queues(); 1222 PMAP_UNLOCK(pm); 1223} 1224 1225vm_paddr_t 1226moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1227{ 1228 struct pvo_entry *pvo; 1229 vm_paddr_t pa; 1230 1231 PMAP_LOCK(pm); 1232 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1233 if (pvo == NULL) 1234 pa = 0; 1235 else 1236 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1237 PMAP_UNLOCK(pm); 1238 return (pa); 1239} 1240 1241/* 1242 * Atomically extract and hold the physical page with the given 1243 * pmap and virtual address pair if that mapping permits the given 1244 * protection. 1245 */ 1246vm_page_t 1247moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1248{ 1249 struct pvo_entry *pvo; 1250 vm_page_t m; 1251 vm_paddr_t pa; 1252 1253 m = NULL; 1254 pa = 0; 1255 PMAP_LOCK(pmap); 1256retry: 1257 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1258 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1259 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1260 (prot & VM_PROT_WRITE) == 0)) { 1261 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1262 goto retry; 1263 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1264 vm_page_hold(m); 1265 } 1266 PA_UNLOCK_COND(pa); 1267 PMAP_UNLOCK(pmap); 1268 return (m); 1269} 1270 1271void 1272moea_init(mmu_t mmu) 1273{ 1274 1275 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1276 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1277 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1278 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1279 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1280 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1281 moea_initialized = TRUE; 1282} 1283 1284boolean_t 1285moea_is_referenced(mmu_t mmu, vm_page_t m) 1286{ 1287 1288 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1289 ("moea_is_referenced: page %p is not managed", m)); 1290 return (moea_query_bit(m, PTE_REF)); 1291} 1292 1293boolean_t 1294moea_is_modified(mmu_t mmu, vm_page_t m) 1295{ 1296 1297 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1298 ("moea_is_modified: page %p is not managed", m)); 1299 1300 /* 1301 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1302 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1303 * is clear, no PTEs can have PTE_CHG set. 1304 */ 1305 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1306 if ((m->oflags & VPO_BUSY) == 0 && 1307 (m->flags & PG_WRITEABLE) == 0) 1308 return (FALSE); 1309 return (moea_query_bit(m, PTE_CHG)); 1310} 1311 1312void 1313moea_clear_reference(mmu_t mmu, vm_page_t m) 1314{ 1315 1316 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1317 ("moea_clear_reference: page %p is not managed", m)); 1318 vm_page_lock_queues(); 1319 moea_clear_bit(m, PTE_REF, NULL); 1320 vm_page_unlock_queues(); 1321} 1322 1323void 1324moea_clear_modify(mmu_t mmu, vm_page_t m) 1325{ 1326 1327 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1328 ("moea_clear_modify: page %p is not managed", m)); 1329 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1330 KASSERT((m->oflags & VPO_BUSY) == 0, 1331 ("moea_clear_modify: page %p is busy", m)); 1332 1333 /* 1334 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1335 * set. If the object containing the page is locked and the page is 1336 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1337 */ 1338 if ((m->flags & PG_WRITEABLE) == 0) 1339 return; 1340 vm_page_lock_queues(); 1341 moea_clear_bit(m, PTE_CHG, NULL); 1342 vm_page_unlock_queues(); 1343} 1344 1345/* 1346 * Clear the write and modified bits in each of the given page's mappings. 1347 */ 1348void 1349moea_remove_write(mmu_t mmu, vm_page_t m) 1350{ 1351 struct pvo_entry *pvo; 1352 struct pte *pt; 1353 pmap_t pmap; 1354 u_int lo; 1355 1356 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1357 ("moea_remove_write: page %p is not managed", m)); 1358 1359 /* 1360 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1361 * another thread while the object is locked. Thus, if PG_WRITEABLE 1362 * is clear, no page table entries need updating. 1363 */ 1364 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1365 if ((m->oflags & VPO_BUSY) == 0 && 1366 (m->flags & PG_WRITEABLE) == 0) 1367 return; 1368 vm_page_lock_queues(); 1369 lo = moea_attr_fetch(m); 1370 powerpc_sync(); 1371 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1372 pmap = pvo->pvo_pmap; 1373 PMAP_LOCK(pmap); 1374 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1375 pt = moea_pvo_to_pte(pvo, -1); 1376 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1377 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1378 if (pt != NULL) { 1379 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1380 lo |= pvo->pvo_pte.pte.pte_lo; 1381 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1382 moea_pte_change(pt, &pvo->pvo_pte.pte, 1383 pvo->pvo_vaddr); 1384 mtx_unlock(&moea_table_mutex); 1385 } 1386 } 1387 PMAP_UNLOCK(pmap); 1388 } 1389 if ((lo & PTE_CHG) != 0) { 1390 moea_attr_clear(m, PTE_CHG); 1391 vm_page_dirty(m); 1392 } 1393 vm_page_flag_clear(m, PG_WRITEABLE); 1394 vm_page_unlock_queues(); 1395} 1396 1397/* 1398 * moea_ts_referenced: 1399 * 1400 * Return a count of reference bits for a page, clearing those bits. 1401 * It is not necessary for every reference bit to be cleared, but it 1402 * is necessary that 0 only be returned when there are truly no 1403 * reference bits set. 1404 * 1405 * XXX: The exact number of bits to check and clear is a matter that 1406 * should be tested and standardized at some point in the future for 1407 * optimal aging of shared pages. 1408 */ 1409boolean_t 1410moea_ts_referenced(mmu_t mmu, vm_page_t m) 1411{ 1412 int count; 1413 1414 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1415 return (0); 1416 1417 count = moea_clear_bit(m, PTE_REF, NULL); 1418 1419 return (count); 1420} 1421 1422/* 1423 * Map a wired page into kernel virtual address space. 1424 */ 1425void 1426moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1427{ 1428 u_int pte_lo; 1429 int error; 1430 int i; 1431 1432#if 0 1433 if (va < VM_MIN_KERNEL_ADDRESS) 1434 panic("moea_kenter: attempt to enter non-kernel address %#x", 1435 va); 1436#endif 1437 1438 pte_lo = PTE_I | PTE_G; 1439 for (i = 0; i < pregions_sz; i++) { 1440 if ((pa >= pregions[i].mr_start) && 1441 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1442 pte_lo = PTE_M; 1443 break; 1444 } 1445 } 1446 1447 PMAP_LOCK(kernel_pmap); 1448 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1449 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1450 1451 if (error != 0 && error != ENOENT) 1452 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1453 pa, error); 1454 1455 /* 1456 * Flush the real memory from the instruction cache. 1457 */ 1458 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1459 moea_syncicache(pa, PAGE_SIZE); 1460 } 1461 PMAP_UNLOCK(kernel_pmap); 1462} 1463 1464/* 1465 * Extract the physical page address associated with the given kernel virtual 1466 * address. 1467 */ 1468vm_offset_t 1469moea_kextract(mmu_t mmu, vm_offset_t va) 1470{ 1471 struct pvo_entry *pvo; 1472 vm_paddr_t pa; 1473 1474 /* 1475 * Allow direct mappings on 32-bit OEA 1476 */ 1477 if (va < VM_MIN_KERNEL_ADDRESS) { 1478 return (va); 1479 } 1480 1481 PMAP_LOCK(kernel_pmap); 1482 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1483 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1484 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1485 PMAP_UNLOCK(kernel_pmap); 1486 return (pa); 1487} 1488 1489/* 1490 * Remove a wired page from kernel virtual address space. 1491 */ 1492void 1493moea_kremove(mmu_t mmu, vm_offset_t va) 1494{ 1495 1496 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1497} 1498 1499/* 1500 * Map a range of physical addresses into kernel virtual address space. 1501 * 1502 * The value passed in *virt is a suggested virtual address for the mapping. 1503 * Architectures which can support a direct-mapped physical to virtual region 1504 * can return the appropriate address within that region, leaving '*virt' 1505 * unchanged. We cannot and therefore do not; *virt is updated with the 1506 * first usable address after the mapped region. 1507 */ 1508vm_offset_t 1509moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1510 vm_offset_t pa_end, int prot) 1511{ 1512 vm_offset_t sva, va; 1513 1514 sva = *virt; 1515 va = sva; 1516 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1517 moea_kenter(mmu, va, pa_start); 1518 *virt = va; 1519 return (sva); 1520} 1521 1522/* 1523 * Returns true if the pmap's pv is one of the first 1524 * 16 pvs linked to from this page. This count may 1525 * be changed upwards or downwards in the future; it 1526 * is only necessary that true be returned for a small 1527 * subset of pmaps for proper page aging. 1528 */ 1529boolean_t 1530moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1531{ 1532 int loops; 1533 struct pvo_entry *pvo; 1534 1535 if (!moea_initialized || (m->flags & PG_FICTITIOUS)) 1536 return FALSE; 1537 1538 loops = 0; 1539 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1540 if (pvo->pvo_pmap == pmap) 1541 return (TRUE); 1542 if (++loops >= 16) 1543 break; 1544 } 1545 1546 return (FALSE); 1547} 1548 1549/* 1550 * Return the number of managed mappings to the given physical page 1551 * that are wired. 1552 */ 1553int 1554moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1555{ 1556 struct pvo_entry *pvo; 1557 int count; 1558 1559 count = 0; 1560 if (!moea_initialized || (m->flags & PG_FICTITIOUS) != 0) 1561 return (count); 1562 vm_page_lock_queues(); 1563 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1564 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1565 count++; 1566 vm_page_unlock_queues(); 1567 return (count); 1568} 1569 1570static u_int moea_vsidcontext; 1571 1572void 1573moea_pinit(mmu_t mmu, pmap_t pmap) 1574{ 1575 int i, mask; 1576 u_int entropy; 1577 1578 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1579 PMAP_LOCK_INIT(pmap); 1580 1581 entropy = 0; 1582 __asm __volatile("mftb %0" : "=r"(entropy)); 1583 1584 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1585 == NULL) { 1586 pmap->pmap_phys = pmap; 1587 } 1588 1589 1590 /* 1591 * Allocate some segment registers for this pmap. 1592 */ 1593 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1594 u_int hash, n; 1595 1596 /* 1597 * Create a new value by mutiplying by a prime and adding in 1598 * entropy from the timebase register. This is to make the 1599 * VSID more random so that the PT hash function collides 1600 * less often. (Note that the prime casues gcc to do shifts 1601 * instead of a multiply.) 1602 */ 1603 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1604 hash = moea_vsidcontext & (NPMAPS - 1); 1605 if (hash == 0) /* 0 is special, avoid it */ 1606 continue; 1607 n = hash >> 5; 1608 mask = 1 << (hash & (VSID_NBPW - 1)); 1609 hash = (moea_vsidcontext & 0xfffff); 1610 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1611 /* anything free in this bucket? */ 1612 if (moea_vsid_bitmap[n] == 0xffffffff) { 1613 entropy = (moea_vsidcontext >> 20); 1614 continue; 1615 } 1616 i = ffs(~moea_vsid_bitmap[i]) - 1; 1617 mask = 1 << i; 1618 hash &= 0xfffff & ~(VSID_NBPW - 1); 1619 hash |= i; 1620 } 1621 moea_vsid_bitmap[n] |= mask; 1622 for (i = 0; i < 16; i++) 1623 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1624 return; 1625 } 1626 1627 panic("moea_pinit: out of segments"); 1628} 1629 1630/* 1631 * Initialize the pmap associated with process 0. 1632 */ 1633void 1634moea_pinit0(mmu_t mmu, pmap_t pm) 1635{ 1636 1637 moea_pinit(mmu, pm); 1638 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1639} 1640 1641/* 1642 * Set the physical protection on the specified range of this map as requested. 1643 */ 1644void 1645moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1646 vm_prot_t prot) 1647{ 1648 struct pvo_entry *pvo; 1649 struct pte *pt; 1650 int pteidx; 1651 1652 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1653 ("moea_protect: non current pmap")); 1654 1655 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1656 moea_remove(mmu, pm, sva, eva); 1657 return; 1658 } 1659 1660 vm_page_lock_queues(); 1661 PMAP_LOCK(pm); 1662 for (; sva < eva; sva += PAGE_SIZE) { 1663 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1664 if (pvo == NULL) 1665 continue; 1666 1667 if ((prot & VM_PROT_EXECUTE) == 0) 1668 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1669 1670 /* 1671 * Grab the PTE pointer before we diddle with the cached PTE 1672 * copy. 1673 */ 1674 pt = moea_pvo_to_pte(pvo, pteidx); 1675 /* 1676 * Change the protection of the page. 1677 */ 1678 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1679 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1680 1681 /* 1682 * If the PVO is in the page table, update that pte as well. 1683 */ 1684 if (pt != NULL) { 1685 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1686 mtx_unlock(&moea_table_mutex); 1687 } 1688 } 1689 vm_page_unlock_queues(); 1690 PMAP_UNLOCK(pm); 1691} 1692 1693/* 1694 * Map a list of wired pages into kernel virtual address space. This is 1695 * intended for temporary mappings which do not need page modification or 1696 * references recorded. Existing mappings in the region are overwritten. 1697 */ 1698void 1699moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1700{ 1701 vm_offset_t va; 1702 1703 va = sva; 1704 while (count-- > 0) { 1705 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1706 va += PAGE_SIZE; 1707 m++; 1708 } 1709} 1710 1711/* 1712 * Remove page mappings from kernel virtual address space. Intended for 1713 * temporary mappings entered by moea_qenter. 1714 */ 1715void 1716moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1717{ 1718 vm_offset_t va; 1719 1720 va = sva; 1721 while (count-- > 0) { 1722 moea_kremove(mmu, va); 1723 va += PAGE_SIZE; 1724 } 1725} 1726 1727void 1728moea_release(mmu_t mmu, pmap_t pmap) 1729{ 1730 int idx, mask; 1731 1732 /* 1733 * Free segment register's VSID 1734 */ 1735 if (pmap->pm_sr[0] == 0) 1736 panic("moea_release"); 1737 1738 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1739 mask = 1 << (idx % VSID_NBPW); 1740 idx /= VSID_NBPW; 1741 moea_vsid_bitmap[idx] &= ~mask; 1742 PMAP_LOCK_DESTROY(pmap); 1743} 1744 1745/* 1746 * Remove the given range of addresses from the specified map. 1747 */ 1748void 1749moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1750{ 1751 struct pvo_entry *pvo; 1752 int pteidx; 1753 1754 vm_page_lock_queues(); 1755 PMAP_LOCK(pm); 1756 for (; sva < eva; sva += PAGE_SIZE) { 1757 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1758 if (pvo != NULL) { 1759 moea_pvo_remove(pvo, pteidx); 1760 } 1761 } 1762 PMAP_UNLOCK(pm); 1763 vm_page_unlock_queues(); 1764} 1765 1766/* 1767 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1768 * will reflect changes in pte's back to the vm_page. 1769 */ 1770void 1771moea_remove_all(mmu_t mmu, vm_page_t m) 1772{ 1773 struct pvo_head *pvo_head; 1774 struct pvo_entry *pvo, *next_pvo; 1775 pmap_t pmap; 1776 1777 vm_page_lock_queues(); 1778 pvo_head = vm_page_to_pvoh(m); 1779 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1780 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1781 1782 MOEA_PVO_CHECK(pvo); /* sanity check */ 1783 pmap = pvo->pvo_pmap; 1784 PMAP_LOCK(pmap); 1785 moea_pvo_remove(pvo, -1); 1786 PMAP_UNLOCK(pmap); 1787 } 1788 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1789 moea_attr_clear(m, LPTE_CHG); 1790 vm_page_dirty(m); 1791 } 1792 vm_page_flag_clear(m, PG_WRITEABLE); 1793 vm_page_unlock_queues(); 1794} 1795 1796/* 1797 * Allocate a physical page of memory directly from the phys_avail map. 1798 * Can only be called from moea_bootstrap before avail start and end are 1799 * calculated. 1800 */ 1801static vm_offset_t 1802moea_bootstrap_alloc(vm_size_t size, u_int align) 1803{ 1804 vm_offset_t s, e; 1805 int i, j; 1806 1807 size = round_page(size); 1808 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1809 if (align != 0) 1810 s = (phys_avail[i] + align - 1) & ~(align - 1); 1811 else 1812 s = phys_avail[i]; 1813 e = s + size; 1814 1815 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1816 continue; 1817 1818 if (s == phys_avail[i]) { 1819 phys_avail[i] += size; 1820 } else if (e == phys_avail[i + 1]) { 1821 phys_avail[i + 1] -= size; 1822 } else { 1823 for (j = phys_avail_count * 2; j > i; j -= 2) { 1824 phys_avail[j] = phys_avail[j - 2]; 1825 phys_avail[j + 1] = phys_avail[j - 1]; 1826 } 1827 1828 phys_avail[i + 3] = phys_avail[i + 1]; 1829 phys_avail[i + 1] = s; 1830 phys_avail[i + 2] = e; 1831 phys_avail_count++; 1832 } 1833 1834 return (s); 1835 } 1836 panic("moea_bootstrap_alloc: could not allocate memory"); 1837} 1838 1839static void 1840moea_syncicache(vm_offset_t pa, vm_size_t len) 1841{ 1842 __syncicache((void *)pa, len); 1843} 1844 1845static int 1846moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1847 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1848{ 1849 struct pvo_entry *pvo; 1850 u_int sr; 1851 int first; 1852 u_int ptegidx; 1853 int i; 1854 int bootstrap; 1855 1856 moea_pvo_enter_calls++; 1857 first = 0; 1858 bootstrap = 0; 1859 1860 /* 1861 * Compute the PTE Group index. 1862 */ 1863 va &= ~ADDR_POFF; 1864 sr = va_to_sr(pm->pm_sr, va); 1865 ptegidx = va_to_pteg(sr, va); 1866 1867 /* 1868 * Remove any existing mapping for this page. Reuse the pvo entry if 1869 * there is a mapping. 1870 */ 1871 mtx_lock(&moea_table_mutex); 1872 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1873 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1874 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1875 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1876 (pte_lo & PTE_PP)) { 1877 mtx_unlock(&moea_table_mutex); 1878 return (0); 1879 } 1880 moea_pvo_remove(pvo, -1); 1881 break; 1882 } 1883 } 1884 1885 /* 1886 * If we aren't overwriting a mapping, try to allocate. 1887 */ 1888 if (moea_initialized) { 1889 pvo = uma_zalloc(zone, M_NOWAIT); 1890 } else { 1891 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1892 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1893 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1894 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1895 } 1896 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1897 moea_bpvo_pool_index++; 1898 bootstrap = 1; 1899 } 1900 1901 if (pvo == NULL) { 1902 mtx_unlock(&moea_table_mutex); 1903 return (ENOMEM); 1904 } 1905 1906 moea_pvo_entries++; 1907 pvo->pvo_vaddr = va; 1908 pvo->pvo_pmap = pm; 1909 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1910 pvo->pvo_vaddr &= ~ADDR_POFF; 1911 if (flags & VM_PROT_EXECUTE) 1912 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1913 if (flags & PVO_WIRED) 1914 pvo->pvo_vaddr |= PVO_WIRED; 1915 if (pvo_head != &moea_pvo_kunmanaged) 1916 pvo->pvo_vaddr |= PVO_MANAGED; 1917 if (bootstrap) 1918 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1919 if (flags & PVO_FAKE) 1920 pvo->pvo_vaddr |= PVO_FAKE; 1921 1922 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1923 1924 /* 1925 * Remember if the list was empty and therefore will be the first 1926 * item. 1927 */ 1928 if (LIST_FIRST(pvo_head) == NULL) 1929 first = 1; 1930 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1931 1932 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1933 pm->pm_stats.wired_count++; 1934 pm->pm_stats.resident_count++; 1935 1936 /* 1937 * We hope this succeeds but it isn't required. 1938 */ 1939 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1940 if (i >= 0) { 1941 PVO_PTEGIDX_SET(pvo, i); 1942 } else { 1943 panic("moea_pvo_enter: overflow"); 1944 moea_pte_overflow++; 1945 } 1946 mtx_unlock(&moea_table_mutex); 1947 1948 return (first ? ENOENT : 0); 1949} 1950 1951static void 1952moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1953{ 1954 struct pte *pt; 1955 1956 /* 1957 * If there is an active pte entry, we need to deactivate it (and 1958 * save the ref & cfg bits). 1959 */ 1960 pt = moea_pvo_to_pte(pvo, pteidx); 1961 if (pt != NULL) { 1962 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1963 mtx_unlock(&moea_table_mutex); 1964 PVO_PTEGIDX_CLR(pvo); 1965 } else { 1966 moea_pte_overflow--; 1967 } 1968 1969 /* 1970 * Update our statistics. 1971 */ 1972 pvo->pvo_pmap->pm_stats.resident_count--; 1973 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1974 pvo->pvo_pmap->pm_stats.wired_count--; 1975 1976 /* 1977 * Save the REF/CHG bits into their cache if the page is managed. 1978 */ 1979 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 1980 struct vm_page *pg; 1981 1982 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1983 if (pg != NULL) { 1984 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 1985 (PTE_REF | PTE_CHG)); 1986 } 1987 } 1988 1989 /* 1990 * Remove this PVO from the PV list. 1991 */ 1992 LIST_REMOVE(pvo, pvo_vlink); 1993 1994 /* 1995 * Remove this from the overflow list and return it to the pool 1996 * if we aren't going to reuse it. 1997 */ 1998 LIST_REMOVE(pvo, pvo_olink); 1999 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2000 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2001 moea_upvo_zone, pvo); 2002 moea_pvo_entries--; 2003 moea_pvo_remove_calls++; 2004} 2005 2006static __inline int 2007moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2008{ 2009 int pteidx; 2010 2011 /* 2012 * We can find the actual pte entry without searching by grabbing 2013 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2014 * noticing the HID bit. 2015 */ 2016 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2017 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2018 pteidx ^= moea_pteg_mask * 8; 2019 2020 return (pteidx); 2021} 2022 2023static struct pvo_entry * 2024moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2025{ 2026 struct pvo_entry *pvo; 2027 int ptegidx; 2028 u_int sr; 2029 2030 va &= ~ADDR_POFF; 2031 sr = va_to_sr(pm->pm_sr, va); 2032 ptegidx = va_to_pteg(sr, va); 2033 2034 mtx_lock(&moea_table_mutex); 2035 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2036 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2037 if (pteidx_p) 2038 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2039 break; 2040 } 2041 } 2042 mtx_unlock(&moea_table_mutex); 2043 2044 return (pvo); 2045} 2046 2047static struct pte * 2048moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2049{ 2050 struct pte *pt; 2051 2052 /* 2053 * If we haven't been supplied the ptegidx, calculate it. 2054 */ 2055 if (pteidx == -1) { 2056 int ptegidx; 2057 u_int sr; 2058 2059 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2060 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2061 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2062 } 2063 2064 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2065 mtx_lock(&moea_table_mutex); 2066 2067 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2068 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2069 "valid pte index", pvo); 2070 } 2071 2072 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2073 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2074 "pvo but no valid pte", pvo); 2075 } 2076 2077 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2078 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2079 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2080 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2081 } 2082 2083 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2084 != 0) { 2085 panic("moea_pvo_to_pte: pvo %p pte does not match " 2086 "pte %p in moea_pteg_table", pvo, pt); 2087 } 2088 2089 mtx_assert(&moea_table_mutex, MA_OWNED); 2090 return (pt); 2091 } 2092 2093 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2094 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2095 "moea_pteg_table but valid in pvo", pvo, pt); 2096 } 2097 2098 mtx_unlock(&moea_table_mutex); 2099 return (NULL); 2100} 2101 2102/* 2103 * XXX: THIS STUFF SHOULD BE IN pte.c? 2104 */ 2105int 2106moea_pte_spill(vm_offset_t addr) 2107{ 2108 struct pvo_entry *source_pvo, *victim_pvo; 2109 struct pvo_entry *pvo; 2110 int ptegidx, i, j; 2111 u_int sr; 2112 struct pteg *pteg; 2113 struct pte *pt; 2114 2115 moea_pte_spills++; 2116 2117 sr = mfsrin(addr); 2118 ptegidx = va_to_pteg(sr, addr); 2119 2120 /* 2121 * Have to substitute some entry. Use the primary hash for this. 2122 * Use low bits of timebase as random generator. 2123 */ 2124 pteg = &moea_pteg_table[ptegidx]; 2125 mtx_lock(&moea_table_mutex); 2126 __asm __volatile("mftb %0" : "=r"(i)); 2127 i &= 7; 2128 pt = &pteg->pt[i]; 2129 2130 source_pvo = NULL; 2131 victim_pvo = NULL; 2132 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2133 /* 2134 * We need to find a pvo entry for this address. 2135 */ 2136 MOEA_PVO_CHECK(pvo); 2137 if (source_pvo == NULL && 2138 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2139 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2140 /* 2141 * Now found an entry to be spilled into the pteg. 2142 * The PTE is now valid, so we know it's active. 2143 */ 2144 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2145 2146 if (j >= 0) { 2147 PVO_PTEGIDX_SET(pvo, j); 2148 moea_pte_overflow--; 2149 MOEA_PVO_CHECK(pvo); 2150 mtx_unlock(&moea_table_mutex); 2151 return (1); 2152 } 2153 2154 source_pvo = pvo; 2155 2156 if (victim_pvo != NULL) 2157 break; 2158 } 2159 2160 /* 2161 * We also need the pvo entry of the victim we are replacing 2162 * so save the R & C bits of the PTE. 2163 */ 2164 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2165 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2166 victim_pvo = pvo; 2167 if (source_pvo != NULL) 2168 break; 2169 } 2170 } 2171 2172 if (source_pvo == NULL) { 2173 mtx_unlock(&moea_table_mutex); 2174 return (0); 2175 } 2176 2177 if (victim_pvo == NULL) { 2178 if ((pt->pte_hi & PTE_HID) == 0) 2179 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2180 "entry", pt); 2181 2182 /* 2183 * If this is a secondary PTE, we need to search it's primary 2184 * pvo bucket for the matching PVO. 2185 */ 2186 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2187 pvo_olink) { 2188 MOEA_PVO_CHECK(pvo); 2189 /* 2190 * We also need the pvo entry of the victim we are 2191 * replacing so save the R & C bits of the PTE. 2192 */ 2193 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2194 victim_pvo = pvo; 2195 break; 2196 } 2197 } 2198 2199 if (victim_pvo == NULL) 2200 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2201 "entry", pt); 2202 } 2203 2204 /* 2205 * We are invalidating the TLB entry for the EA we are replacing even 2206 * though it's valid. If we don't, we lose any ref/chg bit changes 2207 * contained in the TLB entry. 2208 */ 2209 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2210 2211 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2212 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2213 2214 PVO_PTEGIDX_CLR(victim_pvo); 2215 PVO_PTEGIDX_SET(source_pvo, i); 2216 moea_pte_replacements++; 2217 2218 MOEA_PVO_CHECK(victim_pvo); 2219 MOEA_PVO_CHECK(source_pvo); 2220 2221 mtx_unlock(&moea_table_mutex); 2222 return (1); 2223} 2224 2225static int 2226moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2227{ 2228 struct pte *pt; 2229 int i; 2230 2231 mtx_assert(&moea_table_mutex, MA_OWNED); 2232 2233 /* 2234 * First try primary hash. 2235 */ 2236 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2237 if ((pt->pte_hi & PTE_VALID) == 0) { 2238 pvo_pt->pte_hi &= ~PTE_HID; 2239 moea_pte_set(pt, pvo_pt); 2240 return (i); 2241 } 2242 } 2243 2244 /* 2245 * Now try secondary hash. 2246 */ 2247 ptegidx ^= moea_pteg_mask; 2248 2249 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2250 if ((pt->pte_hi & PTE_VALID) == 0) { 2251 pvo_pt->pte_hi |= PTE_HID; 2252 moea_pte_set(pt, pvo_pt); 2253 return (i); 2254 } 2255 } 2256 2257 panic("moea_pte_insert: overflow"); 2258 return (-1); 2259} 2260 2261static boolean_t 2262moea_query_bit(vm_page_t m, int ptebit) 2263{ 2264 struct pvo_entry *pvo; 2265 struct pte *pt; 2266 2267 if (moea_attr_fetch(m) & ptebit) 2268 return (TRUE); 2269 2270 vm_page_lock_queues(); 2271 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2272 MOEA_PVO_CHECK(pvo); /* sanity check */ 2273 2274 /* 2275 * See if we saved the bit off. If so, cache it and return 2276 * success. 2277 */ 2278 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2279 moea_attr_save(m, ptebit); 2280 MOEA_PVO_CHECK(pvo); /* sanity check */ 2281 vm_page_unlock_queues(); 2282 return (TRUE); 2283 } 2284 } 2285 2286 /* 2287 * No luck, now go through the hard part of looking at the PTEs 2288 * themselves. Sync so that any pending REF/CHG bits are flushed to 2289 * the PTEs. 2290 */ 2291 powerpc_sync(); 2292 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2293 MOEA_PVO_CHECK(pvo); /* sanity check */ 2294 2295 /* 2296 * See if this pvo has a valid PTE. if so, fetch the 2297 * REF/CHG bits from the valid PTE. If the appropriate 2298 * ptebit is set, cache it and return success. 2299 */ 2300 pt = moea_pvo_to_pte(pvo, -1); 2301 if (pt != NULL) { 2302 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2303 mtx_unlock(&moea_table_mutex); 2304 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2305 moea_attr_save(m, ptebit); 2306 MOEA_PVO_CHECK(pvo); /* sanity check */ 2307 vm_page_unlock_queues(); 2308 return (TRUE); 2309 } 2310 } 2311 } 2312 2313 vm_page_unlock_queues(); 2314 return (FALSE); 2315} 2316 2317static u_int 2318moea_clear_bit(vm_page_t m, int ptebit, int *origbit) 2319{ 2320 u_int count; 2321 struct pvo_entry *pvo; 2322 struct pte *pt; 2323 int rv; 2324 2325 /* 2326 * Clear the cached value. 2327 */ 2328 rv = moea_attr_fetch(m); 2329 moea_attr_clear(m, ptebit); 2330 2331 /* 2332 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2333 * we can reset the right ones). note that since the pvo entries and 2334 * list heads are accessed via BAT0 and are never placed in the page 2335 * table, we don't have to worry about further accesses setting the 2336 * REF/CHG bits. 2337 */ 2338 powerpc_sync(); 2339 2340 /* 2341 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2342 * valid pte clear the ptebit from the valid pte. 2343 */ 2344 count = 0; 2345 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2346 MOEA_PVO_CHECK(pvo); /* sanity check */ 2347 pt = moea_pvo_to_pte(pvo, -1); 2348 if (pt != NULL) { 2349 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2350 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2351 count++; 2352 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2353 } 2354 mtx_unlock(&moea_table_mutex); 2355 } 2356 rv |= pvo->pvo_pte.pte.pte_lo; 2357 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2358 MOEA_PVO_CHECK(pvo); /* sanity check */ 2359 } 2360 2361 if (origbit != NULL) { 2362 *origbit = rv; 2363 } 2364 2365 return (count); 2366} 2367 2368/* 2369 * Return true if the physical range is encompassed by the battable[idx] 2370 */ 2371static int 2372moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2373{ 2374 u_int prot; 2375 u_int32_t start; 2376 u_int32_t end; 2377 u_int32_t bat_ble; 2378 2379 /* 2380 * Return immediately if not a valid mapping 2381 */ 2382 if (!battable[idx].batu & BAT_Vs) 2383 return (EINVAL); 2384 2385 /* 2386 * The BAT entry must be cache-inhibited, guarded, and r/w 2387 * so it can function as an i/o page 2388 */ 2389 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2390 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2391 return (EPERM); 2392 2393 /* 2394 * The address should be within the BAT range. Assume that the 2395 * start address in the BAT has the correct alignment (thus 2396 * not requiring masking) 2397 */ 2398 start = battable[idx].batl & BAT_PBS; 2399 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2400 end = start | (bat_ble << 15) | 0x7fff; 2401 2402 if ((pa < start) || ((pa + size) > end)) 2403 return (ERANGE); 2404 2405 return (0); 2406} 2407 2408boolean_t 2409moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2410{ 2411 int i; 2412 2413 /* 2414 * This currently does not work for entries that 2415 * overlap 256M BAT segments. 2416 */ 2417 2418 for(i = 0; i < 16; i++) 2419 if (moea_bat_mapped(i, pa, size) == 0) 2420 return (0); 2421 2422 return (EFAULT); 2423} 2424 2425/* 2426 * Map a set of physical memory pages into the kernel virtual 2427 * address space. Return a pointer to where it is mapped. This 2428 * routine is intended to be used for mapping device memory, 2429 * NOT real memory. 2430 */ 2431void * 2432moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2433{ 2434 vm_offset_t va, tmpva, ppa, offset; 2435 int i; 2436 2437 ppa = trunc_page(pa); 2438 offset = pa & PAGE_MASK; 2439 size = roundup(offset + size, PAGE_SIZE); 2440 2441 GIANT_REQUIRED; 2442 2443 /* 2444 * If the physical address lies within a valid BAT table entry, 2445 * return the 1:1 mapping. This currently doesn't work 2446 * for regions that overlap 256M BAT segments. 2447 */ 2448 for (i = 0; i < 16; i++) { 2449 if (moea_bat_mapped(i, pa, size) == 0) 2450 return ((void *) pa); 2451 } 2452 2453 va = kmem_alloc_nofault(kernel_map, size); 2454 if (!va) 2455 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2456 2457 for (tmpva = va; size > 0;) { 2458 moea_kenter(mmu, tmpva, ppa); 2459 tlbie(tmpva); 2460 size -= PAGE_SIZE; 2461 tmpva += PAGE_SIZE; 2462 ppa += PAGE_SIZE; 2463 } 2464 2465 return ((void *)(va + offset)); 2466} 2467 2468void 2469moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2470{ 2471 vm_offset_t base, offset; 2472 2473 /* 2474 * If this is outside kernel virtual space, then it's a 2475 * battable entry and doesn't require unmapping 2476 */ 2477 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2478 base = trunc_page(va); 2479 offset = va & PAGE_MASK; 2480 size = roundup(offset + size, PAGE_SIZE); 2481 kmem_free(kernel_map, base, size); 2482 } 2483} 2484 2485static void 2486moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2487{ 2488 struct pvo_entry *pvo; 2489 vm_offset_t lim; 2490 vm_paddr_t pa; 2491 vm_size_t len; 2492 2493 PMAP_LOCK(pm); 2494 while (sz > 0) { 2495 lim = round_page(va); 2496 len = MIN(lim - va, sz); 2497 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2498 if (pvo != NULL) { 2499 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2500 (va & ADDR_POFF); 2501 moea_syncicache(pa, len); 2502 } 2503 va += len; 2504 sz -= len; 2505 } 2506 PMAP_UNLOCK(pm); 2507} 2508