mmu_oea.c revision 178628
1139825Simp/*- 290643Sbenno * Copyright (c) 2001 The NetBSD Foundation, Inc. 390643Sbenno * All rights reserved. 490643Sbenno * 590643Sbenno * This code is derived from software contributed to The NetBSD Foundation 690643Sbenno * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 790643Sbenno * 890643Sbenno * Redistribution and use in source and binary forms, with or without 990643Sbenno * modification, are permitted provided that the following conditions 1090643Sbenno * are met: 1190643Sbenno * 1. Redistributions of source code must retain the above copyright 1290643Sbenno * notice, this list of conditions and the following disclaimer. 1390643Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1490643Sbenno * notice, this list of conditions and the following disclaimer in the 1590643Sbenno * documentation and/or other materials provided with the distribution. 1690643Sbenno * 3. All advertising materials mentioning features or use of this software 1790643Sbenno * must display the following acknowledgement: 1890643Sbenno * This product includes software developed by the NetBSD 1990643Sbenno * Foundation, Inc. and its contributors. 2090643Sbenno * 4. Neither the name of The NetBSD Foundation nor the names of its 2190643Sbenno * contributors may be used to endorse or promote products derived 2290643Sbenno * from this software without specific prior written permission. 2390643Sbenno * 2490643Sbenno * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2590643Sbenno * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2690643Sbenno * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2790643Sbenno * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2890643Sbenno * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2990643Sbenno * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3090643Sbenno * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3190643Sbenno * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3290643Sbenno * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3390643Sbenno * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3490643Sbenno * POSSIBILITY OF SUCH DAMAGE. 3590643Sbenno */ 36139825Simp/*- 3777957Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3877957Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 3977957Sbenno * All rights reserved. 4077957Sbenno * 4177957Sbenno * Redistribution and use in source and binary forms, with or without 4277957Sbenno * modification, are permitted provided that the following conditions 4377957Sbenno * are met: 4477957Sbenno * 1. Redistributions of source code must retain the above copyright 4577957Sbenno * notice, this list of conditions and the following disclaimer. 4677957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 4777957Sbenno * notice, this list of conditions and the following disclaimer in the 4877957Sbenno * documentation and/or other materials provided with the distribution. 4977957Sbenno * 3. All advertising materials mentioning features or use of this software 5077957Sbenno * must display the following acknowledgement: 5177957Sbenno * This product includes software developed by TooLs GmbH. 5277957Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 5377957Sbenno * derived from this software without specific prior written permission. 5477957Sbenno * 5577957Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 5677957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 5777957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 5877957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 5977957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 6077957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 6177957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 6277957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 6377957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 6477957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 6577957Sbenno * 6678880Sbenno * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 6777957Sbenno */ 68139825Simp/*- 6977957Sbenno * Copyright (C) 2001 Benno Rice. 7077957Sbenno * All rights reserved. 7177957Sbenno * 7277957Sbenno * Redistribution and use in source and binary forms, with or without 7377957Sbenno * modification, are permitted provided that the following conditions 7477957Sbenno * are met: 7577957Sbenno * 1. Redistributions of source code must retain the above copyright 7677957Sbenno * notice, this list of conditions and the following disclaimer. 7777957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 7877957Sbenno * notice, this list of conditions and the following disclaimer in the 7977957Sbenno * documentation and/or other materials provided with the distribution. 8077957Sbenno * 8177957Sbenno * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 8277957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8377957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 8477957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 8577957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 8677957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 8777957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 8877957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 8977957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 9077957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 9177957Sbenno */ 9277957Sbenno 93113038Sobrien#include <sys/cdefs.h> 94113038Sobrien__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 178628 2008-04-27 22:33:43Z marcel $"); 9577957Sbenno 9690643Sbenno/* 9790643Sbenno * Manages physical address maps. 9890643Sbenno * 9990643Sbenno * In addition to hardware address maps, this module is called upon to 10090643Sbenno * provide software-use-only maps which may or may not be stored in the 10190643Sbenno * same form as hardware maps. These pseudo-maps are used to store 10290643Sbenno * intermediate results from copy operations to and from address spaces. 10390643Sbenno * 10490643Sbenno * Since the information managed by this module is also stored by the 10590643Sbenno * logical address mapping module, this module may throw away valid virtual 10690643Sbenno * to physical mappings at almost any time. However, invalidations of 10790643Sbenno * mappings must be done as requested. 10890643Sbenno * 10990643Sbenno * In order to cope with hardware architectures which make virtual to 11090643Sbenno * physical map invalidates expensive, this module may delay invalidate 11190643Sbenno * reduced protection operations until such time as they are actually 11290643Sbenno * necessary. This module is given full information as to which processors 11390643Sbenno * are currently using which maps, and to when physical maps must be made 11490643Sbenno * correct. 11590643Sbenno */ 11690643Sbenno 117118239Speter#include "opt_kstack_pages.h" 118118239Speter 11977957Sbenno#include <sys/param.h> 12080431Speter#include <sys/kernel.h> 12190643Sbenno#include <sys/ktr.h> 12290643Sbenno#include <sys/lock.h> 12390643Sbenno#include <sys/msgbuf.h> 12490643Sbenno#include <sys/mutex.h> 12577957Sbenno#include <sys/proc.h> 12690643Sbenno#include <sys/sysctl.h> 12790643Sbenno#include <sys/systm.h> 12877957Sbenno#include <sys/vmmeter.h> 12977957Sbenno 13090643Sbenno#include <dev/ofw/openfirm.h> 13190643Sbenno 132152180Sgrehan#include <vm/vm.h> 13377957Sbenno#include <vm/vm_param.h> 13477957Sbenno#include <vm/vm_kern.h> 13577957Sbenno#include <vm/vm_page.h> 13677957Sbenno#include <vm/vm_map.h> 13777957Sbenno#include <vm/vm_object.h> 13877957Sbenno#include <vm/vm_extern.h> 13977957Sbenno#include <vm/vm_pageout.h> 14077957Sbenno#include <vm/vm_pager.h> 14192847Sjeff#include <vm/uma.h> 14277957Sbenno 143125687Sgrehan#include <machine/cpu.h> 14497346Sbenno#include <machine/powerpc.h> 14583730Smp#include <machine/bat.h> 14690643Sbenno#include <machine/frame.h> 14790643Sbenno#include <machine/md_var.h> 14890643Sbenno#include <machine/psl.h> 14977957Sbenno#include <machine/pte.h> 150178628Smarcel#include <machine/smp.h> 15190643Sbenno#include <machine/sr.h> 152152180Sgrehan#include <machine/mmuvar.h> 15377957Sbenno 154152180Sgrehan#include "mmu_if.h" 15577957Sbenno 156152180Sgrehan#define MOEA_DEBUG 157152180Sgrehan 15890643Sbenno#define TODO panic("%s: not implemented", __func__); 15977957Sbenno 16090643Sbenno#define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 16190643Sbenno#define TLBSYNC() __asm __volatile("tlbsync"); 16290643Sbenno#define SYNC() __asm __volatile("sync"); 16390643Sbenno#define EIEIO() __asm __volatile("eieio"); 16490643Sbenno 16590643Sbenno#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 16690643Sbenno#define VSID_TO_SR(vsid) ((vsid) & 0xf) 16790643Sbenno#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 16890643Sbenno 169142416Sgrehan#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 170142416Sgrehan#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 171142416Sgrehan#define PVO_WIRED 0x010 /* PVO entry is wired */ 172142416Sgrehan#define PVO_MANAGED 0x020 /* PVO entry is managed */ 173142416Sgrehan#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 174142416Sgrehan#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 17592521Sbenno bootstrap */ 176142416Sgrehan#define PVO_FAKE 0x100 /* fictitious phys page */ 17790643Sbenno#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 17890643Sbenno#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 179142416Sgrehan#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 18090643Sbenno#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 18190643Sbenno#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 18290643Sbenno#define PVO_PTEGIDX_CLR(pvo) \ 18390643Sbenno ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 18490643Sbenno#define PVO_PTEGIDX_SET(pvo, i) \ 18590643Sbenno ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 18690643Sbenno 187152180Sgrehan#define MOEA_PVO_CHECK(pvo) 18890643Sbenno 18990643Sbennostruct ofw_map { 19090643Sbenno vm_offset_t om_va; 19190643Sbenno vm_size_t om_len; 19290643Sbenno vm_offset_t om_pa; 19390643Sbenno u_int om_mode; 19490643Sbenno}; 19577957Sbenno 19690643Sbenno/* 19790643Sbenno * Map of physical memory regions. 19890643Sbenno */ 19997346Sbennostatic struct mem_region *regions; 20097346Sbennostatic struct mem_region *pregions; 201152180Sgrehanu_int phys_avail_count; 20297346Sbennoint regions_sz, pregions_sz; 203100319Sbennostatic struct ofw_map *translations; 20477957Sbenno 20590643Sbennoextern struct pmap ofw_pmap; 20677957Sbenno 20790643Sbenno/* 208134535Salc * Lock for the pteg and pvo tables. 209134535Salc */ 210152180Sgrehanstruct mtx moea_table_mutex; 211134535Salc 212134535Salc/* 21390643Sbenno * PTEG data. 21490643Sbenno */ 215152180Sgrehanstatic struct pteg *moea_pteg_table; 216152180Sgrehanu_int moea_pteg_count; 217152180Sgrehanu_int moea_pteg_mask; 21877957Sbenno 21990643Sbenno/* 22090643Sbenno * PVO data. 22190643Sbenno */ 222152180Sgrehanstruct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 223152180Sgrehanstruct pvo_head moea_pvo_kunmanaged = 224152180Sgrehan LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 225152180Sgrehanstruct pvo_head moea_pvo_unmanaged = 226152180Sgrehan LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 22777957Sbenno 228152180Sgrehanuma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 229152180Sgrehanuma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 23077957Sbenno 23199037Sbenno#define BPVO_POOL_SIZE 32768 232152180Sgrehanstatic struct pvo_entry *moea_bpvo_pool; 233152180Sgrehanstatic int moea_bpvo_pool_index = 0; 23477957Sbenno 23590643Sbenno#define VSID_NBPW (sizeof(u_int32_t) * 8) 236152180Sgrehanstatic u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 23777957Sbenno 238152180Sgrehanstatic boolean_t moea_initialized = FALSE; 23977957Sbenno 24090643Sbenno/* 24190643Sbenno * Statistics. 24290643Sbenno */ 243152180Sgrehanu_int moea_pte_valid = 0; 244152180Sgrehanu_int moea_pte_overflow = 0; 245152180Sgrehanu_int moea_pte_replacements = 0; 246152180Sgrehanu_int moea_pvo_entries = 0; 247152180Sgrehanu_int moea_pvo_enter_calls = 0; 248152180Sgrehanu_int moea_pvo_remove_calls = 0; 249152180Sgrehanu_int moea_pte_spills = 0; 250152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 25190643Sbenno 0, ""); 252152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 253152180Sgrehan &moea_pte_overflow, 0, ""); 254152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 255152180Sgrehan &moea_pte_replacements, 0, ""); 256152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 25790643Sbenno 0, ""); 258152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 259152180Sgrehan &moea_pvo_enter_calls, 0, ""); 260152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 261152180Sgrehan &moea_pvo_remove_calls, 0, ""); 262152180SgrehanSYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 263152180Sgrehan &moea_pte_spills, 0, ""); 26477957Sbenno 26590643Sbenno/* 266152180Sgrehan * Allocate physical memory for use in moea_bootstrap. 26790643Sbenno */ 268152180Sgrehanstatic vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 26977957Sbenno 27090643Sbenno/* 27190643Sbenno * PTE calls. 27290643Sbenno */ 273152180Sgrehanstatic int moea_pte_insert(u_int, struct pte *); 27477957Sbenno 27577957Sbenno/* 27690643Sbenno * PVO calls. 27777957Sbenno */ 278152180Sgrehanstatic int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 27990643Sbenno vm_offset_t, vm_offset_t, u_int, int); 280152180Sgrehanstatic void moea_pvo_remove(struct pvo_entry *, int); 281152180Sgrehanstatic struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 282152180Sgrehanstatic struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 28390643Sbenno 28490643Sbenno/* 28590643Sbenno * Utility routines. 28690643Sbenno */ 287159303Salcstatic void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 288159303Salc vm_prot_t, boolean_t); 289152180Sgrehanstatic void moea_syncicache(vm_offset_t, vm_size_t); 290152180Sgrehanstatic boolean_t moea_query_bit(vm_page_t, int); 291152180Sgrehanstatic u_int moea_clear_bit(vm_page_t, int, int *); 292152180Sgrehanstatic void moea_kremove(mmu_t, vm_offset_t); 29390643Sbennostatic void tlbia(void); 294152180Sgrehanint moea_pte_spill(vm_offset_t); 29590643Sbenno 296152180Sgrehan/* 297152180Sgrehan * Kernel MMU interface 298152180Sgrehan */ 299152180Sgrehanvoid moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 300152180Sgrehanvoid moea_clear_modify(mmu_t, vm_page_t); 301152180Sgrehanvoid moea_clear_reference(mmu_t, vm_page_t); 302152180Sgrehanvoid moea_copy_page(mmu_t, vm_page_t, vm_page_t); 303152180Sgrehanvoid moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 304159303Salcvoid moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 305159303Salc vm_prot_t); 306159627Supsvoid moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 307152180Sgrehanvm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 308152180Sgrehanvm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 309152180Sgrehanvoid moea_init(mmu_t); 310152180Sgrehanboolean_t moea_is_modified(mmu_t, vm_page_t); 311152180Sgrehanboolean_t moea_ts_referenced(mmu_t, vm_page_t); 312152180Sgrehanvm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 313152180Sgrehanboolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 314173708Salcint moea_page_wired_mappings(mmu_t, vm_page_t); 315152180Sgrehanvoid moea_pinit(mmu_t, pmap_t); 316152180Sgrehanvoid moea_pinit0(mmu_t, pmap_t); 317152180Sgrehanvoid moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 318152180Sgrehanvoid moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 319152180Sgrehanvoid moea_qremove(mmu_t, vm_offset_t, int); 320152180Sgrehanvoid moea_release(mmu_t, pmap_t); 321152180Sgrehanvoid moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 322152180Sgrehanvoid moea_remove_all(mmu_t, vm_page_t); 323160889Salcvoid moea_remove_write(mmu_t, vm_page_t); 324152180Sgrehanvoid moea_zero_page(mmu_t, vm_page_t); 325152180Sgrehanvoid moea_zero_page_area(mmu_t, vm_page_t, int, int); 326152180Sgrehanvoid moea_zero_page_idle(mmu_t, vm_page_t); 327152180Sgrehanvoid moea_activate(mmu_t, struct thread *); 328152180Sgrehanvoid moea_deactivate(mmu_t, struct thread *); 329152180Sgrehanvoid moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 330152180Sgrehanvoid *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 331152180Sgrehanvoid moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 332152180Sgrehanvm_offset_t moea_kextract(mmu_t, vm_offset_t); 333152180Sgrehanvoid moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 334152180Sgrehanboolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 335164895Sgrehanboolean_t moea_page_executable(mmu_t, vm_page_t); 336152180Sgrehan 337152180Sgrehanstatic mmu_method_t moea_methods[] = { 338152180Sgrehan MMUMETHOD(mmu_change_wiring, moea_change_wiring), 339152180Sgrehan MMUMETHOD(mmu_clear_modify, moea_clear_modify), 340152180Sgrehan MMUMETHOD(mmu_clear_reference, moea_clear_reference), 341152180Sgrehan MMUMETHOD(mmu_copy_page, moea_copy_page), 342152180Sgrehan MMUMETHOD(mmu_enter, moea_enter), 343159303Salc MMUMETHOD(mmu_enter_object, moea_enter_object), 344152180Sgrehan MMUMETHOD(mmu_enter_quick, moea_enter_quick), 345152180Sgrehan MMUMETHOD(mmu_extract, moea_extract), 346152180Sgrehan MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 347152180Sgrehan MMUMETHOD(mmu_init, moea_init), 348152180Sgrehan MMUMETHOD(mmu_is_modified, moea_is_modified), 349152180Sgrehan MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 350152180Sgrehan MMUMETHOD(mmu_map, moea_map), 351152180Sgrehan MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 352173708Salc MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 353152180Sgrehan MMUMETHOD(mmu_pinit, moea_pinit), 354152180Sgrehan MMUMETHOD(mmu_pinit0, moea_pinit0), 355152180Sgrehan MMUMETHOD(mmu_protect, moea_protect), 356152180Sgrehan MMUMETHOD(mmu_qenter, moea_qenter), 357152180Sgrehan MMUMETHOD(mmu_qremove, moea_qremove), 358152180Sgrehan MMUMETHOD(mmu_release, moea_release), 359152180Sgrehan MMUMETHOD(mmu_remove, moea_remove), 360152180Sgrehan MMUMETHOD(mmu_remove_all, moea_remove_all), 361160889Salc MMUMETHOD(mmu_remove_write, moea_remove_write), 362152180Sgrehan MMUMETHOD(mmu_zero_page, moea_zero_page), 363152180Sgrehan MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 364152180Sgrehan MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 365152180Sgrehan MMUMETHOD(mmu_activate, moea_activate), 366152180Sgrehan MMUMETHOD(mmu_deactivate, moea_deactivate), 367152180Sgrehan 368152180Sgrehan /* Internal interfaces */ 369152180Sgrehan MMUMETHOD(mmu_bootstrap, moea_bootstrap), 370152180Sgrehan MMUMETHOD(mmu_mapdev, moea_mapdev), 371152180Sgrehan MMUMETHOD(mmu_unmapdev, moea_unmapdev), 372152180Sgrehan MMUMETHOD(mmu_kextract, moea_kextract), 373152180Sgrehan MMUMETHOD(mmu_kenter, moea_kenter), 374152180Sgrehan MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 375164895Sgrehan MMUMETHOD(mmu_page_executable, moea_page_executable), 376152180Sgrehan 377152180Sgrehan { 0, 0 } 378152180Sgrehan}; 379152180Sgrehan 380152180Sgrehanstatic mmu_def_t oea_mmu = { 381152180Sgrehan MMU_TYPE_OEA, 382152180Sgrehan moea_methods, 383152180Sgrehan 0 384152180Sgrehan}; 385152180SgrehanMMU_DEF(oea_mmu); 386152180Sgrehan 387152180Sgrehan 38890643Sbennostatic __inline int 38990643Sbennova_to_sr(u_int *sr, vm_offset_t va) 39077957Sbenno{ 39190643Sbenno return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 39290643Sbenno} 39377957Sbenno 39490643Sbennostatic __inline u_int 39590643Sbennova_to_pteg(u_int sr, vm_offset_t addr) 39690643Sbenno{ 39790643Sbenno u_int hash; 39890643Sbenno 39990643Sbenno hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 40090643Sbenno ADDR_PIDX_SHFT); 401152180Sgrehan return (hash & moea_pteg_mask); 40277957Sbenno} 40377957Sbenno 40490643Sbennostatic __inline struct pvo_head * 40596250Sbennopa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 40677957Sbenno{ 40790643Sbenno struct vm_page *pg; 40877957Sbenno 40990643Sbenno pg = PHYS_TO_VM_PAGE(pa); 41090643Sbenno 41196250Sbenno if (pg_p != NULL) 41296250Sbenno *pg_p = pg; 41396250Sbenno 41490643Sbenno if (pg == NULL) 415152180Sgrehan return (&moea_pvo_unmanaged); 41690643Sbenno 41790643Sbenno return (&pg->md.mdpg_pvoh); 41877957Sbenno} 41977957Sbenno 42090643Sbennostatic __inline struct pvo_head * 42190643Sbennovm_page_to_pvoh(vm_page_t m) 42290643Sbenno{ 42390643Sbenno 42490643Sbenno return (&m->md.mdpg_pvoh); 42590643Sbenno} 42690643Sbenno 42777957Sbennostatic __inline void 428152180Sgrehanmoea_attr_clear(vm_page_t m, int ptebit) 42977957Sbenno{ 43090643Sbenno 431159928Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 43290643Sbenno m->md.mdpg_attrs &= ~ptebit; 43377957Sbenno} 43477957Sbenno 43577957Sbennostatic __inline int 436152180Sgrehanmoea_attr_fetch(vm_page_t m) 43777957Sbenno{ 43877957Sbenno 43990643Sbenno return (m->md.mdpg_attrs); 44077957Sbenno} 44177957Sbenno 44290643Sbennostatic __inline void 443152180Sgrehanmoea_attr_save(vm_page_t m, int ptebit) 44490643Sbenno{ 44590643Sbenno 446159928Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 44790643Sbenno m->md.mdpg_attrs |= ptebit; 44890643Sbenno} 44990643Sbenno 45077957Sbennostatic __inline int 451152180Sgrehanmoea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 45277957Sbenno{ 45390643Sbenno if (pt->pte_hi == pvo_pt->pte_hi) 45490643Sbenno return (1); 45590643Sbenno 45690643Sbenno return (0); 45777957Sbenno} 45877957Sbenno 45977957Sbennostatic __inline int 460152180Sgrehanmoea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 46177957Sbenno{ 46290643Sbenno return (pt->pte_hi & ~PTE_VALID) == 46390643Sbenno (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 46490643Sbenno ((va >> ADDR_API_SHFT) & PTE_API) | which); 46590643Sbenno} 46677957Sbenno 46790643Sbennostatic __inline void 468152180Sgrehanmoea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 46990643Sbenno{ 470159928Salc 471159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 472159928Salc 47390643Sbenno /* 47490643Sbenno * Construct a PTE. Default to IMB initially. Valid bit only gets 47590643Sbenno * set when the real pte is set in memory. 47690643Sbenno * 47790643Sbenno * Note: Don't set the valid bit for correct operation of tlb update. 47890643Sbenno */ 47990643Sbenno pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 48090643Sbenno (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 48190643Sbenno pt->pte_lo = pte_lo; 48277957Sbenno} 48377957Sbenno 48490643Sbennostatic __inline void 485152180Sgrehanmoea_pte_synch(struct pte *pt, struct pte *pvo_pt) 48677957Sbenno{ 48777957Sbenno 488159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 48990643Sbenno pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 49077957Sbenno} 49177957Sbenno 49290643Sbennostatic __inline void 493152180Sgrehanmoea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 49477957Sbenno{ 49577957Sbenno 496159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 497159928Salc 49890643Sbenno /* 49990643Sbenno * As shown in Section 7.6.3.2.3 50090643Sbenno */ 50190643Sbenno pt->pte_lo &= ~ptebit; 50290643Sbenno TLBIE(va); 50390643Sbenno EIEIO(); 50490643Sbenno TLBSYNC(); 50590643Sbenno SYNC(); 50677957Sbenno} 50777957Sbenno 50890643Sbennostatic __inline void 509152180Sgrehanmoea_pte_set(struct pte *pt, struct pte *pvo_pt) 51077957Sbenno{ 51177957Sbenno 512159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 51390643Sbenno pvo_pt->pte_hi |= PTE_VALID; 51490643Sbenno 51577957Sbenno /* 51690643Sbenno * Update the PTE as defined in section 7.6.3.1. 51790643Sbenno * Note that the REF/CHG bits are from pvo_pt and thus should havce 51890643Sbenno * been saved so this routine can restore them (if desired). 51977957Sbenno */ 52090643Sbenno pt->pte_lo = pvo_pt->pte_lo; 52190643Sbenno EIEIO(); 52290643Sbenno pt->pte_hi = pvo_pt->pte_hi; 52390643Sbenno SYNC(); 524152180Sgrehan moea_pte_valid++; 52590643Sbenno} 52677957Sbenno 52790643Sbennostatic __inline void 528152180Sgrehanmoea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 52990643Sbenno{ 53090643Sbenno 531159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 53290643Sbenno pvo_pt->pte_hi &= ~PTE_VALID; 53390643Sbenno 53477957Sbenno /* 53590643Sbenno * Force the reg & chg bits back into the PTEs. 53677957Sbenno */ 53790643Sbenno SYNC(); 53877957Sbenno 53990643Sbenno /* 54090643Sbenno * Invalidate the pte. 54190643Sbenno */ 54290643Sbenno pt->pte_hi &= ~PTE_VALID; 54377957Sbenno 54490643Sbenno SYNC(); 54590643Sbenno TLBIE(va); 54690643Sbenno EIEIO(); 54790643Sbenno TLBSYNC(); 54890643Sbenno SYNC(); 54977957Sbenno 55090643Sbenno /* 55190643Sbenno * Save the reg & chg bits. 55290643Sbenno */ 553152180Sgrehan moea_pte_synch(pt, pvo_pt); 554152180Sgrehan moea_pte_valid--; 55577957Sbenno} 55677957Sbenno 55790643Sbennostatic __inline void 558152180Sgrehanmoea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 55990643Sbenno{ 56090643Sbenno 56190643Sbenno /* 56290643Sbenno * Invalidate the PTE 56390643Sbenno */ 564152180Sgrehan moea_pte_unset(pt, pvo_pt, va); 565152180Sgrehan moea_pte_set(pt, pvo_pt); 56690643Sbenno} 56790643Sbenno 56877957Sbenno/* 56990643Sbenno * Quick sort callout for comparing memory regions. 57077957Sbenno */ 57190643Sbennostatic int mr_cmp(const void *a, const void *b); 57290643Sbennostatic int om_cmp(const void *a, const void *b); 57390643Sbenno 57490643Sbennostatic int 57590643Sbennomr_cmp(const void *a, const void *b) 57677957Sbenno{ 57790643Sbenno const struct mem_region *regiona; 57890643Sbenno const struct mem_region *regionb; 57977957Sbenno 58090643Sbenno regiona = a; 58190643Sbenno regionb = b; 58290643Sbenno if (regiona->mr_start < regionb->mr_start) 58390643Sbenno return (-1); 58490643Sbenno else if (regiona->mr_start > regionb->mr_start) 58590643Sbenno return (1); 58690643Sbenno else 58790643Sbenno return (0); 58890643Sbenno} 58977957Sbenno 59090643Sbennostatic int 59190643Sbennoom_cmp(const void *a, const void *b) 59290643Sbenno{ 59390643Sbenno const struct ofw_map *mapa; 59490643Sbenno const struct ofw_map *mapb; 59590643Sbenno 59690643Sbenno mapa = a; 59790643Sbenno mapb = b; 59890643Sbenno if (mapa->om_pa < mapb->om_pa) 59990643Sbenno return (-1); 60090643Sbenno else if (mapa->om_pa > mapb->om_pa) 60190643Sbenno return (1); 60290643Sbenno else 60390643Sbenno return (0); 60477957Sbenno} 60577957Sbenno 60677957Sbennovoid 607178628Smarcelpmap_cpu_bootstrap(volatile uint32_t *trcp, int ap) 608178628Smarcel{ 609178628Smarcel u_int sdr; 610178628Smarcel int i; 611178628Smarcel 612178628Smarcel trcp[0] = 0x1000; 613178628Smarcel trcp[1] = (uint32_t)&pmap_cpu_bootstrap; 614178628Smarcel 615178628Smarcel if (ap) { 616178628Smarcel __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 617178628Smarcel __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 618178628Smarcel isync(); 619178628Smarcel __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 620178628Smarcel __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 621178628Smarcel isync(); 622178628Smarcel } 623178628Smarcel 624178628Smarcel trcp[0] = 0x1001; 625178628Smarcel 626178628Smarcel for (i = 1; i < 4; i++) { 627178628Smarcel __asm __volatile("mtdbatu %0,%1" :: "n"(i), "r"(0)); 628178628Smarcel __asm __volatile("mtibatu %0,%1" :: "n"(i), "r"(0)); 629178628Smarcel isync(); 630178628Smarcel } 631178628Smarcel 632178628Smarcel trcp[0] = 0x1002; 633178628Smarcel 634178628Smarcel __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 635178628Smarcel __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 636178628Smarcel isync(); 637178628Smarcel 638178628Smarcel trcp[0] = 0x1003; 639178628Smarcel 640178628Smarcel for (i = 0; i < 16; i++) 641178628Smarcel mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 642178628Smarcel 643178628Smarcel trcp[0] = 0x1004; 644178628Smarcel 645178628Smarcel __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 646178628Smarcel __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 647178628Smarcel __asm __volatile("sync"); 648178628Smarcel 649178628Smarcel trcp[0] = 0x1005; 650178628Smarcel 651178628Smarcel sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 652178628Smarcel __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 653178628Smarcel isync(); 654178628Smarcel 655178628Smarcel trcp[0] = 0x1006; 656178628Smarcel trcp[1] = sdr; 657178628Smarcel} 658178628Smarcel 659178628Smarcelvoid 660152180Sgrehanmoea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 66177957Sbenno{ 66297346Sbenno ihandle_t mmui; 66390643Sbenno phandle_t chosen, mmu; 66490643Sbenno int sz; 66590643Sbenno int i, j; 666103604Sgrehan int ofw_mappings; 667178628Smarcel uint32_t trace[2]; 668143200Sgrehan vm_size_t size, physsz, hwphyssz; 66990643Sbenno vm_offset_t pa, va, off; 67077957Sbenno 67199037Sbenno /* 672103604Sgrehan * Set up BAT0 to map the lowest 256 MB area 67399037Sbenno */ 67499037Sbenno battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 67599037Sbenno battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 67699037Sbenno 67799037Sbenno /* 67899037Sbenno * Map PCI memory space. 67999037Sbenno */ 68099037Sbenno battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 68199037Sbenno battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 68299037Sbenno 68399037Sbenno battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 68499037Sbenno battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 68599037Sbenno 68699037Sbenno battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 68799037Sbenno battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 68899037Sbenno 68999037Sbenno battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 69099037Sbenno battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 69199037Sbenno 69299037Sbenno /* 69399037Sbenno * Map obio devices. 69499037Sbenno */ 69599037Sbenno battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 69699037Sbenno battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 69799037Sbenno 69877957Sbenno /* 69990643Sbenno * Use an IBAT and a DBAT to map the bottom segment of memory 70090643Sbenno * where we are. 70177957Sbenno */ 702152180Sgrehan __asm (".balign 32; \n" 703149958Sgrehan "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 704131808Sgrehan "mtdbatu 0,%0; mtdbatl 0,%1; isync" 705178628Smarcel :: "r"(battable[0].batu), "r"(battable[0].batl)); 70699037Sbenno 70799037Sbenno /* map pci space */ 708178628Smarcel __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 709178628Smarcel __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 710178628Smarcel isync(); 71177957Sbenno 71297346Sbenno mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 713152180Sgrehan CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 71497346Sbenno 71597346Sbenno qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 71697346Sbenno for (i = 0; i < pregions_sz; i++) { 717103604Sgrehan vm_offset_t pa; 718103604Sgrehan vm_offset_t end; 719103604Sgrehan 72097346Sbenno CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 72197346Sbenno pregions[i].mr_start, 72297346Sbenno pregions[i].mr_start + pregions[i].mr_size, 72397346Sbenno pregions[i].mr_size); 724103604Sgrehan /* 725103604Sgrehan * Install entries into the BAT table to allow all 726103604Sgrehan * of physmem to be convered by on-demand BAT entries. 727103604Sgrehan * The loop will sometimes set the same battable element 728103604Sgrehan * twice, but that's fine since they won't be used for 729103604Sgrehan * a while yet. 730103604Sgrehan */ 731103604Sgrehan pa = pregions[i].mr_start & 0xf0000000; 732103604Sgrehan end = pregions[i].mr_start + pregions[i].mr_size; 733103604Sgrehan do { 734103604Sgrehan u_int n = pa >> ADDR_SR_SHFT; 735152180Sgrehan 736103604Sgrehan battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 737103604Sgrehan battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 738103604Sgrehan pa += SEGMENT_LENGTH; 739103604Sgrehan } while (pa < end); 74097346Sbenno } 74197346Sbenno 74297346Sbenno if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 743152180Sgrehan panic("moea_bootstrap: phys_avail too small"); 74497346Sbenno qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 74590643Sbenno phys_avail_count = 0; 74691793Sbenno physsz = 0; 747143234Sgrehan hwphyssz = 0; 748143234Sgrehan TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 74997346Sbenno for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 75090643Sbenno CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 75190643Sbenno regions[i].mr_start + regions[i].mr_size, 75290643Sbenno regions[i].mr_size); 753143200Sgrehan if (hwphyssz != 0 && 754143200Sgrehan (physsz + regions[i].mr_size) >= hwphyssz) { 755143200Sgrehan if (physsz < hwphyssz) { 756143200Sgrehan phys_avail[j] = regions[i].mr_start; 757143200Sgrehan phys_avail[j + 1] = regions[i].mr_start + 758143200Sgrehan hwphyssz - physsz; 759143200Sgrehan physsz = hwphyssz; 760143200Sgrehan phys_avail_count++; 761143200Sgrehan } 762143200Sgrehan break; 763143200Sgrehan } 76490643Sbenno phys_avail[j] = regions[i].mr_start; 76590643Sbenno phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 76690643Sbenno phys_avail_count++; 76791793Sbenno physsz += regions[i].mr_size; 76877957Sbenno } 76991793Sbenno physmem = btoc(physsz); 77077957Sbenno 77177957Sbenno /* 77290643Sbenno * Allocate PTEG table. 77377957Sbenno */ 77490643Sbenno#ifdef PTEGCOUNT 775152180Sgrehan moea_pteg_count = PTEGCOUNT; 77690643Sbenno#else 777152180Sgrehan moea_pteg_count = 0x1000; 77877957Sbenno 779152180Sgrehan while (moea_pteg_count < physmem) 780152180Sgrehan moea_pteg_count <<= 1; 78177957Sbenno 782152180Sgrehan moea_pteg_count >>= 1; 78390643Sbenno#endif /* PTEGCOUNT */ 78477957Sbenno 785152180Sgrehan size = moea_pteg_count * sizeof(struct pteg); 786152180Sgrehan CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 78790643Sbenno size); 788152180Sgrehan moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 789152180Sgrehan CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 790152180Sgrehan bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 791152180Sgrehan moea_pteg_mask = moea_pteg_count - 1; 79277957Sbenno 79390643Sbenno /* 79494839Sbenno * Allocate pv/overflow lists. 79590643Sbenno */ 796152180Sgrehan size = sizeof(struct pvo_head) * moea_pteg_count; 797152180Sgrehan moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 79890643Sbenno PAGE_SIZE); 799152180Sgrehan CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 800152180Sgrehan for (i = 0; i < moea_pteg_count; i++) 801152180Sgrehan LIST_INIT(&moea_pvo_table[i]); 80277957Sbenno 80390643Sbenno /* 804134535Salc * Initialize the lock that synchronizes access to the pteg and pvo 805134535Salc * tables. 806134535Salc */ 807159928Salc mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 808159928Salc MTX_RECURSE); 809134535Salc 810134535Salc /* 81190643Sbenno * Initialise the unmanaged pvo pool. 81290643Sbenno */ 813152180Sgrehan moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 81499037Sbenno BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 815152180Sgrehan moea_bpvo_pool_index = 0; 81677957Sbenno 81777957Sbenno /* 81890643Sbenno * Make sure kernel vsid is allocated as well as VSID 0. 81977957Sbenno */ 820152180Sgrehan moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 82190643Sbenno |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 822152180Sgrehan moea_vsid_bitmap[0] |= 1; 82377957Sbenno 82490643Sbenno /* 825133862Smarius * Set up the Open Firmware pmap and add it's mappings. 82690643Sbenno */ 827152180Sgrehan moea_pinit(mmup, &ofw_pmap); 82890643Sbenno ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 829126478Sgrehan ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 83090643Sbenno if ((chosen = OF_finddevice("/chosen")) == -1) 831152180Sgrehan panic("moea_bootstrap: can't find /chosen"); 83290643Sbenno OF_getprop(chosen, "mmu", &mmui, 4); 83390643Sbenno if ((mmu = OF_instance_to_package(mmui)) == -1) 834152180Sgrehan panic("moea_bootstrap: can't get mmu package"); 83590643Sbenno if ((sz = OF_getproplen(mmu, "translations")) == -1) 836152180Sgrehan panic("moea_bootstrap: can't get ofw translation count"); 837100319Sbenno translations = NULL; 838131401Sgrehan for (i = 0; phys_avail[i] != 0; i += 2) { 839131401Sgrehan if (phys_avail[i + 1] >= sz) { 840100319Sbenno translations = (struct ofw_map *)phys_avail[i]; 841131401Sgrehan break; 842131401Sgrehan } 843100319Sbenno } 844100319Sbenno if (translations == NULL) 845152180Sgrehan panic("moea_bootstrap: no space to copy translations"); 84690643Sbenno bzero(translations, sz); 84790643Sbenno if (OF_getprop(mmu, "translations", translations, sz) == -1) 848152180Sgrehan panic("moea_bootstrap: can't get ofw translations"); 849152180Sgrehan CTR0(KTR_PMAP, "moea_bootstrap: translations"); 85097346Sbenno sz /= sizeof(*translations); 85190643Sbenno qsort(translations, sz, sizeof (*translations), om_cmp); 852103604Sgrehan for (i = 0, ofw_mappings = 0; i < sz; i++) { 85390643Sbenno CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 85490643Sbenno translations[i].om_pa, translations[i].om_va, 85590643Sbenno translations[i].om_len); 85677957Sbenno 857103604Sgrehan /* 858103604Sgrehan * If the mapping is 1:1, let the RAM and device on-demand 859103604Sgrehan * BAT tables take care of the translation. 860103604Sgrehan */ 861103604Sgrehan if (translations[i].om_va == translations[i].om_pa) 862103604Sgrehan continue; 86377957Sbenno 864103604Sgrehan /* Enter the pages */ 86590643Sbenno for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 86690643Sbenno struct vm_page m; 86777957Sbenno 86890643Sbenno m.phys_addr = translations[i].om_pa + off; 869159705Srink PMAP_LOCK(&ofw_pmap); 870159303Salc moea_enter_locked(&ofw_pmap, 871152180Sgrehan translations[i].om_va + off, &m, 872103604Sgrehan VM_PROT_ALL, 1); 873159705Srink PMAP_UNLOCK(&ofw_pmap); 874103604Sgrehan ofw_mappings++; 87577957Sbenno } 87677957Sbenno } 87777957Sbenno 87890643Sbenno /* 879178261Smarcel * Calculate the last available physical address. 880178261Smarcel */ 881178261Smarcel for (i = 0; phys_avail[i + 2] != 0; i += 2) 882178261Smarcel ; 883178261Smarcel Maxmem = powerpc_btop(phys_avail[i + 1]); 884178261Smarcel 885178261Smarcel /* 88690643Sbenno * Initialize the kernel pmap (which is statically allocated). 88790643Sbenno */ 888134329Salc PMAP_LOCK_INIT(kernel_pmap); 88990643Sbenno for (i = 0; i < 16; i++) { 89090643Sbenno kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 89177957Sbenno } 89290643Sbenno kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 893139401Sgrehan kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 89490643Sbenno kernel_pmap->pm_active = ~0; 89577957Sbenno 896178628Smarcel pmap_cpu_bootstrap(trace, 0); 89777957Sbenno tlbia(); 89877957Sbenno 89990643Sbenno pmap_bootstrapped++; 900178261Smarcel 901178261Smarcel /* 902178261Smarcel * Set the start and end of kva. 903178261Smarcel */ 904178261Smarcel virtual_avail = VM_MIN_KERNEL_ADDRESS; 905178261Smarcel virtual_end = VM_MAX_KERNEL_ADDRESS; 906178261Smarcel 907178261Smarcel /* 908178261Smarcel * Allocate a kernel stack with a guard page for thread0 and map it 909178261Smarcel * into the kernel page map. 910178261Smarcel */ 911178261Smarcel pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 912178261Smarcel va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 913178261Smarcel virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 914178261Smarcel CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 915178261Smarcel thread0.td_kstack = va; 916178261Smarcel thread0.td_kstack_pages = KSTACK_PAGES; 917178261Smarcel for (i = 0; i < KSTACK_PAGES; i++) { 918178261Smarcel moea_kenter(mmup, va, pa);; 919178261Smarcel pa += PAGE_SIZE; 920178261Smarcel va += PAGE_SIZE; 921178261Smarcel } 922178261Smarcel 923178261Smarcel /* 924178261Smarcel * Allocate virtual address space for the message buffer. 925178261Smarcel */ 926178261Smarcel pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE); 927178261Smarcel msgbufp = (struct msgbuf *)virtual_avail; 928178261Smarcel va = virtual_avail; 929178261Smarcel virtual_avail += round_page(MSGBUF_SIZE); 930178261Smarcel while (va < virtual_avail) { 931178261Smarcel moea_kenter(mmup, va, pa);; 932178261Smarcel pa += PAGE_SIZE; 933178261Smarcel va += PAGE_SIZE; 934178261Smarcel } 93577957Sbenno} 93677957Sbenno 93777957Sbenno/* 93890643Sbenno * Activate a user pmap. The pmap must be activated before it's address 93990643Sbenno * space can be accessed in any way. 94077957Sbenno */ 94177957Sbennovoid 942152180Sgrehanmoea_activate(mmu_t mmu, struct thread *td) 94377957Sbenno{ 94496250Sbenno pmap_t pm, pmr; 94577957Sbenno 94677957Sbenno /* 947103604Sgrehan * Load all the data we need up front to encourage the compiler to 94890643Sbenno * not issue any loads while we have interrupts disabled below. 94977957Sbenno */ 95090643Sbenno pm = &td->td_proc->p_vmspace->vm_pmap; 95177957Sbenno 952152180Sgrehan if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL) 95396250Sbenno pmr = pm; 95496250Sbenno 95590643Sbenno pm->pm_active |= PCPU_GET(cpumask); 95696250Sbenno PCPU_SET(curpmap, pmr); 95777957Sbenno} 95877957Sbenno 95991483Sbennovoid 960152180Sgrehanmoea_deactivate(mmu_t mmu, struct thread *td) 96191483Sbenno{ 96291483Sbenno pmap_t pm; 96391483Sbenno 96491483Sbenno pm = &td->td_proc->p_vmspace->vm_pmap; 96591483Sbenno pm->pm_active &= ~(PCPU_GET(cpumask)); 96696250Sbenno PCPU_SET(curpmap, NULL); 96791483Sbenno} 96891483Sbenno 96977957Sbennovoid 970152180Sgrehanmoea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 97177957Sbenno{ 97296353Sbenno struct pvo_entry *pvo; 97396353Sbenno 974134329Salc PMAP_LOCK(pm); 975152180Sgrehan pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 97696353Sbenno 97796353Sbenno if (pvo != NULL) { 97896353Sbenno if (wired) { 97996353Sbenno if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 98096353Sbenno pm->pm_stats.wired_count++; 98196353Sbenno pvo->pvo_vaddr |= PVO_WIRED; 98296353Sbenno } else { 98396353Sbenno if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 98496353Sbenno pm->pm_stats.wired_count--; 98596353Sbenno pvo->pvo_vaddr &= ~PVO_WIRED; 98696353Sbenno } 98796353Sbenno } 988134329Salc PMAP_UNLOCK(pm); 98977957Sbenno} 99077957Sbenno 99177957Sbennovoid 992152180Sgrehanmoea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 99377957Sbenno{ 99497385Sbenno vm_offset_t dst; 99597385Sbenno vm_offset_t src; 99697385Sbenno 99797385Sbenno dst = VM_PAGE_TO_PHYS(mdst); 99897385Sbenno src = VM_PAGE_TO_PHYS(msrc); 99997385Sbenno 100097385Sbenno kcopy((void *)src, (void *)dst, PAGE_SIZE); 100177957Sbenno} 100277957Sbenno 100377957Sbenno/* 100490643Sbenno * Zero a page of physical memory by temporarily mapping it into the tlb. 100577957Sbenno */ 100677957Sbennovoid 1007152180Sgrehanmoea_zero_page(mmu_t mmu, vm_page_t m) 100877957Sbenno{ 100994777Speter vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1010178265Smarcel void *va = (void *)pa; 101177957Sbenno 101290643Sbenno bzero(va, PAGE_SIZE); 101377957Sbenno} 101477957Sbenno 101577957Sbennovoid 1016152180Sgrehanmoea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 101777957Sbenno{ 101899666Sbenno vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1019178265Smarcel void *va = (void *)(pa + off); 102099666Sbenno 1021178265Smarcel bzero(va, size); 102277957Sbenno} 102377957Sbenno 102499571Spetervoid 1025152180Sgrehanmoea_zero_page_idle(mmu_t mmu, vm_page_t m) 102699571Speter{ 1027178265Smarcel vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1028178265Smarcel void *va = (void *)pa; 102999571Speter 1030178265Smarcel bzero(va, PAGE_SIZE); 103199571Speter} 103299571Speter 103377957Sbenno/* 103490643Sbenno * Map the given physical page at the specified virtual address in the 103590643Sbenno * target pmap with the protection requested. If specified the page 103690643Sbenno * will be wired down. 103777957Sbenno */ 103877957Sbennovoid 1039152180Sgrehanmoea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 104090643Sbenno boolean_t wired) 104177957Sbenno{ 1042159303Salc 1043159303Salc vm_page_lock_queues(); 1044159303Salc PMAP_LOCK(pmap); 1045159324Salc moea_enter_locked(pmap, va, m, prot, wired); 1046159303Salc vm_page_unlock_queues(); 1047159303Salc PMAP_UNLOCK(pmap); 1048159303Salc} 1049159303Salc 1050159303Salc/* 1051159303Salc * Map the given physical page at the specified virtual address in the 1052159303Salc * target pmap with the protection requested. If specified the page 1053159303Salc * will be wired down. 1054159303Salc * 1055159303Salc * The page queues and pmap must be locked. 1056159303Salc */ 1057159303Salcstatic void 1058159303Salcmoea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1059159303Salc boolean_t wired) 1060159303Salc{ 106190643Sbenno struct pvo_head *pvo_head; 106292847Sjeff uma_zone_t zone; 106396250Sbenno vm_page_t pg; 106496250Sbenno u_int pte_lo, pvo_flags, was_exec, i; 106590643Sbenno int error; 106677957Sbenno 1067152180Sgrehan if (!moea_initialized) { 1068152180Sgrehan pvo_head = &moea_pvo_kunmanaged; 1069152180Sgrehan zone = moea_upvo_zone; 107090643Sbenno pvo_flags = 0; 107196250Sbenno pg = NULL; 107296250Sbenno was_exec = PTE_EXEC; 107390643Sbenno } else { 1074110172Sgrehan pvo_head = vm_page_to_pvoh(m); 1075110172Sgrehan pg = m; 1076152180Sgrehan zone = moea_mpvo_zone; 107790643Sbenno pvo_flags = PVO_MANAGED; 107896250Sbenno was_exec = 0; 107990643Sbenno } 1080134535Salc if (pmap_bootstrapped) 1081159303Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1082159303Salc PMAP_LOCK_ASSERT(pmap, MA_OWNED); 108377957Sbenno 1084142416Sgrehan /* XXX change the pvo head for fake pages */ 1085142416Sgrehan if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) 1086152180Sgrehan pvo_head = &moea_pvo_kunmanaged; 1087142416Sgrehan 108896250Sbenno /* 108996250Sbenno * If this is a managed page, and it's the first reference to the page, 109096250Sbenno * clear the execness of the page. Otherwise fetch the execness. 109196250Sbenno */ 1092142416Sgrehan if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 109396250Sbenno if (LIST_EMPTY(pvo_head)) { 1094152180Sgrehan moea_attr_clear(pg, PTE_EXEC); 109596250Sbenno } else { 1096152180Sgrehan was_exec = moea_attr_fetch(pg) & PTE_EXEC; 109796250Sbenno } 109896250Sbenno } 109996250Sbenno 110096250Sbenno /* 110196250Sbenno * Assume the page is cache inhibited and access is guarded unless 110296250Sbenno * it's in our available memory array. 110396250Sbenno */ 110490643Sbenno pte_lo = PTE_I | PTE_G; 110597346Sbenno for (i = 0; i < pregions_sz; i++) { 110697346Sbenno if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 110797346Sbenno (VM_PAGE_TO_PHYS(m) < 110897346Sbenno (pregions[i].mr_start + pregions[i].mr_size))) { 110996250Sbenno pte_lo &= ~(PTE_I | PTE_G); 111096250Sbenno break; 111196250Sbenno } 111296250Sbenno } 111377957Sbenno 1114164229Salc if (prot & VM_PROT_WRITE) { 111590643Sbenno pte_lo |= PTE_BW; 1116164765Sgrehan if (pmap_bootstrapped) 1117164765Sgrehan vm_page_flag_set(m, PG_WRITEABLE); 1118164229Salc } else 111990643Sbenno pte_lo |= PTE_BR; 112077957Sbenno 1121142416Sgrehan if (prot & VM_PROT_EXECUTE) 1122142416Sgrehan pvo_flags |= PVO_EXECUTABLE; 112377957Sbenno 112490643Sbenno if (wired) 112590643Sbenno pvo_flags |= PVO_WIRED; 112677957Sbenno 1127142416Sgrehan if ((m->flags & PG_FICTITIOUS) != 0) 1128142416Sgrehan pvo_flags |= PVO_FAKE; 1129142416Sgrehan 1130152180Sgrehan error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 113196250Sbenno pte_lo, pvo_flags); 113290643Sbenno 113396250Sbenno /* 113496250Sbenno * Flush the real page from the instruction cache if this page is 113596250Sbenno * mapped executable and cacheable and was not previously mapped (or 113696250Sbenno * was not mapped executable). 113796250Sbenno */ 113896250Sbenno if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 113996250Sbenno (pte_lo & PTE_I) == 0 && was_exec == 0) { 114077957Sbenno /* 114190643Sbenno * Flush the real memory from the cache. 114277957Sbenno */ 1143152180Sgrehan moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 114496250Sbenno if (pg != NULL) 1145152180Sgrehan moea_attr_save(pg, PTE_EXEC); 114677957Sbenno } 1147103604Sgrehan 1148103604Sgrehan /* XXX syncicache always until problems are sorted */ 1149152180Sgrehan moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 115077957Sbenno} 115177957Sbenno 1152159303Salc/* 1153159303Salc * Maps a sequence of resident pages belonging to the same object. 1154159303Salc * The sequence begins with the given page m_start. This page is 1155159303Salc * mapped at the given virtual address start. Each subsequent page is 1156159303Salc * mapped at a virtual address that is offset from start by the same 1157159303Salc * amount as the page is offset from m_start within the object. The 1158159303Salc * last page in the sequence is the page with the largest offset from 1159159303Salc * m_start that can be mapped at a virtual address less than the given 1160159303Salc * virtual address end. Not every virtual page between start and end 1161159303Salc * is mapped; only those for which a resident page exists with the 1162159303Salc * corresponding offset from m_start are mapped. 1163159303Salc */ 1164159303Salcvoid 1165159303Salcmoea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1166159303Salc vm_page_t m_start, vm_prot_t prot) 1167159303Salc{ 1168159303Salc vm_page_t m; 1169159303Salc vm_pindex_t diff, psize; 1170159303Salc 1171159303Salc psize = atop(end - start); 1172159303Salc m = m_start; 1173159303Salc PMAP_LOCK(pm); 1174159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1175159303Salc moea_enter_locked(pm, start + ptoa(diff), m, prot & 1176159303Salc (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1177159303Salc m = TAILQ_NEXT(m, listq); 1178159303Salc } 1179159303Salc PMAP_UNLOCK(pm); 1180159303Salc} 1181159303Salc 1182159627Supsvoid 1183152180Sgrehanmoea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1184159627Sups vm_prot_t prot) 1185117045Salc{ 1186117045Salc 1187159303Salc PMAP_LOCK(pm); 1188159303Salc moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1189152180Sgrehan FALSE); 1190159303Salc PMAP_UNLOCK(pm); 1191159627Sups 1192117045Salc} 1193117045Salc 1194131658Salcvm_paddr_t 1195152180Sgrehanmoea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 119677957Sbenno{ 119796353Sbenno struct pvo_entry *pvo; 1198134329Salc vm_paddr_t pa; 119996353Sbenno 1200134329Salc PMAP_LOCK(pm); 1201152180Sgrehan pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1202134329Salc if (pvo == NULL) 1203134329Salc pa = 0; 1204134329Salc else 1205134329Salc pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1206134329Salc PMAP_UNLOCK(pm); 1207134329Salc return (pa); 120877957Sbenno} 120977957Sbenno 121077957Sbenno/* 1211120336Sgrehan * Atomically extract and hold the physical page with the given 1212120336Sgrehan * pmap and virtual address pair if that mapping permits the given 1213120336Sgrehan * protection. 1214120336Sgrehan */ 1215120336Sgrehanvm_page_t 1216152180Sgrehanmoea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1217120336Sgrehan{ 1218132666Salc struct pvo_entry *pvo; 1219120336Sgrehan vm_page_t m; 1220120336Sgrehan 1221120336Sgrehan m = NULL; 1222134329Salc vm_page_lock_queues(); 1223134329Salc PMAP_LOCK(pmap); 1224152180Sgrehan pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1225132666Salc if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) && 1226132666Salc ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW || 1227132666Salc (prot & VM_PROT_WRITE) == 0)) { 1228132666Salc m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1229120336Sgrehan vm_page_hold(m); 1230120336Sgrehan } 1231134329Salc vm_page_unlock_queues(); 1232134329Salc PMAP_UNLOCK(pmap); 1233120336Sgrehan return (m); 1234120336Sgrehan} 1235120336Sgrehan 123690643Sbennovoid 1237152180Sgrehanmoea_init(mmu_t mmu) 123877957Sbenno{ 123977957Sbenno 1240152180Sgrehan CTR0(KTR_PMAP, "moea_init"); 1241147217Salc 1242152180Sgrehan moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1243125442Sgrehan NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1244125442Sgrehan UMA_ZONE_VM | UMA_ZONE_NOFREE); 1245152180Sgrehan moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1246125442Sgrehan NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1247125442Sgrehan UMA_ZONE_VM | UMA_ZONE_NOFREE); 1248152180Sgrehan moea_initialized = TRUE; 124977957Sbenno} 125077957Sbenno 125190643Sbennoboolean_t 1252152180Sgrehanmoea_is_modified(mmu_t mmu, vm_page_t m) 125390643Sbenno{ 125496353Sbenno 1255110172Sgrehan if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 125696353Sbenno return (FALSE); 125796353Sbenno 1258152180Sgrehan return (moea_query_bit(m, PTE_CHG)); 125990643Sbenno} 126090643Sbenno 126190643Sbennovoid 1262152180Sgrehanmoea_clear_reference(mmu_t mmu, vm_page_t m) 126390643Sbenno{ 1264110172Sgrehan 1265110172Sgrehan if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1266110172Sgrehan return; 1267152180Sgrehan moea_clear_bit(m, PTE_REF, NULL); 126890643Sbenno} 126990643Sbenno 1270110172Sgrehanvoid 1271152180Sgrehanmoea_clear_modify(mmu_t mmu, vm_page_t m) 1272110172Sgrehan{ 1273110172Sgrehan 1274110172Sgrehan if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1275110172Sgrehan return; 1276152180Sgrehan moea_clear_bit(m, PTE_CHG, NULL); 1277110172Sgrehan} 1278110172Sgrehan 127991403Ssilby/* 1280160889Salc * Clear the write and modified bits in each of the given page's mappings. 1281160889Salc */ 1282160889Salcvoid 1283160889Salcmoea_remove_write(mmu_t mmu, vm_page_t m) 1284160889Salc{ 1285160889Salc struct pvo_entry *pvo; 1286160889Salc struct pte *pt; 1287160889Salc pmap_t pmap; 1288160889Salc u_int lo; 1289160889Salc 1290160889Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1291160889Salc if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1292160889Salc (m->flags & PG_WRITEABLE) == 0) 1293160889Salc return; 1294160889Salc lo = moea_attr_fetch(m); 1295160889Salc SYNC(); 1296160889Salc LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1297160889Salc pmap = pvo->pvo_pmap; 1298160889Salc PMAP_LOCK(pmap); 1299160889Salc if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) { 1300160889Salc pt = moea_pvo_to_pte(pvo, -1); 1301160889Salc pvo->pvo_pte.pte_lo &= ~PTE_PP; 1302160889Salc pvo->pvo_pte.pte_lo |= PTE_BR; 1303160889Salc if (pt != NULL) { 1304160889Salc moea_pte_synch(pt, &pvo->pvo_pte); 1305160889Salc lo |= pvo->pvo_pte.pte_lo; 1306160889Salc pvo->pvo_pte.pte_lo &= ~PTE_CHG; 1307160889Salc moea_pte_change(pt, &pvo->pvo_pte, 1308160889Salc pvo->pvo_vaddr); 1309160889Salc mtx_unlock(&moea_table_mutex); 1310160889Salc } 1311160889Salc } 1312160889Salc PMAP_UNLOCK(pmap); 1313160889Salc } 1314160889Salc if ((lo & PTE_CHG) != 0) { 1315160889Salc moea_attr_clear(m, PTE_CHG); 1316160889Salc vm_page_dirty(m); 1317160889Salc } 1318160889Salc vm_page_flag_clear(m, PG_WRITEABLE); 1319160889Salc} 1320160889Salc 1321160889Salc/* 1322152180Sgrehan * moea_ts_referenced: 132391403Ssilby * 132491403Ssilby * Return a count of reference bits for a page, clearing those bits. 132591403Ssilby * It is not necessary for every reference bit to be cleared, but it 132691403Ssilby * is necessary that 0 only be returned when there are truly no 132791403Ssilby * reference bits set. 132891403Ssilby * 132991403Ssilby * XXX: The exact number of bits to check and clear is a matter that 133091403Ssilby * should be tested and standardized at some point in the future for 133191403Ssilby * optimal aging of shared pages. 133291403Ssilby */ 1333152180Sgrehanboolean_t 1334152180Sgrehanmoea_ts_referenced(mmu_t mmu, vm_page_t m) 133590643Sbenno{ 1336110172Sgrehan int count; 1337110172Sgrehan 1338110172Sgrehan if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1339110172Sgrehan return (0); 1340110172Sgrehan 1341152180Sgrehan count = moea_clear_bit(m, PTE_REF, NULL); 1342110172Sgrehan 1343110172Sgrehan return (count); 134490643Sbenno} 134590643Sbenno 134677957Sbenno/* 134790643Sbenno * Map a wired page into kernel virtual address space. 134877957Sbenno */ 134977957Sbennovoid 1350152180Sgrehanmoea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 135177957Sbenno{ 135290643Sbenno u_int pte_lo; 135390643Sbenno int error; 135490643Sbenno int i; 135577957Sbenno 135690643Sbenno#if 0 135790643Sbenno if (va < VM_MIN_KERNEL_ADDRESS) 1358152180Sgrehan panic("moea_kenter: attempt to enter non-kernel address %#x", 135990643Sbenno va); 136090643Sbenno#endif 136177957Sbenno 1362103604Sgrehan pte_lo = PTE_I | PTE_G; 1363103604Sgrehan for (i = 0; i < pregions_sz; i++) { 1364103604Sgrehan if ((pa >= pregions[i].mr_start) && 1365103604Sgrehan (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 136690643Sbenno pte_lo &= ~(PTE_I | PTE_G); 136777957Sbenno break; 136877957Sbenno } 1369103604Sgrehan } 137077957Sbenno 1371135172Salc PMAP_LOCK(kernel_pmap); 1372152180Sgrehan error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1373152180Sgrehan &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 137490643Sbenno 137590643Sbenno if (error != 0 && error != ENOENT) 1376152180Sgrehan panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 137790643Sbenno pa, error); 137890643Sbenno 137977957Sbenno /* 138090643Sbenno * Flush the real memory from the instruction cache. 138177957Sbenno */ 138290643Sbenno if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1383152180Sgrehan moea_syncicache(pa, PAGE_SIZE); 138477957Sbenno } 1385135172Salc PMAP_UNLOCK(kernel_pmap); 138677957Sbenno} 138777957Sbenno 138894838Sbenno/* 138994838Sbenno * Extract the physical page address associated with the given kernel virtual 139094838Sbenno * address. 139194838Sbenno */ 139290643Sbennovm_offset_t 1393152180Sgrehanmoea_kextract(mmu_t mmu, vm_offset_t va) 139477957Sbenno{ 139594838Sbenno struct pvo_entry *pvo; 1396134329Salc vm_paddr_t pa; 139794838Sbenno 1398125185Sgrehan#ifdef UMA_MD_SMALL_ALLOC 1399125185Sgrehan /* 1400125185Sgrehan * Allow direct mappings 1401125185Sgrehan */ 1402125185Sgrehan if (va < VM_MIN_KERNEL_ADDRESS) { 1403125185Sgrehan return (va); 1404125185Sgrehan } 1405125185Sgrehan#endif 1406125185Sgrehan 1407134329Salc PMAP_LOCK(kernel_pmap); 1408152180Sgrehan pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1409152180Sgrehan KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1410134329Salc pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1411134329Salc PMAP_UNLOCK(kernel_pmap); 1412134329Salc return (pa); 141377957Sbenno} 141477957Sbenno 141591456Sbenno/* 141691456Sbenno * Remove a wired page from kernel virtual address space. 141791456Sbenno */ 141877957Sbennovoid 1419152180Sgrehanmoea_kremove(mmu_t mmu, vm_offset_t va) 142077957Sbenno{ 142191456Sbenno 1422152180Sgrehan moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 142377957Sbenno} 142477957Sbenno 142577957Sbenno/* 142690643Sbenno * Map a range of physical addresses into kernel virtual address space. 142790643Sbenno * 142890643Sbenno * The value passed in *virt is a suggested virtual address for the mapping. 142990643Sbenno * Architectures which can support a direct-mapped physical to virtual region 143090643Sbenno * can return the appropriate address within that region, leaving '*virt' 143190643Sbenno * unchanged. We cannot and therefore do not; *virt is updated with the 143290643Sbenno * first usable address after the mapped region. 143377957Sbenno */ 143490643Sbennovm_offset_t 1435152180Sgrehanmoea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1436152180Sgrehan vm_offset_t pa_end, int prot) 143777957Sbenno{ 143890643Sbenno vm_offset_t sva, va; 143977957Sbenno 144090643Sbenno sva = *virt; 144190643Sbenno va = sva; 144290643Sbenno for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1443152180Sgrehan moea_kenter(mmu, va, pa_start); 144490643Sbenno *virt = va; 144590643Sbenno return (sva); 144677957Sbenno} 144777957Sbenno 144877957Sbenno/* 144991403Ssilby * Returns true if the pmap's pv is one of the first 145091403Ssilby * 16 pvs linked to from this page. This count may 145191403Ssilby * be changed upwards or downwards in the future; it 145291403Ssilby * is only necessary that true be returned for a small 145391403Ssilby * subset of pmaps for proper page aging. 145491403Ssilby */ 145590643Sbennoboolean_t 1456152180Sgrehanmoea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 145790643Sbenno{ 1458110172Sgrehan int loops; 1459110172Sgrehan struct pvo_entry *pvo; 1460110172Sgrehan 1461152180Sgrehan if (!moea_initialized || (m->flags & PG_FICTITIOUS)) 1462110172Sgrehan return FALSE; 1463110172Sgrehan 1464110172Sgrehan loops = 0; 1465110172Sgrehan LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1466110172Sgrehan if (pvo->pvo_pmap == pmap) 1467110172Sgrehan return (TRUE); 1468110172Sgrehan if (++loops >= 16) 1469110172Sgrehan break; 1470110172Sgrehan } 1471110172Sgrehan 1472110172Sgrehan return (FALSE); 147390643Sbenno} 147477957Sbenno 1475173708Salc/* 1476173708Salc * Return the number of managed mappings to the given physical page 1477173708Salc * that are wired. 1478173708Salc */ 1479173708Salcint 1480173708Salcmoea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1481173708Salc{ 1482173708Salc struct pvo_entry *pvo; 1483173708Salc int count; 1484173708Salc 1485173708Salc count = 0; 1486173708Salc if (!moea_initialized || (m->flags & PG_FICTITIOUS) != 0) 1487173708Salc return (count); 1488173708Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1489173708Salc LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1490173708Salc if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1491173708Salc count++; 1492173708Salc return (count); 1493173708Salc} 1494173708Salc 1495152180Sgrehanstatic u_int moea_vsidcontext; 149677957Sbenno 149790643Sbennovoid 1498152180Sgrehanmoea_pinit(mmu_t mmu, pmap_t pmap) 149990643Sbenno{ 150090643Sbenno int i, mask; 150190643Sbenno u_int entropy; 150277957Sbenno 1503152180Sgrehan KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1504134329Salc PMAP_LOCK_INIT(pmap); 1505126478Sgrehan 150690643Sbenno entropy = 0; 150790643Sbenno __asm __volatile("mftb %0" : "=r"(entropy)); 150877957Sbenno 150990643Sbenno /* 151090643Sbenno * Allocate some segment registers for this pmap. 151190643Sbenno */ 151290643Sbenno for (i = 0; i < NPMAPS; i += VSID_NBPW) { 151390643Sbenno u_int hash, n; 151477957Sbenno 151577957Sbenno /* 151690643Sbenno * Create a new value by mutiplying by a prime and adding in 151790643Sbenno * entropy from the timebase register. This is to make the 151890643Sbenno * VSID more random so that the PT hash function collides 151990643Sbenno * less often. (Note that the prime casues gcc to do shifts 152090643Sbenno * instead of a multiply.) 152177957Sbenno */ 1522152180Sgrehan moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1523152180Sgrehan hash = moea_vsidcontext & (NPMAPS - 1); 152490643Sbenno if (hash == 0) /* 0 is special, avoid it */ 152590643Sbenno continue; 152690643Sbenno n = hash >> 5; 152790643Sbenno mask = 1 << (hash & (VSID_NBPW - 1)); 1528152180Sgrehan hash = (moea_vsidcontext & 0xfffff); 1529152180Sgrehan if (moea_vsid_bitmap[n] & mask) { /* collision? */ 153090643Sbenno /* anything free in this bucket? */ 1531152180Sgrehan if (moea_vsid_bitmap[n] == 0xffffffff) { 1532152180Sgrehan entropy = (moea_vsidcontext >> 20); 153390643Sbenno continue; 153490643Sbenno } 1535152180Sgrehan i = ffs(~moea_vsid_bitmap[i]) - 1; 153690643Sbenno mask = 1 << i; 153790643Sbenno hash &= 0xfffff & ~(VSID_NBPW - 1); 153890643Sbenno hash |= i; 153977957Sbenno } 1540152180Sgrehan moea_vsid_bitmap[n] |= mask; 154190643Sbenno for (i = 0; i < 16; i++) 154290643Sbenno pmap->pm_sr[i] = VSID_MAKE(i, hash); 154390643Sbenno return; 154490643Sbenno } 154577957Sbenno 1546152180Sgrehan panic("moea_pinit: out of segments"); 154777957Sbenno} 154877957Sbenno 154977957Sbenno/* 155090643Sbenno * Initialize the pmap associated with process 0. 155177957Sbenno */ 155277957Sbennovoid 1553152180Sgrehanmoea_pinit0(mmu_t mmu, pmap_t pm) 155477957Sbenno{ 155577957Sbenno 1556152180Sgrehan moea_pinit(mmu, pm); 155790643Sbenno bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 155877957Sbenno} 155977957Sbenno 156094838Sbenno/* 156194838Sbenno * Set the physical protection on the specified range of this map as requested. 156294838Sbenno */ 156390643Sbennovoid 1564152180Sgrehanmoea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1565152180Sgrehan vm_prot_t prot) 156690643Sbenno{ 156794838Sbenno struct pvo_entry *pvo; 156894838Sbenno struct pte *pt; 156994838Sbenno int pteidx; 157094838Sbenno 1571152180Sgrehan CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 157294838Sbenno eva, prot); 157394838Sbenno 157494838Sbenno 157594838Sbenno KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1576152180Sgrehan ("moea_protect: non current pmap")); 157794838Sbenno 157894838Sbenno if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1579152180Sgrehan moea_remove(mmu, pm, sva, eva); 158094838Sbenno return; 158194838Sbenno } 158294838Sbenno 1583132220Salc vm_page_lock_queues(); 1584134329Salc PMAP_LOCK(pm); 158594838Sbenno for (; sva < eva; sva += PAGE_SIZE) { 1586152180Sgrehan pvo = moea_pvo_find_va(pm, sva, &pteidx); 158794838Sbenno if (pvo == NULL) 158894838Sbenno continue; 158994838Sbenno 159094838Sbenno if ((prot & VM_PROT_EXECUTE) == 0) 159194838Sbenno pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 159294838Sbenno 159394838Sbenno /* 159494838Sbenno * Grab the PTE pointer before we diddle with the cached PTE 159594838Sbenno * copy. 159694838Sbenno */ 1597152180Sgrehan pt = moea_pvo_to_pte(pvo, pteidx); 159894838Sbenno /* 159994838Sbenno * Change the protection of the page. 160094838Sbenno */ 160194838Sbenno pvo->pvo_pte.pte_lo &= ~PTE_PP; 160294838Sbenno pvo->pvo_pte.pte_lo |= PTE_BR; 160394838Sbenno 160494838Sbenno /* 160594838Sbenno * If the PVO is in the page table, update that pte as well. 160694838Sbenno */ 1607159928Salc if (pt != NULL) { 1608152180Sgrehan moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1609159928Salc mtx_unlock(&moea_table_mutex); 1610159928Salc } 161194838Sbenno } 1612132220Salc vm_page_unlock_queues(); 1613134329Salc PMAP_UNLOCK(pm); 161477957Sbenno} 161577957Sbenno 161691456Sbenno/* 161791456Sbenno * Map a list of wired pages into kernel virtual address space. This is 161891456Sbenno * intended for temporary mappings which do not need page modification or 161991456Sbenno * references recorded. Existing mappings in the region are overwritten. 162091456Sbenno */ 162190643Sbennovoid 1622152180Sgrehanmoea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 162377957Sbenno{ 1624110172Sgrehan vm_offset_t va; 162577957Sbenno 1626110172Sgrehan va = sva; 1627110172Sgrehan while (count-- > 0) { 1628152180Sgrehan moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1629110172Sgrehan va += PAGE_SIZE; 1630110172Sgrehan m++; 1631110172Sgrehan } 163290643Sbenno} 163377957Sbenno 163491456Sbenno/* 163591456Sbenno * Remove page mappings from kernel virtual address space. Intended for 1636152180Sgrehan * temporary mappings entered by moea_qenter. 163791456Sbenno */ 163890643Sbennovoid 1639152180Sgrehanmoea_qremove(mmu_t mmu, vm_offset_t sva, int count) 164090643Sbenno{ 1641110172Sgrehan vm_offset_t va; 164291456Sbenno 1643110172Sgrehan va = sva; 1644110172Sgrehan while (count-- > 0) { 1645152180Sgrehan moea_kremove(mmu, va); 1646110172Sgrehan va += PAGE_SIZE; 1647110172Sgrehan } 164877957Sbenno} 164977957Sbenno 165090643Sbennovoid 1651152180Sgrehanmoea_release(mmu_t mmu, pmap_t pmap) 165290643Sbenno{ 1653103604Sgrehan int idx, mask; 1654103604Sgrehan 1655103604Sgrehan /* 1656103604Sgrehan * Free segment register's VSID 1657103604Sgrehan */ 1658103604Sgrehan if (pmap->pm_sr[0] == 0) 1659152180Sgrehan panic("moea_release"); 1660103604Sgrehan 1661103604Sgrehan idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1662103604Sgrehan mask = 1 << (idx % VSID_NBPW); 1663103604Sgrehan idx /= VSID_NBPW; 1664152180Sgrehan moea_vsid_bitmap[idx] &= ~mask; 1665134329Salc PMAP_LOCK_DESTROY(pmap); 166677957Sbenno} 166777957Sbenno 166891456Sbenno/* 166991456Sbenno * Remove the given range of addresses from the specified map. 167091456Sbenno */ 167190643Sbennovoid 1672152180Sgrehanmoea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 167377957Sbenno{ 167491456Sbenno struct pvo_entry *pvo; 167591456Sbenno int pteidx; 167691456Sbenno 1677132220Salc vm_page_lock_queues(); 1678134329Salc PMAP_LOCK(pm); 167991456Sbenno for (; sva < eva; sva += PAGE_SIZE) { 1680152180Sgrehan pvo = moea_pvo_find_va(pm, sva, &pteidx); 168191456Sbenno if (pvo != NULL) { 1682152180Sgrehan moea_pvo_remove(pvo, pteidx); 168391456Sbenno } 168491456Sbenno } 1685140538Sgrehan PMAP_UNLOCK(pm); 1686132220Salc vm_page_unlock_queues(); 168777957Sbenno} 168877957Sbenno 168994838Sbenno/* 1690152180Sgrehan * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1691110172Sgrehan * will reflect changes in pte's back to the vm_page. 1692110172Sgrehan */ 1693110172Sgrehanvoid 1694152180Sgrehanmoea_remove_all(mmu_t mmu, vm_page_t m) 1695110172Sgrehan{ 1696110172Sgrehan struct pvo_head *pvo_head; 1697110172Sgrehan struct pvo_entry *pvo, *next_pvo; 1698134329Salc pmap_t pmap; 1699110172Sgrehan 1700120336Sgrehan mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1701120336Sgrehan 1702110172Sgrehan pvo_head = vm_page_to_pvoh(m); 1703110172Sgrehan for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1704110172Sgrehan next_pvo = LIST_NEXT(pvo, pvo_vlink); 1705133166Sgrehan 1706152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 1707134329Salc pmap = pvo->pvo_pmap; 1708134329Salc PMAP_LOCK(pmap); 1709152180Sgrehan moea_pvo_remove(pvo, -1); 1710134329Salc PMAP_UNLOCK(pmap); 1711110172Sgrehan } 1712110172Sgrehan vm_page_flag_clear(m, PG_WRITEABLE); 1713110172Sgrehan} 1714110172Sgrehan 1715110172Sgrehan/* 171690643Sbenno * Allocate a physical page of memory directly from the phys_avail map. 1717152180Sgrehan * Can only be called from moea_bootstrap before avail start and end are 171890643Sbenno * calculated. 171983682Smp */ 172090643Sbennostatic vm_offset_t 1721152180Sgrehanmoea_bootstrap_alloc(vm_size_t size, u_int align) 172283682Smp{ 172390643Sbenno vm_offset_t s, e; 172490643Sbenno int i, j; 172583682Smp 172690643Sbenno size = round_page(size); 172790643Sbenno for (i = 0; phys_avail[i + 1] != 0; i += 2) { 172890643Sbenno if (align != 0) 172990643Sbenno s = (phys_avail[i] + align - 1) & ~(align - 1); 173090643Sbenno else 173190643Sbenno s = phys_avail[i]; 173290643Sbenno e = s + size; 173390643Sbenno 173490643Sbenno if (s < phys_avail[i] || e > phys_avail[i + 1]) 173590643Sbenno continue; 173690643Sbenno 173790643Sbenno if (s == phys_avail[i]) { 173890643Sbenno phys_avail[i] += size; 173990643Sbenno } else if (e == phys_avail[i + 1]) { 174090643Sbenno phys_avail[i + 1] -= size; 174190643Sbenno } else { 174290643Sbenno for (j = phys_avail_count * 2; j > i; j -= 2) { 174390643Sbenno phys_avail[j] = phys_avail[j - 2]; 174490643Sbenno phys_avail[j + 1] = phys_avail[j - 1]; 174590643Sbenno } 174690643Sbenno 174790643Sbenno phys_avail[i + 3] = phys_avail[i + 1]; 174890643Sbenno phys_avail[i + 1] = s; 174990643Sbenno phys_avail[i + 2] = e; 175090643Sbenno phys_avail_count++; 175190643Sbenno } 175290643Sbenno 175390643Sbenno return (s); 175483682Smp } 1755152180Sgrehan panic("moea_bootstrap_alloc: could not allocate memory"); 175683682Smp} 175783682Smp 175890643Sbennostatic void 1759152180Sgrehanmoea_syncicache(vm_offset_t pa, vm_size_t len) 176077957Sbenno{ 176190643Sbenno __syncicache((void *)pa, len); 176290643Sbenno} 176377957Sbenno 176490643Sbennostatic void 176590643Sbennotlbia(void) 176690643Sbenno{ 176790643Sbenno caddr_t i; 176890643Sbenno 176990643Sbenno SYNC(); 177090643Sbenno for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 177190643Sbenno TLBIE(i); 177290643Sbenno EIEIO(); 177390643Sbenno } 177490643Sbenno TLBSYNC(); 177590643Sbenno SYNC(); 177677957Sbenno} 177777957Sbenno 177890643Sbennostatic int 1779152180Sgrehanmoea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 178090643Sbenno vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 178177957Sbenno{ 178290643Sbenno struct pvo_entry *pvo; 178390643Sbenno u_int sr; 178490643Sbenno int first; 178590643Sbenno u_int ptegidx; 178690643Sbenno int i; 1787103604Sgrehan int bootstrap; 178877957Sbenno 1789152180Sgrehan moea_pvo_enter_calls++; 179096250Sbenno first = 0; 1791103604Sgrehan bootstrap = 0; 179290643Sbenno 179390643Sbenno /* 179490643Sbenno * Compute the PTE Group index. 179590643Sbenno */ 179690643Sbenno va &= ~ADDR_POFF; 179790643Sbenno sr = va_to_sr(pm->pm_sr, va); 179890643Sbenno ptegidx = va_to_pteg(sr, va); 179990643Sbenno 180090643Sbenno /* 180190643Sbenno * Remove any existing mapping for this page. Reuse the pvo entry if 180290643Sbenno * there is a mapping. 180390643Sbenno */ 1804152180Sgrehan mtx_lock(&moea_table_mutex); 1805152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 180690643Sbenno if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 180796334Sbenno if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 180896334Sbenno (pvo->pvo_pte.pte_lo & PTE_PP) == 180996334Sbenno (pte_lo & PTE_PP)) { 1810152180Sgrehan mtx_unlock(&moea_table_mutex); 181192521Sbenno return (0); 181296334Sbenno } 1813152180Sgrehan moea_pvo_remove(pvo, -1); 181490643Sbenno break; 181590643Sbenno } 181690643Sbenno } 181790643Sbenno 181890643Sbenno /* 181990643Sbenno * If we aren't overwriting a mapping, try to allocate. 182090643Sbenno */ 1821152180Sgrehan if (moea_initialized) { 182292847Sjeff pvo = uma_zalloc(zone, M_NOWAIT); 182392521Sbenno } else { 1824152180Sgrehan if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1825152180Sgrehan panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1826152180Sgrehan moea_bpvo_pool_index, BPVO_POOL_SIZE, 182799037Sbenno BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 182892521Sbenno } 1829152180Sgrehan pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1830152180Sgrehan moea_bpvo_pool_index++; 1831103604Sgrehan bootstrap = 1; 183292521Sbenno } 183390643Sbenno 183490643Sbenno if (pvo == NULL) { 1835152180Sgrehan mtx_unlock(&moea_table_mutex); 183690643Sbenno return (ENOMEM); 183790643Sbenno } 183890643Sbenno 1839152180Sgrehan moea_pvo_entries++; 184090643Sbenno pvo->pvo_vaddr = va; 184190643Sbenno pvo->pvo_pmap = pm; 1842152180Sgrehan LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 184390643Sbenno pvo->pvo_vaddr &= ~ADDR_POFF; 184490643Sbenno if (flags & VM_PROT_EXECUTE) 184590643Sbenno pvo->pvo_vaddr |= PVO_EXECUTABLE; 184690643Sbenno if (flags & PVO_WIRED) 184790643Sbenno pvo->pvo_vaddr |= PVO_WIRED; 1848152180Sgrehan if (pvo_head != &moea_pvo_kunmanaged) 184990643Sbenno pvo->pvo_vaddr |= PVO_MANAGED; 1850103604Sgrehan if (bootstrap) 1851103604Sgrehan pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1852142416Sgrehan if (flags & PVO_FAKE) 1853142416Sgrehan pvo->pvo_vaddr |= PVO_FAKE; 1854142416Sgrehan 1855152180Sgrehan moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 185690643Sbenno 185790643Sbenno /* 185890643Sbenno * Remember if the list was empty and therefore will be the first 185990643Sbenno * item. 186090643Sbenno */ 186196250Sbenno if (LIST_FIRST(pvo_head) == NULL) 186296250Sbenno first = 1; 1863142416Sgrehan LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 186490643Sbenno 186590643Sbenno if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1866134453Salc pm->pm_stats.wired_count++; 1867134453Salc pm->pm_stats.resident_count++; 186890643Sbenno 186990643Sbenno /* 187090643Sbenno * We hope this succeeds but it isn't required. 187190643Sbenno */ 1872152180Sgrehan i = moea_pte_insert(ptegidx, &pvo->pvo_pte); 187390643Sbenno if (i >= 0) { 187490643Sbenno PVO_PTEGIDX_SET(pvo, i); 187590643Sbenno } else { 1876152180Sgrehan panic("moea_pvo_enter: overflow"); 1877152180Sgrehan moea_pte_overflow++; 187890643Sbenno } 1879152180Sgrehan mtx_unlock(&moea_table_mutex); 188090643Sbenno 188190643Sbenno return (first ? ENOENT : 0); 188277957Sbenno} 188377957Sbenno 188490643Sbennostatic void 1885152180Sgrehanmoea_pvo_remove(struct pvo_entry *pvo, int pteidx) 188677957Sbenno{ 188790643Sbenno struct pte *pt; 188877957Sbenno 188990643Sbenno /* 189090643Sbenno * If there is an active pte entry, we need to deactivate it (and 189190643Sbenno * save the ref & cfg bits). 189290643Sbenno */ 1893152180Sgrehan pt = moea_pvo_to_pte(pvo, pteidx); 189490643Sbenno if (pt != NULL) { 1895152180Sgrehan moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1896159928Salc mtx_unlock(&moea_table_mutex); 189790643Sbenno PVO_PTEGIDX_CLR(pvo); 189890643Sbenno } else { 1899152180Sgrehan moea_pte_overflow--; 1900142416Sgrehan } 190190643Sbenno 190290643Sbenno /* 190390643Sbenno * Update our statistics. 190490643Sbenno */ 190590643Sbenno pvo->pvo_pmap->pm_stats.resident_count--; 190690643Sbenno if (pvo->pvo_pte.pte_lo & PVO_WIRED) 190790643Sbenno pvo->pvo_pmap->pm_stats.wired_count--; 190890643Sbenno 190990643Sbenno /* 191090643Sbenno * Save the REF/CHG bits into their cache if the page is managed. 191190643Sbenno */ 1912142416Sgrehan if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 191390643Sbenno struct vm_page *pg; 191490643Sbenno 191592067Sbenno pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 191690643Sbenno if (pg != NULL) { 1917152180Sgrehan moea_attr_save(pg, pvo->pvo_pte.pte_lo & 191890643Sbenno (PTE_REF | PTE_CHG)); 191990643Sbenno } 192090643Sbenno } 192190643Sbenno 192290643Sbenno /* 192390643Sbenno * Remove this PVO from the PV list. 192490643Sbenno */ 192590643Sbenno LIST_REMOVE(pvo, pvo_vlink); 192690643Sbenno 192790643Sbenno /* 192890643Sbenno * Remove this from the overflow list and return it to the pool 192990643Sbenno * if we aren't going to reuse it. 193090643Sbenno */ 193190643Sbenno LIST_REMOVE(pvo, pvo_olink); 193292521Sbenno if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1933152180Sgrehan uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 1934152180Sgrehan moea_upvo_zone, pvo); 1935152180Sgrehan moea_pvo_entries--; 1936152180Sgrehan moea_pvo_remove_calls++; 193777957Sbenno} 193877957Sbenno 193990643Sbennostatic __inline int 1940152180Sgrehanmoea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 194177957Sbenno{ 194290643Sbenno int pteidx; 194377957Sbenno 194490643Sbenno /* 194590643Sbenno * We can find the actual pte entry without searching by grabbing 194690643Sbenno * the PTEG index from 3 unused bits in pte_lo[11:9] and by 194790643Sbenno * noticing the HID bit. 194890643Sbenno */ 194990643Sbenno pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 195090643Sbenno if (pvo->pvo_pte.pte_hi & PTE_HID) 1951152180Sgrehan pteidx ^= moea_pteg_mask * 8; 195290643Sbenno 195390643Sbenno return (pteidx); 195477957Sbenno} 195577957Sbenno 195690643Sbennostatic struct pvo_entry * 1957152180Sgrehanmoea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 195877957Sbenno{ 195990643Sbenno struct pvo_entry *pvo; 196090643Sbenno int ptegidx; 196190643Sbenno u_int sr; 196277957Sbenno 196390643Sbenno va &= ~ADDR_POFF; 196490643Sbenno sr = va_to_sr(pm->pm_sr, va); 196590643Sbenno ptegidx = va_to_pteg(sr, va); 196690643Sbenno 1967152180Sgrehan mtx_lock(&moea_table_mutex); 1968152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 196990643Sbenno if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 197090643Sbenno if (pteidx_p) 1971152180Sgrehan *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 1972134535Salc break; 197390643Sbenno } 197490643Sbenno } 1975152180Sgrehan mtx_unlock(&moea_table_mutex); 197690643Sbenno 1977134535Salc return (pvo); 197877957Sbenno} 197977957Sbenno 198090643Sbennostatic struct pte * 1981152180Sgrehanmoea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 198277957Sbenno{ 198390643Sbenno struct pte *pt; 198477957Sbenno 198590643Sbenno /* 198690643Sbenno * If we haven't been supplied the ptegidx, calculate it. 198790643Sbenno */ 198890643Sbenno if (pteidx == -1) { 198990643Sbenno int ptegidx; 199090643Sbenno u_int sr; 199177957Sbenno 199290643Sbenno sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 199390643Sbenno ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1994152180Sgrehan pteidx = moea_pvo_pte_index(pvo, ptegidx); 199590643Sbenno } 199690643Sbenno 1997152180Sgrehan pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 1998159928Salc mtx_lock(&moea_table_mutex); 199990643Sbenno 200090643Sbenno if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2001152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 200290643Sbenno "valid pte index", pvo); 200390643Sbenno } 200490643Sbenno 200590643Sbenno if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2006152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 200790643Sbenno "pvo but no valid pte", pvo); 200890643Sbenno } 200990643Sbenno 201090643Sbenno if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 201190643Sbenno if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 2012152180Sgrehan panic("moea_pvo_to_pte: pvo %p has valid pte in " 2013152180Sgrehan "moea_pteg_table %p but invalid in pvo", pvo, pt); 201477957Sbenno } 201590643Sbenno 201690643Sbenno if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 201790643Sbenno != 0) { 2018152180Sgrehan panic("moea_pvo_to_pte: pvo %p pte does not match " 2019152180Sgrehan "pte %p in moea_pteg_table", pvo, pt); 202090643Sbenno } 202190643Sbenno 2022159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 202390643Sbenno return (pt); 202477957Sbenno } 202577957Sbenno 202690643Sbenno if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2027152180Sgrehan panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2028152180Sgrehan "moea_pteg_table but valid in pvo", pvo, pt); 202990643Sbenno } 203077957Sbenno 2031159928Salc mtx_unlock(&moea_table_mutex); 203290643Sbenno return (NULL); 203377957Sbenno} 203478880Sbenno 203578880Sbenno/* 203690643Sbenno * XXX: THIS STUFF SHOULD BE IN pte.c? 203778880Sbenno */ 203890643Sbennoint 2039152180Sgrehanmoea_pte_spill(vm_offset_t addr) 204078880Sbenno{ 204190643Sbenno struct pvo_entry *source_pvo, *victim_pvo; 204290643Sbenno struct pvo_entry *pvo; 204390643Sbenno int ptegidx, i, j; 204490643Sbenno u_int sr; 204590643Sbenno struct pteg *pteg; 204690643Sbenno struct pte *pt; 204778880Sbenno 2048152180Sgrehan moea_pte_spills++; 204990643Sbenno 205094836Sbenno sr = mfsrin(addr); 205190643Sbenno ptegidx = va_to_pteg(sr, addr); 205290643Sbenno 205378880Sbenno /* 205490643Sbenno * Have to substitute some entry. Use the primary hash for this. 205590643Sbenno * Use low bits of timebase as random generator. 205678880Sbenno */ 2057152180Sgrehan pteg = &moea_pteg_table[ptegidx]; 2058152180Sgrehan mtx_lock(&moea_table_mutex); 205990643Sbenno __asm __volatile("mftb %0" : "=r"(i)); 206090643Sbenno i &= 7; 206190643Sbenno pt = &pteg->pt[i]; 206278880Sbenno 206390643Sbenno source_pvo = NULL; 206490643Sbenno victim_pvo = NULL; 2065152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 206678880Sbenno /* 206790643Sbenno * We need to find a pvo entry for this address. 206878880Sbenno */ 2069152180Sgrehan MOEA_PVO_CHECK(pvo); 207090643Sbenno if (source_pvo == NULL && 2071152180Sgrehan moea_pte_match(&pvo->pvo_pte, sr, addr, 207290643Sbenno pvo->pvo_pte.pte_hi & PTE_HID)) { 207390643Sbenno /* 207490643Sbenno * Now found an entry to be spilled into the pteg. 207590643Sbenno * The PTE is now valid, so we know it's active. 207690643Sbenno */ 2077152180Sgrehan j = moea_pte_insert(ptegidx, &pvo->pvo_pte); 207878880Sbenno 207990643Sbenno if (j >= 0) { 208090643Sbenno PVO_PTEGIDX_SET(pvo, j); 2081152180Sgrehan moea_pte_overflow--; 2082152180Sgrehan MOEA_PVO_CHECK(pvo); 2083152180Sgrehan mtx_unlock(&moea_table_mutex); 208490643Sbenno return (1); 208590643Sbenno } 208690643Sbenno 208790643Sbenno source_pvo = pvo; 208890643Sbenno 208990643Sbenno if (victim_pvo != NULL) 209090643Sbenno break; 209190643Sbenno } 209290643Sbenno 209378880Sbenno /* 209490643Sbenno * We also need the pvo entry of the victim we are replacing 209590643Sbenno * so save the R & C bits of the PTE. 209678880Sbenno */ 209790643Sbenno if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2098152180Sgrehan moea_pte_compare(pt, &pvo->pvo_pte)) { 209990643Sbenno victim_pvo = pvo; 210090643Sbenno if (source_pvo != NULL) 210190643Sbenno break; 210290643Sbenno } 210390643Sbenno } 210478880Sbenno 2105134535Salc if (source_pvo == NULL) { 2106152180Sgrehan mtx_unlock(&moea_table_mutex); 210790643Sbenno return (0); 2108134535Salc } 210990643Sbenno 211090643Sbenno if (victim_pvo == NULL) { 211190643Sbenno if ((pt->pte_hi & PTE_HID) == 0) 2112152180Sgrehan panic("moea_pte_spill: victim p-pte (%p) has no pvo" 211390643Sbenno "entry", pt); 211490643Sbenno 211578880Sbenno /* 211690643Sbenno * If this is a secondary PTE, we need to search it's primary 211790643Sbenno * pvo bucket for the matching PVO. 211878880Sbenno */ 2119152180Sgrehan LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 212090643Sbenno pvo_olink) { 2121152180Sgrehan MOEA_PVO_CHECK(pvo); 212290643Sbenno /* 212390643Sbenno * We also need the pvo entry of the victim we are 212490643Sbenno * replacing so save the R & C bits of the PTE. 212590643Sbenno */ 2126152180Sgrehan if (moea_pte_compare(pt, &pvo->pvo_pte)) { 212790643Sbenno victim_pvo = pvo; 212890643Sbenno break; 212990643Sbenno } 213090643Sbenno } 213178880Sbenno 213290643Sbenno if (victim_pvo == NULL) 2133152180Sgrehan panic("moea_pte_spill: victim s-pte (%p) has no pvo" 213490643Sbenno "entry", pt); 213590643Sbenno } 213678880Sbenno 213790643Sbenno /* 213890643Sbenno * We are invalidating the TLB entry for the EA we are replacing even 213990643Sbenno * though it's valid. If we don't, we lose any ref/chg bit changes 214090643Sbenno * contained in the TLB entry. 214190643Sbenno */ 214290643Sbenno source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 214378880Sbenno 2144152180Sgrehan moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2145152180Sgrehan moea_pte_set(pt, &source_pvo->pvo_pte); 214690643Sbenno 214790643Sbenno PVO_PTEGIDX_CLR(victim_pvo); 214890643Sbenno PVO_PTEGIDX_SET(source_pvo, i); 2149152180Sgrehan moea_pte_replacements++; 215090643Sbenno 2151152180Sgrehan MOEA_PVO_CHECK(victim_pvo); 2152152180Sgrehan MOEA_PVO_CHECK(source_pvo); 215390643Sbenno 2154152180Sgrehan mtx_unlock(&moea_table_mutex); 215590643Sbenno return (1); 215690643Sbenno} 215790643Sbenno 215890643Sbennostatic int 2159152180Sgrehanmoea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 216090643Sbenno{ 216190643Sbenno struct pte *pt; 216290643Sbenno int i; 216390643Sbenno 2164159928Salc mtx_assert(&moea_table_mutex, MA_OWNED); 2165159928Salc 216690643Sbenno /* 216790643Sbenno * First try primary hash. 216890643Sbenno */ 2169152180Sgrehan for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 217090643Sbenno if ((pt->pte_hi & PTE_VALID) == 0) { 217190643Sbenno pvo_pt->pte_hi &= ~PTE_HID; 2172152180Sgrehan moea_pte_set(pt, pvo_pt); 217390643Sbenno return (i); 217478880Sbenno } 217590643Sbenno } 217678880Sbenno 217790643Sbenno /* 217890643Sbenno * Now try secondary hash. 217990643Sbenno */ 2180152180Sgrehan ptegidx ^= moea_pteg_mask; 2181165362Sgrehan 2182152180Sgrehan for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 218390643Sbenno if ((pt->pte_hi & PTE_VALID) == 0) { 218490643Sbenno pvo_pt->pte_hi |= PTE_HID; 2185152180Sgrehan moea_pte_set(pt, pvo_pt); 218690643Sbenno return (i); 218790643Sbenno } 218890643Sbenno } 218978880Sbenno 2190152180Sgrehan panic("moea_pte_insert: overflow"); 219190643Sbenno return (-1); 219278880Sbenno} 219384921Sbenno 219490643Sbennostatic boolean_t 2195152180Sgrehanmoea_query_bit(vm_page_t m, int ptebit) 219684921Sbenno{ 219790643Sbenno struct pvo_entry *pvo; 219890643Sbenno struct pte *pt; 219984921Sbenno 2200123560Sgrehan#if 0 2201152180Sgrehan if (moea_attr_fetch(m) & ptebit) 220290643Sbenno return (TRUE); 2203123560Sgrehan#endif 220484921Sbenno 220590643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2206152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 220784921Sbenno 220890643Sbenno /* 220990643Sbenno * See if we saved the bit off. If so, cache it and return 221090643Sbenno * success. 221190643Sbenno */ 221290643Sbenno if (pvo->pvo_pte.pte_lo & ptebit) { 2213152180Sgrehan moea_attr_save(m, ptebit); 2214152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 221590643Sbenno return (TRUE); 221690643Sbenno } 221790643Sbenno } 221884921Sbenno 221990643Sbenno /* 222090643Sbenno * No luck, now go through the hard part of looking at the PTEs 222190643Sbenno * themselves. Sync so that any pending REF/CHG bits are flushed to 222290643Sbenno * the PTEs. 222390643Sbenno */ 222490643Sbenno SYNC(); 222590643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2226152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 222790643Sbenno 222890643Sbenno /* 222990643Sbenno * See if this pvo has a valid PTE. if so, fetch the 223090643Sbenno * REF/CHG bits from the valid PTE. If the appropriate 223190643Sbenno * ptebit is set, cache it and return success. 223290643Sbenno */ 2233152180Sgrehan pt = moea_pvo_to_pte(pvo, -1); 223490643Sbenno if (pt != NULL) { 2235152180Sgrehan moea_pte_synch(pt, &pvo->pvo_pte); 2236159928Salc mtx_unlock(&moea_table_mutex); 223790643Sbenno if (pvo->pvo_pte.pte_lo & ptebit) { 2238152180Sgrehan moea_attr_save(m, ptebit); 2239152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 224090643Sbenno return (TRUE); 224190643Sbenno } 224290643Sbenno } 224384921Sbenno } 224484921Sbenno 2245123354Sgallatin return (FALSE); 224684921Sbenno} 224790643Sbenno 2248110172Sgrehanstatic u_int 2249152180Sgrehanmoea_clear_bit(vm_page_t m, int ptebit, int *origbit) 225090643Sbenno{ 2251110172Sgrehan u_int count; 225290643Sbenno struct pvo_entry *pvo; 225390643Sbenno struct pte *pt; 225490643Sbenno int rv; 225590643Sbenno 225690643Sbenno /* 225790643Sbenno * Clear the cached value. 225890643Sbenno */ 2259152180Sgrehan rv = moea_attr_fetch(m); 2260152180Sgrehan moea_attr_clear(m, ptebit); 226190643Sbenno 226290643Sbenno /* 226390643Sbenno * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 226490643Sbenno * we can reset the right ones). note that since the pvo entries and 226590643Sbenno * list heads are accessed via BAT0 and are never placed in the page 226690643Sbenno * table, we don't have to worry about further accesses setting the 226790643Sbenno * REF/CHG bits. 226890643Sbenno */ 226990643Sbenno SYNC(); 227090643Sbenno 227190643Sbenno /* 227290643Sbenno * For each pvo entry, clear the pvo's ptebit. If this pvo has a 227390643Sbenno * valid pte clear the ptebit from the valid pte. 227490643Sbenno */ 2275110172Sgrehan count = 0; 227690643Sbenno LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2277152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 2278152180Sgrehan pt = moea_pvo_to_pte(pvo, -1); 227990643Sbenno if (pt != NULL) { 2280152180Sgrehan moea_pte_synch(pt, &pvo->pvo_pte); 2281110172Sgrehan if (pvo->pvo_pte.pte_lo & ptebit) { 2282110172Sgrehan count++; 2283152180Sgrehan moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2284110172Sgrehan } 2285159928Salc mtx_unlock(&moea_table_mutex); 228690643Sbenno } 228790643Sbenno rv |= pvo->pvo_pte.pte_lo; 228890643Sbenno pvo->pvo_pte.pte_lo &= ~ptebit; 2289152180Sgrehan MOEA_PVO_CHECK(pvo); /* sanity check */ 229090643Sbenno } 229190643Sbenno 2292110172Sgrehan if (origbit != NULL) { 2293110172Sgrehan *origbit = rv; 2294110172Sgrehan } 2295110172Sgrehan 2296110172Sgrehan return (count); 229790643Sbenno} 229899038Sbenno 229999038Sbenno/* 2300103604Sgrehan * Return true if the physical range is encompassed by the battable[idx] 2301103604Sgrehan */ 2302103604Sgrehanstatic int 2303152180Sgrehanmoea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2304103604Sgrehan{ 2305103604Sgrehan u_int prot; 2306103604Sgrehan u_int32_t start; 2307103604Sgrehan u_int32_t end; 2308103604Sgrehan u_int32_t bat_ble; 2309103604Sgrehan 2310103604Sgrehan /* 2311103604Sgrehan * Return immediately if not a valid mapping 2312103604Sgrehan */ 2313103604Sgrehan if (!battable[idx].batu & BAT_Vs) 2314103604Sgrehan return (EINVAL); 2315103604Sgrehan 2316103604Sgrehan /* 2317103604Sgrehan * The BAT entry must be cache-inhibited, guarded, and r/w 2318103604Sgrehan * so it can function as an i/o page 2319103604Sgrehan */ 2320103604Sgrehan prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2321103604Sgrehan if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2322103604Sgrehan return (EPERM); 2323103604Sgrehan 2324103604Sgrehan /* 2325103604Sgrehan * The address should be within the BAT range. Assume that the 2326103604Sgrehan * start address in the BAT has the correct alignment (thus 2327103604Sgrehan * not requiring masking) 2328103604Sgrehan */ 2329103604Sgrehan start = battable[idx].batl & BAT_PBS; 2330103604Sgrehan bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2331103604Sgrehan end = start | (bat_ble << 15) | 0x7fff; 2332103604Sgrehan 2333103604Sgrehan if ((pa < start) || ((pa + size) > end)) 2334103604Sgrehan return (ERANGE); 2335103604Sgrehan 2336103604Sgrehan return (0); 2337103604Sgrehan} 2338103604Sgrehan 2339152180Sgrehanboolean_t 2340152180Sgrehanmoea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2341133855Sssouhlal{ 2342133855Sssouhlal int i; 2343103604Sgrehan 2344133855Sssouhlal /* 2345133855Sssouhlal * This currently does not work for entries that 2346133855Sssouhlal * overlap 256M BAT segments. 2347133855Sssouhlal */ 2348133855Sssouhlal 2349133855Sssouhlal for(i = 0; i < 16; i++) 2350152180Sgrehan if (moea_bat_mapped(i, pa, size) == 0) 2351133855Sssouhlal return (0); 2352133855Sssouhlal 2353133855Sssouhlal return (EFAULT); 2354133855Sssouhlal} 2355133855Sssouhlal 2356164895Sgrehanboolean_t 2357164895Sgrehanmoea_page_executable(mmu_t mmu, vm_page_t pg) 2358164895Sgrehan{ 2359164895Sgrehan return ((moea_attr_fetch(pg) & PTE_EXEC) == PTE_EXEC); 2360164895Sgrehan} 2361164895Sgrehan 2362103604Sgrehan/* 236399038Sbenno * Map a set of physical memory pages into the kernel virtual 236499038Sbenno * address space. Return a pointer to where it is mapped. This 236599038Sbenno * routine is intended to be used for mapping device memory, 236699038Sbenno * NOT real memory. 236799038Sbenno */ 236899038Sbennovoid * 2369152180Sgrehanmoea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 237099038Sbenno{ 2371103604Sgrehan vm_offset_t va, tmpva, ppa, offset; 2372103604Sgrehan int i; 2373103604Sgrehan 2374103604Sgrehan ppa = trunc_page(pa); 237599038Sbenno offset = pa & PAGE_MASK; 237699038Sbenno size = roundup(offset + size, PAGE_SIZE); 237799038Sbenno 237899038Sbenno GIANT_REQUIRED; 237999038Sbenno 2380103604Sgrehan /* 2381103604Sgrehan * If the physical address lies within a valid BAT table entry, 2382103604Sgrehan * return the 1:1 mapping. This currently doesn't work 2383103604Sgrehan * for regions that overlap 256M BAT segments. 2384103604Sgrehan */ 2385103604Sgrehan for (i = 0; i < 16; i++) { 2386152180Sgrehan if (moea_bat_mapped(i, pa, size) == 0) 2387103604Sgrehan return ((void *) pa); 2388103604Sgrehan } 2389103604Sgrehan 2390118365Salc va = kmem_alloc_nofault(kernel_map, size); 239199038Sbenno if (!va) 2392152180Sgrehan panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 239399038Sbenno 239499038Sbenno for (tmpva = va; size > 0;) { 2395152180Sgrehan moea_kenter(mmu, tmpva, ppa); 239699038Sbenno TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 239799038Sbenno size -= PAGE_SIZE; 239899038Sbenno tmpva += PAGE_SIZE; 2399103604Sgrehan ppa += PAGE_SIZE; 240099038Sbenno } 240199038Sbenno 240299038Sbenno return ((void *)(va + offset)); 240399038Sbenno} 240499038Sbenno 240599038Sbennovoid 2406152180Sgrehanmoea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 240799038Sbenno{ 240899038Sbenno vm_offset_t base, offset; 240999038Sbenno 2410103604Sgrehan /* 2411103604Sgrehan * If this is outside kernel virtual space, then it's a 2412103604Sgrehan * battable entry and doesn't require unmapping 2413103604Sgrehan */ 2414103604Sgrehan if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2415103604Sgrehan base = trunc_page(va); 2416103604Sgrehan offset = va & PAGE_MASK; 2417103604Sgrehan size = roundup(offset + size, PAGE_SIZE); 2418103604Sgrehan kmem_free(kernel_map, base, size); 2419103604Sgrehan } 242099038Sbenno} 2421